| 28th week of 2009 patent applcation highlights part 23 |
| Patent application number | Title | Published |
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| 20090175058 | METHOD AND APPARATUS FOR A POWER SUPPLY CONTROLLER RESPONSIVE TO A FEEDFORWARD SIGNAL - An apparatus and method of switching a switch of a power supply in response to an input voltage signal are disclosed. According to aspects of the present invention, a power supply controller includes a switch duty cycle controller coupled to receive a feedback signal and a duty cycle adjust signal. The switch duty cycle controller is coupled to generate a drive signal coupled to control switching of a switch, which is coupled to an energy transfer element, to regulate energy delivered from an input of a power supply to an output of the power supply. The power supply controller also includes a gain selector circuit coupled to receive an input voltage signal, which is representative of an input voltage to the power supply, to generate the duty cycle adjust signal received by the switch duty cycle controller. The maximum duty cycle of the drive signal to be varied in response to a plurality of linear functions over a range of values of the input voltage signal. | 2009-07-09 |
| 20090175059 | POWER CONVERTER APPARATUS AND POWER CONVERTER APPARATUS CONTROL METHOD - A converter section converts a three-phase ac input voltage into a dc voltage, and an inverter section converts the dc voltage converted by the converter section into a prescribed three-phase ac output voltage. The converter section converts the three-phase ac input voltage into the dc voltage on the basis of trapezoidal waveform voltage instruction signals from a trapezoidal waveform voltage instruction signal generating part and a carrier signal from a carrier signal generating part. The inverter section converts the dc voltage converted by the converter section | 2009-07-09 |
| 20090175060 | POWER TRANSMISSION CONTROL DEVICE, NON-CONTACT POWER TRANSMISSION SYSTEM, POWER TRANSMITTING DEVICE, ELECTRONIC INSTRUMENT, AND WAVEFORM MONITOR CIRCUIT - A power transmission control device includes a power-transmitting-side control circuit that controls an operation of a power transmitting device, a driver control circuit that controls operations of a first power transmitting driver and a second power transmitting driver, and a waveform detection circuit that performs a waveform detection process based on a monitor signal from a waveform monitor circuit. The first power transmitting driver drives a first node of a primary coil directly, and the second power transmitting driver drives a second node of the primary coil through a capacitor. A switch circuit is provided in the waveform monitor circuit, the switch circuit being situated in a signal path between the primary coil and a low-level power supply potential. The power-transmitting-side control circuit causes the switch circuit to be turned ON/OFF using a switch control signal. | 2009-07-09 |
| 20090175061 | INSTANTANEOUS LOAD CURRENT CONTROL SCHEME FOR VOLTAGE FED DC TO AC INVERTER SUPPLYING RESISTIVE-INDUCTIVE LOAD - A control system is provided for controlling varying alternating current (AC) to a load with varying resistance and inductance. A plurality of nested control loops may employ cascaded proportional controllers to provide desired control of a pulse width modulation (PWM) block to control an inverter that supplies AC power to the load. An AC feedback signal may be supplied to each proportional controller. An AC feed forward signal may be added to outputs of the proportional controllers. | 2009-07-09 |
| 20090175062 | FEEDBACK STRUCTURE FOR AN SRAM CELL - Embodiments of the present disclosure provide a feedback structure, a method of constructing a feedback structure and an integrated circuit employing the feedback structure. In one embodiment, the feedback structure is for use with an integrated circuit and includes a local interconnect configured to electrically connect an output of a CMOS inverter to another circuit in the integrated circuit. Additionally, the feedback structure also includes an interconnect extension to the local interconnect configured to proximately extend along a gate structure of the CMOS inverter to provide a reactive coupling between the output and the gate structure. | 2009-07-09 |
| 20090175063 | SEMICONDUCTOR MEMORY DEVICE INCLUDING MEMORY CELL ARRAY HAVING MEMORY CELLS USING FLOATING BODY TRANSISTORS - A semiconductor memory device includes a memory cell array, which includes a cell array having multiple cell blocks. Each cell block includes source and word lines arranged in one direction, bit lines arranged in a perpendicular direction, and memory cells having corresponding floating bodies. Adjacent memory cells share source or drain regions to form common source or drain regions, respectively. The source regions are arranged in a word line direction and connected to corresponding source lines, and the drain regions are arranged in the bit line direction and connected to corresponding bit lines. Gates of the memory cells are arranged in the word line direction and are connected to form the word lines. The source lines are formed on a layer of the word lines, and the bit lines are formed at a different layer to be insulated from the word and source lines. | 2009-07-09 |
| 20090175064 | SEMICONDUCTOR MEMORY DEVICE WITH REDUCED COUPLING NOISE - A semiconductor device includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells provided at the intersections of the plurality of word lines and the plurality of bit lines and each of that includes a MIS transistor and a memory element, a decoder circuit for selecting a plurality of word lines, and a sense-amplifier circuit for determining information that is read from any of the plurality of memory cells to any of the plurality of bit lines, wherein a twist connector for switching the wiring order of the plurality of word lines is provided and level-stabilizing circuits, for supplying the potential level of a non-selected state to the plurality of word lines in the non-selected state are arranged in the area below the twist connector. | 2009-07-09 |
| 20090175065 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor memory device including a ferroelectric memory includes: a nonvolatile memory having higher data retention capability under high temperature than the ferroelectric memory; and a connection circuit for switching between connection and disconnection of the ferroelectric memory and the nonvolatile memory. The ferroelectric memory receives, through the connection circuit, at least part of data which is unique to the device and which has been written into the nonvolatile memory, and retains the received data. | 2009-07-09 |
| 20090175066 | High-speed DRAM including hierarchical read circuits - DRAM includes hierarchical read circuits with multi-divided bit lines, wherein a local read circuit receives an output from a memory cell through a bit line, a segment read circuit receives an output from one of multiple local read circuits through a segment read line, and a block read circuit receives an output from one of multiple segment read circuits through a block read line. Thus a voltage difference is converted to a time difference by the read circuits. In this manner, a time-domain sensing scheme is realized to differentiate high data and low data. For instance, high data is quickly transferred to a latch circuit through the read circuits with high gain, but low data is rejected by a locking signal based on high data as a reference signal. Additionally, various alternatives are described. And structures for the memory cell and layouts for the read circuits are illustrated. | 2009-07-09 |
| 20090175067 | SRAM EMPLOYING A READ-ENABLING CAPACITANCE - Embodiments of the present disclosure provide a memory element, a method of constructing a memory element, a method of operating a memory cell, an SRAM cell and an integrated circuit. In one embodiment, the memory element includes a pair of cross-connected CMOS inverters having first and second storage nodes. Additionally, the memory element also includes a capacitive component connected between the first and second storage nodes and configured to provide a supplemental capacitance to extend a read signal for sensing a memory state of the inverters. | 2009-07-09 |
| 20090175068 | SRAM DEVICE, AND SRAM DEVICE DESIGN STRUCTURE, WITH ADAPTABLE ACCESS TRANSISTORS - An SRAM device comprising a pair of MCSFETs connected as access transistors (pass gates). An SRAM device design structure embodied or stored in a machine readable medium includes two MCSFETs connected as access transistors. | 2009-07-09 |
| 20090175069 | STORAGE CELL HAVING BUFFER CIRCUIT FOR DRIVING THE BITLINE - An integrated circuit includes a memory array including a plurality of memory cells, the memory cells include a core storage element having at least a first storage node (S) and a complementary second storage node (S-bar), and a first pass gate ) coupled to the first storage node (S). A single bitline (BL) is coupled to a node in a source drain path of the first pass gate. The BL is for Reading data from and Writing data to the first storage node (S). A buffer circuit includes a second pass gate and a driver transistor, wherein the second pass gate is coupled between the driver transistor and the source drain path of the first pass gate. A gate of the driver transistor is coupled to the second storage node (S-bar). At least one wordline (WL) is coupled to the first pass gate and the second pass gate. | 2009-07-09 |
| 20090175070 | DUAL NODE ACCESS STORAGE CELL HAVING BUFFER CIRCUITS - An integrated circuit includes an array of memory cells, each including a core storage element with first and second complementary storage nodes and first and second cell pass transistors coupled to the first and second storage nodes, respectively. In the cell, a first bitline (BL) is coupled to a first BL node in a source drain path of the first cell pass transistor, and a second BL is coupled to a second BL node in a source drain path of the second cell pass transistor. Each of the memory cells also includes a first buffer circuit comprising a first buffer pass transistor and a first driver transistor coupled to the source drain path of the first cell pass transistor, where the first buffer pass transistor is between the first BL node and the first driver transistor. The memory cells also include a second buffer circuit comprising a second buffer pass transistor and a second driver transistor coupled to a source drain path of the second cell pass transistor, where the second buffer pass transistor is between the second BL node and the second driver transistor. The gates of the first and second driver transistors are coupled to the second and first storage nodes, respectively. The cells include at least a first wordline coupled to the first and second cell pass transistors and the first and second buffer pass transistors. | 2009-07-09 |
| 20090175071 | PHASE CHANGE MEMORY DYNAMIC RESISTANCE TEST AND MANUFACTURING METHODS - A method for testing an integrated circuit memory device includes applying a sequence of test pulses to a memory cell on the device, where the test pulses result in current through the memory cell having an amplitude dependent on the test pulse. Resistance in the memory cell is measured in response to the sequence of test pulses. A parameter set is extracted from the resistance measurements which includes at least one numerical coefficient that models dependency of the measured resistance on the amplitude of the current through the memory cell. The extracted numerical coefficient or coefficients are associated with the memory device, and used for controlling manufacturing operations. | 2009-07-09 |
| 20090175072 | PHASE-CHANGE RANDOM ACCESS MEMORY DEVICES AND RELATED METHODS OF OPERATION - A phase-change random access memory (PRAM) device includes a plurality of banks, a plurality of column redundancy cell arrays, and a plurality of column redundancy write drivers. Each of the plurality of column redundancy cell arrays corresponds to at least one of the banks. Each of the plurality of column redundancy write drivers corresponds to at least one of the column redundancy cell arrays. The column redundancy write drivers are configured to transmit respective redundancy test data to the corresponding ones of the column redundancy cell arrays in response to a test control signal, which may be activated in response to each program pulse for writing data. Related test and access methods are also discussed. | 2009-07-09 |
| 20090175073 | Nanostructure-Based Memory - Improved memory devices that include one or more nanostructures such as carbon nanotubes or other nanostructures, as well as systems and devices incorporating such improved memory devices, are disclosed. In at least some embodiments, the improved memory device is of a nonvolatile type such as a flash memory device, and employs a pair of triodes that form a memory cell, where each triode employs at least one carbon nanotube. Also disclosed are methods of operating and fabricating such improved memory devices. | 2009-07-09 |
| 20090175074 | DEVICE FOR READING A LOW-CONSUMPTION NON-VOLATILE MEMORY AND ITS IMPLEMENTING METHOD - The reading device enables a non-volatile memory consisting of a matrix of memory cells (T | 2009-07-09 |
| 20090175075 | FLASH MEMORY STORAGE APPARATUS, FLASH MEMORY CONTROLLER, AND SWITCHING METHOD THEREOF - A flash memory storage apparatus including a multi level cell (MLC) NAND flash memory, a flash memory controller, and a host transmission bus is provided. The MLC NAND flash memory includes a plurality of blocks for storing data, wherein each of the blocks has an upper page and a lower page, and the writing speed of the lower page is faster than that of the upper page. The flash memory controller is electrically connected to the MLC NAND flash memory and is used for executing storage mode switching steps. The host transmission bus is electrically connected to the flash memory controller and is used for communicating with a host. The flash memory storage apparatus provided by the present invention can provide multiple storage modes in order to store different data. | 2009-07-09 |
| 20090175076 | Memory device and method for estimating characteristics of multi-bit cell - Memory devices and/or methods that may estimate characteristics of multi-bit cell are provided. A memory device may include: a multi-bit cell array; a monitoring unit to extract a threshold voltage change over time value for reference threshold voltage states selected from a plurality of threshold voltage states corresponding to data stored in the multi-bit cell array; and an estimation unit to estimate a threshold voltage change over time values for the plurality of threshold voltage states based on the extracted threshold voltage change. Through this, it is possible to monitor a change over time of threshold voltages of a memory cell. | 2009-07-09 |
| 20090175077 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - This disclosure concerns a memory including: word lines extending to a first direction; bit lines extending to a second direction crossing the first direction; a memory cell array including cell blocks each including memory cells respectively provided corresponding to intersection points of the word lines and the bit lines; and sense amplifiers provided corresponding to the bit lines, wherein the sense amplifiers copies existing data stored in a first cell block within the memory cell array to a plurality of memory cells, the memory cells being included in second and third cell blocks different from the first cell block, and alternately arranged in an extension direction of the word lines and also alternately arranged in an extension direction of the bit lines, and the sense amplifiers reads data from the second cell block or the third cell block, at a time of outputting data to outside of the sense amplifiers. | 2009-07-09 |
| 20090175078 | APPARATUS FOR REDUCING THE IMPACT OF PROGRAM DISTURB - The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different verify levels are used for a particular word line (or other grouping of storage elements) during a programming process. In another embodiment, different compare levels are used for a particular word (or other grouping of storage elements) during a read process. | 2009-07-09 |
| 20090175079 | STRUCTURES AND METHODS TO STORE INFORMATION REPRESENTABLE BY A MULTIPLE-BIT BINARY WORD IN ELECTRICALLY ERASABLE, PROGRAMMABLE READ-ONLY MEMORY (EEPROM) - Innovative structures and methods to store information capable of being represented by an n-bit binary word in electrically erasable Programmable Read-Only memories (EEPROM) are disclosed. To program a state below the highest threshold voltage for an N-type Field Effect Transistor (NFET) based EEPROM, the stored charge in the floating gate for the highest threshold voltage is erased down to the desired threshold voltage level of the EEPROM by applying an appropriate voltage to the control gate and drain of the NFET. The erase-down uses drain-avalanche-hot hole injection (DAHHI) for the NFET memory device to achieve the precise threshold voltage desired for the NFET EEPROM device. The method takes advantage of the self-convergent mechanism from the DAHHI current in the device, when the device reaches a steady state. For a “READ” operation, a read voltage is applied to the control gate and the drain is connected by a current load to the positive voltage supply. Using the distinctive threshold voltage associated with the different stored charges, the output voltage from the drain is distinctively recognized and converted back to the original n-bit word. A similar method for a PFET EEPROM is also disclosed. | 2009-07-09 |
| 20090175080 | Flash EEprom System With Simultaneous Multiple Data Sector Programming and Storage of Physical Block Characteristics in Other Designated Blocks - A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data. The stream of data may further be transformed in order to tend to even out the wear among the blocks of memory. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell. | 2009-07-09 |
| 20090175081 | NAND FLASH MEMORY HAVING MULTIPLE CELL SUBSTRATES - A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during an erase operation, such that unselected well sectors are inhibited from receiving the erase voltage. When the area of the well sectors decrease, a corresponding decrease in the capacitance of each well sector results. Accordingly, higher speed erasing of the NAND flash memory cells relative to a single well memory bank is obtained when the charge pump circuit drive capacity remains unchanged. Alternately, a constant erase speed corresponding to a single well memory bank is obtained by matching a well segment having a specific area to a charge pump with reduced drive capacity. A reduced drive capacity charge pump will occupy less semiconductor chip area, thereby reducing cost. | 2009-07-09 |
| 20090175082 | Flash EEprom System With Simultaneous Multiple Data Sector Programming and Storage of Physical Block Characteristics in Other Designated Blocks - A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data. The stream of data may further be transformed in order to tend to even out the wear among the blocks of memory. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell. | 2009-07-09 |
| 20090175083 | Nonvolatile Semiconductor Memory Device - The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines. | 2009-07-09 |
| 20090175084 | Buffering systems for accessing multiple layers of memory in integrated circuits - Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles. | 2009-07-09 |
| 20090175085 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF WRITING AND READING THE SAME - MOS transistors each having different ON withstanding voltages that are drain withstanding voltages when gates thereof are turned on are formed on the same substrate. One of the MOS transistors having the lower ON withstand voltage is used as a memory element. Using the fact that the drain withstanding voltage is low when a gate thereof is turned on, a short-circuit occurs in a PN junction between a drain and the substrate of the one of the MOS transistors having the lower ON withstand voltage to write data. | 2009-07-09 |
| 20090175086 | ENABLE SIGNAL GENERATOR METHOD AND APPARATUS - According to the embodiments described herein, an enable signal generator has two stages. Each stage offsets transistor performance variation in the other stage to produce an enable signal output relatively immune from the effects associated with transistor mismatches. In one embodiment, a memory device comprises a plurality of memory cells, sense amplifier circuitry and the enable signal generator. The sense amplifier circuitry is coupled to one or more of the memory cells and senses the state of the one or more memory cells when enabled. The enable signal generator has first and second stages and generates an enable signal applied to the sense amplifier circuitry. The enable signal generator counteracts delay variation when generating the enable signal so that operation of the enable signal generator is substantially unaffected by transistor performance variation in either stage of the enable signal generator. | 2009-07-09 |
| 20090175087 | METHOD OF VERIFYING PROGRAMMING OPERATION OF FLASH MEMORY DEVICE - A method is provided for verifying a programming operation of a flash memory device. The flash memory device includes at least one memory string in which a string selection transistor, multiple memory cells and a ground selection transistor are connected in series, and the programming operation is performed with respect to a selected memory cell in the memory string. The method includes applying a voltage, obtained by adding a threshold voltage of the string selection transistor to a power supply voltage, to a string selection line connected to the string selection transistor; applying a ground voltage to wordlines connected to each of the memory cells and a ground selection line connected to the ground selection transistor; precharging a bitline connected to the memory string to the power supply voltage; and determining whether a programming operation of the selected memory cell is complete. | 2009-07-09 |
| 20090175088 | METHOD AND ARCHITECTURE FOR FAST FLASH MEMORY PROGRAMMING - Embodiments of the present invention disclose a method of utilizing a flash memory array to decrease programming time while maintaining sufficient read speeds. An array of cells is programmed and read in pages that are oriented in the column direction, parallel to the bit lines in the array. An erased cell in the present invention is a cell in the “off” state. According to the present invention a cell is programmed by lowering the threshold voltage of the cell, thereby turning the cell “on.” An array of cells is programmed read in a sector-by-sector method, wherein a sector consists of units situated diagonally adjacent to each other, and a unit consists of multiple parallel column-oriented pages. | 2009-07-09 |
| 20090175089 | Retention in NVM with top or bottom injection - Retention of charges in a nonvolatile memory (NVM) cell having a nitride-based injector (such as SiN, SIRN, SiON) for facilitating injection of holes into a charge-storage layer (for NROM, nitride) of a charge-storage stack (for NROM, ONO) may be improved by providing an insulating layer (for NROM, oxide) between the charge-storage layer and the injector has a thickness of at least 3 nm. Top and bottom injectors are disclosed. Methods of operating NVM cells are disclosed. The NVM cell may be NROM, SONOS, or other oxide-nitride technology NVM cells such as SANOS, MANOS, TANOS. | 2009-07-09 |
| 20090175090 | Buffered DRAM - A buffered DRAM that can be utilized in a DIMM or RDIMM package to reduce the load on the data lines connected to the package is presented. A buffered DRAM can include a DRAM memory cell; and a buffer coupled to receive data lines and strobe signals, the buffer further coupled to receive address and command signals. If data access is directed to a second DRAM, the buffer buffers the data and strobe signals for access by the second DRAM. If data access is directed to the buffered DRAM the buffer buffers the data and strobe signals for access by the DRAM memory cell. | 2009-07-09 |
| 20090175091 | APPARATUS AND METHODS FOR AN INPUT CIRCUIT FOR A SEMICONDUCTOR MEMORY APPARATUS - An input circuit for a semiconductor memory apparatus comprising a input unit configured to selectively latch a plurality of external signals and output the latched signal; and a control unit coupled to the input unit, the control unit configured to control the operations of the input unit according to an operation mode of the semiconductor memory apparatus is described herein. | 2009-07-09 |
| 20090175092 | Semiconductor Memory Devices for Controlling Latency - A semiconductor memory device includes a command buffer that receives an external command and outputs a first command signal, a clock buffer that receives an external clock signal and outputs a first internal clock signal, a delay measurement and initialization unit that receives the first internal clock signal and a fourth internal clock signal and responsively outputs a second internal clock signal and a plurality of delayed signals corresponding to a delay time between when the external clock signal is input and data is output, a delay locked loop that receives the second internal clock signal and outputs a third internal clock signal and the fourth internal clock signal, a latency signal generation unit that delays the first command signal by a delay time between when the second internal clock signal is input to the delay locked loop and when the third internal clock signal is output from the delay locked loop, and then outputs the delayed first command signal as a latency signal, in response to the second and third internal clock signals and the delayed signals, and a data output buffer that outputs the data in response to the latency signal and the third internal clock signal. | 2009-07-09 |
| 20090175093 | APPARATUS FOR CONTROLLING COLUMN SELECTING SIGNAL FOR SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF CONTROLLING THE SAME - An apparatus for controlling a column selecting signal of semiconductor memory apparatus comprising a column decoder that outputs a first column selecting signal, a signal control unit that outputs a second column selecting signal that is generated by controlling an enable period of the first column selecting signal, and an output control unit that outputs the first column selecting signal or the second column selecting signal in response to the input of a predetermined voltage detecting signal. | 2009-07-09 |
| 20090175094 | CURRENT SENSING METHOD AND APPARATUS FOR A MEMORY ARRAY - A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory cells, which substantially eliminates leakage current through half-selected memory cells. The bit line current which is sensed arises largely from only the current through the selected memory cell. A noise detection line in the memory array reduces the effect of coupling from unselected word lines to the selected bit line. In a preferred embodiment, a three-dimensional memory array having a plurality of rail-stacks forming bit lines on more than one layer, includes at least one noise detection line associated with each layer of bit lines. A sensing circuit is connected to a selected bit line and to its associated noise detection line. | 2009-07-09 |
| 20090175095 | VOLTAGE SENSING CIRCUIT AND METHOD FOR OPERATING THE SAME - A voltage sensing circuit is capable of controlling a pumping voltage to be stably generated in a low voltage environment. The voltage sensing circuit includes a current mirror having first and second terminals, a first switching element configured to control current on the first terminal of the current mirror by a reference voltage, a second switching element configured to control current from the second terminal of the current mirror in response to a pumping voltage, and a third switching element configured to control current sources of the first and second switching elements to receive a negative voltage. | 2009-07-09 |
| 20090175096 | SEMICONDUCTOR DEVICE AND METHOD FOR BOOSTING WORD LINE - A semiconductor device of the present invention includes a booster circuit that boosts a selected word line (WL) to a given voltage higher than a power supply voltage and a charge pump circuit that retains the boosted word line (WL) at the first given voltage. When the booster circuit boosts the word line, the voltage level is degraded as the time goes. However, it is possible to program the memory cell and read out thereof properly by retaining the voltage of the word line with the charge pump circuit. | 2009-07-09 |
| 20090175097 | Method for detecting erroneous word lines of a memory array and device thereof - A method detects if a word line of a memory array is broken. The method includes writing a first datum to a memory cell when coupling a corresponding word line to a voltage source, writing a second datum different from the first datum to the memory cell when the coupling between the corresponding word line and the voltage source is decoupled, reading the stored data of the memory cell, and determining if the word line is broken according to the read data, the first datum, and the second datum. | 2009-07-09 |
| 20090175098 | SEMICONDUCTOR MEMORY DEVICE INCLUDING FLOATING BODY TRANSISTOR MEMORY CELL ARRAY AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a memory cell array including a plurality of memory cells, where each memory cell includes a transistor with a floating body region in which majority carriers are accumulated in a steady state. In write and read operations, a first data state corresponding to the steady state is written to and read from at least one selected memory cell of the memory cell array by supplying a first bipolar current through the at least one selected memory cell, and a second data state is written to and read from the at least one selected memory cell by supplying a second bipolar current which is smaller than the first bipolar current through the at least one selected memory cell. In a refresh operation, memory cells of the memory cell array storing the second data state are refreshed | 2009-07-09 |
| 20090175099 | Single End Read Module for Register Files - A read module for register files includes at least one local I/O module coupled to a memory cell for outputting a value stored in the memory cell; and at least one global bit line driver having an input terminal coupled to the local I/O module, and a output terminal coupled to a global bit line for selectively pre-charging the global bit line at a default voltage in response to a local pre-charge signal, and outputting the value stored in the memory cell to the global bit line when the local pre-charge signal is not asserted. | 2009-07-09 |
| 20090175100 | METHOD AND APPARATUS FOR STORAGE DEVICE WITH A LOGIC UNIT AND METHOD FOR MANUFACTURING SAME - Method and apparatus that relate to a storage device comprising a plurality of memory cells, an interface device configured to connect the storage device to a host system and configured to transmit signals to read and write data from the host system to the memory cells via a first and second data path, and a logic unit. The logic unit is configured to read and write data from the plurality of memory cells via the second data path, and configured to perform logic operations on data stored in the plurality of memory cells. When performing read and write operations, the first data path excludes the logic unit, and the second data path includes the logic unit. Furthermore, the logic unit is communicatively coupled between the interface device and the plurality of memory cells. Additionally, a method for manufacturing the memory device is provided. | 2009-07-09 |
| 20090175101 | Self-feedback control pipeline architecture for memory read path applications - A memory reading apparatus transfers digital data from a memory array that is independent of external clocking rate, where the data transmission time is not limited by the external clock period, and the internal timing of controls permits flexible column selection and no conflicts in the timing between external clock signals and internal bit line sensing ready signal. The memory read apparatus has a data read path circuit and a memory read control apparatus. The data read path circuit is in communication with the memory to acquire the selected data read from the memory, synchronize the selected data, and transfer the selected data from the memory. The memory read control apparatus is in communications with the data read path circuit for selecting the data to be read from the memory, for providing self-feedback signals for synchronizing the selected data for transfer from the memory. | 2009-07-09 |
| 20090175102 | METHOD FOR CONTROLLING ACCESS OF A MEMORY - A memory access control method is provided. By decoding a read-write command, a mode register set (MRS) signal is generated. When the MRS signal is enabled, a latch outputs a bank-select signal. The bank-select signal is then decoded to generate a register-select signal. Then, an address signal is written into a register selected by the register-select signal. The value of a certain register can be used to determine whether to enable the error check function. Thus, the next generation memory structure with the CRC function can be compatible with the conventional memory structure. | 2009-07-09 |
| 20090175103 | SEMICONDUCTOR MEMORY ASYNCHRONOUS PIPELINE - An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it. | 2009-07-09 |
| 20090175104 | Three dimensional structure memory - A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques. | 2009-07-09 |
| 20090175105 | Semiconductor memory device that includes an address coding method for a multi-word line test - Example embodiments relate to a semiconductor memory device that includes an address coding method for a multi-word line test, for example, an address coding method to test a semiconductor memory device having a cell block row selection circuit. The semiconductor memory device may include a plurality of memory cell blocks, where each memory cell block may include memory cells coupled to a bit line. The method may include coding row addresses of the memory cell block by dividing one or more row addresses corresponding to cell blocks of the memory cell block to create sub-cell blocks and adding the sub-cell blocs into the main cell blocks to create a logical memory block, which enables word lines of the main cell blocks and sub-cell blocks at the same time. | 2009-07-09 |
| 20090175106 | APPARATUS FOR IMPLEMENTING EFUSE SENSE AMPLIFIER TESTING WITHOUT BLOWING THE EFUSE - Apparatus implements effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem. | 2009-07-09 |
| 20090175107 | Apparatus for and Method of Current Leakage Reduction in Static Random Access Memory Arrays - A novel and useful mechanism for reducing current leakage in a static random access memory array which significantly reduces the power requirements of the memory array. The method enables the steady state of all local and global bit lines in an SRAM array to be discharged during both active and inactive modes. The memory array consists of memory cells having an N channel field effect transistor read stack. A mechanism is provided to evaluate data from memory cells where the steady state of local and global read bit lines is discharged. | 2009-07-09 |
| 20090175108 | Integrated Circuit, Cell Arrangement, Method for Manufacturing an Integrated Circuit and for Reading a Memory Cell Status, Memory Module - An integrated circuit having a cell arrangement is provided. The cell arrangement may include a memory cell and a reference cell. The memory cell has a first memory cell status and a second memory cell status. The reference cell is set to an intermediate memory cell status between the first memory cell status and the second memory cell status. | 2009-07-09 |
| 20090175109 | CURRENT-MODE SENSE AMPLIFIER AND SENSE AMPLIFYING METHOD - A current-mode sense amplifier comprises a first current mirror, a second current mirror and an amplifying circuit. The first current mirror outputs a cell current to a memory cell and duplicates the cell current to generate a mirrored cell current. The second current mirror outputs a reference current to the reference cell and duplicates the reference current to generate a mirrored reference current. The amplifying circuit comprises a first switch, second switch, third switch and fourth switch. The first switch has first and second terminals for respectively receiving the mirrored cell and reference currents. The second and third switches have first terminals respectively coupled to the first and second terminals of the first switch, and control terminals respectively coupled to the second and first terminals of the first switch. The fourth switch is connected to second terminals of the second and third switches. | 2009-07-09 |
| 20090175110 | Non-volatile memory element and method of operation therefor - A very small magnetic tunnel junction is formed on a semiconductor p-i-n diode. Spin-polarized current which is generated by circular polarized light or elliptically-polarized light, is injected into a free layer of the magnetic tunnel junction so that magnetization direction (two opposite directions) in the free layer is changed based on the information, whereby information is stored in the memory element. | 2009-07-09 |
| 20090175111 | CIRCUIT HAVING GATE OXIDE PROTECTION FOR LOW VOLTAGE FUSE READS AND HIGH VOLTAGE FUSE PROGRAMMING - A circuit for reading and programming a fuse. The electronic circuit includes a data fuse coupled to a data node and a reference fuse coupled to a reference node. A programming circuit is coupled to the data node, wherein the programming circuit is configured to, when activated, cause the data fuse to be programmed. A sensing circuit is configured to draw current from the data node and the reference node in order to develop a voltage differential between the data node and the reference node during a read operation. A read circuit is configured to, when activated, enable the sensing circuit to develop the voltage differential during the read operation. A protection circuit is configured to form a voltage divider within the sensing circuit during programming of the fuse. | 2009-07-09 |
| 20090175112 | Table lookup voltage compensation for memory cells - Systems and methods of regulating voltage at a memory cell are disclosed. An address for the memory cell is determined. Table lookups based on the address are performed. The table lookups yield voltage compensation parameters that can be used to set voltages on the terminals (e.g., source and drain) of the memory cell. | 2009-07-09 |
| 20090175113 | CHARACTERIZATION OF BITS IN A FUNCTIONAL MEMORY - Embodiments of the present disclosure provide an integrated circuit including a functional memory and methods of characterizing a component or a defect of a memory cell in the functional memory. In one embodiment, the functional memory includes row and column periphery units having periphery sourcing and sinking voltage supply ports, an array of memory cells organized in rows and columns and a word line controlled by a word line driver that provides row access to a memory cell of the array. Additionally, the functional memory also includes a bit line controlled by a direct bit line access circuit that provides direct bit line access to the memory cell through a bit line analog access port and an independent voltage supply port. | 2009-07-09 |
| 20090175114 | MULTI-PORT SEMICONDUCTOR MEMORY DEVICE HAVING VARIABLE ACCESS PATHS AND METHOD THEREFOR - A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports. | 2009-07-09 |
| 20090175115 | MEMORY DEVICE, METHOD FOR ACCESSING A MEMORY DEVICE AND METHOD FOR ITS MANUFACTURING - Embodiments relates to a memory device, comprising a plurality of memory cells, said memory cells being addressable by a plurality of addresses, an interface for reading and/or writing data from a host system to said memory device, said interface comprising at least an address bus and a clock signal line, said address bus being configured to transmit a first part of an address at the leading edge of said clock signal and a second part of an address at the trailing edge of said clock signal. | 2009-07-09 |
| 20090175116 | CLOCK SYNCHRONIZATION CIRCUIT AND OPERATION METHOD THEREOF - A semiconductor memory device with a clock synchronization circuit capable of performing a desired phase/frequency locking operation, without the jitter peaking phenomenon and the pattern jitter of an oscillation control voltage signal using injection locking. The device includes a phase-locked loop that detects a phase/frequency difference between a feedback clock signal and a reference clock signal to generate an oscillation control voltage signal corresponding to the detected phase/frequency difference, and generates the feedback clock signal corresponding to the oscillation control voltage signal. An injection locking oscillation unit sets up a free running frequency in response to the oscillation control voltage signal and generates an internal clock signal which is synchronized with the reference clock signal. | 2009-07-09 |
| 20090175117 | Conveying screw member for plastic granule cutting and transporting mechanism - A conveying screw member for a plastic granule cutting and transporting mechanism includes a plastic granule collector, a heating conduit, a conveying screw, a plastic granule molding structure and a power transmission device. The plastic granule collector is a hollow cylinder which has an outlet being positioned thereon. The heating conduit is a longitudinal hollow tube which has a round hole being respectively positioned at both ends. The conveying screw member which has the conveying screw being set thereon, and the reversing screws and two supporting bases being respectively set at both ends is installed in the heating conduit. The plastic granule molding structure is equipped near the edge of the end of the heating conduit. The power transmission device is installed near the plastic granule collector and attached to the supporting base of one end of the conveying screw member. | 2009-07-09 |
| 20090175118 | Extrusion method and apparatus - An extrusion apparatus including a mixing chamber comprising two intersecting housing bores and an inlet positioned to receive material into the mixing chamber. Two screw shafts are supported for rotation about respective generally parallel axes and include respective screw sections positioned for co-wiping intermeshing rotation within the respective housing bores of the mixing chamber. The apparatus supports screw shaft rotational speeds greater than approximately 800 rpm and includes screw shaft conveying portions that are rotatably cantilevered for self-journaled support within respective separate conveying chambers arranged generally parallel to one another downstream of the mixing chamber. | 2009-07-09 |
| 20090175119 | SINGLE SCREW EXTRUDER FOR PROCESSING OF LOW VISCOSITY PRECONDITIONED MATERIALS - Improved single screw extruders systems ( | 2009-07-09 |
| 20090175120 | EXTRUDER HAVING VARIABLE MID-BARREL RESTRICTION AND ADJACENT HIGH INTENSITY MIXING ASSEMBLY - Improved, high Specific Mechanical Energy extrusion systems ( | 2009-07-09 |
| 20090175121 | Process and mixing unit for the preparation of isocyanates by phosgenation of primary amines - The invention relates to a mixer reactor of the rotor-stator type. This mixer reactor comprises a substantially rotationally symmetric housing which has a distributing chamber, a mixing chamber, a front plate that modifies the cross-section of the housing between these two chambers, and there are separate inlets into the mixing chamber for at least two substances and an outlet for removing the mixed material or product. The inlet for the first substance is provided in the axis of rotation of the mixing chamber. Two or more channels are aligned radially outward from this inlet, and the first substance is transported through these channels and into the mixing chamber. The inlet for the at least second substance is constructed in the form of a plurality of openings in the front plate, these inlet openings being are arranged rotationally symmetrically to the axis of rotation. Each of these inlet openings for the at least second substance has a corresponding pin which can be displaced in the axial direction. | 2009-07-09 |
| 20090175122 | Homogenizer Device Having Horizontally Mounted Gear Rims - In the case of a homogenizer device ( | 2009-07-09 |
| 20090175123 | CONTROL DRIP MIXER ATTACHMENT - A control drip mixer attachment is in combination with a hub type food mixer. The control drip mixer attachment includes a container with a side wall and a bottom wall forming an interior of the container. A shaft is connected to the container, with the shaft being adapted and arranged to be removably inserted into a hub section of the mixer. An outlet opening is in fluid communication with the interior of the container near the bottom wall and is located vertically above the bowl of the mixer. | 2009-07-09 |
| 20090175124 | Method and Apparatus for Positioning a Center of a Seismic Source - The present invention provides a method and apparatus for positioning a center of a seismic source. The method includes determining a desired center-of-source of the seismic source and selecting one of a first and a second plurality of guns to form the seismic source based upon the desired center-of-source, a center-of-source of the first plurality being different than a center-of-source of the second plurality. | 2009-07-09 |
| 20090175125 | Direct Mapping of Oil-Saturated Subsurface Formations - The propagation of a compressional wave in a reservoir rock causes the pore fluids to flow within the pores and pore connections; this internal flow of the pore fluid exhibits hysteretic and viscoelastic behavior. This nonlinear behavior is directly related to the viscosity of the pore fluids. Pore fluids that have higher viscosity like oil, after being disturbed due to a sudden change in pressure applied by a seismic impulse, require a larger time-constant to return to its original state of equilibrium. This larger time-constant generates lower seismic frequencies, and becomes the differentiating characteristic on a seismic image between the lower-viscosity pore fluid like water against the higher-viscosity pore fluid like oil. Mapping these lower frequencies on a seismic reflection image highlights the oil-bearing volume of the reservoir rock formations versus the volume of the reservoir rock formations saturated with water or gas. | 2009-07-09 |
| 20090175126 | FREQUENCY SHIFT RESERVOIR LOCALIZATION - A method and system of detecting and mapping a subsurface hydrocarbon reservoir includes acquiring seismic data having a plurality of components, applying a data transform to the seismic data to obtain seismic data spectral component maxima and maxima profiles, and recording the maxima or maxima profile in a form for display. | 2009-07-09 |
| 20090175127 | MULTIBEAM SOUNDER - The sounder according to the invention comprises two transmit-receive antennas ( | 2009-07-09 |
| 20090175128 | SONAR IMAGING SYSTEM WITH A SYNTHETIC APERTURE - A synthetic antenna sonar system, includes:
| 2009-07-09 |
| 20090175129 | ULTRASOUND EMISSION DERATIZATION METHOD AND DEVICE - An ultrasound emission deratization device is described, comprising generation means (A, B, D) of a first ultrasound frequency (P1) and a second ultrasound frequency (P2) which are alternated, with a predetermined mean emission time for each of the two, and randomly variable time range pauses between a minimum and a maximum between one and the other. | 2009-07-09 |
| 20090175130 | Device for operating an electronic multifunctional device - An operating mechanism of a multifunctional device which can be worn on the wrist and has a housing with integrated electronics. The operating mechanism is integrated into the housing and has an operating element which is a one-piece or multi-piece setting stem. The setting stem partly crosses the housing, and the setting stem is arranged parallel to a planar enlargement of the housing and is rotatably and linearly moveably mounted. The setting stem can be moved linearly parallel to the longitudinal axis and rotatively about the rotational axis/longitudinal axis by a first operating watch button and optionally with a second operating watch button. The movement of the setting stem triggers various contacts on a contact plate, from which contacts electronic signals are sent to the electronics, as a result of which the electronic control of the multifunctional device is effected. | 2009-07-09 |
| 20090175131 | Alarm Clock Having Audio File Playback Capabilities - Described is an alarm clock for playing selected audio files according to a time-based schedule. More specifically, the alarm clock is adapted to maintain a calendar and a clock and to store a plurality of audio files. The alarm clock assigns each audio file a corresponding date and time, and when an assigned date and time occurs, the alarm clock plays the corresponding audio file such that file is perceivable by a user. | 2009-07-09 |
| 20090175132 | INITIATING PLAYING OF DATA USING AN ALARM CLOCK - An alarm clock device includes a monitor for monitoring a transmission of a selected station, a detector for detecting, in the transmission of the selected station, at least one milestone. A controller operating in response to detection of the milestone is provided to store, in a memory, data of the transmission after the milestone was detected, and to initiate playing of the data at a selected wakeup time. According to the present invention, the data is recorded in response to detecting a transmission of a selected station selected from a plurality of stations. | 2009-07-09 |
| 20090175133 | Electronic Calendar Apparatus - This invention provides an electronic calendar apparatus which comprises a display screen of at least 4.9 inches in diagonal dimension, a clock for generating date and time information, a nonvolatile storage device configured to store scheduling information, and a processing unit configured to control the display of the stored scheduling information on the display screen based on the date and time information generated by the clock, wherein the display screen, the clock, the nonvolatile memory and the processing unit are enclosed in a single enclosure, so that the electronic calendar apparatus can be either placed on a desk or hung on a wall. | 2009-07-09 |
| 20090175134 | Alarm and managing method thereof - The present invention provides a method of managing an alarm. According to the method of the invention, step (a) is firstly performed to control the alarm to ring at a predetermined time and generate a first question. Secondly, step (b) is performed to receive a first answer inputted by a user. Thirdly, step (c) is performed to judge whether the first answer matches a first default answer. If the first answer matches the first default answer, step (d) is finally performed to control the alarm to stop ringing. | 2009-07-09 |
| 20090175135 | INTEGRATED WATCH BAND AND METHODS THEREFOR - The present invention includes an integrated (composite) watchband and process for making a watchband that integrates a high tensile strength fabric (e.g. an aramid fabric) within the watchband via an injection molding process. The resultant integrated watchband exhibits greatly increased strength while maintaining all the necessary characteristics of a conventional band. | 2009-07-09 |
| 20090175136 | Recording and reproducing apparatus as well as recording and reproducing method - A recording and reproducing apparatus and a recording and reproducing method capable of making correspond to original data without recording repeated data are provided. The recording and reproducing apparatus includes: reproducing element | 2009-07-09 |
| 20090175137 | REPRODUCING METHOD FOR REPRODUCING REAL TIME DATA FROM A DISK-SHAPED INFORMATION RECORDING MEDIUM - A standard reproduction model for ensuring real time reproducing on a disk-shaped information recording medium, includes a pickup ( | 2009-07-09 |
| 20090175138 | SERVO CONTROLLING APPARATUS AND METHOD OF HOLOGRAPHIC INFORMATION RECORDING/REPRODUCING SYSTEM - A servo controlling apparatus of a holographic information recording/reproducing system changes the foci of reference light and signal light in a depth direction of a holographic information storage medium to record information over a plurality of information layers. A servo control is changed from a normal servo operation to a between-movement servo operation while movement between information layers is made during a recording operation, and the servo control is changed back to the normal servo operation when the movement between information layers is completed. The between-movement servo operation maintains a servo control state that exists before the movement between information layers. | 2009-07-09 |
| 20090175139 | RECORDING MEDIUM FOR STORING LINKING TYPE INFORMATION AND METHOD OF PROCESSING DEFECTIVE AREA USING THE SAME - A recording medium storing information indicating that linking is applied immediately after the defective area, distinguishing a linking type which occurs in a general incremental recording mode from a linking type which occurs after the defective area. Defective areas are detected and registered in a predetermined area (recording management data (RMD) area) before user data is recorded or while user data is being recorded in the recording medium having a plurality of continuous basic recording units, such as a digital versatile disc-rewritable (DVD-RW) in which recording and reproducing can be done repeatedly. Linking is not only applied in an incremental recording mode or in a restricted overwrite recording mode, but linking is also applied to an area immediately after the defective area which is registered in the defect list, increasing reliability of the user data. | 2009-07-09 |
| 20090175140 | OPTICAL DISC APPARATUS - An optical disc apparatus which detects an envelope of a tracking error signal in a record or playback mode of an optical disc having recording layers of a multilayer structure, which quantifies a variation caused by multilayer interference (to ΔTES), and which restricts a recording or playback rate when a relationship ΔTES>Vth is satisfied for a predetermined threshold Vth. With such an arrangement, degradation of a recording or reproducing performance or generation of running-off-track resulting from a variation in the tracking error signal caused by stray light reflected by ones of recording layers of the optical disc which are not a recording or reproducing target layer can be suppressed, and a good recording or playback quality can be obtained even in such an optical disc having the plurality of recording layers laminated therein. | 2009-07-09 |
| 20090175141 | WRITE-ONCE OPTICAL DISC, AND METHOD AND APPARATUS FOR RECORDING MANAGEMENT INFORMATION ON WRITE-ONCE OPTICAL DISC - A recording medium, and a method and apparatus for recording and/or reproducing management information on/from the recording medium are discussed. According to an embodiment, the invention provides an apparatus includes components so that the apparatus finalizes the recording medium when receiving request of an external host or when a temporary defect management area located in at least one of a non-data area and a non-user data area becomes full, where a controller is configured to control the components so that the apparatus records the latest defect list information written in the temporary defect management area onto a final defect management area when finalizing the recording medium. | 2009-07-09 |
| 20090175142 | METHOD AND SYSTEM OF RECORDING DATA ON A STORAGE MEDIUM - A method of recording data on a storage medium is provided. A first recording indicator is written on the storage medium to indicate a first state of a data recording thereon. A second recording indicator is written on the storage medium to indicate a second state of the data recording thereon. A recording status of the data recording is determined accordingly in accordance with the first and second indicators. | 2009-07-09 |
| 20090175143 | RECORDING SYSTEM, RECORDING APPARATUS, AND RECORD CONTROL SIGNAL GENERATING APPARATUS - A signal generating unit of a formatter inputs a misalignment amount δ unique to an individual recording apparatus and record data into a record signal compensation unit, and in accordance with these the record signal compensation unit generates a compensated beam deflection signal and substrate velocity signal to a beam unit and rotation and movement drive unit. With this arrangement, it is possible to perform compensation which matches errors in individual unit, in response to the errors (mechanical errors) in assembly dimension precision of parts and control precision of control devices which can vary among individual unit of the recording apparatus. | 2009-07-09 |
| 20090175144 | INFORMATION RECORDING METHOD AND APPARATUS - An information recording method, including detecting a synchronous signal and first address information from a recording medium, on which the synchronous signal and the first address information have been preformatted in a wobbled groove track, which is divided into a first unit with a predetermined length on the wobbled groove track. The method further includes constructing the track into second units, the second unit having a length different from the first unit with the predetermined length, and generating second address information indicating the constructed second units. | 2009-07-09 |
| 20090175145 | FORWARD SENSE SIGNAL GENERATION - A device for recording information on a record carrier ( | 2009-07-09 |
| 20090175146 | Data Recording/Reproducing Method and Apparatus - A data recording/reproducing method and apparatus which are capable of accurately and stably controlling a gap between a recording medium and a head of the data recording/reproducing apparatus are disclosed. The data recording/reproducing method includes: outputting at least one signal based on a light beam reflected from a recording medium; detecting a minimum value and a maximum value of the output signal; and adjusting a gap between a head of a data recording/reproducing apparatus and the recording medium according to the minimum value and the maximum value. | 2009-07-09 |
| 20090175147 | Reducing written-in errors in servo patterns - A method for writing servo onto a disk of a hard disk drive. The method includes writing a plurality of spiral servo signals with a head. The spiral servo signals are used to generate position error signals and write a plurality of servo patterns. A write current of the head is varied for at least one servo pattern. A PES/WC relationship between the position error signals and the write current is determined and a plurality of final servo patterns are written by utilizing the PES/WC relationship and varying the write current. Varying the write current changes the trailing edge of the servo bits and controls the position of the track center. The PES/WC relationship allows the system to compensate for excursions within a single revolution of the disk. | 2009-07-09 |
| 20090175148 | Holographic system, in particular for holographic data storage - In order, in the case of a holographic system, in particular for holographic data storage, comprising a radiation source for emission of a radiation an objective lens, a signal evaluation means, a detector and an optical data storage medium, the optical data storage medium having at least one data carrier layer and at least one beam-reflecting layer, to provide a solution which forms a small, compact and robust unit, in the case of which the signal beam crosses the reference beam only once, which avoids the use of optical beam splitters and requires a minimal alignment outlay, it is proposed that the objective lens has a plurality of sections, at least two beams that run parallel passing through the objective lens in a respective section and the at least two beams focusing at respectively separate locations on a plane in the optical data storage medium, at least one beam reflected in the optical data storage medium passing through the objective lens again in a respective further section. | 2009-07-09 |
| 20090175149 | HOLOGRAPHIC INFORMATION RECORDING AND/OR REPRODUCING APPARATUS - A holographic information recording and/or reproducing apparatus includes a light pickup optical system and a recording power control unit. The light pickup optical system illuminates reference light and signal light onto an information storing medium. The recording power control unit controls the light pickup optical system such that recording power of the reference light is the same as that of signal light. | 2009-07-09 |
| 20090175150 | MULTI-CHANNEL OPTICAL PICKUP AND OPTICAL RECORDING/REPRODUCING APPARATUS EMPLOYING THE SAME - A multi-channel optical pick-up and a multi-channel optical recording and/or reproducing apparatus employing the same, the multi-channel optical pick-up including: a plurality of light sources including a center light source closest to an optical axis from among the plurality of light sources and at least one off-axis light source farther than the center light source to the optical axis; an objective lens to condense a plurality of light beams respectively emitted from the plurality light sources onto a plurality of tracks of an information storage medium; and an optical path length changing element to compensate for defocus that occurs due to the at least one off-axis light source distanced from the optical axis when a center light beam from the center light source and at least one off-axis light beam from the at least one off-axis light source form spots on the information storage medium. | 2009-07-09 |
| 20090175151 | OPTICAL DISC, OPTICAL DISC DRIVE, OPTICAL DISC RECORDING/REPRODUCING METHOD, AND INTEGRATED CIRCUIT - An address format for appropriately controlling the recording linear density and the number of information recording layers is provided in order to increase the recording capacity of an information recording medium such as an optical disc or the like in a range in which a necessary S/N ratio can be guaranteed. An optical disc includes an information recording layer having a concentric or spiral track, and has a format for describing a track address, which is pre-recorded on the track or is to be added to data that is to be recorded on the information recording layer. The format includes layer information regarding the information recording layer and address information regarding the track address. | 2009-07-09 |
| 20090175152 | OPTICAL DISK APPARATUS AND OPTICAL PICKUP - Provided is an optical disk apparatus that suppresses shortening of the life time of a light source, degradation of the signal quality involved in an increase in quantum noise, and lowering of the slope efficiency, which are caused by a temperature increase of the light source by a lowering in the heat radiation performance of the light source due to size reduction or thickness reduction of the apparatus. As a specific structure, the optical disk apparatus includes an optical pickup including: a light source; a light source drive circuit; an optical base housing an optical system for guiding light emitted from the light source to a disk-shaped recording medium; a first heat radiation member connected to the light source; and a second heat radiation member connected to the light source drive circuit. | 2009-07-09 |
| 20090175153 | Electrical-Effect Data Recording Medium that Includes a Localized Electrical Conduction Layer - An electrical-effect data recording medium is preferably formed by a successive stacking of a protective layer, a localized electrical conduction layer, a recording layer, a thin layer forming an electrode and a substrate. The localized electrical conduction layer is formed by a low electrical conductivity material, in which inclusions having a higher electrical conductivity than that of the material are dispersed. The inclusions can be oblong or spherical in shape and the material presents a non-linear electrical conduction. | 2009-07-09 |
| 20090175154 | Disk with Embedded Flash Memory and Disc Drive - A disc has an outer section on which digital media can be recorded and a core in its center in which a flash memory is embedded with the core having a central hole and electrical contacts to the flash memory. A disc drive has a drive spindle that is to extend into the disc core central hole with one of the spindle or spindle hub having electrical contacts to engage with the core electrical contacts so that data can be written into and/or read from the core flash memory by electronic components of the drive. | 2009-07-09 |
| 20090175155 | OPTICAL DISC, OPTICAL DISC DRIVE, OPTICAL DISC RECORDING/REPRODUCING METHOD, AND INTEGRATED CIRCUIT - A big pattern for a run-in area which allows data reproduction to be performed stably even when the recording density of an optical disc is increased is provided. An optical disc according to the present invention includes tracks, each of which divided into a plurality of recording blocks. Each of the plurality of blocks includes a run-in area and a data area. In the run-in area, a prescribed run-in bit pattern is recordable; and in the data area, bit patterns having a plurality of bit lengths obtained by modulating data as a recording target in accordance with a prescribed modulation rule are recordable. In this optical disc, at least one of spatial frequencies corresponding to the bit patterns having the plurality of bit lengths is higher than a cutoff frequency. The run-in bit pattern recordable in the run-in area includes the bit patterns having the plurality of bit lengths, from which the bit pattern corresponding to the frequency higher than the OTF cutoff frequency has been excluded. | 2009-07-09 |
| 20090175156 | Communication Apparatus and Method - Methods and apparatuses for communication are provided. | 2009-07-09 |
| 20090175157 | ECHO CANCELLATION DEVICE FOR FULL DUPLEX COMMUNICATION SYSTEMS - An apparatus for echo cancellation in a transceiver of a full duplex communication system, where the transceiver includes a transmitter for transmitting a transmit signal and a receiver for receiving a receive signal, includes: an echo cancellation signal generator, coupled to the transmitter, for receiving the transmit signal and for generating an echo cancellation signal according to the transmit signal, wherein the echo cancellation signal reflects an effect of an impedance of a channel and a parasitic capacitor of the transceiver; and a calculation module coupled to the transmitter, the receiver, and the echo cancellation signal generator for receiving the receive signal and for canceling the echo of the receive signal according to the echo cancellation signal to generate an echo-cancelled signal, wherein the effect of the impedance of the channel and the parasitic capacitor of the transceiver in the echo-cancelled signal is reduced. | 2009-07-09 |
