| 28th week of 2009 patent applcation highlights part 12 |
| Patent application number | Title | Published |
|---|
| 20090173958 | LIGHT EMITTING DEVICES WITH HIGH EFFICIENCY PHOSPOR STRUCTURES - A light emitting device includes a light emitting die configured to emit light having a first dominant wavelength, and an index matched wavelength conversion structure configured to receive light emitted by the light emitting die. The index matched wavelength conversion structure includes wavelength converting particles having a first index of refraction embedded in a matrix material. The matrix material has a second index of refraction that may be substantially matched to the first index of refraction. The light emitting device may include a graded index layer having an index of refraction that is continuously graded from a first index of refraction in a first region of the graded index layer near the light emitting die to a second index of refraction in the graded index layer away from the light emitting die. | 2009-07-09 |
| 20090173959 | Panel-Shaped Semiconductor Module - A solar battery module as a panel-shaped semiconductor module comprises multiple rod-shaped electric power generation semiconductor elements arranged in multiple rows and columns, a conductive connection mechanism connecting in series multiple semiconductor elements in each column and electrically connecting in parallel multiple semiconductor elements in each row, and a conductive inner metal case housing the multiple semiconductor elements and constituting the conductive connection mechanism, wherein each row of semiconductor elements is housed in each reflecting surface-forming groove of the inner metal case, the positive electrodes of the semiconductor electrodes are connected to the bottom plate and the negative electrodes are connected to finger leads, and the top is covered with a transparent cover member. | 2009-07-09 |
| 20090173960 | SEMICONDUCTOR LIGHT EMITTING DEVICE WITH PRE-FABRICATED WAVELENGTH CONVERTING ELEMENT - A semiconductor light emitting device is provided with a separately fabricated wavelength converting element. The wavelength converting element, of e.g., phosphor and glass, is produced in a sheet that is separated into individual wavelength converting elements, which are bonded to light emitting devices. The wavelength converting elements may be grouped and stored according to their wavelength converting properties. The wavelength converting elements may be selectively matched with a semiconductor light emitting device, to produce a desired mixture of primary and secondary light. | 2009-07-09 |
| 20090173961 | Led Semiconductor Body and Use of an Led Semiconductor body - An LED semiconductor body comprising a first radiation-generating active layer and a second radiation-generating active layer, the first active layer and the second active layer being arranged one above another in the vertical direction. | 2009-07-09 |
| 20090173962 | SEMICONDUCTOR LIGHT-EMITTING DEVICE, METHOD OF MANUFACTURING THE SAME, AND LAMP INCLUDING THE SAME - A semiconductor light-emitting device having a high light emission property and preventing an electrode from being peeled off during wire bonding. Also disclosed is a method of manufacturing a semiconductor light-emitting device | 2009-07-09 |
| 20090173963 | Light-emitting device - The present invention is related to a light-emitting device. The present invention illustrates a vertical light-emitting device in one embodiment, comprising the following elements: a conductive substrate includes a through-hole, a patterned semiconductor structure disposed on a first surface of the substrate, a first bonding pad and a second bonding pad disposed on a second surface of the substrate, a conductive line passing through the through-hole connecting electrically the semiconductor structure layer, and an insulation layer on at least one sidewall of the through-hole insulates the conductive line form the substrate. The present invention illustrates a horizontal light-emitting device in another embodiment, comprising the following elements: a substrate includes a first tilted sidewall, a patterned semiconductor structure disposed on a first surface of the substrate, a first conductive line is disposed on at least the first tilted sidewall of the substrate and connecting electrically the patterned semiconductor structure. | 2009-07-09 |
| 20090173964 | METHOD OF FORMING A CARBON NANOTUBE-BASED CONTACT TO SEMICONDUCTOR - Manufacturers encounter limitations in forming low resistance ohmic electrical contact to semiconductor material P-type Gallium Nitride (p-GaN), commonly used in photonic applications, such that the contact is highly transparent to the light emission of the device. Carbon nanotubes (CNTs) can address this problem due to their combined metallic and semiconducting characteristics in conjunction with the fact that a fabric of CNTs has high optical transparency. The physical structure of the contact scheme is broken down into three components, a) the GaN, b) an interface material and c) the metallic conductor. The role of the interface material is to make suitable contact to both the GaN and the metal so that the GaN, in turn, will make good electrical contact to the metallic conductor that interfaces the device to external circuitry. A method of fabricating contact to GaN using CNTs and metal while maintaining protection of the GaN surface is provided. | 2009-07-09 |
| 20090173965 | METHOD OF MANUFACTURING NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE AND NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE MANUFACTURED USING THE METHOD - There are provided a method of manufacturing a nitride semiconductor light emitting device and a nitride semiconductor light emitting device manufactured using the same. A method of manufacturing a nitride semiconductor light emitting device according to an aspect of the invention includes: forming a mask layer on a substrate; removing a portion of the mask layer to form openings provided as regions where light emitting structures are formed; forming a light emitting structure by sequentially growing a first conductivity type nitride semiconductor layer, an active layer, and a second conductivity type nitride semiconductor layer on the substrate through each of the openings of the mask layer; and forming first and second electrodes to be electrically connected to the first and second conductivity type nitride semiconductor layers, respectively. | 2009-07-09 |
| 20090173966 | INTEGRATED LOW LEAKAGE DIODE - An integrated low leakage diode suitable for operation in a power integrated circuit has a structure similar to a lateral power MOSFET, but with the current flowing through the diode in the opposite direction to a conventional power MOSFET. The anode is connected to the gate and the comparable MOSFET source region which has highly doped regions of both conductivity types connected to the channel region to thereby create a lateral bipolar transistor having its base in the channel region. A second lateral bipolar transistor is formed in the cathode region. As a result, substantially all of the diode current flows at the upper surface of the diode thereby minimizing the substrate leakage current. A deep highly doped region in contact with the layers forming the emitter and the base of the vertical parasitic bipolar transistor inhibits the ability of the vertical parasitic transistor to fully turn on. | 2009-07-09 |
| 20090173967 | STRAINED-CHANNEL FET COMPRISING TWIST-BONDED SEMICONDUCTOR LAYER - This invention provides a strained-channel field effect transistor (FET) in which the semiconductor of the channel of the FET is formed in a compliant substrate layer disposed over a twist-bonded semiconductor interface. This FET geometry increases the efficacy of local stress elements such as stress liners and embedded lattice-mismatched source/drain regions by mechanically decoupling the semiconductor of the channel region from the underlying rigid substrate. These strained-channel FETs may be incorporated into complementary metal oxide semiconductor (CMOS) circuits in various combinations. In one embodiment of this invention, both pFETs and nFETs are in a twist-bonded (001) silicon layer on a (001) silicon base layer. In another embodiment, pFETs are in a twist-bonded (011) silicon layer on a (001) silicon base layer and nFETs are in a conventional, non-twist-bonded (001) silicon base layer. This invention also provides a twist-bonded semiconductor layer on a polycrystalline base layer, as well as methods for fabricating the aforementioned FETs. | 2009-07-09 |
| 20090173968 | Field Effect Transistor - A semiconductor device | 2009-07-09 |
| 20090173969 | Semiconductor Device - A semiconductor device having an AlGaN—GaN heterojunction structure including an AlGaN layer and a GaN layer which device exhibits no changes over time in sheet resistance. | 2009-07-09 |
| 20090173970 | METHOD OF FABRICATING HETERO-JUNCTION BIPOLAR TRANSISTOR (HBT) AND STRUCTURE THEREOF - A method of fabricating a hetero-junction bipolar transistor (HBT) is disclosed, where the HBT has a structure incorporating a hetero-junction bipolar structure disposed on a substrate including of silicon crystalline orientation <110>. The hetero-junction bipolar structure may include an emitter, a base and a collector. The substrate may include a shallow-trench-isolation (STI) region and a deep trench region on which the collector is disposed. The substrate may include of a region of silicon crystalline orientation <100> in addition to silicon crystalline orientation <110> to form a composite substrate by using hybrid orientation technology (HOT). The region of crystalline orientation <100> may be disposed on crystalline orientation <110>. Alternatively, the region of silicon crystalline orientation <110> may be disposed on crystalline orientation <100>. | 2009-07-09 |
| 20090173971 | MEMORY CELL LAYOUT STRUCTURE WITH OUTER BITLINE - An integrated circuit (IC) includes a memory cell having source/drain regions for defining source/drains of a first pull-up or pull-down (PU/PD) transistor for a first storage node, a second PU/PD transistor for a second storage node, and driver, cell pass, and buffer pass transistors. The memory cell includes a first gate electrode region for the first PU/PD and driver transistors, a second gate electrode region for the cell pass and buffer pass transistors, and a third gate electrode region for the second PU/PD transistor. The third gate electrode region and the cell pass transistor are coupled to the first storage node and the first gate electrode region is coupled to the second storage node. The buffer pass and driver transistors are coupled to a source/drain path of the cell pass transistor and the buffer pass transistor is coupled between a bitline (BL) node and the driver transistor. | 2009-07-09 |
| 20090173972 | SEMICONDUCTOR DEVICE - In a substrate power supply cell, a portion of a substrate power supply wiring is exposed by forming a power supply wiring in a U-shape, and a connection portion to an upper-layer wiring is provided at a boundary portion of the substrate power supply cell. Thereby, a leakage current is reduced without a decrease in signal wiring efficiency. | 2009-07-09 |
| 20090173973 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a semiconductor (e.g., a silicon substrate), an electrically conductive region (e.g., a source region and a drain region) which is in contact with the semiconductor to form a Schottky junction, and an insulator. The insulator is in contact with the semiconductor and the electrically conductive region, and has a fixed-charge containing region which contains a fixed charge and extends across a boundary between the semiconductor and the electrically conductive region. | 2009-07-09 |
| 20090173974 | TWO-BY-TWO PIXEL STRUCTURE IN AN IMAGING SYSTEM-ON-CHIP - The claimed subject matter provides systems and/or methods that facilitate mitigating an impact resulting from mismatch between signal chains in a CMOS imaging System-on-Chip (iSoC) sensor. Two-by-two pixel structures can be a basic building block upon which a pixel array is constructed. Further, each two-by-two pixel structure can be associated with a read bus that carries a sampled signal to a top end and a bottom end of a chip. Moreover, multiplexers at either end of the chip can select a subset of the read buses from which to receive a subset of the sampled signals. Accordingly, pixels in a first color plane can be read, processed, etc. on the same side of the chip (e.g., utilizing a common signal chain), while pixels in at least one second color plane can be read, processed, etc. on the other side of the chip (e.g., employing a differing signal chain). | 2009-07-09 |
| 20090173975 | WELL FOR CMOS IMAGER AND METHOD OF FORMATION - A well region of a first conductivity type located in a substrate of the first conductivity type and below about half the channel length of an electrically active portion of a transistor gate is disclosed. The well region is laterally displaced from a charge collection region of a second conductivity type of a pinned photodiode. | 2009-07-09 |
| 20090173976 | Light-Sensing Device for Multi-Spectral Imaging - A method of fabricating multi-spectral photo-sensors including photo-diodes incorporating stacked epitaxial superlattices monolithically integrated with CMOS devices on a common semiconductor substrate. | 2009-07-09 |
| 20090173977 | Method of MRAM fabrication with zero electrical shorting - An MTJ cell without footings and free from electrical short-circuits across a tunneling barrier layer is formed by using a Ta hard mask layer and a combination of etches. A first etch patterns the Ta hard mask, while a second etch uses O | 2009-07-09 |
| 20090173978 | SEMICONDUCTOR MEMORY CELL AND SEMICONDUCTOR MEMORY ARRAY USING THE SAME - A memory element including a first FET, and a selection switch including a second FET are connected in series, and a semiconductor film and a dielectric film stacked over a substrate form a common channel and a common gate insulating film in the first and second FETs. A first gate electrode of the first FET and a second gate electrode of the second FET are formed on the dielectric film, and a drain electrode and a source electrode are formed on the semiconductor film. Under the semiconductor film, a back-gate electrode is formed with a ferroelectric film interposed therebetween, and the ends of the semiconductor film that forms the channel are located inwardly of the ends of the back-gate electrode. | 2009-07-09 |
| 20090173979 | ALD OF AMORPHOUS LANTHANIDE DOPED TiOX FILMS - The use of atomic layer deposition (ALD) to form an amorphous dielectric layer of titanium oxide (TiO | 2009-07-09 |
| 20090173980 | PROVIDING ISOLATION FOR WORDLINE PASSING OVER DEEP TRENCH CAPACITOR - A memory cell has an access transistor and a capacitor with an electrode disposed within a deep trench. STI oxide covers at least a portion of the electrode, and a liner covers a remaining portion of the electrode. The liner may be a layer of nitride over a layer of oxide. Some of the STI may cover a portion of the liner. In a memory array a pass wordline may be isolated from the electrode by the STI oxide and the liner. | 2009-07-09 |
| 20090173981 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor storage device has a first laminated portion including first insulating layers and first conductive layers laminated alternately, and a second laminated portion provided on an upper surface of the first laminated portion and including a second conductive layer formed between second insulating layers. The first laminated portion has a first semiconductor layer formed so as to contact with a gate insulating film and extend in a laminated direction. The second laminated portion has a second semiconductor layer formed so as to contact with a third insulating layer and the first semiconductor layer and extend in the laminated direction. The first semiconductor layer is of a first conductive type, and a portion of the second semiconductor layer which contacts with the side surface of the second conductive layer is of a second conductive type. | 2009-07-09 |
| 20090173982 | METHOD FOR FORMING MEMORY CELL AND DEVICE - A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to selectively electrically couple the storage capacitor with the shared digitline. The digitline couples with adjacent memory cells and the plurality of access transistor selects which adjacent memory cell is coupled to the shared digitline. A method of forming the memory cell includes forming a buried digitline in the substrate and a vertical pillar in the substrate immediately adjacent to the buried digitline. A dual gate transistor is formed on the vertical pillar with a first end electrically coupled to the buried digitline and a second end coupled to a storage capacitor formed thereto. | 2009-07-09 |
| 20090173983 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device, comprising: a substrate; a floating body region formed in the substrate, a gate electrode formed above a first surface region of the floating body region via a gate insulating film, the gate electrode being connected to a word line; and source and drain regions, respectively, formed on second and third surface regions of the floating body region, the source region being connected to a source line and providing a first electric capacity at an interface relative to the floating body region, the drain region being connected to a bit line and providing a second electric capacity at an interface relative to the floating body region, the second electric capacity being smaller than the first electric capacity. | 2009-07-09 |
| 20090173984 | INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT - The present invention provides an integrated circuit with a floating body transistor comprising two source/drain regions and a floating body region arranged between the two source/drain regions comprising: a back gate electrode separated from the floating body by a first dielectric layer; a control gate electrode, separated from the floating body by a second dielectric layer and overlying the back gate electrode; and a third dielectric layer arranged between the back gate electrode and the control gate electrode. The present invention provides also a method of manufacturing an integrated circuit and a method of operating an integrated circuit. | 2009-07-09 |
| 20090173985 | Dense arrays and charge storage devices - There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing. | 2009-07-09 |
| 20090173986 | Semiconductor Devices Including Gate Structures and Leakage Barrier Oxides - Methods of forming a semiconductor device may include forming a tunnel oxide layer on a semiconductor substrate, forming a gate structure on the tunnel oxide layer, forming a leakage barrier oxide, and forming an insulating spacer. More particularly, the tunnel oxide layer may be between the gate structure and the substrate, and the gate structure may include a first gate electrode on the tunnel oxide layer, an inter-gate dielectric on the first gate electrode, and a second gate electrode on the inter-gate dielectric with the inter-gate dielectric between the first and second gate electrodes. The leakage barrier oxide may be formed on sidewalls of the second gate electrode. The insulating spacer may be formed on the leakage barrier oxide with the leakage barrier oxide between the insulating spacer and the sidewalls of the second gate electrode. In addition, the insulating spacer and the leakage barrier oxide may include different materials. Related structures are also discussed. | 2009-07-09 |
| 20090173987 | FLASH MEMORY DEVICE WITH ISOLATION STRUCTURE - A flash memory device includes trenches that are formed at regions on a semiconductor substrate spaced apart from one another at predetermined distances, buried floating gates buried into the trenches, a plurality of isolation structures formed between the buried floating gates, and a dielectric film and a control gate formed on the buried floating gates | 2009-07-09 |
| 20090173988 | FLASH MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A flash memory device includes control gates that are formed to completely surround the top and sides of floating gates. The control gates are located between the floating gates that are adjacent in the word line direction as well as the floating gates that are adjacent in the bit line direction. The present flash memory device reduces a shift in a threshold voltage resulting from interference among floating gates and increases an overlapping area of the floating gate and the control gates. Thus, there is an effect in that the coupling ratio can be increased. | 2009-07-09 |
| 20090173989 | NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory of an aspect of the present invention includes a memory cell including, a charge storage layer on a gate insulating film, a multilayer insulator on the charge storage layer, and a control gate electrode on the multilayer insulator, the gate insulating film including a first tunnel film, a first high-dielectric-constant film on the first tunnel film and offering a greater dielectric constant than the first tunnel film, and a second tunnel film on the first high-dielectric-constant film and having the same configuration as that of the first tunnel film, the multilayer insulator including a first insulating film, a second high-dielectric-constant film on the first insulating film and offering a greater dielectric constant than the first insulating film, and a second insulating film on the second high-dielectric-constant film and having the same configuration as that of the first insulating film. | 2009-07-09 |
| 20090173990 | STRUCTURES FOR AND METHOD OF SILICIDE FORMATION ON MEMORY ARRAY AND PERIPHERAL LOGIC DEVICES - A memory device and peripheral circuitry on a substrate are described, made by a process that includes forming a charge trapping structure having a first thickness over a first area. A first gate dielectric layer having a second thickness is formed for low-voltage transistors. A second gate dielectric layer having a third thickness, greater than the second thickness, is formed for high-voltage transistors. Polysilicon is deposited and patterned to define word lines and transistor gates. The thickness of the second gate dielectric layer in regions adjacent the gates, and over a source and drain regions, is reduced to a thickness that is close to that of the second thickness. | 2009-07-09 |
| 20090173991 | METHODS FOR FORMING RHODIUM-BASED CHARGE TRAPS AND APPARATUS INCLUDING RHODIUM-BASED CHARGE TRAPS - Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge traps in electronic structures for use in a wide range of electronic devices and systems. In an embodiment, conductive nanoparticles are deposited on a dielectric layer by a plasma-assisted deposition process such that each conductive nanoparticle is isolated from the other conductive nanoparticles to configure the conductive nanoparticles as charge traps. | 2009-07-09 |
| 20090173992 | SEMICONDUCTOR DEVICE WITH IMPROVED PERFORMANCE CHARACTERISTICS - The semiconductor device includes an active region, a recess, a Fin channel region, a gate insulating film, and a gate electrode. The active region is defined by a device isolation structure formed in a semiconductor substrate. The recess is formed by etching the active region and its neighboring device isolation structure using an island shaped recess gate mask as an etching mask. The Fin channel region is formed on the semiconductor substrate at a lower part of the recess. The gate insulating film is formed over the active region including the Fin channel region and the recess. The gate electrode is formed over the gate insulating film to fill up the Fin channel region and the recess. | 2009-07-09 |
| 20090173993 | Structure and Method of Forming a Topside Contact to a Backside Terminal of a Semiconductor Device - A vertically conducting semiconductor device includes a semiconductor substrate having a topside surface and a backside surface. The semiconductor substrate serves as a terminal of the vertically conducting device for biasing the vertically conducting device during operation. An epitaxial layer extends over the topside surface of the semiconductor substrate but terminates prior to reaching an edge of the semiconductor substrate so as to form a recessed region along a periphery of the semiconductor substrate. An interconnect layer extends into the recessed region but terminates prior to reaching an edge of the semiconductor substrate. The interconnect layer electrically contacts the topside surface of the semiconductor substrate in the recessed region to thereby provide a topside contact to the semiconductor substrate. | 2009-07-09 |
| 20090173994 | RECESS GATE TRANSISTOR - A recess gate of a semiconductor device is provided, comprising: a substrate having a recess formed therein; a metal layer formed at the bottom of the recess; a polysilicon layer formed over the metal layer; and a source region and a drain region formed adjacent to the polysilicon layer and spaced from the metal layer. A method of forming a semiconductor device is also provided, comprising forming a substrate and a source and drain layer; forming a recess and depositing a gate insulation layer therein; forming a first conductive layer on the gate insulation layer; forming a first conductive layer pattern by recessing the first conductive layer; forming a second conductive layer on the first conductive layer pattern; forming a second conductive layer pattern by patterning the second conductive layer to overlap the source and drain layer; depositing an insulating layer on the second conductive layer pattern and the source and drain layer; and planarizing the insulating layer to form a cap on the second conductive layer pattern. | 2009-07-09 |
| 20090173995 | TRENCH SEMICONDUCTOR DEVICE OF IMPROVED VOLTAGE STRENGTH, AND METHOD OF FABRICATION - A trench IGBT is disclosed which includes a semiconductor substrate having formed therein a set of cell trenches formed centrally and a set of annular guard trenches concentrically surrounding the cell trenches. The cell trenches receive cell trench conductors via cell trench insulators for providing IGBT cells. The guard trenches receive guard trench conductors via guard trench insulators for enabling the IGBT to withstand higher voltages through mitigation of field concentrations. Capacitive coupling conductors overlie the guard trench conductors via a dielectric layer, each for capacitively coupling together two neighboring ones of the guard trench conductors. The capacitive coupling conductors are easily adjustably variable in shape, size and placement relative to the guard trench conductors for causing the individual guard trench conductors to possess potentials for an optimal contour of the depletion layer. | 2009-07-09 |
| 20090173996 | Recess Gate Type Transistor - A semiconductor device having recess gates and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having inverse triangular recesses formed therein; a gate insulating film having a designated thickness formed on the semiconductor substrate; gate electrodes formed on the gate insulating film so that the gate electrodes fill the inverse triangular recesses and protrude from the surface of the semiconductor substrate; and first and second junction regions formed in the semiconductor substrate and opposed to each other so that the corresponding one of the gate electrodes is interposed therebetween. | 2009-07-09 |
| 20090173997 | MOSFET AND METHOD FOR MANUFACTURING MOSFET - The present invention provides a MOSFET and so forth that offer high breakdown voltage and low on-state loss (high channel mobility and low gate threshold voltage) and that can easily achieve normally OFF. A drift layer | 2009-07-09 |
| 20090173998 | Semiconductor device and manufacturing method thereof - In a MIS transistor of which gate length is 10 nm or less, a gate insulator comprising a silicon oxide film formed on a silicon substrate and a high-k film formed on the silicon oxide film has a nitrided region including more nitrogen at the lateral side than at the central side in the gate-length direction, and including more nitrogen at the upper side than at the lower side in the film thickness direction. The reliability and characteristics of a MIS transistor using a gate insulator including a high-k (high dielectric constant) film is enhanced. | 2009-07-09 |
| 20090173999 | FIELD EFFECT TRANSISTOR WITH GATE HAVING VARYING SHEET RESISTANCE - A field effect transistor (FET) comprising a gate structure that includes at least one gate having a varying sheet resistance in a direction between a source contact and a drain contact. In an illustrative embodiment, the FET can be configured to operate as a radio frequency switch. In this case, the FET can provide improved performance with respect to both the off-state capacitances and radio frequency isolations over similar FETs implemented with typical gates. | 2009-07-09 |
| 20090174000 | SEMICONDUCTOR DEVICE INCLUDING INSULATED-GATE FIELD-EFFECT TRANSISTOR - Fins of semiconductor are formed on the substrate. Each of the fins is located separately from one another. A gate insulating film is formed on side surfaces of the fins. A gate electrode is formed on the gate insulating film. The gate electrode extends to cross over the fins. A gate contact portion is provided to supply an electric signal. In the fins, first drain regions and first source regions are formed respectively so as to sandwich portions of the fins located below the gate electrode. A width of first one of the fins is larger than that of second one of the fins which is more distant from the gate contact portion than the first one of the fins. | 2009-07-09 |
| 20090174001 | SEMICONDUCTOR DEVICE HAVING FIN TRANSISTOR AND PLANAR TRANSISTOR AND ASSOCIATED METHODS OF MANUFACTURE - Disclosed is a fin transistor and a planar transistor and a method of forming the same. The fin transistor and the planar transistor are formed to have gate electrodes with similar thicknesses by selectively recessing a semiconductor substrate in a planar region where the planar transistor is formed. | 2009-07-09 |
| 20090174002 | MOSFET HAVING A HIGH STRESS IN THE CHANNEL REGION - Source and drain extension regions are selectively removed by a dopant concentration dependent etch or a doping type dependent etch, and an embedded stress-generating material such as SiGe alloy or a Si:C alloy in the source and drain extension regions is grown on a semiconductor substrate. The embedded stress-generating material may be grown only in the source and drain extension regions, or in the source and drain extension regions and in deep source and drain regions. In one embodiment, an etch process that removes doped semiconductor regions of one conductivity type selective to doped semiconductor regions of another conductivity type may be employed. In another embodiment, a dopant concentration dependent etch process that removes doped semiconductor regions irrespective of the conductivity type selective to undoped semiconductor regions may be employed. | 2009-07-09 |
| 20090174003 | DUAL WORK FUNCTION DEVICE WITH STRESSOR LAYER AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a dual work function semiconductor device is disclosed. In one aspect, the method relates to providing a substrate with a first and a second region. A gate dielectric is formed overlying the first and the second region. A metal gate layer is formed overlying the gate dielectric on the first and the second region. The metal gate layer has a first (as-deposited) work function that can be modified upon inducing strain thereon. The method further relates to selecting a first strain which induces a first pre-determined work function shift (ΔWF1) in the first (as-deposited) work function of the metal gate layer on the first region and selectively forming a first strained conductive layer overlying the metal gate layer on the first region, the first strained conductive layer exerting the selected first strain on the metal gate layer. | 2009-07-09 |
| 20090174004 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device including a semiconductor substrate having first and second device regions. A first trench is formed in the first region and a second trench is formed in the second region. The first trench and the second trench have different widths and different depths. The first trench and the second trench define device isolation regions and active regions. | 2009-07-09 |
| 20090174005 | SEMICONDUCTOR DEVICE WITH GATE-UNDERCUTTING RECESSED REGION - A semiconductor device comprises a gate structure on a semiconductor substrate and a recessed region in the semiconductor substrate. The recessed region has a widest lateral opening that is near a top surface of the semiconductor substrate. The widest lateral opening undercuts the gate structure. | 2009-07-09 |
| 20090174006 | STRUCTURE AND METHOD OF CREATING ENTIRELY SELF-ALIGNED METALLIC CONTACTS - The semiconductor structure is provided that has entirely self-aligned metallic contacts. The semiconductor structure includes at least one field effect transistor located on a surface of a semiconductor substrate. The at least one field effect transistor includes a gate conductor stack comprising a lower layer of polysilicon and an upper layer of a first metal semiconductor alloy, the gate conductor stack having sidewalls that include at least one spacer. The structure further includes a second metal semiconductor alloy layer located within the semiconductor substrate at a footprint of the at least one spacer. The structure also includes a first metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re located on, and self-aligned to the first metal semiconductor alloy layer and a second metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re located on, and self-aligned to the second metal semiconductor alloy layer. | 2009-07-09 |
| 20090174007 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprising: a support substrate; an insulating film formed on the support substrate; a semiconductor film formed on the insulating film; a gate insulating film formed on the semiconductor film; a gate electrode film formed on the gate insulating film; and a source region and a drain region formed in the semiconductor film so as to sandwich the gate insulating film in a gate length direction, the source and drain regions contacting the insulating film at the bottom surface, and the semiconductor memory device storing data corresponding to the amount of charges accumulated in the semiconductor film surrounded by the insulating film, the gate insulating film, and the source and drain regions and electrically floated, wherein a border length between the source region and the gate insulating film contiguous to each other is different from a border length between the drain region and the gate insulating film to each other. | 2009-07-09 |
| 20090174008 | METHOD AND STRUCTURE TO PROTECT FETs FROM PLASMA DAMAGE DURING FEOL PROCESSING - Protecting a FET from plasma damage during FEOL processing by forming a FET-like structure in conjunction with and adjacent to an FET, in a same well as the FET, but having a body doped opposite to the well polarity. The FET-like structure is formed with thinner oxide than the gate oxide of the FET, has a gate structure (poly) connected with the gate of the FET, and may be shorted out by the first metal layer (M | 2009-07-09 |
| 20090174009 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - The semiconductor device includes the concentration of the impurity of the first conductivity type in a doped channel layer of a first conductivity type in the pass transistor is set at a relatively low value, and pocket regions of the first conductivity type in a pass transistor are formed so as to be relatively shallow with a relatively high impurity concentration. | 2009-07-09 |
| 20090174010 | SRAM DEVICE STRUCTURE INCLUDING SAME BAND GAP TRANSISTORS HAVING GATE STACKS WITH HIGH-K DIELECTRICS AND SAME WORK FUNCTION - An SRAM semiconductor device includes: at least a first and a second field effect transistor formed on a same substrate, each of the transistors including a gate stack, each gate stack including a semiconductor layer disposed on a metal layer, the metal layer being disposed on a high-k dielectric layer located over a chemical region, wherein the metal layer of the first gate stack and the metal layer of the second gate stack have approximately a same work function, and wherein each channel region has approximately a same band gap. | 2009-07-09 |
| 20090174011 | Semiconductor device having guard ring - A semiconductor device includes an internal circuit region on a semiconductor substrate, at least one guard ring on the semiconductor substrate, the guard ring surrounding the internal circuit region, and at least one current blocking unit on the semiconductor substrate, the current blocking unit being configured to block an electric current flowing from the guard ring to the semiconductor substrate. | 2009-07-09 |
| 20090174012 | Field Effect Transistor - Provided is a field effect transistor, provided with a gate electrode | 2009-07-09 |
| 20090174013 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a silicon substrate, an SiO film, and a High-K film. The SiO film is first formed on the silicon substrate and then subjected to a nitridation process to obtain an SiON film from the SiO film. The nitridation process is performed such that nitrogen concentration in the SiO film decreases from an interface with the silicon substrate below and an interface with the High-K film above, and nitrogen having predetermined concentration or more is introduced in a thickness within a range of 0.2 nm to 1 nm from the interface with the silicon substrate. The SiON film is etched up to a depth to which nitrogen of the predetermined concentration or more is introduced. The High-K film is then formed on the SiON film. | 2009-07-09 |
| 20090174014 | Micromechanical Actuators Comprising Semiconductors on a Group III Nitride Basis - A semiconductor actuator includes a substrate base, a bending structure which is connected to the substrate base and can be deflected at least partially relative to the substrate base. The bending structure has semiconductor compounds on the basis of nitrides of main group III elements and at least two electrical supply contacts which impress an electrical current in or for applying an electrical voltage to the bending structure. At least two of the supply contacts are disposed at a spacing from each other respectively on the bending structure and/or integrated in the latter. | 2009-07-09 |
| 20090174015 | Memory Cell and Method of Forming a Magnetic Tunnel Junction (MTJ) of a Memory Cell - A memory including a memory cell and method for producing the memory cell are disclosed. The memory includes a substrate in a first plane. A first metal connection extending in a second plane is provided. The second plane is substantially perpendicular to the first plane. A magnetic tunnel junction (MTJ) is provided having a first layer coupled to the metal connection such that the first layer of the MTJ is oriented along the second plane. | 2009-07-09 |
| 20090174016 | MAGNETIC MEMORY DEVICE - A magnetic memory device is provided in which, even when a recording layer having an asymmetric shape and a local via are formed over a strap wiring with a sufficient distance allowed therebetween, increase in the size of the magnetic memory device can be suppressed. The magnetic memory device includes the strap wiring, the local via, and a magnetic recording element (TMR element). The TMR element includes a fixed layer and the recording layer. The planar shape of the recording layer is asymmetric with respect to the direction of the easy magnetization axis of the recording layer and is symmetric with respect to the axis of symmetry perpendicular to the easy magnetization axis. The contoured portion of the recording layer on the side closer to the center of area of the recording layer is opposed to the local via formation side. | 2009-07-09 |
| 20090174017 | SOLID-STATE IMAGE SENSOR AND METHOD FOR MANUFACTURING THEREOF AS WELL AS SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF - A solid-state image sensor and a method for manufacturing thereof and a semiconductor device and a method for manufacturing thereof are provided. A semiconductor substrate is made to be the thin film without using an SOI substrate and cost is reduced. An edge detection portion having hardness larger than that of a semiconductor substrate is formed in the thickness direction of the semiconductor substrate; the semiconductor substrate is made to be the thin film until a position where the edge detection portion is exposed by chemical mechanical polishing from the rear surface; and means Tr | 2009-07-09 |
| 20090174018 | CONSTRUCTION METHODS FOR BACKSIDE ILLUMINATED IMAGE SENSORS - A method of constructing a backside illuminated image sensor is described. The method includes the steps of forming a semiconductor wafer, forming at least electrical contacts in the semiconductor wafer, forming, in a handle wafer separate from the semiconductor wafer, a plurality of via holes, attaching the semiconductor wafer to the handle wafer such that the via holes in the handle wafer are aligned with the respective electrical contacts on the semiconductor wafer, removing the substrate layer from the semiconductor wafer, removing at least a portion of the handle wafer to expose the plurality of via holes, filling each of the exposed via holes with a conductive material and applying a solder material to each of the exposed via holes such that the conductive material in each of the via holes is electrically connected to the solder material. | 2009-07-09 |
| 20090174019 | IMAGE SENSING DEVICE AND MANUFACTURE METHOD THEREOF - An image sensing device for receiving an incident light having an incident angle and photo signals formed thereby is provided. The image sensing device includes a micro prism and a micro lens for adjusting the incident angle and converging the incident light, respectively, a photo sensor for converting the photo signals into electronic signals, and an IC stacking layer for processing the electronic signals. | 2009-07-09 |
| 20090174020 | SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A solid state imaging device includes a substrate having a plurality of pixels and a plurality of on-chip lenses arranged above the substrate, each on-chip lens having a lens surface formed by subjecting a transparent photosensitive film to exposure using a mask having a gradation pattern and development so that the lens surface serves to correct shading in accordance with the gradation pattern. | 2009-07-09 |
| 20090174021 | PHOTODIODE FOR MULTIPLE WAVELENGTH OPERATION - A photodiode includes a substrate having a first semiconductor type surface region on at least a portion thereof, and a second semiconductor type surface layer formed in a portion of the surface region. A multi-layer anti-reflective coating (ARC) is on the second semiconductor type surface layer, wherein the multi-layer ARC comprises at least two different dielectric layers. A layer resistant to oxide etch is above a peripheral portion the multi-layer ARC. Further layers are above the layer resistant to oxide etch, and thereby above the peripheral portion the multi-layer ARC. A window extends down to the multi-layer ARC. A photodiode region is formed by a pn-junction of the first semiconductor type surface region and the second semiconductor type surface layer. | 2009-07-09 |
| 20090174022 | Hyperspectral imaging device - An hyperspectral imaging device comprising semiconductor nanocrystals is provided. | 2009-07-09 |
| 20090174023 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor element is formed on a first surface of the substrate. A resin layer is formed over a second surface of the substrate which is opposite to the first surface of the substrate and on a part of the side surface of the substrate. A step is formed on the side surface of the substrate. The width of the upper section of the substrate with a step is narrower than the lower section of the substrate with a step. Therefore, the substrate can also be a protrusion. | 2009-07-09 |
| 20090174024 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - Embodiments relate to an image sensor and a method of manufacturing the same. According to embodiments, an image sensor may include a first substrate having circuitry formed thereon. It may further include a photodiode bonded to the first substrate and electrically connected to the circuitry, and a contact plug at a pixel border that may be electrically connected with the circuitry and the photodiode. According to embodiments, the photodiode may include a first conductive type ion implantation region selectively provided in a crystalline semiconductor layer, and a second conductive type ion implantation region in contact with one side surface of the first conductive type ion implantation region. | 2009-07-09 |
| 20090174025 | Image Sensor and Method for Manufacturing the Same - An image sensor can include a first substrate, an insulating layer, a photodiode, and a via plug. A circuitry including an interconnection can be formed on the first substrate. The insulating layer is formed over the first substrate so that the insulating layer covers the interconnection. The photodiode is formed in a crystalline semiconductor layer and then bonded to the first substrate while contacting the insulating layer. The via plug is provided by removing portions of the photodiode and the insulating layer to expose an upper portion of the interconnection to form a via hole, and filling the via hole with a conductive metal. The via plug electrically connects the photodiode to the interconnection. | 2009-07-09 |
| 20090174026 | SILICON-BASED VISIBLE AND NEAR-INFRARED OPTOELECTRIC DEVICES - In one aspect, the present invention provides a silicon photodetector having a surface layer that is doped with sulfur inclusions with an average concentration in a range of about 0.5 atom percent to about 1.5 atom percent. The surface layer forms a diode junction with an underlying portion of the substrate. A plurality of electrical contacts allow application of a reverse bias voltage to the junction in order to facilitate generation of an electrical signal, e.g., a photocurrent, in response to irradiation of the surface layer. The photodetector exhibits a responsivity greater than about 1 A/W for incident wavelengths in a range of about 250 nm to about 1050 nm, and a responsivity greater than about 0.1 A/W for longer wavelengths, e.g., up to about 3.5 microns. | 2009-07-09 |
| 20090174027 | INTEGRATED CIRCUIT INCLUDING ISOLATION REGIONS SUBSTANTIALLY THROUGH SUBSTRATE - An integrated circuit including a substrate and trench isolation regions. The substrate supports a device. The trench isolation regions are configured to laterally isolate the device. The trench isolation regions extend substantially through the substrate. | 2009-07-09 |
| 20090174028 | Fuse in a Semiconductor Device and Method for Forming the Same - A fuse of a semiconductor device, and a method for forming the same, wherein the fuse includes a zigzag-shaped fuse portion on a planar structure, thereby reducing energy when the fuse is cut. The laser irradiation time can be reduced, thereby preventing fuse cutting defects and damages on a neighboring fuse. Also, a laser point where a laser is irradiated is not affected by misalignment, thereby improving characteristics of the fuse. | 2009-07-09 |
| 20090174029 | Semiconductor device and method of fabricating the same - A semiconductor device is provided including a first fuse link having a copper-containing metal film, a second fuse link having a polysilicon film, a semiconductor substrate, and a field insulating film formed on the semiconductor substrate. The second fuse link is formed on the field insulating film. An interlayer insulating film is provided between the first fuse link and the second fuse link. The first fuse link is electrically connected to the second fuse link via a first plug formed in the interlayer insulating film. | 2009-07-09 |
| 20090174030 | LINEARITY CAPACITOR STRUCTURE AND METHOD | 2009-07-09 |
| 20090174031 | DRAM HAVING DEEP TRENCH CAPACITORS WITH LIGHTLY DOPED BURIED PLATES - By controlling buried plate doping level and bias condition, different capacitances can be obtained from capacitors on the same chip with the same layout and deep trench process. The capacitors may be storage capacitors of DRAM/eDRAM cells. The doping concentration may be less than 3E19cm−3, a voltage difference between the biases of the buried electrodes may be at least 0.5V, and a capacitance of one capacitor may be at least 1.2 times, such as 2.0 times the capacitance of another capacitor. | 2009-07-09 |
| 20090174032 | RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device includes: a semiconductor substrate; a three dimensional cell array formed by a plurality of unit cell array blocks of two dimensional arrangement on the semiconductor substrate, the unit cell array block being formed by stacking a plurality of unit cell arrays including a first wiring, a second wiring crossing with the first wiring, and a variable resistance element connected at an intersection of the both wirings; a reading/writing/driving circuit formed on the semiconductor substrate under the three dimensional cell array; a first via region which is arranged in an end portion of the unit cell array block, and in which a via wiring for connecting the first wiring in each layer to the reading/writing/driving circuit is formed; and a second via region which is arranged in an end portion of the unit cell array block, and in which a via wiring for connecting the second wiring in each layer to the reading/writing/driving circuit is formed. When the first wiring is longer than the second wiring, the number of via arrangements in the first via region is set larger than that in the second via region. | 2009-07-09 |
| 20090174033 | ADJUSTIBLE RESISTOR FOR USE IN A RESISTIVE DIVIDER CIRCUIT AND METHOD FOR MANUFACTURING - A method of manufacturing a resistive divider circuit, comprising providing a silicon body ( | 2009-07-09 |
| 20090174034 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SUCH A DEVICE - The invention relates to a semiconductor device ( | 2009-07-09 |
| 20090174035 | Semiconductor Device - A semiconductor device includes a semiconductor substrate formed of at least two kinds of group III elements and nitrogen, an active layer formed on the semiconductor substrate, and a nitride semiconductor layer formed on a surface of the semiconductor substrate and formed between the semiconductor substrate and the active layer. The nitride semiconductor layer is formed of the same constituent elements of the semiconductor substrate. A composition ratio of the lightest element among the group III elements of the nitride semiconductor layer is higher than a composition ratio of the corresponding element of the semiconductor substrate. | 2009-07-09 |
| 20090174036 | PLASMA CURING OF PATTERNING MATERIALS FOR AGGRESSIVELY SCALED FEATURES - A methodology is disclosed that enables the fabrication of semiconductor devices (i.e., STI structures, gates, and interconnects) with significantly reduced line edge roughness (LER) and line width roughness (LEW) post lithography patterning. The inventive methodology entails the use of an inert species containing plasma tuned to enhanced its' vacuum ultra violet (VUV) emissions post lithography and/or post one of the etch processes of a given feature (on an identical etch platform) to entice increased crosslinking of one or more patterning materials, thus enabling increased etch resistance and reduced LER and LEW post etching processing. | 2009-07-09 |
| 20090174037 | SEMICONDUCTOR SUBSTRATE, METHOD OF FABRICATING THE SAME, METHOD OF FABRICATING SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATING IMAGE SENSOR - In an example embodiment, an image sensor includes a semiconductor layer and isolation regions disposed in the semiconductor layer. The isolation regions define active regions of the semiconductor layer. The image sensor further includes photoelectric converters disposed in the semiconductor layer and at least one wiring layer disposed over a top surface of the semiconductor layer. The image sensor also includes color filters disposed below a bottom surface of the semiconductor layer and lenses disposed below the color filters. Each lens is arranged to concentrate incoming light into an area spanned by a corresponding photoelectric converter. | 2009-07-09 |
| 20090174038 | PRODUCTION OF SINGLE-CRYSTAL SEMICONDUCTOR MATERIAL USING A NANOSTRUCTURE TEMPLATE - A method of producing single-crystal semiconductor material comprises: providing a template material; creating a mask on top of the template material; using the mask to form a plurality of nanostructures in the template material; and growing the single-crystal semiconductor material onto the nanostructures. | 2009-07-09 |
| 20090174039 | Semiconductor device and method of forming the same - A semiconductor device and a method of forming the same are provided. A semiconductor device may comprise a semiconductor substrate including a main surface configured to define a groove, a trench, and a cavity sequentially disposed downward from a given region of the main surface and open toward the main surface. | 2009-07-09 |
| 20090174040 | SACRIFICIAL PILLAR DIELECTRIC PLATFORM - Briefly, in accordance with one or more embodiments, a dielectric platform is at least partially formed in a semiconductor substrate and extending at least partially below a surface of a semiconductor substrate. The dielectric platform may include structural pillars formed by backfilling a first plurality of cavities etched in the substrate, and a second plurality of cavities formed by etching away sacrificial pillars disposed between the structural pillars. The second plurality of cavities may be capped to hermetically seal the second plurality of cavities to impart the dielectric constant of the material contained therein, for example air, to the characteristic dielectric constant of the dielectric platform. Alternatively, the second plurality of cavities may be backfilled with a material having a lower dielectric constant than the substrate, for example silicon dioxide where the substrate comprises silicon. | 2009-07-09 |
| 20090174041 | ULTRAVIOLET BLOCKING STRUCTURE AND METHOD FOR SEMICONDUCTOR DEVICE - Structures and methods for blocking ultraviolet rays during a film depositing process for semiconductor device are disclosed. In one embodiment, a semiconductor device includes an oxide-nitride-oxide (ONO) film formed on a semiconductor substrate, a gate electrode formed on the ONO film, a lower layer insulation film formed on the ONO film and the gate electrode, and a ultraviolet (UV) blocking layer based on a plurality of granular particles scattered in at least one insulation film formed on lower layer insulation film, where the UV blocking layer suppresses UV rays generated during an additional film deposition from reaching the ONO film. | 2009-07-09 |
| 20090174042 | RADIO FREQUENCY OVER-MOLDED LEADFRAME PACKAGE - An over-molded leadframe (e.g., a Quad Flat No-lead (QFN)) package capable of operating at frequencies in the range of about five gigahertz (GHz) to about 300 GHz and a method of making the over-molded leadframe package are disclosed. The over-molded leadframe package includes a capacitance lead configured to substantially reduce and/or offset the inductance created by one or more wirebonds used to connect an integrated circuit (IC) chip on the package to an input/output (I/O) lead. The IC chip is connected to the capacitance lead via one or more wirebonds, and the capacitance lead is then connected to the I/O lead via at least a second wirebond. Thus, inductance created by the one or more wirebonds on the package is substantially reduced and/or offset by the capacitance lead prior to a signal being output by the package and/or received by the IC chip. | 2009-07-09 |
| 20090174043 | Flexible contactless wire bonding structure and methodology for semiconductor device - A semiconductor device such as a field-effect transistor, improved to reduce device resistance, comprises a leadframe which includes a die paddle integral with a first set of leads and a second set of leads that is electrically isolated from the first set, a semiconductor die having its lower surface positioned on, and electrically connected to, the die paddle, and a conductive layer on the upper surface of the die. At least one electrically conductive wire, preferably plural wires, extend laterally across the second surface of the semiconductor die, are in electrical contact with the conductive layer, and interconnect corresponding second leads on opposite sides of the die. The plural wires may be welded to leads in succession by alternate ball and wedge bonds on each lead. The conductive layer may be an aluminized layer on which is formed a thin layer a solderable material, such as tin. A solder is deposited on the tin layer, enmeshing the wires. The wires, which preferably are made of copper, then may be bonded to the electrically conductive layer by melting the solder paste, preferably by heating the leadframe, allowing the solder to reflow and wet the wires, and then cool to produce a low resistance mass between the leads. | 2009-07-09 |
| 20090174044 | Multi-chip package - A semiconductor package is disclosed. Particularly, a multi-chip package is disclosed, which can stably maintain insulation between a plurality of semiconductor chips and effectively release heat to the outside. The semiconductor package includes an insulation layer including a diamond layer formed by a chemical vapor deposition method between a lead frame or a heat sink and the semiconductor chips disposed thereon. | 2009-07-09 |
| 20090174045 | Bump Pad Metallurgy Employing An Electrolytic Cu / Electorlytic Ni / Electrolytic Cu Stack - An electroless Cu layer is formed on each side of a packaging substrate containing a core, at least one front metal interconnect layer, and at least one backside metal interconnect layer. A photoresist is applied on both electroless Cu layers and lithographically patterned. First electrolytic Cu portions are formed on exposed surfaces of the electroless Cu layers, followed by formation of electrolytic Ni portions and second electrolytic Cu portions. The electrolytic Ni portions provide enhanced resistance to electromigration, while the second electrolytic Cu portions provide an adhesion layer for a solder mask and serves as an oxidation protection layer. Some of the first electrolytic Cu may be masked by lithographic means to block formation of electrolytic Ni portions and second electrolytic Cu portions thereupon as needed. Optionally, the electrolytic Ni portions may be formed directly on electroless Cu layers. | 2009-07-09 |
| 20090174046 | SEMICONDUCTOR PACKAGE WITH AN EMBEDDED PRINTED CIRCUIT BOARD AND STACKED DIE - A two tier power module has, in one form thereof, a PC board having upper and lower traces with an opening in the insulating material that contains a power device which has upward extending solder bump connections. An upper leadframe is mounted on the solder bumps and the upper tracks of the PC board. Vias in the PC board connect selected upper and lower traces. A control device is mounted atop the leadframe and wire bonded to the leadframe, and the assembly is encapsulated leaving exposed the bottom surfaces of the lower traces of the PC board as external connections. In another form the PC board is replaced by a planar leadframe and the upper leadframe has stepped sections which make connections with the planar leadframe, the bottom surfaces of the planar leadframe forming external connections of the module. | 2009-07-09 |
| 20090174047 | Semiconductor Die Packages Having Overlapping Dice, System Using the Same, and Methods of Making the Same - Disclosed are semiconductor die packages having overlapping dice, systems that use such packages, and methods of making such packages. An exemplary die package comprises a leadframe, a first semiconductor die, and a second semiconductor die that has a recessed portion in one of its surfaces. The first die is disposed over a first portion of the leadframe, and the second die is disposed over a second portion of the leadframe with its recess portion overlying at least a portion of the first die. Another exemplary die package comprises a leadframe with a recessed area, a first semiconductor die disposed in the recessed area, and a second semiconductor die overlying at least a portion of the first die. Preferably, electrically conductive regions of both dice are electrically coupled to a conductive region of the leadframe to provide an interconnection between dice that has very low parasitic capacitance and inductance. | 2009-07-09 |
| 20090174048 | DIE PACKAGE INCLUDING SUBSTRATE WITH MOLDED DEVICE - A package is disclosed. The package includes a premolded substrate having a leadframe structure, a first device attached to the leadframe structure, and a molding material covering at least part of the leadframe structure and the first device. It also includes a second device attached to the premolded substrate. | 2009-07-09 |
| 20090174049 | ULTRA THIN IMAGE SENSOR PACKAGE STRUCTURE AND METHOD FOR FABRICATION - An image sensor package having at least one chip supporting bar secured to a top surface of an image sensor chip. The thickness of the chip supporting bar is absorbed within a vertical dimension of wire loops that connect bonding pads to leads so that the chip supporting bar does not contribute to the thickness of the image sensor package. An exposed back surface of the image sensor chip enhances thermal dissipation. | 2009-07-09 |
| 20090174050 | IN-PLANE SILICON HEAT SPREADER AND METHOD THEREFOR - A method of (and heat spreader for) dissipating heat from a heat source, includes providing a plurality of heat flux paths from the heat source, to remove the heat from the heat source. | 2009-07-09 |
| 20090174051 | Semiconductor package and semiconductor device - A package structure which aims at improvement in function, miniaturization, and systematization of a semiconductor integrated circuit having been made into multichip is offered. | 2009-07-09 |
| 20090174052 | ELECTRONIC COMPONENT, SEMICONDUCTOR PACKAGE, AND ELECTRONIC DEVICE - In a conventional UBM made of, for example, Cu, Ni, or NiP, there has been a problem that when an electronic component is held in high-temperature conditions for an extended period, the barrier characteristic of the UBM is lost and the bonding strength decreases due to formation of a brittle alloy layer at a bonding interface. The present invention improves the problem of decrease in long-term connection reliability of a solder connection portion after storage at high temperatures. An electronic component comprises the electronic component includes an electrode pad formed on a substrate or a semiconductor element and a barrier metal layer formed to cover the electrode pad and the barrier metal layer comprises a CuNi alloy layer on the side opposite the side in contact with the electrode pad, the CuNi alloy layer containing 15 to 60 at % of Cu and 40 to 85 at % of Ni. | 2009-07-09 |
| 20090174053 | Substrate for semiconductor device, resin-sealed semiconductor device, method for manufacturing said substrate for semiconductor device and method for manufacturing said resin-sealed semiconductor device - A substrate | 2009-07-09 |
| 20090174054 | Module with Flat Construction and Method for Placing Components - A module for electrical components is proposed in which connection surfaces that can be bonded are provided on a multi-layer substrate with integrated wiring; a component chip is bonded on the top that has bond pads on its surface pointing upward and that contacts the substrate by means of bonding wires. Here, the wire guide of the bonding wires is so that they are each bonded with a ball on a connection surface and with the wedge directly on one of the bond pads. | 2009-07-09 |
| 20090174055 | Leadless Semiconductor Packages - An encapsulation technique for leadless semiconductor packages entails: (a) attaching a plurality of dice ( | 2009-07-09 |
| 20090174056 | SEMICONDUCTOR MODULE - A semiconductor module is disclosed. One embodiment provides a first semiconductor chip having a first contact pad on a first main surface and a second contact pad on a second main surface, a first electrically conductive layer applied to the first main surface, a second electrically conductive layer applied to the second main surface, and an electrically insulating material covering the first electrically conductive layer, wherein a surface of the second electrically conductive layer forms an external contact pad and the second electrically conductive layer has a thickness of less than 200 μm. | 2009-07-09 |
| 20090174057 | SEMICONDUCTOR DEVICE AND PROGRAMMING METHOD - The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion. | 2009-07-09 |
