| 27th week of 2011 patent applcation highlights part 37 |
| Patent application number | Title | Published |
|---|
| 20110165729 | METHOD OF PACKAGING SEMICONDUCTOR DEVICE - Quad Flat No-Lead packaged devices are manufactured using two singulation operations with two different saw blades of varying widths with the first singulation operation using a wider saw blade than the second singulation operation. Between singulation operations, the exposed portions of the leads are plated with a solderable metal. By performing the second singulation operation within the first cut made by the first singulation, at least half of the exposed metal of the leads remains plated. Thus, better solder joints may be formed, which allows for simpler visual inspection. | 2011-07-07 |
| 20110165730 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method of stacking semiconductor chips in layers over a semiconductor substrate having, close to its main surface, semiconductor chips, connecting semiconductor chips in different layers to enable signal transmission, and singularizing the layered semiconductor chips into pieces. The method includes steps of forming an insulating layer on the main surface of the semiconductor substrate; stacking the semiconductor chips over the semiconductor chips of the semiconductor substrate in such a manner as to interpose the insulating layer between them and an opposite surface of each disposed semiconductor chip opposes the insulating layer, the opposite surface being opposite to the main surface; forming, in each of the disposed semiconductor chips, a via hole penetrating from the main to the opposite surface; and forming a connection which enables signal transmission between the disposed semiconductor chips and the corresponding semiconductor chips of the semiconductor substrate via the via holes. | 2011-07-07 |
| 20110165731 | Method for Fabricating Array-Molded Package-on-Package - An improved semiconductor device package is manufactured by attaching semiconductor chips ( | 2011-07-07 |
| 20110165732 | Semiconductor Package Having Buss-Less Substrate - A ball grid array device with an insulating substrate ( | 2011-07-07 |
| 20110165733 | MICROELECTRONIC PACKAGES AND METHODS THEREFOR - A method of making a microelectronic assembly can include molding a dielectric material around at least two conductive elements which project above a height of a substrate having a microelectronic element mounted thereon, so that remote surfaces of the conductive elements remain accessible and exposed within openings extending from an exterior surface of the molded dielectric material. The remote surfaces can be disposed at heights from said surface of said substrate which are lower or higher than a height of the exterior surface of the molded dielectric material from the substrate surface. The conductive elements can be arranged to simultaneously carry first and second different electric potentials: e.g., power, ground or signal potentials. | 2011-07-07 |
| 20110165734 | MANUFACTURING METHOD OF SEMI-CONDUCTOR CHIP PACKAGE - A manufacturing method of a semiconductor chip package includes molding a semiconductor chip and a number of passive devices after arranging on a film the semiconductor chip and the passive devices located in a vacant space around the periphery of the semiconductor chip; removing the film, forming an adhesive layer in a film-removed area, and attaching a conductive layer to the adhesive layer; etching a conductive layer to thereby form a conductive circuit pattern; and providing one or more conductive pads, which electrically connect the conductive circuit pattern to the semiconductor chip and to the passive devices. | 2011-07-07 |
| 20110165735 | Flexible Interposer for Stacking Semiconductor Chips and Connecting Same to Substrate - A semiconductor device with a first ( | 2011-07-07 |
| 20110165736 | Mounting structures for integrated circuit modules - A structure of an integrated circuit module includes a wiring board, a plurality of integrated circuits and at least one terminating resistance circuit. The wiring board has a mounting region on at least one surface thereof. The plurality of integrated circuits are mounted in the mounting region of the wiring board and spaced from one another in a first direction. The at least one terminating resistance circuit is arranged between at least two adjacent integrated circuits, and coupled to an output of a last of the plurality of integrated circuits. | 2011-07-07 |
| 20110165737 | Method for designing semiconductor integrated circuit which includes metallic wiring connected to gate electrode and satisfies antenna criterion - A method of forming a semiconductor integrated circuit, includes providing a first logic cell, a second logic cell and a metallic wiring connected to the first logic cell and a gate electrode of the second logic cell, and providing a third logic cell including a gate electrode connected to the metallic wiring, such that the third logic cell makes no contribution to a logic operation of the semiconductor integrated circuit, in order that an antenna ratio of the first gate electrode to the metallic wiring does not satisfy an antenna criterion, and an antenna ratio of the first gate electrode and the second gate electrode to the metallic wiring satisfies the antenna criterion. | 2011-07-07 |
| 20110165738 | Field effect transistor and method for manufacturing the same - A method for manufacturing a field effect transistor, includes: forming a mask of an insulating film on a semiconductor layer containing Si formed on a semiconductor substrate; forming the semiconductor layer into a mesa structure by performing etching with the use of the mask, the mesa structure extending in a direction parallel to an upper face of the semiconductor substrate; narrowing a distance between two sidewalls of the mesa structure and flattening the sidewalls by performing a heat treatment in a hydrogen atmosphere, the two sidewalls extending in the direction and facing each other; forming a gate insulating film covering the mesa structure having the sidewalls flattened; forming a gate electrode covering the gate insulating film; and forming source and drain regions at portions of the mesa structure, the portions being located on two sides of the gate electrode. | 2011-07-07 |
| 20110165739 | ULTRA-THIN SOI CMOS WITH RAISED EPITAXIAL SOURCE AND DRAIN AND EMBEDDED SIGE PFET EXTENSION - A method for improving channel carrier mobility in ultra-thin Silicon-on-oxide (UTSOI) FET devices by integrating an embedded pFET SiGe extension with raised source/drain regions. The method includes selectively growing embedded SiGe (eSiGe) extensions in pFET regions and forming strain-free raised Si or SiGe source/drain (RSD) regions on CMOS. The eSiGe extension regions enhance hole mobility in the pFET channels and reduce resistance in the pFET extensions. The strain-free raised source/drain regions reduce contact resistance in both UTSOI pFETs and nFETs. | 2011-07-07 |
| 20110165740 | Semiconductor Device and Method For Manufacturing Semiconductor Device - An object is to provide a semiconductor device including a microcrystalline semiconductor film with favorable quality and a method for manufacturing the semiconductor device. In a thin film transistor formed using a microcrystalline semiconductor film, yttria-stabilized zirconia having a fluorite structure is formed in the uppermost layer of a gate insulating film in order to improve quality of a microcrystalline semiconductor film to be formed in the initial stage of deposition. The microcrystalline semiconductor film is deposited on the yttria-stabilized zirconia, so that the microcrystalline semiconductor film around an interface with a base particularly has favorable crystallinity while by crystallinity of the base. | 2011-07-07 |
| 20110165741 | DISPLAY DEVICE, METHOD FOR MANUFACTURING THEREOF, AND TELEVISION DEVICE - The invention provides a display device and a method for manufacturing thereof by increasing a material efficiently as well as simplifying steps. Also, the invention provides a technique for forming a pattern such as a wiring, that is used for forming a display device, to have a predetermined shape with an excellent controllability. The method for manufacturing a display device includes the steps of: forming a lyophobic region; selectively irradiating laser beam in the lyophobic region to form a lyophilic region; selectively discharging a composition, that contains a conductive material, in the lyophilic region to form a gate electrode layer; forming a gate insulating layer and a semiconductor layer over the gate electrode layer; discharging a composition containing a conductive material over the semiconductor layer to form a source electrode layer and a drain electrode layer; and forming a pixel electrode layer on the source or drain electrode layer. | 2011-07-07 |
| 20110165742 | PIXEL STRUCTURE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a pixel structure includes providing a substrate having a pixel area. A first metal layer, a gate insulator and a semiconductor layer are formed on the substrate and patterned by using a first half-tone mask or a gray-tone mask to form a transistor pattern, a lower capacitance pattern and a lower circuit pattern. Next, a dielectric layer and an electrode layer both covering the three patterns are sequentially formed and patterned to expose a part of the lower circuit pattern, a part of the lower capacitance pattern and a source/drain region of the transistor pattern. A second metal layer formed on the electrode layer and the electrode layer are patterned by using a second half-tone mask or the gray-tone mask to form an upper circuit pattern, a source/drain pattern and an upper capacitance pattern. A portion of the electrode layer constructs a pixel electrode. | 2011-07-07 |
| 20110165743 | METHOD FOR MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - When a natural oxide film is left at the interface between a metal silicide layer and a silicon nitride film, in various heating steps (steps involving heating of a semiconductor substrate, such as various insulation film and conductive film deposition steps) after deposition of the silicon nitride film, the metal silicide layer partially abnormally grows due to oxygen of the natural oxide film occurring on the metal silicide layer surface. A substantially non-bias (including low bias) plasma treatment is performed in a gas atmosphere containing an inert gas as a main component on the top surface of a metal silicide film of nickel silicide or the like over source/drain of a field-effect transistor forming an integrated circuit. Then, a silicon nitride film serving as an etching stop film of a contact process is deposited. As a result, without causing undesirable cutting of the metal silicide film, the natural oxide film over the top surface of the metal silicide film can be removed. | 2011-07-07 |
| 20110165744 | MEMORY ARRAY WITH ULTRA-THIN ETCHED PILLAR SURROUND GATE ACCESS TRANSISTORS AND BURIED DATA/BIT LINES - A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a corresponding data/bit line. The access transistors have a pillar extending generally upward with a source region formed so as to be in electrical communication with the corresponding data/bit line and a drain region formed generally at an upper portion of the pillar and a surround gate structure substantially completely encompassing the pillar in lateral directions and extending substantially the entire vertical extent of the pillar and word lines extending generally in a second direction and in electrical contact with a corresponding surround gate structure at least a first surface thereof such that bias voltage applied to a given word line is communicated substantially uniformly in a laterally symmetric extent about the corresponding pillar via the surround gate structure. | 2011-07-07 |
| 20110165745 | NONVOLATILE SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory according to examples of the present invention comprises a memory cell and a peripheral transistor. The memory cell has a first intergate insulating film having a multilayer structure and provided on a floating gate electrode and an isolation insulating layer. The peripheral transistor has a second intergate insulating film having a multilayer structure and provided on a first gate electrode and a second isolation insulating layer. The first and second intergate insulating films have the same structure, and a lowermost insulating layer of the first intergate insulating film on the first isolation insulating layer is thinner than a lowermost insulating layer of the second intergate insulating film on the second isolation insulating layer. | 2011-07-07 |
| 20110165746 | Novel Profile of Flash Memory Cells - A semiconductor structure includes a semiconductor substrate; a tunneling layer on the semiconductor substrate; a source region adjacent the tunneling layer; and a floating gate on the tunneling layer. The floating gate comprises a first edge having an upper portion and a lower portion, wherein the lower portion is recessed from the upper portion. The semiconductor structure further includes a blocking layer on the floating gate, wherein the blocking layer has a first edge facing a same direction as the first edge of the floating gate. | 2011-07-07 |
| 20110165747 | SEMICONDUCTOR APPARATUS AND FABRICATION METHOD THEREOF - A method for manufacturing a semiconductor apparatus includes forming a contact pad layer over a substrate in an active region; patterning the contact pad layer and the substrate to form a first trench, the first trench defining a contact pad pattern; etching the substrate to form a second trench that extends vertically from the first trench; forming a gate insulating pattern over the substrate in the second trench; and forming a buried gate in the second trench. | 2011-07-07 |
| 20110165748 | LDMOS WITH DOUBLE LDD AND TRENCHED DRAIN - A LDMOS with double LDD and trenched drain is disclosed. According to some preferred embodiment of the present invention, the structure contains a double LDD region, including a high energy implantation to form lightly doped region and a low energy implantation thereon to provide a low resistance path for current flow without degrading breakdown voltage. At the same time, a P+ junction made by source mask is provided underneath source region to avoid latch-up effect from happening. | 2011-07-07 |
| 20110165749 | METHOD OF MAKING A SEMICONDUCTOR STRUCTURE USEFUL IN MAKING A SPLIT GATE NON-VOLATILE MEMORY CELL - A method of making a semiconductor device on a semiconductor layer is provided. The method includes: forming a select gate dielectric layer over the semiconductor layer; forming a select gate layer over the select gate dielectric layer; and forming a sidewall of the select gate layer by removing at least a portion of the select gate layer. The method further includes growing a sacrificial layer on at least a portion of the sidewall of the select gate layer and under at least a portion of the select gate layer and removing the sacrificial layer to expose a surface of the at least portion of the sidewall of the select gate layer and a surface of the semiconductor layer under the select gate layer. The method further includes forming a control gate dielectric layer, a charge storage layer, and a control gate layer. | 2011-07-07 |
| 20110165750 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING STRUCTURES - In methods of manufacturing a semiconductor device, a plurality of gate structures spaced apart from each other and oxide layer patterns. A sputtering process using the oxide layer patterns as a sputtering target to connect the oxide layer patterns on the adjacent gate structures to each other is performed, so that a gap is formed between the gate structures. A volume of the gap is formed uniformly to have desired volume by controlling a thickness of the oxide layer patterns. | 2011-07-07 |
| 20110165751 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device which previously form sidewalls between lower electrodes to prevent bunkers and leaning phenomena during a sacrificial layer dip out process, thereby improving characteristic of the device, is provided. The method includes forming a mesh pattern defining a storage node region over a semiconductor substrate, forming a lower electrode over the semiconductor substrate and sidewalls of the mesh pattern, forming a dielectric layer over the semiconductor substrate including the lower electrode, and forming an upper electrode over the dielectric layer. | 2011-07-07 |
| 20110165752 | PHASE CHANGE MEMORY DEVICE CAPABLE OF INCREASING SENSING MARGIN AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device capable of increasing a sensing margin and a method for manufacturing the same. The phase change memory device includes a semiconductor substrate formed with a device isolation structure which defines active regions; first conductivity type impurity regions formed in surfaces of the active regions and having the shape of a line; a second conductivity type well formed in the semiconductor substrate at a position lower than the device isolation structure; a second conductivity type ion-implantation layer formed in the semiconductor substrate at a boundary between a lower end of the device isolation structure and the semiconductor substrate; a plurality of vertical PN diodes formed on the first conductivity type impurity regions; and phase change memory cells formed on the vertical PN diodes. | 2011-07-07 |
| 20110165753 | Method for Making Self Aligning Pillar Memory Cell Device - A method for making a memory cell assembly includes forming a memory cell access layer over a substrate to create an access device with a bottom electrode. A memory material layer is formed over the memory cell access layer in electrical contact with the bottom electrode. A first electrically conductive layer is formed over the memory material layer. A first mask, extending in a first direction, is formed over the first electrically conductive layer and then trimmed so that those portions of the first electrically conductive layer and the memory material layer not covered by the first mask are removed. | 2011-07-07 |
| 20110165754 | POLYSILICON STRUCTURES RESISTANT TO LASER ANNEAL LIGHTPIPE WAVEGUIDE EFFECTS - Laser scan annealing of integrated circuits offers advantages compared to rapid thermal annealing and furnace annealing, but can induce overheating in regions of components with polysilicon layers. Segmented polysilicon elements to reduce overheating is disclosed, as well as a method of forming components with segments polysilicon elements. | 2011-07-07 |
| 20110165755 | Semiconductor Component Arrangement Comprising a Trench Transistor - Disclosed is a semiconductor component arrangement and a method for producing a semiconductor component arrangement. The method comprises producing a trench transistor structure with at least one trench disposed in the semiconductor body and with at least an gate electrode disposed in the at least one trench. An electrode structure is disposed in at least one further trench and comprises at least one electrode. The at least one trench of the transistor structure and the at least one further trench are produced by common process steps. Furthermore, the at least one electrode of the electrode structure and the gate electrode are produced by common process steps. | 2011-07-07 |
| 20110165756 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a guard ring surrounding a memory cell region; a peripheral circuit region outside of the guard ring; a supporting film formed on the guard ring and on the peripheral circuit region; and a contact plug formed in the peripheral circuit region. The guard ring and the contact plug are completely filled with the same conductive material. | 2011-07-07 |
| 20110165757 | SEMICONDUCTOR DEVICES HAVING DUAL TRENCH, METHODS OF FABRICATING THE SAME, AND ELECTRONIC SYSTEM HAVING THE SAME - A semiconductor device having a dual trench and methods of fabricating the same, a semiconductor module, an electronic circuit board, and an electronic system are provided. The semiconductor device includes a semiconductor substrate having a cell region including a cell trench and a peripheral region including a peripheral trench. The cell trench is filled with a core insulating material layer, and the peripheral trench is filled with a padding insulating material layer conformably formed on an inner surface thereof and a core insulating material layer formed on an inner surface of the padding insulating material layer. The core insulating material layer has a greater fluidity than the padding insulating material layer. | 2011-07-07 |
| 20110165758 | METHOD FOR MAKING A STRUCTURE COMPRISING A STEP FOR IMPLANTING IONS IN ORDER TO STABILIZE THE ADHESIVE BONDING INTERFACE - The invention relates to a method for making a structure for use ion applications in the fields of electronics, optics or optoelectronics. The structure includes a thin layer of semiconducting material on a supporting substrate. The method includes bonding the thin layer onto the supporting substrate by molecular adhesion at a bonding interface to obtain a structure; implanting ions at the bonding interface to transfer atoms from the thin layer to transfer atoms between the thin layer and the supporting substrate or vice versa; and heat-treating the structure in order to stabilize the bonding interface. | 2011-07-07 |
| 20110165759 | Tuning Capacitance to Enhance FET Stack Voltage Withstand - An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero. | 2011-07-07 |
| 20110165760 | METHOD OF PRODUCING BIPOLAR TRANSISTOR STRUCTURES IN A SEMICONDUCTOR PROCESS - In the method of producing bipolar transistor structures in a semiconductor process, an advanced epitaxial trisilane process can be used without the risk of poly stringers being formed. A base window is structured in a polycrystalline silicon layer covered with an oxide layer, and a further step is epitaxial growing of a silicon layer in the base window from trisilane. The window structuring is performed in a sequence of anisotropic etch and isotropic ash steps, thereby creating stepped and inwardly sloping window edges. Due to the inwardly sloping side walls of the window, the epitaxially grown silicon layer is formed without inwardly overhanging structures, and the cause of poly stringers forming is thus eliminated. | 2011-07-07 |
| 20110165761 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES FABRICATED BY THE SAME - Example methods and example embodiments include methods of fabricating semiconductor devices and semiconductor devices fabricated by the same. Example fabricating methods include forming a first nanowire, oxidizing the first nanowire to form a first nanostructure including a first insulator and a second nanowire, and oxidizing the second nanowire to form a second nanostructure including a second insulator and nanodots. Example semiconductor devices include nanostructures including nanodots and nanostructures providing storage nodes in memory devices. | 2011-07-07 |
| 20110165762 | MONOSILANE OR DISILANE DERIVATIVES AND METHOD FOR LOW TEMPERATURE DEPOSITION OF SILICON-CONTAINING FILMS USING THE SAME - This invention relates to silicon precursor compositions for forming silicon-containing films by low temperature (e.g., <550° C.) chemical vapor deposition processes for fabrication of ULSI devices and device structures. Such silicon precursor compositions comprise at least a silane or disilane derivative that is substituted with at least one alkylhydrazine functional groups and is free of halogen substitutes. | 2011-07-07 |
| 20110165763 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE - A semiconductor device has a semiconductor body with a semiconductor device structure including at least a first electrode and a second electrode. Between the two electrodes, a drift region is arranged, the drift region including charge compensation zones and drift zones arranged substantially parallel to one another. At least one charge carrier storage region which is at least partially free of charge compensation zones is arranged in the semiconductor body. | 2011-07-07 |
| 20110165764 | METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE - A first silicon carbide substrate having a first back-side surface and a second silicon carbide substrate having a second back-side surface are prepared. The first and second silicon carbide substrates are placed so as to expose each of the first and second back-side surfaces in one direction. A connecting portion is formed to connect the first and second back-side surfaces to each other. The step of forming the connecting portion includes a step of forming a growth layer made of silicon carbide on each of the first and second back-side surfaces, using a sublimation method of supplying a sublimate thereto in the one direction. | 2011-07-07 |
| 20110165765 | Semiconductor Device and Method of Manufacturing the Same - In the substrate and the epitaxial layer, isolation regions are formed to divide the substrate and the epitaxial layer into a plurality of element formation regions. Each of the isolation regions is formed by connecting first and second P type buried diffusion layers with a P type diffusion layer. By disposing the second P type buried diffusion layer between the first P type buried diffusion layer and the P type diffusion layer, a lateral diffusion width of the first P type buried diffusion layer is reduced. This structure allows a formation region of the isolation region to be reduced in size. | 2011-07-07 |
| 20110165766 | T-GATE FORMING METHOD FOR HIGH ELECTRON MOBILITY TRANSISTOR AND GATE STRUCTURE THEREOF - A T-gate forming method for a high electron mobility transistor includes the steps of: coating a first, a second and a third resist, each having an electron beam sensitivity different from each other, on a semiconductor substrate; performing a first exposure process by using an electron beam on the semiconductor substrate and then selectively developing the third resist; defining a gate head area by selectively developing the second resist to have a developed width wider than that of the third resist; performing a second exposure process by using an electron beam on the semiconductor substrate and then selectively developing the first resist in a bent shape at a temperature lower than in the development of the second and the third steps; and depositing metallic materials on the resists and then removing them to form a T-gate. | 2011-07-07 |
| 20110165767 | SELECTIVE IMPLEMENTATION OF BARRIER LAYERS TO ACHIEVE THRESHOLD VOLTAGE CONTROL IN CMOS DEVICE FABRICATION WITH HIGH-k DIELECTRICS - The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric. | 2011-07-07 |
| 20110165768 | Semiconductor Device Having a Modified Recess Channel Gate and a Method for Fabricating the Same - A semiconductor device having a modified recess channel gate includes active regions defined by a device isolation layer and arranged at regular intervals on a semiconductor substrate, each active region extending in a major axis and a minor axis direction, a trench formed in each active region, the trench including a stepped bottom surface in the minor axis direction of the active region, and a recess gate formed in the trench. | 2011-07-07 |
| 20110165769 | NONVOLATILE MEMORY DEVICE WITH MULTIPLE BLOCKING LAYERS AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device with a blocking layer controlling the transfer of electric charges in a charge storage layer includes the blocking layer having a first blocking layer in contact with the charge storage layer and a second blocking layer over the first blocking layer, wherein the first blocking layer has a greater energy band gap than the second blocking layer and the second blocking layer has a greater permittivity than the first blocking layer. | 2011-07-07 |
| 20110165770 | Non-volatile memory device - A non-volatile memory device includes a memory cell region which is formed on a semiconductor substrate to store predetermined information, and a peripheral circuit region which is formed on the semiconductor substrate. The memory cell region includes a gate electrode; and a charge storage layer, the charge storage layer being formed to be a notch or wedge shape having an edge extending into both sides of a bottom end of the gate electrode. The peripheral circuit region includes no charge storage layer therein. | 2011-07-07 |
| 20110165771 | METHOD OF FORMING VIAS IN SILICON CARBIDE AND RESULTING DEVICES AND CIRCUITS - A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding. The method includes fabricating a semiconductor device in epitaxial layers on a surface of a silicon carbide substrate and with at least one metal contact for the device on the uppermost surface of the epitaxial layer. The opposite surface of the substrate is then ground and polished until it is substantially transparent. The polished surface of the silicon carbide substrate is then masked to define a predetermined location for at least one via that is opposite the device metal contact and etching the desired via in steps. The first etching step etches through the silicon carbide substrate at the desired masked location until the etch reaches the epitaxial layer. The second etching step etches through the epitaxial layer to the device contacts. Finally, the via is metallized. | 2011-07-07 |
| 20110165772 | CARRIER SOLVENT COMPOSITIONS, COATINGS COMPOSITIONS, AND METHODS TO PRODUCE THICK POLYMER COATINGS - Compositions and methods useful for the coating of polymeric materials onto substrates, for example, electronic device substrates such as semiconductor wafers, are provided. These compositions and methods are particularly suitable manipulating thickness of a polymeric coating in a single coating event. Such methods to control photoresist thickness are used to facilitate the layering of electronic circuitry in a three-dimensional fashion. Furthermore, the compositions of the present invention may be effectively used to deposit thick films of polymeric material in a uniform manner onto inorganic substrates which provides a significant benefit over conventional systems. | 2011-07-07 |
| 20110165773 | Circuit Signal Connection Interface - A circuit signal connection interface, a manufacturing method thereof, and an electronic device using the same are provided. The circuit signal connection interface includes a first signal line and a second signal line juxtaposed to each other, an insulation layer, and a first conductive pad. The first conductive pad electrically connects to the first signal line, and crosses the second signal line. The insulation layer is disposed between the second signal line and the first conductive pad. The electronic device further includes a circuit device including a first conducting bump and a second conducting bump connected to each other in a parallel manner. The first conducting bump electrically connects to a first portion of the first conductive pad while the second conducting bump electrically connects to a second portion of the first conductive pad. | 2011-07-07 |
| 20110165774 | Contact and Via Interconnects Using Metal Around Dielectric Pillars - An integrated circuit containing a vertical interconnect that includes a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure. An upper conductive structure contacts a top surface of the vertical interconnect. A process of forming an integrated circuit that includes forming a vertical interconnect that has a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure, and an upper conductive structure contacts a top surface of the vertical interconnect. | 2011-07-07 |
| 20110165775 | THIN FILM FORMING METHOD - According to the present invention, a thin film having a desired thickness is formed on an inner sidewall of a step with excellent step coverage in a film forming step and an etching step at least once, respectively. In an embodiment of the present invention, a target material is deposited on a substrate ( | 2011-07-07 |
| 20110165776 | Bond Pad Connection to Redistribution Lines Having Tapered Profiles - An integrated circuit structure includes a semiconductor substrate having a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate, wherein the TSV has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is formed over the backside of the semiconductor substrate and connected to the back end of the TSV. A passivation layer is over the RDL with an opening formed in the passivation layer, wherein a portion of a top surface of the RDL and a sidewall of the RDL are exposed through the opening. A metal finish is formed in the opening and contacting the portion of the top surface and the sidewall of the RDL. | 2011-07-07 |
| 20110165777 | Method and Slurry for Tuning Low-K Versus Copper Removal Rates During Chemical Mechanical Polishing - A composition and associated method for the chemical mechanical planarization (CMP) of metal substrates on semiconductor wafers are described. The composition contains a nonionic fluorocarbon surfactant and a per-type oxidizer (e.g., hydrogen peroxide). The composition and associated method are effective in controlling removal rates of low-k films during copper CMP and provide for tune-ability in removal rates of low-k films in relation to removal rates of copper, tantalum, and oxide films. | 2011-07-07 |
| 20110165778 | ELECTRON BEAM DEPICTING PATTERN DESIGN, PHOTOMASK, METHODS OF DEPICTING AND FABRICATING PHOTOMASK, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - A method of depicting a photomask using e-beams includes preparing a photomask having an e-beam resist, depicting the e-beam resist and forming an e-beam resist pattern on the photomask. Depicting the e-beam resist includes irradiating e-beams to an e-beam depiction region without irradiating the e-beams to an e-beam non-depiction region disposed in the e-beam depiction region. The e-beam depiction region and the e-beam non-depiction region are formed using an e-beam resist pattern having the same polarity. | 2011-07-07 |
| 20110165779 | METHOD OF ORIENTING AN UPPER ELECTRODE RELATIVE TO A LOWER ELECTRODE FOR BEVEL EDGE PROCESSING - Methods for orienting an upper electrode relative to a lower electrode are provided. The lower electrode is configured to have a desired existing orientation in a process chamber to define active and inactive process zones in the process chamber for processing a wafer. The method includes configuring each electrode with a reference surface, where a lower electrode reference surface is in the desired existing orientation and an upper electrode reference surface to be oriented parallel to the lower electrode reference surface. Then, temporarily holding the upper electrode reference surface oriented parallel to the lower electrode reference surface, and securing the upper electrode to a drive to mount the upper electrode reference surface parallel to the lower electrode reference surface. Other method configurations are also disclosed and illustrated. | 2011-07-07 |
| 20110165780 | METHODS OF FORMING RUTHENIUM-CONTAINING FILMS BY ATOMIC LAYER DEPOSITION - A method of forming ruthenium-containing films by atomic layer deposition is provided. The method comprises delivering at least one precursor to a substrate, the at least one precursor corresponding in structure to Formula I: (L)Ru(CO) | 2011-07-07 |
| 20110165781 | FLOWABLE DIELECTRIC USING OXIDE LINER - Methods of forming silicon oxide layers are described. The methods include mixing a carbon-free silicon-containing precursor with a radical-nitrogen precursor, and depositing a silicon-and-nitrogen-containing layer on a substrate. The radical-nitrogen precursor is formed in a plasma by flowing a hydrogen-and-nitrogen-containing precursor into the plasma. Prior to depositing the silicon-and-nitrogen-containing layer, a silicon oxide liner layer is formed to improve adhesion, smoothness and flowability of the silicon-and-nitrogen-containing layer. The silicon-and-nitrogen-containing layer may be converted to a silicon-and-oxygen-containing layer by curing and annealing the film. Methods also include forming a silicon oxide liner layer before applying a spin-on silicon-containing material. | 2011-07-07 |
| 20110165782 | CIRCUIT BOARD CLAMP MEANS - An electrical connector for connecting the bare end of a horizontal conductor with a horizontal printed circuit board, including a sectional housing having a base member seated on the printed circuit board. The base member contains an open-topped chamber and includes a vertical front wall the upper edge of which contains a vertical slot communicating with the chamber. A cover member is normally seated on the base member to close the chamber and the upper end of the slot. A lower electrically conductive cage member is arranged in the bottom of the chamber for electrical connection with the printed circuit board. The cover member is removable from the base member to open the tops of the chamber and the slot, thereby to permit the horizontal conductor bare end to be displaced laterally vertically downwardly into the slot and housing chamber toward electrical engagement with the lower cage member. | 2011-07-07 |
| 20110165783 | Dual Card Connector - A dual card connector assembly electrically connects two cards to a system board. The connector assembly includes an insulating housing and an electrical contact area for electrically coupling the connector to a system board. The insulating housing includes a first elongated slot disposed on a front side of the connector and adapted to receive a connection end of a first card, the first elongated slot including a plurality of electrical contacts for mating with corresponding contacts on the first card, and a second elongated slot disposed on a back side of the connector and adapted to receive a connection end of a second i card, the second elongated slot including a plurality of electrical contacts for mating with corresponding contacts on the second card. | 2011-07-07 |
| 20110165784 | ELECTRICAL CONNECTOR ASSEMBLY - Electrical connectors for interconnecting circuit boards. One such connector includes an integral flange for mounting a guidance pin in any of multiple orientations. A corresponding keying block may have a polarization component that can be mounted in a corresponding number of positions. The connector can accept conductive elements with different shapes for signals and grounds, but the housing may be adapted to receive either type of contact in any contact location. Protection of contact elements from excessive yield is provided within the insulative housing of the backplane connector. On the daughter card connector, height difference between ground and signal contacts in wafer assemblies protects components from electrostatic discharge. | 2011-07-07 |
| 20110165785 | MODULAR LEAD INTERCONNECTOR - An end interconnector for one or both ends of a lead body of an electrical lead for an implantable medical device. The interconnector has an insulative body having a receptacle at its first end for each of a plurality of wire filars from the lead body, and a receiver at its second end for each of a plurality of connection wires extending from the medical device, such as an electrode tip. The interconnector provides electrical connection between the plurality of wire filars and the plurality of connection wires. | 2011-07-07 |
| 20110165786 | High Pressure, High Temperature Standoff for Electrical Connector in an Underground Well - A standoff for providing a fluid-tight seal for an electrical connection in a well between an electrical conductor extending from down hole of the well and a power source conductor extending from an above-ground power source is enclosed by and extends through and further into the wellbore. The power source conductor extends down hole to a connector for connecting the power source conductor to the electrical conductor The standoff includes a rigid tube adapted to extend through a wellhead barrier of the well and terminate at a lower end A rubber boot surrounds the rigid tube An electrical insulative tubular body has a hole forming a first inner surface surrounding the power source cable between the lower end of the rigid tube and the connector, the rubber boot surrounding the tubular body A sleeve is placed at one end of the tubular body and has a second, larger hole | 2011-07-07 |
| 20110165787 | CONNECTION APPARATUS - A connection apparatus includes a male plug which may be mated into bayonet-type engagement with a female socket. The plug has at least one radially projecting lug and the socket has at least one axially extending insertion channel and at least one adjoining locking channel within which the lug may be received. The locking channel includes at least one depression which is located radially angularly offset from the insertion channel. Engagement between the lug with the depression resists unintentional detachment of the connection. | 2011-07-07 |
| 20110165788 | ELECTRICAL CONNECTOR - An electrical connector comprising a manipulative lever operative to engage with a mating electrical connector, which has a body portion and a pair of end portions connected respectively with both ends of the body portion and supported respectively by a pair of supporting structures provided in a conductive shell covering partially an insulated housing, wherein each of the end portions of the manipulative lever comprises an elongated portion stretching to be bent from the body portion and a top end portion stretching further from the elongated portion so as to extend as a whole in a first direction from an end portion to a central portion of the insulated housing, the top end portion protrudes from the elongated portion in a direction perpendicular to an imaginary central axis of the elongated portion to form a stepped portion between the elongated portion and the top end portion, and a stopper member provided in the supporting structure engages with the stepped portion so as to prevent the end portion of the manipulative lever from getting out of the supporting structure when the end portion is shifted in a second direction opposite to the first direction. | 2011-07-07 |
| 20110165789 | SNAP-ON COAXIAL CABLE CONNECTOR - A coaxial cable connector includes an elongated body extending in a longitudinal direction between a mating end and a cable end. The coaxial cable connector also includes a center contact held by the body. A locking member is circumferentially disposed around the body at the mating end. The locking member has teeth configured to mechanically engage a threaded area of a mating connector to securely attach the coaxial cable connector to the mating connector. The locking member is slidably coupled to the body such that the locking member moves with respect to the body along the longitudinal direction to enable the teeth to align with the threaded area along the longitudinal direction. | 2011-07-07 |
| 20110165790 | ELECTRICAL CONNECTOR - An electrical connector which comprises an insulated housing on which a first engaging portion is provided for engaging with a second engaging portion provided in a mating electrical connector, first contacts arranged in a predetermined direction on the insulated housing and operative to come into contact with second contacts provided in the mating electrical connector, a conductive shell for covering partially the insulated housing, and an aligning cover attached to the conductive shell and operative to cause end portions thereof in the predetermined direction to engage respectively with end portions in the predetermined direction of the mating electrical connector for aligning the insulated housing with the mating electrical connector when the first engaging portion is engaged with the second engaging portion, and with which the first engaging portion can be appropriately and smoothly put in engagement with the second engaging portion. | 2011-07-07 |
| 20110165791 | ADAPTER EQUIPPED WITH A WIRE WINDING AND HOLDING APPARATUS - An adapter equipped with a wire winding and holding apparatus comprises a circuit laying section to hold a conversion circuit, a wire holding section to define a holding space and a wire winder movably held in the holding space. The wire winder includes two conducting wire ends which are extensible and retractable and electrically connected to each other. One of the conducting wire ends is electrically connected to the conversion circuit. Two positioning arms are extended from the same side of the adapter to define the holding space. The wire winder is guided by the two positioning arms and movably pulled out or retracted in the holding space to be anchored. The two positioning arms have respectively an extended laying space communicating with the circuit laying space. | 2011-07-07 |
| 20110165792 | CONFIGURATION AID FOR ORIENTING A CONNECTOR WITH RESPECT TO A RECEPTACLE - An electronic connector comprises an outer shell having a first side and a second side, an insulative seat body having a first side and a second side, a plurality of terminals extending along the first side of the insulative seat body, and a configuration aid formed on the outer shell. The insulative seat body is disposed within an interior of the outer shell such that the first side of the insulative seat body is oriented toward the first side of the outer shell and the second side of the insulative seat body is oriented toward the second side of the outer shell. The configuration aid is structured to indicate the orientation of the terminals with respect to the first side of the outer shell. | 2011-07-07 |
| 20110165793 | Waterproof Insulated Connector - The invention involves relates to a waterproof insulated connector, which improves any electrical connection of a power supply, a USB, a VGA, a socket of electric equipment, an SD, an MS, an MMC and the like into a connection which can realize water-proof and insulation performances completely. Whether a connector of the electric equipment is connected or not, the plug and the socket are waterproof and can be directly connected in water or other media absolutely without damaging the electric equipment and causing electric shock accidents, and the multi-connection can realize mutual isolation. The waterproof performance is realized by an isolating cavity consisting of a gating isolate component made of a dielectric elastomer, a shell and a hollow waterproof ring. The waterproof isolation connector and the method thereof have innovation in technology and lead users to an electric world with high safety and humanization. | 2011-07-07 |
| 20110165794 | Electrical connector - An electrical connector sub-assembly including a housing having at least one electrical contact receiving area configured to receive an electrical contact; and a terminal position assurance (TPA) member located on a front section of the housing. The TPA member is laterally movable on the front section between an unlocked position and a locked position. The TPA member comprises two spaced sections configured to lock the electrical contact in the electrical contact receiving area at two spaced locations when the TPA member is moved to the locked position. This prevents unintentional withdrawal of the electrical contact from the electrical contact receiving area. | 2011-07-07 |
| 20110165795 | CONNECTOR ASSEMBLY - A connector assembly can include a connector with a ground pin and a case. The case can have an electrically conductive surface. A capacitor is connected to the ground pin. The capacitor is also connected to the electrically conductive surface. The capacitor can be connected between the electrically conductive surface and the ground pin so that the electrically conductive surface and the ground pin are capacitively coupled. | 2011-07-07 |
| 20110165796 | Electrical connector with shell and status switch - The invention relates to a female electrical connector having a contact volume for receiving a jack, a shell for securing the position of the connector relative to a substrate and a status switch, which is adapted to be operated by inserting the jack into the contact volume. In order to provide for a smaller connector, the present invention provides that the switch is at least partially integrated into the shell. | 2011-07-07 |
| 20110165797 | BOARD-TO-BOARD CONNECTOR - The board-to-board connector has a configuration in which first stage fitting guides ( | 2011-07-07 |
| 20110165798 | Connector, Connector Assembling System and Method of Assembling a Connector - An electrical connector is presented, including a plurality of connector wafers coupled by a coupling piece, each wafer including a housing accommodating a plurality of contact elements, said housing having opposite side edges, an insertion side exposing the contact elements, a back side and opposite main faces. The connector wafers are provided with first coupling means extending along at least a portion of a side edge thereof. The coupling piece is provided with second coupling means extending along at least a portion thereof. The first and second coupling means are arranged for engaging each other, in a coupled situation, on a plurality of distinct engagement positions along the respective coupling means. | 2011-07-07 |
| 20110165799 | ELECTRICAL CONNECTOR FOR HOLDING A LAMP - An electrical connector includes an insulative housing, a contact and an operation member. The insulative housing defines a lamp receiving room and a board receiving room communicating with the lamp receiving room. The contact includes a retaining portion retained in the housing, a pair of first elastic arms exploding to the lamp receiving room and a second elastic arm exploding to the board receiving room. Each first elastic arm includes an inner portion and an outer portion, the inner portions defining a receiving cavity therebetween with an entrance from which a lamp is inserted to the receiving cavity and clamped by the two inner portions. The operation member defines a pair of side plates inserted in the lamp receiving room to urge free distal ends of the outer portions of the contact to press against the inner portions at positions far away from the entrance. | 2011-07-07 |
| 20110165800 | TERMINAL FITTING - Provided is a terminal fitting capable of reliably press-bonding a core wire made of aluminum or aluminum alloy. A terminal fitting | 2011-07-07 |
| 20110165801 | Crimp Terminal for Aluminum Electric Cable - A crimp terminal | 2011-07-07 |
| 20110165802 | VESSEL PROPULSION SYSTEM FOR WATERCRAFT - A ship propulsion system for watercraft contains at least one propeller, by which a drive force can be created for the watercraft. The ship propulsion further contains an electric motor, the rotor of which is directly mechanically coupled to the at least one propeller via a shaft such that the at least one propeller may be brought into a respective rotating movement by a rotation of the rotor. In order to cool the rotor of the electric motor a thermosiphon is disposed in the shaft, and the propeller serves as a heat sink for a working medium of the thermosiphon. | 2011-07-07 |
| 20110165803 | Method for performing overhead work using air-propelled vessel with articulating member - A method of using a wide, flat-bottom, buoyant, amphibious hull with a powered articulating member mounted on the deck. The hull is propelled by at least one engine-driven propeller rotating above the hull. The hull has a shallow draft and distributes its weight over a large area. These features cooperatively provide a vehicle capable of performing overhead work, such as installing or servicing power transmission poles, towers, or other structures located in environmentally sensitive wetlands, swamps, marshes, shallow water, or other terrain. | 2011-07-07 |
| 20110165804 | BREASTSTROKE SWIMMING TRAINING PADDLES WITH FINS - A training paddle for use by a swimmer comprises a base configured to accommodate a hand of the swimmer. A strap holds the base to the hand. A raised fin that extends upward from the base directs water away from flowing between the hand and the base. | 2011-07-07 |
| 20110165805 | FLOTATION DEVICE - A flotation device for use by an individual in a body of water, comprising two flexible, selectively inflatable sleeve elements having an elongated belt extending therebetween. The sleeve elements each include a coupling assembly for coupling the belt to the sleeve, and a clasp device for securing the ends of the belt around the girth of the user. | 2011-07-07 |
| 20110165806 | FABRIC FOR AIRBAG AND METHOD OF PREPARING THE SAME - The present invention relates to a fabric for an airbag, in particular, a fabric for an airbag comprising the polyester fiber, and a method of preparing the same. The fabric for the airbag according to the present invention is prepared by using a polyester fiber having the cross-section thereof in a flat shape, and there are advantages in that the present fabric is thinner than the fabric made of the circular cross-sectional fiber. It is possible to reduce the amount of the coating resin used and to lighten the weight of the product because of the low surface irregularity and the porosity. Also, the present fabric is superior in tensile strength, tearing strength, air permeability, and the folding property in a module system of the airbag apparatus. | 2011-07-07 |
| 20110165807 | Non-Coated Fabric for Outdoor Applications - A non-coated fabric for outdoor applications is provided that is made up of a woven fabric and a chemical composition applied to the woven fabric. The woven fabric is made from multifilament yarns that are solution dyed and have a UV rating of at least 500 hours. The chemical composition is applied to the woven fabric and incorporated into the fabric such that the fabric has a hydrostatic pressure of at least 45 cm. | 2011-07-07 |
| 20110165808 | SUPERHYDROPHOBIC COATING - A composition for coating comprising at least one compound of formula I and optionally at least one compound of formula II | 2011-07-07 |
| 20110165809 | SOLUBLE TERMINALLY MODIFIED IMIDE OLIGOMER USING 2-PHENYL-4, 4'-DIAMINODIPHENYL ETHER, VARNISH, CURED PRODUCT THEREOF, IMIDE PREPREG THEREOF, AND FIBER-REINFORCED LAMINATE HAVING EXCELLENT HEAT RESISTANCE - A novel terminally modified imide oligomer having excellent solubility in organic solvents, excellent solution storage stability, and excellent molding properties such as low melt viscosity. Also, a varnish obtained by dissolving the terminally modified imide oligomer in an organic solvent; a cure product obtained by using the terminally modified imide oligomer and having excellent thermal and mechanical characteristics such as heat resistance, elastic modulus, tensile strength at break and tensile elongation at break; a prepreg; and a fiber-reinforced laminate. The soluble terminally modified imide oligomer is represented by general formula (1). In the formula, R | 2011-07-07 |
| 20110165810 | FIBER COMPOSITE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a fiber composite which allows control of a wide range of air permeability from low air permeability to high air permeability to be achieved with a small mass per unit area of resin, and to provide a method for manufacturing the same. A film material | 2011-07-07 |
| 20110165811 | Article Formed From Electrospinning A Dispersion - An article of fibers includes a cured compound. The fibers are formed from electrospinning a dispersion. The dispersion includes a liquid and a condensation curable compound. A content of the liquid in the dispersion is reduced such that the condensation curable compound cures. The article is formed from a method of manufacturing which includes the step of forming the dispersion. The method also includes the step of electro spinning the dispersion to reduce the content of the liquid such that the condensation curable compound cures. | 2011-07-07 |
| 20110165812 | LINE-AT-A-TIME FOIL DISPLAY - A display device comprising a light guide ( | 2011-07-07 |
| 20110165813 | SYSTEM FOR DISPLAYING IMAGES AND FABRICATION METHOD THEREOF - The invention provides a system for displaying image and a fabrication method thereof. The system comprises an organic electroluminescent display device comprising a first substrate divided into a pixel region and a non-pixel region, a conductive layer formed in the non-pixel region, a second substrate corresponding to the first substrate, a first electrode formed on the second substrate, an organic electroluminescent layer formed on the first electrode, and a second electrode formed on the organic electroluminescent layer and electrically connected to the conductive layer. The system further includes an exterior circuit electrically connected to the conductive layer for transmitting signals. | 2011-07-07 |
| 20110165814 | LASER BEAM IRRADIATION APPARATUS FOR SUBSTRATE SEALING, SUBSTRATE SEALING METHOD, AND METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DISPLAY DEVICE USING THE SAME - A laser beam irradiation apparatus and method of manufacturing an organic light emitting display device using the same are disclosed. The laser beam irradiation apparatus is configured to irradiate a laser beam to an object extending in a first direction while moving the laser beam relative to the object in the first direction, where the laser beam has a cross-section taken in a plane perpendicular to a second direction in which the laser beam is irradiated from the apparatus, the cross-section comprising two substantially symmetrical portions that are substantially symmetrical about a centerline of the cross-section extending in the first direction, where the cross-section has a centerline length taken in the centerline, where at least part of the substantially symmetrical portions has a length in the first direction that is longer than the centerline length. | 2011-07-07 |
| 20110165815 | Laser Beam Irradiation Apparatus for Substrate Sealing and Method of Manufacturing Organic Light Emitting Display Device Using the Same - A laser beam irradiation apparatus irradiates a laser beam onto a sealing unit disposed between a first substrate and a second substrate so as to seal the first substrate and the second substrate. A center portion of the laser beam comprises a first beam profile having a beam intensity which increases toward a beam center portion, and a center of each of a plurality of peripheral portions of the laser beam is included in an area onto which the first beam profile is irradiated. The plurality of peripheral portions are symmetrically distributed around the first beam profile, and comprise a plurality of second beam profiles having the same beam intensities. The first beam profile and the plurality of second beam profiles are symmetrically distributed around a center point of the first beam profile and move in synchronization with one another. | 2011-07-07 |
| 20110165816 | Laser Beam Irradiation Apparatus for Substrate Sealing, Substrate Sealing Method, and Method of Manufacturing Organic Light Emitting Display Device Using the Same - A laser beam irradiation apparatus irradiates a laser beam onto a sealing unit disposed between a first substrate and a second substrate so as to seal the first substrate and the second substrate. The laser beam has a beam intensity which increases from a center portion to an end portion of the laser beam on a surface which is perpendicular to a proceeding direction of the laser beam. The beam intensity at the center portion of the laser beam is half of the beam intensity at the end portion of the laser beam or less, and the laser beam has a beam profile which is symmetrical relative to the proceeding direction of the laser beam. | 2011-07-07 |
| 20110165817 | DISPLAY MANUFACTURING METHOD - A method for manufacturing a display, where the display includes a light-transmissive substrate adhering to a display substrate that forms a display surface side of a display body. An edge of at least either an adhesion surface of the display substrate or an adhesion surface of the light-transmissive substrate is coated with an adhesive. The display substrate and the light-transmissive substrate are positioned in an offset manner to provide overlapping and non overlapping regions. For example, an edge of each of two adhesion surfaces overlap with each other, and other regions do not overlap with each other. The display substrate and the light-transmissive substrate are relatively moved to a position where an edge of the display substrate and an edge of the light-transmissive substrate respectively overlap with other edges in a state in which adhesive reservoirs are formed while maintaining a fixed gap between the two adhesion surfaces. | 2011-07-07 |
| 20110165818 | METHOD FOR PRODUCING PLASMA DISPLAY PANEL - Provided is a manufacturing method that allows even a PDP having high-definition cells to exhibit excellent image display performance with reduced power consumption by effectively preventing impurities from adhering to the protective layer. Specifically, in a pre-baking step, a back substrate | 2011-07-07 |
| 20110165819 | INTELLECTUAL TRAINING TOY - To provide an intellectual training toy which can suppress noise and improve safety, and which has a significant effect on developing children's intellect, maintaining or recovering the mental and physical functions of the elderly, and other purposes. | 2011-07-07 |
| 20110165820 | DOLL KIT - A toy kit for creating a three-dimensional object such as an Easter egg, or a doll having a humanoid or animal appearance is described. The kit has at least two parts formed of resiliently deformable material. One of the part or parts includes posts extending outwardly from a surface thereof for mating with corresponding holes formed in the other part or parts. | 2011-07-07 |
| 20110165821 | METHOD AND APPARATUS FOR PRODUCING AMBULATORY MOTION - Apparatus for ambulatory motion includes an exit slot of non-zero width and a bar or leg of non-zero and non-uniform width extending through the slot and connected to a crank constrains the bar or leg in a manner that produces nearly rectilinear motion of a distal end of the bar or leg when a proximal end of the bar or leg is connected to a crank and the crank is rotated. | 2011-07-07 |
| 20110165822 | RARE EARTH MAGNET HOLDING JIG, CUTTING MACHINE, AND CUTTING METHOD - A magnet holding jig comprises a platform and first and second holders disposed on opposite sides of the platform. The platform is provided with channels, the holders are comb-shaped to define digits and slits, the channels and the slits being aligned to define guide paths for permitting entry of a cutting tool therein, and the holders are also configured as digitate hooks. The holder hooks are in contact with a rare earth magnet block resting on the platform. The holders are pushed inward at their lower portions so as to bring each hook digit of the second holder in pressure abutment with the magnet block at a higher level than each hook digit of the first holder for thereby holding the magnet block in place on the platform. | 2011-07-07 |
| 20110165823 | SEMICONDUCTOR SUBSTRATE PLANARIZATION APPARATUS AND PLANARIZATION METHOD - A planarization apparatus and method that thins and planarizes a substrate by grinding and polishing the rear surface of the substrate with high throughput, and that fabricates a semiconductor substrate with reduced adhered contaminants. A planarization apparatus that houses various mechanism elements in semiconductor substrate loading/unloading stage chamber, a rear-surface polishing stage chamber, and a rear-surface grinding stage chamber. The throughput time of the rear-surface polishing stage that simultaneously polishes two substrates is typically about double the throughput time of the rear-surface grinding stage that grinds one substrate. | 2011-07-07 |
| 20110165824 | GLASS SUBSTRATE FOR INFORMATION RECORDING MEDIUM AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a method for manufacturing a glass substrate for an information recording medium having a high level of cleanness and superior smoothness. The manufacturing method includes a step for washing a disk-shaped glass plate with an acid washing liquid, a step for removing at least part of a surface layer, which is formed on the surface of the glass plate, by performing grinding with diamond abrasion grains, and a step for washing the surface with a neutral or alkaline washing liquid. | 2011-07-07 |
| 20110165825 | POLISHING APPARATUS - A polishing apparatus according to the present invention is a polishing apparatus for polishing a periphery (a bevel portion, a notch portion, an edge-cut portion) of a substrate (W) by bringing a polishing tool ( | 2011-07-07 |
| 20110165826 | ABRASIVE ARTICLE INCORPORATING AN INFILTRATED ABRASIVE SEGMENT - An abrasive article includes a base, an abrasive member comprising three distinct phases bonded to each other including abrasive particles, a metal matrix, and an infiltrant. The abrasive article further includes a backing region between the abrasive member and the base, wherein the backing region comprises a laser welded bond joint. | 2011-07-07 |
| 20110165827 | Carcass Cleaning Method, Device and Machine - Steam is discharged onto a carcass surface from a plurality of steam discharge jets, and impurities, steam and condensate are drawn in from the surface through a plurality of suction nozzles adapted to following an uneven surface of the carcass. A cleaning device for cleaning the surface comprises steam discharge jets and suction nozzles adapted to following an uneven surface of the carcass. Jets and nozzles may be combined into nozzle arrangements adapted to deflect resiliently. Nozzle arrangements may be made from a hose having a central lumen and a number of narrow channels embedded into the hose wall. A cleaning machine may incorporate the cleaning device as well as automated machinery for sweeping it across the carcass surface. | 2011-07-07 |
| 20110165828 | LIGHTWEIGHT CABIN PRESSURE THRUST RECOVERY OUTFLOW VALVE - An aircraft cabin pressure control system outflow thrust recovery valve includes a frame, a valve element, and actuation hardware. The frame, valve element, and at least a portion of the actuation hardware are made of composite material. The actuation hardware is disposed external to the frame. | 2011-07-07 |
