| 27th week of 2012 patent applcation highlights part 22 |
| Patent application number | Title | Published |
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| 20120169371 | INPUT BUFFER SYSTEM WITH A DUAL-INPUT BUFFER SWITCHING FUNCTION AND METHOD THEREOF - An input buffer system with a dual-input buffer switching function includes a first input buffer, a second input buffer, and a multiplexer. The first input buffer is used for outputting a first signal when an input signal is at a logic-high voltage, and the first input buffer is turned off when the input signal is at a logic-low voltage. The second input buffer is used for outputting a second signal when the input signal is at the logic-low voltage. The multiplexer is coupled to the first input buffer and the second input buffer for outputting the first signal or the second signal according to a self refresh signal. | 2012-07-05 |
| 20120169372 | DIFFERENTIAL LOGIC CIRCUIT, FREQUENCY DIVIDER, AND FREQUENCY SYNTHESIZER - A differential logic circuit including a current source circuit which is connected to a current control terminal and generates a current, the current value is controlled by a signal received from the current control terminal, a differential unit which, based on the current from the current source circuit, inputs a plurality of logic signals, performs a logic operation, and outputs a result of the logic operation from a pair of differential signal output terminals thereof, a load circuit which is connected to the pair of differential signal output terminals, and a load control circuit which monitors a change of the current value and controls a load of the load circuit based on a result of the monitoring. | 2012-07-05 |
| 20120169373 | GLITCH FREE CLOCK SWITCHING CIRCUIT - A glitch free clock switching circuit includes a first enable synchronization logic that generates a first clock enable in response to a first enable from a first enable generation logic. The clock switching circuit includes a second enable synchronization logic that generates a second clock enable in response to a second enable from a second enable generation logic. A logic gate is coupled to an output of the second enable synchronization logic that selects the second clock signal as a logic gate output if the second enable is logic high. A priority multiplexer receives a first clock signal, the first enable and the logic gate output. The multiplexer configured to select the first clock signal as the clock output if the first enable is logic high, irrespective of the logic gate output. | 2012-07-05 |
| 20120169374 | APPARATUS AND METHOD FOR OBTAINING MAXIMUM VALUE AND MINIMUM VALUE IN PLURALITY OF DIGITAL INPUT SIGNALS - The present invention relates to a digital signal processing circuit, and more particularly, to a method and apparatus for generating a maximum value or a minimum value used for designing the digital signal processing circuit. An apparatus for obtaining a maximum value or a minimum value from N digital input signals may include N×W bit processing elements to receive an input of W bits of each of the N digital input signals, W OR operators to receive an input of N operation values output from bit processing elements, and to perform an OR operation, respectively, and W inverters to invert an output value for each of the W OR operators. | 2012-07-05 |
| 20120169375 | PROGRAMMABLE PULSE WIDTH DISCRIMINATOR - Disclosed is a programmable pulse width discriminator circuit operable to receive a set of parameters from a user and indicate when an input signal satisfies conditions set by the user-defined parameters. The input signal is sampled by the pulse width discriminator circuit to detect a desired state of the input signal. The user may set the parameters such that the pulse width discriminator indicates the condition wherein the number of consecutive samples for which the input signal is the desired state is (i) greater than a first threshold value, (ii) less than a second threshold value, or (iii) between the first and second threshold values. In these embodiments, the user sets the first and second threshold values and selects which set of conditions are indicated by the output of the circuit. | 2012-07-05 |
| 20120169376 | DEGLITCHER WITH PROGRAMMABLE HYSTERESIS - Disclosed is a deglitcher circuit having a programmable hysteresis. The deglitcher samples a received input signal, wherein the input signal may include one or more glitches. Responsive to a change in state of the sampled input signal, the deglitcher counts the number of samples of the changed state of the input signal. The count value increments with each sampled changed state, and decrements with each sampled original state of the input signal. When the count value reaches a threshold, the state of the output signal is changed. The output signal of the disclosed deglitcher circuit provides an accurate, glitch-free reconstruction of the sampled input signal. Additionally, the disclosed deglitcher circuit reduces the number of memory elements required for a given number of samples of the input signal, thereby allowing for a larger number of samples to be taken without necessarily having to increase the memory elements required by the deglitcher. | 2012-07-05 |
| 20120169377 | Circuit Arrangement including a Common Source Sense-FET - A current sensing circuit arrangement is disclosed. The circuit arrangement includes a load transistor for controlling a load current to a load being coupled to a drain electrode of the load transistor. A sense transistor is coupled to the load transistor. The sense transistor has a drain electrode that provides a measurement current representative of the load current. The load transistor and the sense transistor are field effect transistors having a common source electrode. A measurement circuit is configured to receive the measurement current from the sense transistor and to generate an output signal therefrom, the output signal being representative of the load current. | 2012-07-05 |
| 20120169378 | DIFFERENTIAL DATA SENSING - A first sensing circuit has input terminals coupled to a true differential signal line and a complementary differential signal line. A second sensing circuit also has input terminals coupled to said true signal and said complementary signal. Each sensing circuit has a true signal sensing path and a complementary signal sensing path. The first sensing circuit has an imbalance that is biased towards the complementary signal sensing path, while the second sensing circuit has an imbalance that is biased towards the true signal sensing path. Outputs from the first and second sensing circuits are processed by a logic circuit producing an output signal that is indicative of whether there a sufficient differential signal for sensing has been developed between the true differential signal line and the complementary differential signal line. | 2012-07-05 |
| 20120169379 | VOLTAGE HOLD CIRCUIT - A voltage hold circuit includes four switches, an operational amplifier and a capacitor. By turning the switches on and off, the operational amplifier functions as a unity-gain buffer. In the normal operation mode, the positive input end of the operational amplifier is coupled to a node, and the output end of the operational amplifier is coupled to the capacitor. Thus the voltage of the capacitor is equal to the voltage of the node. In the power off mode, the positive input end of the operational amplifier is coupled d to the capacitor, and the output end of the operational amplifier is coupled to the node. Thus the voltage of the node is equal to the voltage of the capacitor. Therefore, the voltage hold circuit is able to hold the voltage of the node in the power down state. | 2012-07-05 |
| 20120169380 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a first output driver configured to drive a first comparison signal, which is generated by comparing a voltage of a pad coupled to an external resistor with an upper-limit reference voltage, according to drivability determined by a pull-up code and a pull-down code, and output the driven signal as first output data; and a second output driver configured to drive a second comparison signal, which is generated by comparing the voltage of the pad with a lower-limit reference voltage, according to the drivability determined by the pull-up code and the pull-down code, and output the driven signal as second output data. | 2012-07-05 |
| 20120169381 | OUTPUT SLEW RATE CONTROL - This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver circuit such as a DRAM output driver on a die. A selectable combination of series coupled transistors are configured as a parallel array of complementary inverter pairs to provide a divided voltage to a calibrator. The calibrator is configured to respond to a differential voltage to adjust the divided voltage such that the differential voltage is forced to zero. The calibrator outputs a plurality of discrete signals from an up/down counter to toggle the individual transistors of the parallel array to increase and decrease a collective current. In some embodiments, transistor channel currents are modulated to step-adjust a voltage based on a ratio associated with a static resistance. In various embodiments, the divided voltage is an analog voltage based on a resistance associated with trim circuitry. | 2012-07-05 |
| 20120169382 | DIVIDING METHOD AND DIVIDING APPARATUS FOR GENERATING NOISE-REDUCED FREQUENCY DIVIDED SIGNAL BY UTILIZING NOISE REDUCING CIRCUIT - A dividing apparatus is provided. The dividing apparatus includes a frequency dividing circuit and a noise reducing circuit. The frequency dividing circuit is arranged to receive a first clock signal and generate a frequency divided signal corresponding to the first clock signal. The noise reducing circuit is coupled to the frequency dividing circuit and arranged to receive a second clock signal and the frequency divided signal, and is utilized for referring to the second clock signal and the frequency divided signal to reduce noise of the frequency divided signal to generate a noise-reduced frequency divided signal. The first and second clock signals may be identical clock signals or different clock signals. | 2012-07-05 |
| 20120169383 | LEVEL CONVERSION CIRCUIT AND SEMICONDUCTOR DEVICE - A first conversion circuit converts a first clock signal based on a signal level of a first voltage into a second clock signal based on a signal level of a second voltage. A flip-flop circuit supplied with the first voltage as an operation voltage latches and outputs a signal, which is based on the signal level of the first voltage, in accordance with the first clock signal. A second conversion circuit supplied with the second voltage as an operation voltage converts a signal level of an input signal, which is based on an output signal of the flip-flop circuit, into the signal level of the second voltage in synchronization with the second clock signal. | 2012-07-05 |
| 20120169384 | FREQUENCY DIVIDER ARRANGEMENT AND METHOD FOR PROVIDING A QUADRATURE OUTPUT SIGNAL - A frequency divider arrangement for providing a quadrature output signal with a quadrature output signal frequency, includes a signal source for providing a base signal with a base signal frequency at the output side. Further, the frequency divider arrangement includes a first integer number quadrature divider with a first divider ratio for receiving the base signal on the input side and for providing a first quadrature signal with a first quadrature signal frequency according to the first divider ratio of the first integer number quadrature divider. | 2012-07-05 |
| 20120169385 | ELECTRONIC DEVICE WITH RESET CIRCUIT - A reset circuit used for resetting a processing unit of an electronic device includes a switch control unit, a first switch unit, and a reset signal generation unit. The switch control unit controls the on and off state of the first switch unit according to users' operation. The reset signal generation unit outputs a reset signal after the first switch unit has been off for a predetermined time period. The reset signal generation unit stops outputting the reset signal as the first switch unit turns on. The processing unit is reset when receiving the reset signal. | 2012-07-05 |
| 20120169386 | RESETTING CIRCUIT - An exemplary resetting circuit adapted for regulating a voltage on an output terminal of a shift register is disclosed. The resetting circuit includes a reset driving module and a reset module. The reset driving module is received with an enable signal to output a control voltage signal to an output terminal of the reset driving module. The reset module is electrically coupled to the output terminal of the shift register and the output terminal of the reset circuit driving module, and is controlled by the control voltage signal on the output terminal of the reset driving module to determine whether switching on an electrical path between the output terminal of the shift register and a gate-off voltage level. | 2012-07-05 |
| 20120169387 | OSCILLATOR WITH EXTERNAL VOLTAGE CONTROL AND INTERPOLATIVE DIVIDER IN THE OUTPUT PATH - An oscillator output is controlled from an external voltage control terminal using an interpolative divider as a frequency modulator. The oscillator includes a reference clock generator, analog to digital converter, and an interpolative divider. Nominal output frequency is determined by the frequency of the reference clock and the nominal divide value of the interpolative divider. The divide value is changed according to the voltage control input value which is converted to a digital value via an analog to digital converter. Multiple interpolative dividers may be coupled to the single reference clock generator and each have a voltage control input and analog to digital converter. | 2012-07-05 |
| 20120169388 | METHOD AND APPARATUS FOR REDUCING OSCILLATION IN SYNCHRONOUS CIRCUITS - Control signal oscillation filtering circuits, delay locked loops, clock synchronization methods and devices and systems incorporating the control signal oscillation filtering circuits are described. An oscillation filtering circuit includes a first oscillation filter configured to filter oscillations and a majority filter configured to average filter an output of a phase detector and generate in response thereto control signals to an adjustable delay line. | 2012-07-05 |
| 20120169389 | DESKEWING APPARATUS FOR OSCILLOSCOPE - A deskewing apparatus includes a power supply connector, a oscillator, a first switch unit, a second switch unit, a first logic member, a second logic member, a clock generator and a plurality of output channels. The oscillator generates an electrical signal with a predetermined frequency and sinusoidal waveform. The first switch unit and the second switch unit each generates on/off signals by controlling power on/off. The first logic member and the second logic member generate logic signals according to the corresponding on/off signals from the first switch unit and the second switch unit. The clock generator multiplies the frequency of the electrical signal based on the combination of the logic signals and converting the electrical signal from sinusoidal waveform into rectangular waveform. The output channels output the converted electrical signal. | 2012-07-05 |
| 20120169390 | DRIVE STRENGTH ADJUSTMENT THROUGH VOLTAGE AUTO-SENSE - An integrated circuit supports auto-sense of voltage for drive strength adjustment. The method may comprise detecting an input voltage received at an auto-sense pad integrated on a mobile multimedia processing (MMP) chip. The input voltage may be a power supply voltage of the peripheral device received during power-up of the MMP chip, power-up of the peripheral circuitry, and/or dynamically while the MMP is powered-up. The auto-sense pad may adjust drive strength of at least one other pad, which may be an output pad or a bidirectional pad, integrated on the MMP chip may be configured to operate using the determined output voltage. A rise time and/or fall time of signals output by the MMP chip may be varied by the adjustment of the drive strength. | 2012-07-05 |
| 20120169391 | DUTY CYCLE CORRECTOR AND DUTY CYCLE CORRECTION METHOD - The invention relates to a duty cycle corrector for generating from an input clock signal an output clock signal having a desired duty cycle. The duty cycle corrector comprises a pulse generating stage for generating from the input clock signal a pulsed clock signal. The pulse generating stage converts rising edges of the input clock signal into pulses, each of which pulses is shorter than the desired duty cycle times the clock period. The duty cycle corrector further comprises a pulse stretching stage for generating from the pulsed clock signal the output clock signal, the pulse stretching stage delaying falling edges of the pulsed clock signal by a controlled delay. The duty cycle corrector may comprise a duty cycle detector for generating a control signal as a function of the duty cycle of the output clock signal, and a feedback path for delivering the control signal to the pulse stretching stage so as to increase the controlled delay when the duty cycle is less than the desired duty cycle and to decrease the controlled delay when the duty cycle is greater than the desired duty cycle. The invention also relates to a method of generating from an input clock signal an output clock signal having a desired duty cycle. | 2012-07-05 |
| 20120169392 | MIN-TIME HARDENDED PULSE FLOP - A flop circuit is disclosed. The flop circuit includes an input circuit configured to hold a logic value of an input signal received on its input node. The flop circuit further includes a storage circuit configured to, responsive to a pulse clock transitioning to a first logic level, receive and store the logic value and a complement of the logic value. A transfer circuit is coupled between the input circuit and the storage circuit, wherein the transfer circuit is configured to transfer the logic value from the input circuit to the storage circuit responsive to the pulse clock transitioning to the first logic level. The transfer circuit includes a first float node and a second float node and is configured such that at least one of the float nodes is floating during a portion of the operational cycle of the flop circuit. | 2012-07-05 |
| 20120169393 | PROCESSING CLOCK SIGNALS - A circuit for processing a clock signal including first and second clock edges of different polarities, the circuit including an inverter for inverting a first clock edge to generate an inverted first clock edge and inverting a second clock edge to generate an inverted second clock edge; a first pass gate for receiving the inverted clock edge and outputting a first trigger signal of a first polarity; and a second pass gate for receiving the second clock edge and outputting a second trigger signal of the first polarity, wherein the second pass gate is controlled to open responsive to the inverted second clock edge; whereby the delay between the first clock edge and the first trigger signal is substantially equal to the delay between the second clock edge and second trigger signal. | 2012-07-05 |
| 20120169394 | METHOD FOR BUFFERING CLOCK SKEW BY USING A LOGICAL EFFORT - A method buffers clock skew by using a logical effort, and is applicable to a clock tree that stays in a strong-inversion region, a moderate-inversion region, or a weak-inversion region. The method includes establishing in the clock tree a temperature sensor and a tunable-width buffer, and establishing width and temperature comparative lists according to a logical effort equation, for the tunable-width buffer to be individually applied to the strong-inversion region, the moderate-inversion region, and the weak-inversion region; selecting one from the width and temperature comparative lists that corresponds to one of the inversion regions in which the clock tree stays, enabling the temperature sensor to sense a temperature, and searching the selected width and temperature comparative list for a width that corresponds to the temperature sensed by the temperature sensor; and enabling the tunable-width buffer to perform a width modulation process according to the searched width. | 2012-07-05 |
| 20120169395 | LEVEL SHIFTER - A level shifter, converting an input signal into an output signal for level shifting, including a leakage blocking circuit having cascaded P-channel transistors and one N-channel transistor. The P-channel transistor at a beginning stage provides a gate for receiving the input signal and a source coupled to a gate of the P-channel transistor at a secondary stage. At intermediate stages, each P-channel transistor provides a source coupled to a gate of the subsequently cascaded P-channel transistor. At a final stage, the P-channel transistor provides a source coupled to a voltage source and a drain coupled to an output terminal of the leakage blocking circuit for the outputting of the output signal. The N-channel transistor has a gate which is coupled to receive the input signal as well, a source coupled to a common voltage, and a drain coupled to the output terminal of the leakage blocking circuit. | 2012-07-05 |
| 20120169396 | VOLTAGE DOWN CONVERTER - A voltage down converter includes a first driver having a first input terminal configured to generate a first voltage by using an external voltage in response to a first driving signal being inputted to the first input terminal, a control circuit configured to output the first driving signal to the first input terminal in response to a level of the first voltage, a second driver having a second input terminal configured to generate a second voltage by using the external voltage in response to the first driving signal or a second driving signal being inputted to the second input terminal, wherein the first driving signal is transferred from the first input terminal to the second input terminal through a conductive line, and a driving control circuit configured to generate the second driving signal and transferred to the second input terminal in response to a level of the second voltage. | 2012-07-05 |
| 20120169397 | Mixed Signal Integrator Incorporating Extended Integration Duration - A mixed-signal integrator, having an analog input and a digital output, is adapted to perform an integration operation partially in the analog domain and partially in the digital domain while eliminating the limitations of a conventional analog integrator. The integrator also digitizes a signal of interest without the use of a conventional sampling operation followed by a conventional analog-to-digital converter. The analog integrator portion generates an analog integration signal limited between low and high rail voltages defined by two comparators with corresponding threshold voltages. When either rail voltage is reached, the polarity of the input signal is reversed to prevent the integration result from exceeding that rail. Each such event is also tracked in digital logic, which provides a count whenever two consecutive such events correspond to the two different rails. At the end of the integration duration this count serves as the digital representation of the integration result. | 2012-07-05 |
| 20120169398 | Method and Apparatus for Use in Improving Linearity of MOSFETs Using an Accumulated Charge Sink - A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOT MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime. | 2012-07-05 |
| 20120169399 | CIRCUIT AND METHOD FOR GENERATING A CLOCK SIGNAL - A clock source is configured to provide an oscillating signal to be divided into a clock signal. A temperature sensor senses a first temperature of the clock source. The clock source is subjected to at least one second temperature implemented by a temperature alteration module. A calibration module calibrates the clock signal based on the at least one second temperature, the first temperature, a reference signal, and the oscillating signal at the at least one second temperature. | 2012-07-05 |
| 20120169400 | DUAL MODE TOUCH SENSING MODULE AND DUAL MODE TOUCH SENSING DISPLAY - A dual mode touch sensing display includes a display module, and a dual mode touch sensing module disposed at the display module. The dual mode touch sensing module includes a plurality of first conductors, a plurality of second conductors, and a switch unit. The first conductors extend in a first direction. The second conductors extend in a second direction intersecting the first direction. The switch unit includes a first switch circuit coupled to the first conductors and capable of interconnecting at least a portion of the first conductors to form sensing loops, and a second switch circuit coupled to the second conductors and capable of interconnecting at least a portion of the second conductors to form sensing loops. | 2012-07-05 |
| 20120169401 | Electrode Crossovers - In one embodiment, a touch sensor includes drive electrodes. The drive electrodes include drive electrode structures that are each coupled to an adjacent drive electrode structure by a first strip of conductive material. The touch sensor also includes sense electrodes. The sense electrodes include sense electrode structures that are each coupled to an adjacent sense electrode structure by a second strip of conductive material. The sense electrode structures are formed on a same layer as the drive electrode structures. The first or second strip of conductive material include one or more conductive crossovers that each couple two drive electrode structures to each other or couple two sense electrode structures to each other. | 2012-07-05 |
| 20120169402 | SEMICONDUCTOR DEVICE - A semiconductor device includes an electric fuse circuit and a program protective circuit. The electric fuse circuit includes a fuse element and a transistor connected together in series and placed between a program power supply and a grounding, and controlling sections. The program protective circuit is placed in parallel with the electric fuse circuit and between the program power supply and the grounding. When a surge voltage is applied between the program power supply and the grounding, the foregoing structure allows a part of a surge electric current can flow through the program protective circuit. | 2012-07-05 |
| 20120169403 | POWER HARVESTING IN OPEN DRAIN TRANSMITTERS - A transmitter having at least one channel comprising a first differential circuit driven by a differential data signal, the first differential circuit configured to output the differential data at a first and second output and a first control circuit coupled between the first differential circuit and the first and second output, the first control circuit driven by a drive voltage. | 2012-07-05 |
| 20120169404 | Exponential Charge Pump - An exponential multistage charge pump is disclosed. Node voltages in a pumpcell in one stage of the charge pump are used to control operation of clock drivers in a subsequent stage of the charge pump, thereby eliminating the need for level shifters. | 2012-07-05 |
| 20120169405 | METHOD AND APPARATUS FOR GENERATING VOLTAGE - An apparatus for generating an output voltage includes a boosting circuit configured to generate the output voltage by boosting an input voltage based on a boosting rate, and a pump level controller configured to control the boosting rate in response to the input voltage. | 2012-07-05 |
| 20120169406 | CHARGE PUMP AND DRIVER INTEGRATED CIRCUIT USING THE SAME - A charge pump including an output terminal, an external capacitor, and a switch module is provided. The output terminal is coupled to an internal capacitor disposed inside an integrated circuit (IC). The external capacitor is disposed outside the IC. The switch module, coupled to the external capacitor and the internal capacitor configured to control the external capacitor and the internal capacitor to charge and discharge by turns. In a first operating period, the switch module controls the external capacitor to charge without providing current to the output terminal, and controls the internal capacitor to discharge to the output terminal. | 2012-07-05 |
| 20120169407 | VOLTAGE GENERATOR AND NONVOLATILE MEMORY DEVICE INCLUDING THE SAME - A voltage generator includes a high voltage generator configured to include a plurality of pump circuits for generating various levels of a high voltage in response to clock signals, wherein the plurality of pump circuits are configured to receive enable signals corresponding to a level of voltage to be generated, where the enable signals are generated in response to internal operation signals. And a clock transfer circuit configured to generate a clock enable signal by comparing the high voltage and a reference voltage and to selectively provide the clock signals to each of the pump circuits in response to the clock enable signal and each of the enable signals. | 2012-07-05 |
| 20120169408 | VOLTAGE BOOSTER - A voltage booster device may include a plurality of multiplication stages arranged in a sequence so that an input terminal of each multiplication stage, with the exception of a first multiplication stage, is connected to an output terminal of a previous multiplication stage. Each multiplication stage may include pumping circuitry for accumulating an electric charge proportional to a pump voltage value of the multiplication stage. Each multiplication stage may also include a phase signal generating circuit for switching the multiplication stages between a transfer phase and a maintaining phase. In at least one of the stages, the pumping circuitry may include at least two series connected charge accumulators. A terminal may be shared between the charge accumulators and may be connected through biasing circuitry to an output terminal of a previous multiplication stage for forcing the charge accumulators within a threshold potential drop value. | 2012-07-05 |
| 20120169409 | CHARGE PUMP CIRCUITS, SYSTEMS, AND OPERATIONAL METHODS THEREOF - A charge pump circuit includes at least one stage between an input end and an output end. The at least one stage includes a first CMOS transistor coupled with a first capacitor and a second CMOS transistor coupled with a second capacitor. The at least one stage is capable of receiving a first timing signal and a second timing signal for pumping an input voltage at the input end to an output voltage at the output end. During a transitional period of the first timing signal and the second timing signal, the at least one stage is capable of substantially turning off at least one of the first CMOS transistor and the second CMOS transistor for substantially reducing leakage currents flowing through at least one of the first CMOS transistor and the second CMOS transistor. | 2012-07-05 |
| 20120169410 | TECHNIQUE TO MINIMIZE VDS MISMATCH DRIVEN VOLTAGE SWING VARIATION IN OPEN DRAIN TRANSMITTER - A switching circuit includes a source follower current mirror having an input, an output, a first source terminal, a bias terminal, and a second source terminal; a current source coupled to the input of the current mirror; an output terminal coupled to the output of the current mirror; a first bias transistor coupled to the first source terminal; a second bias transistor coupled to bias terminal of the current mirror; and a driver transistor coupled to the second source terminal. An input transistor in the current mirror is sized such that the input voltage is substantially independent of the supply voltage. | 2012-07-05 |
| 20120169411 | DEVICE AND METHOD FOR COMPENSATING FOR VOLTAGE DROPS - A device that includes at least one current consuming component. The device is characterized by including a compensation circuit adapted to compare between a voltage level at a sensing point within an integrated circuit and between a reference voltage derived from a voltage peak level at the sensing point; and to selectively increase the voltage at the sensing point in response to the comparison. A method for compensating for voltage drops in an integrated circuit, the method includes providing at least a first supply voltage to an integrated circuit; the method is characterized by including: comparing between a voltage level at a sensing point within an integrated circuit to a reference voltage derived from a voltage peak level at the sensing point; and selectively increasing the voltage at the sensing point in response to the comparison. | 2012-07-05 |
| 20120169412 | FAST POWER-ON BIAS CIRCUIT - Conventional bias circuits exhibit a number of limitations, including the time required to power-up a bias circuit following a low-power state. Large current surges in the supply network induce ringing, further complicating a power-up process. Example embodiments reduce power-up time and minimize current surges in the supply by selectively charging and discharging capacitance to the circuit during power-up and power-down of the bias circuit. | 2012-07-05 |
| 20120169413 | BANDGAP VOLTAGE REFERENCE CIRCUIT, SYSTEM, AND METHOD FOR REDUCED OUTPUT CURVATURE - A bandgap voltage reference circuit includes a current generation stage configured to generate a proportional to absolute temperature (PTAT) current and a complementary to absolute temperature (CTAT) current and to generate a reference current by combining the PTAT and CTAT currents. An output stage is coupled to the current generation stage and configured to combine the PTAT current and the CTAT current to generate a bandgap voltage reference. A curvature correction circuit is configured to generate a curvature correction current that mirrors the reference current generated from the PTAT and CTAT currents. The curvature correction current has a ratio relative to the reference current given by a current ratio parameter having value that is less than one, equal to one, or greater than one. In this way the value of the current ratio parameter can be varied to cancel a non-linear dependence on temperature of the bandgap voltage reference, thereby providing a curvature-compensated bandgap voltage reference. | 2012-07-05 |
| 20120169414 | METAMATERIAL POWER AMPLIFIER SYSTEMS - Power amplifying systems and modules and components therein are designed based on CRLH structures, providing high efficiency and linearity. | 2012-07-05 |
| 20120169415 | SEMICONDUCTOR DEVICE INCLUDING BODY CONNECTED FETS - A semiconductor device is disclosed. The structure includes: a first field-effect transistor (FET); and a second FET of similar polarity to the first FET, wherein a body of the first FET is electrically coupled to a body of the second FET, and a source of the first FET is electrically coupled to a source of the second FET, such that a body voltage of the second FET controls a body voltage of the first FET. | 2012-07-05 |
| 20120169416 | CIRCUIT AND METHOD FOR REDUCING INPUT LEAKAGE IN CHOPPED AMPLIFIER DURING OVERLOAD CONDITIONS - A chopper-stabilized amplifier ( | 2012-07-05 |
| 20120169417 | CURRENT GENERATOR - A current generating circuit for providing one or more than one load current is provided. The current generating circuit includes: one or more than one operational amplifier, coupled to a reference voltage source, wherein each positive input end of the one or more than one operational amplifier receives the reference voltage source; | 2012-07-05 |
| 20120169418 | LOW DISSIPATION AMPLIFIER - A low dissipation, low distortion amplifier includes a driver amplifier stage and a main output stage, with a plurality of impedance networks providing, among other things, feedback paths from outputs of the driver and main output stages to the input of the driver stage. The impedance networks also provide coupling paths from the outputs of the driver and main output stages to the load. The impedance networks can all be formed of resistors, capacitors, or network combinations thereof. An additional feedback path can be added from the load to the driver stage to flatten out the frequency response at low frequencies. The driver and main output stages may be operated in Class AB and B modes respectively, and/or in Class G or H modes. An intermediate amplifier driver stage may be added between the driver and main output stages. | 2012-07-05 |
| 20120169419 | Receiver with Wide Dynamic Range and Low Power Consumption - Some embodiments of the invention relate a circuit having a first and a second electrically connected voltage domains, respectively biased at different supply voltages (e.g., the first voltage domain biased at a low bias voltage and the second voltage domain biased at a second, different supply voltage). The apparatus further comprises a first DC current source coupled to one of the voltage domains (e.g., the first voltage domain having a low DC voltage potential) and a second DC current source coupled to the other voltage domain (e.g., the second voltage domain having a high DC voltage potential). The first and second DC current sources are configured to provide a DC cancellation current having a value that cancels a DC current generated by the potential difference between the first and second voltage domains. | 2012-07-05 |
| 20120169420 | CIRCUIT AND METHOD FOR AMPLIFYING A DIGITAL SIGNAL - An amplifier circuit includes an amplifier unit that is configured to receive an input signal and generate a switching output signal. A level shifter is configured to shift the amplitude of the input signal to have a shifted amplitude that is proportional to a peak-to-peak amplitude of the switching output signal. | 2012-07-05 |
| 20120169421 | AUDIO AMPLIFYING CIRCUIT WITH IMPROVED NOISE PERFORMANCE - An amplifying circuit includes a first circuit component configured to receive and amplify first and second input voltages to generate an output voltage. The first circuit component is formed by a first amplifier and a second amplifier. A second circuit component is configured to provide a first offset current that is associated with a first input current of the first amplifier. The first offset current compensates for variation in the first input current. A third circuit component is configured to provide a second offset current that is associated with a second input current of the second amplifier. The second offset current compensates for variation in the second input current. | 2012-07-05 |
| 20120169422 | Amplifier with Non-Linear Current Mirror - An amplifier with a non-linear current mirror comprises an amplification stage having an input terminal for an input signal as well as an output stage coupled to the amplification stage by a current mirror stage. The current mirror stage comprises at least one mirror transistor coupled to the amplification stage and at least one output transistor coupled to the output stage. The amplifier comprises two variable resistive elements, each of them connected in series to one of the mirror transistor and the output transistor. A tuning stage is adapted to tune the variable resistive elements in response to the input signal. | 2012-07-05 |
| 20120169423 | RADIO FREQUENCY AMPLIFIER CIRCUIT - A radio frequency amplifier circuit according to the present invention is for providing a radio frequency amplifier circuit with high output and high efficiency, and includes (i) a first harmonic processing circuit ( | 2012-07-05 |
| 20120169424 | Apparatus and Method for Providing Amplifier Linearity Information - An apparatus for providing a linearity information associated with an amplifier includes an operating state determinator and an evaluator. The operating state determinator is configured to obtain information describing a gain of the amplifier for at least one bias condition of the amplifier. The evaluator is configured to obtain the linearity information based on both the information describing the gain of the amplifier and information about the at least one bias condition of the amplifier using a gain-bias characteristic of the amplifier. A bias circuit including the apparatus for providing the linearity information is also disclosed. A corresponding method for providing the linearity information includes: using the information describing the gain of the amplifier and the information about the at least one bias condition with the gain-bias characteristics to determine a relation of a current operating point described by the information with respect to the gain-bias characteristic; and deriving the linearity information from said relation. | 2012-07-05 |
| 20120169425 | DC-DC CONVERTER SWITCHING TRANSISTOR CURRENT MEASUREMENT TECHNIQUE - A method is described comprising conducting a first current through a switching transistor. The method also comprises conducting a second current through a pair of transistors whose conductive channels are coupled in series with respect to each other and are together coupled in parallel across the switching transistor's conductive channel. The second current is less than and proportional to the first current. | 2012-07-05 |
| 20120169426 | MULTI-BAND FREQUENCY OSCILLATING DEVICE - An oscillating device is provided that has several oscillators. Each oscillator has a capacitive inductive resonant circuit and a flow-through conduction circuit having a negative flow-through conduction. The inductive elements of the oscillators are mutually coupled. Each oscillator also has short-circuit or not short-circuit the capacitive element of the oscillator. The oscillating device also has a controllable commutating means arranged to activate one oscillator at a time. | 2012-07-05 |
| 20120169427 | Force-mode distributed wave oscillator and amplifier systems - A Force-Mode Distributed Wave Oscillator (FMDWO) that provides accurate multiple phases of an oscillation, a Force Mode Distributed Wave Antenna as a radiating element, a Force-Mode Distributed Oscillator Amplifier (FMDOA) and an array of amplifiers capable of operating as a beam forming phased-array antenna driver. Two distinct force mode mechanisms, one delay-based and the other geometry-based, utilizing inverter amplifiers, inject an oscillation on independent conductor loops or rings via transmission lines forming a differential transmission medium for the oscillation wave. Once the oscillation wave is initiated through the forcing mechanisms, the oscillations continue uninterrupted independent of any external triggering. | 2012-07-05 |
| 20120169428 | AC COUPLED STACK INDUCTOR FOR VOLTAGE CONTROLLED OSCILLATOR - A voltage controlled oscillator (VCO) may include a stack of a plurality of non-connected inductors that are magnetically and/or electrically through capacitor (AC) coupled to each other and not directly physically connected to each other. The plurality of inductors includes a first inductor connected to a supply voltage and a second inductor connected to a VCO control voltage. The VCO may include a first varactor having a gate coupled to a first terminal of the second inductor to receive the VCO control voltage, a second varactor having a gate coupled to a second terminal of the second inductor to receive the VCO control voltage, and an oscillator sub-circuit coupled to first and second terminals of the first inductor. In one example implementation, the second inductor may contribute to the overall inductance of the inductor stack and provide AC decoupling and/or DC coupling between the VCO control voltage and the varactor(s). | 2012-07-05 |
| 20120169429 | CIRCUIT ARRANGEMENT FOR CREATING MICROWAVE OSCILLATIONS - An electronic oscillator of a circuit arrangement for creating microwave oscillations with two transistors as amplifier elements and with a resonator ( | 2012-07-05 |
| 20120169430 | INPUT APPARATUS ON CHIP FOR DIFFERENTIAL SIGNALS AND BALUN THEREOF - An on-chip balun is disclosed. The balun includes a first transmission line, a second transmission line and a coupling transmission line. A terminal of the first transmission line receives a first signal. A terminal of the second transmission line receives a second signal and the other terminal of the second transmission line is coupled to a reference voltage. A terminal of the coupling transmission line receives the reference voltage, and the other terminal is directly connected to the other terminal of the first transmission line. The coupling transmission line and the second transmission line are disposed in parallel for coupling the second signal to generate a coupling signal on the coupling transmission line. The first and second signals are differential signals and the phases of the second signal and the coupling signal are opposite. | 2012-07-05 |
| 20120169431 | MICROWAVE HARMONIC PROCESSING CIRCUIT - A microwave harmonic processing circuit includes (n−1) parallel open ended stubs differing in length, connected in parallel to an output terminal of a serial transmission line at a single point, and having predetermined electrical lengths corresponding to second to higher n-th (n is any integer) harmonics, respectively, the serial transmission line having an input terminal connected to an output terminal of a transistor and having a predetermined electrical length; a first strip conductor connecting the serial transmission line to two parallel open ended stubs of the (n−1) parallel open ended stubs at a single connecting point; a second strip conductor connecting the (n−3) parallel open ended stubs to each other at a single connecting point; a ground layer disposed between first strip conductor and second strip conductor; and a via electrically connecting a connecting portion of first strip conductor and a connecting portion of second strip conductor. | 2012-07-05 |
| 20120169432 | IC Package With Embedded Filters - Methods and systems for filters embedded in an integrated circuit package are disclosed and may include controlling filtering of signals within an integrated circuit via one or more filter components embedded within a multi-layer package bonded to the integrated circuit. The one or more filter components may be electrically coupled to one or more switchable capacitors within the integrated circuit. The filter components may include transmission line devices, microstrip filters, transformers, surface mount devices, inductors, and/or coplanar waveguide filters. The filter components may be fabricated utilizing metal conductive layers and/or ferromagnetic layers deposited on and/or embedded within the multi-layer package. The integrated circuit may be electrically coupled to the multi-layer package utilizing a flip-chip bonding technique. | 2012-07-05 |
| 20120169433 | DIGITAL SIGNAL FILTER - A passive filter circuit filters an input signal to attenuate an undesired frequency. The passive filter circuit includes a first stage and a second stage. The input to the first stage is the input signal. The first stage includes a first inductor and a first branch coupled to the output of the first inductor. The first branch includes a first capacitor and a second inductor. The first stage is coupled to the second stage. The second stage includes a third inductor and a second branch coupled to the output of the third inductor. The second branch includes a second capacitor. Other embodiments are also described and claimed. | 2012-07-05 |
| 20120169434 | FILTER - A filter includes a multilayer body including a plurality of insulator layers stacked on top of one another. Outer electrodes are provided on surfaces of the multilayer body. A first resonator is connected to a first one of the outer electrodes and includes a first coil. A second resonator is connected to a second one of the outer electrodes and includes a second coil. A third resonator includes a third coil that is magnetically coupled with the first and second coils. The first and second coils are respectively defined by coil conductor layers provided on an insulator layer. The third coil is defined by via hole conductors that penetrate through the insulator layer in a z-axis direction. | 2012-07-05 |
| 20120169435 | MICROWAVE AND MILLIMETER-WAVE COMPACT TUNABLE CAVITY FILTER - An electrical device that comprises a tunable cavity filter that includes a container and a post. The container encloses a cavity therein, wherein interior surfaces of the container are covered with a metal layer. The post is configured be movable through an opening in the container such that at least a portion of the post is locatable inside of the cavity. | 2012-07-05 |
| 20120169436 | MICROWAVE FILTER - A microwave filter is provided that includes a transmission line having a signal input port and a signal output port, a stub connected to the transmission line between the input port and the output port, and a spurline embedded in the stub. The microwave filter is configured to substantially attenuate a frequency while substantially passing at least one predetermined odd harmonic of the frequency. | 2012-07-05 |
| 20120169437 | COMPACT BANDPASS FILTER WITH NO THIRD ORDER RESPONSE - A bandpass filter passes a range of frequencies with low loss while suppressing frequencies above and below the passed range of frequencies. One or more spurlines is included into the existing structure of the bandpass filter so that a selected odd multiple of the passed frequency range is suppressed. | 2012-07-05 |
| 20120169438 | HDMI RECEIVER - An embodiment of a transmitter includes an amplifier having first and second differential output nodes, a first supply node, a first pull-up impedance having a first node coupled to the first differential output node and having a second node coupled to the supply node, and a second pull-up impedance having a first node coupled to the second differential output node and having a second node coupled to the supply node. An embodiment of a receiver includes an amplifier having first and second differential input nodes, a first supply node, a first pull-up impedance having a first node coupled to the first differential input node and having a second node coupled to the supply node, and a second pull-up impedance having a first node coupled to the second differential input node and having a second node coupled to the supply node. In an embodiment, the transmitter and receiver are capacitively coupled to one another. | 2012-07-05 |
| 20120169439 | BATTERY AND WIRELESS COMMUNICATION APPARATUS - Used is a battery a battery ( | 2012-07-05 |
| 20120169440 | MOVABLE CONTACTOR ASSEMBLY FOR CURRENT LIMITING TYPE CIRCUIT BREAKER - A movable contactor assembly for a current limiting type circuit breaker comprises a movable contactor having a pair of curved protrusions having cam profiles, a shaft to rotatably support the movable contactor located therein, a pair of contact levers each having a contact surface contactable with the curved protrusion of the movable contactor and a pair of spring supporting recess portions and a pair of springs each having both end portions supported by the spring supporting recess portions, the pair of springs applying an elastic force as contact pressure for maintaining a contact state between the movable contactor and the stationary contactor when the movable contactor is located at the first position, and applying the elastic force in a direction to separate the movable contactor from the stationary contactor when the movable contactor is moved over a dead point while rotating toward the second position. | 2012-07-05 |
| 20120169441 | ELECTROMAGNET DEVICE AND SWITCH DEVICE USING ELECTROMAGNET DEVICE - In a switch device in which the main circuit contact sections of the switch device, an insulating rod, a driving rod, a contact pressure spring, an open spring, and an electromagnet are all coaxially arranged, a problem exists in that the axial dimension of the switch device becomes large. The present invention has been made to solve the aforementioned problem. An object is to obtain an electromagnet device and a switch device using the electromagnet device, in which shortening the axial dimension of the switch device is achieved by arranging the main circuit contact sections of the switch device, the insulating rod, the driving rod, the contact pressure spring, the open spring, and a part of the electromagnet in the same axial range. Particularly, the open spring and the electromagnet are arranged in the same axial region. | 2012-07-05 |
| 20120169442 | VIBRATION GENERATING SHOE AND VIBRATION DEVICE THEREOF - The present invention relates to a vibration generating shoe including: an upper part; an outsole part disposed on the underside of the upper part; and a vibration device having a vibration plate adapted to transmit vibrations to the shoe, a first magnet attached to the vibration plate, a second magnet disposed above the first magnet in such a manner as to have a repulsive force against the top surface of the first magnet, and a third magnet disposed below the first magnet in such a manner as to have a repulsive force against the underside surface of the first magnet, whereby a portion of the vibration plate to which the first magnet is fixed is vibrated between the second magnet and the third magnet. | 2012-07-05 |
| 20120169443 | HIGH POWER INDUCTANCE DEVICE - A high power inductance device enables a large ferrite magnetic core to be manufactured at low cost and with ease and improves heat radiation efficiency to reduce an increase in the temperature of the core. The inductance device has a ferrite magnetic core and a winding wire wound around the ferrite magnetic core and is mounted on a heat radiation structure through at least one of the front surfaces of the ferrite magnetic core. The ferrite magnetic core is made of a core aggregate obtained by arranging side by side a plurality of ferrite cores | 2012-07-05 |
| 20120169444 | LAMINATED INDUCTOR AND METHOD OF MANUFACTURING THE SAME - There is provided is a laminated inductor, including: a ceramic main body in which a plurality of ceramic layers are stacked; a plurality of inner electrodes formed on the plurality of ceramic layers and having a contact area with the ceramic layer that is 10% or less than that of the entire area of the ceramic layer; and via electrodes having a coil structure by connecting the plurality of inner electrodes. | 2012-07-05 |
| 20120169445 | TRANSFORMER AND FLAT PANEL DISPLAY DEVICE HAVING THE SAME - There are provided a transformer and a flat panel display device having the same. The transformer includes: a bobbin, around which a coil is wound; and an input/output terminal installed in the bobbin, a lead portion of the coil wound around the bobbin being connected to the input/output terminal, wherein the input/output terminal has a stopper portion protruded from at least one face and limiting a winding position of the coil such that the lead portion of the coil is wound therearound to be separated from the bobbin. | 2012-07-05 |
| 20120169446 | TRANSFORMER CAPABLE OF MAINTAINING HEIGHT - A transformer capable of maintaining its height is provided. The transformer is formed on a circuit board having a receiving hole. The transformer comprises a winding module, two magnetic core modules contacting and holding the winding module, a plurality of pins and at least one supporting means. The winding module comprises a winding baseboard and a winding pillar where a winding structure is formed thereon. The winding pillar is received in the receiving hole. Each of the pins comprises a first bent part separating the corresponding pin into a first portion connected to the winding baseboard and a second portion connected to the circuit board around the receiving hole. The supporting means is formed between the first portion of at least one of the pins and the circuit board to contact the first portion and the circuit board to maintain the distance between them. | 2012-07-05 |
| 20120169447 | NANOCOMPOSITE POWDER FOR INNER ELECTRODE OF MULTILAYER CERAMIC ELECTRONIC DEVICE AND FABRICATING METHOD THEREOF - There are disclosed a nanocomposite powder for an inner electrode of a multilayer ceramic electronic device and a manufacturing method thereof. The nanocomposite powder for an inner electrode of a multilayer ceramic electronic device includes a first metal particle having electrical conductivity, and a second metal coating layer formed on a top surface or a bottom surface of the first metal particle and having a higher melting point than that of the first metal particle. | 2012-07-05 |
| 20120169448 | TRANSFORMER CAPABLE OF ADJUSTING HEIGHT - A transformer capable of adjusting its height is provided. The transformer is formed on a circuit board having a receiving hole. The transformer comprises a winding module, two magnetic core modules, a plurality of pins and a plurality of supporting bulges. The winding module comprises a winding baseboard and a winding pillar where a winding structure is formed thereon. The winding pillar is received in the receiving hole. The winding baseboard further comprises a corresponding surface heading to the circuit board. The magnetic core modules contact and hold the winding module. The pins are formed on the edge of the to winding baseboard to be connected to the circuit board around the receiving hole. The supporting bulges are formed between the corresponding surface and the circuit board, wherein the height of the corresponding surface relative to the circuit board is adjusted according to the supporting bulges. | 2012-07-05 |
| 20120169449 | INDUCTOR - An inductor includes a first core, a conducting wire, a second core and a first lead frame. There is an accommodating space formed on a first side of the first core and there is a recess portion formed on a second side of the first core, wherein the first side is opposite to the second side. The first core has a first height. The conducting wire is disposed in the accommodating space. The second core is disposed on the first side of the first core and covers the accommodating space. The first lead frame has an embedded portion embedded in the recess portion. The embedded portion has a second height. After embedding the embedded portion in the recess portion of the first core, a total height of the embedded portion and the first core is smaller than the sum of the first height and the second height. | 2012-07-05 |
| 20120169450 | LEAD-OUT TUBE - A lead-out tube for high-voltage transformers is disclosed along with a method of manufacturing a lead-out tube. The lead-out tube can include a shielding tube of an electrically conductive material which extends a hollow-cylindrically around an at least sectionally curved path in an axial direction. A hollow-cylindrical shaped electrical insulating layer can be arranged at a first radial distance around the shielding tube along the axial extent. Sectionally flexible strips can be arranged along the at least sectionally curved path adjacent to one another at a second radial distance around the shielding tube. The insulating layer can be wound from a tape-like insulating material around the sectionally flexible strips. | 2012-07-05 |
| 20120169451 | SHAPE MEMORY ALLOY ACTUATED CIRCUIT BREAKER - A thermal trip unit for a circuit breaker having a primary conductive path for conducting a load current is provided. The thermal trip unit comprises a shape memory alloy (SMA) member adapted to change from a first shape to a second shape at a predetermined thermal condition, a holding member coupled electrically in series with the circuit breaker primary conductive path, said holding member arranged to operatively support said SMA member, wherein said SMA member is configured and disposed within the circuit breaker to trigger a trip response of the circuit breaker at said predetermined thermal condition. | 2012-07-05 |
| 20120169452 | ESD PROTECTION DEVICE AND MANUFACTURING METHOD THEREFOR - An ESD protection device includes opposed electrodes in a ceramic base material and a discharge auxiliary electrode in contact with each of the opposed electrodes which is arranged so as to provide a bridge from the opposed electrode on one side to the opposed electrode on the other side, the discharge auxiliary electrode includes metallic particles, semiconductor particles, and a vitreous material, and bonding is provided through the vitreous material between the metallic particles, between the semiconductor particles, and between the metallic particles and the semiconductor particles. The metallic particles have an average particle diameter X of about 1.0 μm or more, and the relationship between the thickness Y of the discharge auxiliary electrode and the average particle diameter X of the metallic particles satisfies about 0.5≦Y/X≦ about 3. | 2012-07-05 |
| 20120169453 | ELECTRONIC LOCK WITH POWER FAILURE CONTROL CIRCUIT - An electronic lock with power failure control circuit includes a lock mechanism having a latchbolt movable between extended and a retracted positions and an electrically powered lock actuator to lock and unlock the latchbolt. The power failure control circuit includes a microcontroller and the lock is connected to a primary power source and an auxiliary power source, preferably supercapacitors and charger that can be turned on by the microcontroller and off when the charger signals a full charge. A power monitor circuit detects low voltage on the primary power supply and sets a power failure interrupt causing the microcontroller to execute power failure instructions that control the actuator so that the lock is placed into a desired locked or unlocked final state during the power failure. upon detection of the return of good power, the system resets the lock. | 2012-07-05 |
| 20120169454 | LISTENING SYSTEM COMPRISING AN ALERTING DEVICE AND A LISTENING DEVICE - A listening system that eases the acknowledgement of ‘alarm signals’, as e.g. issued by alarm indicators, in the environment of a user in difficult listening situations. The listening system is adapted to issue specific ALARM mode signals to the user corresponding to said external alarm signals, when said listening system is in an ALARM mode. An advantage of the present system is that a user is able to take notice of alarms from normal indicators even in case of a hearing impairment and/or when located in a noisy environment. The system may e.g. be used for the hearing instruments, ear protection devices, earphones, headsets or combinations thereof. | 2012-07-05 |
| 20120169455 | MASS SENSING PLATFORM - An apparatus is disclosed comprising a platform operable to support a human. The apparatus also includes at least one cable suspending the platform. The apparatus also includes an elongation sensor engaged with the at least one cable. The elongation sensor is operable to emit a signal in response to elongation of the at least one cable. A method of using the apparatus is also disclosed. The method includes the step of positioning the platform adjacent to one of a machine and a path along which the machine moves. The method also includes the step of detecting a mass on the platform by emitting the signal from the elongation sensor in response to elongation of the at least one cable. The method also includes the step of disengaging the machine in response to the detecting step. | 2012-07-05 |
| 20120169456 | NUCLEAR GAUGES AND METHODS OF CONFIGURATION AND CALIBRATION OF NUCLEAR GAUGES - Nuclear gauges and method of configuration and methods of calibrations of the nuclear gauges are provided. The nuclear gauges are used in measuring the density and/or moisture of construction-related materials. The nuclear gauge can include a gauge housing having a vertical cavity therethrough and at least one radiation detector located within the housing. The nuclear gauge can include a vertically moveable source rod and a radiation source operatively positioned within a distal end of the source rod. | 2012-07-05 |
| 20120169457 | METHOD AND SYSTEM FOR DYNAMICALLY ASSIGNING ACCESS RIGHTS - The system and method take changes in a person's or groups' status and by following a series of steps (rules) ensures that the person or groups are given proper access to a secure location. The system has at least one access control device for controlling the flow of persons in a physical setting to at least one secure area. An access control database of the system contains information regarding criteria for allowing access to the at least one secure area. A control system receives information from the at least one access control device and compares it to the access control database to determine if access is to be granted. A rules unit gathers information from various sources and updates the access control database. | 2012-07-05 |
| 20120169458 | Method and System for Monitoring Physical Security and Notifying if Anomalies - A method and system for monitoring access requests for physical access to a location includes a plurality of access control devices for control accessing to specific locations. The system determines if access is authorized based on comparing information associated with the request with a database. Access is granted to a physical location based on the comparison of information. In addition, the system compares an access request to prior access requests. The system determines if the access request is an anomaly from previous requests. If the access request is an anomaly from previous requests, the system notifies an operator that the access request is an anomaly. | 2012-07-05 |
| 20120169459 | SYSTEM AND METHOD FOR PASSIVELY ACQUIRING EXISTING CUSTOMERS' MOBILE PHONE NUMBERS FROM CUSTOMER SERVICE LOGS - An entity passively acquires an existing customer's mobile phone number and links the customer's mobile phone number to the customer's account without requesting the customer to actively provide customer identifying information. This is accomplished by capturing the customer's mobile phone number when the customer uses a mobile phone to contact the entity and checking whether the captured mobile phone number is in a customer database. If the captured mobile phone number is not in the customer database, the customer using the mobile phone number may be validated by determining that the customer corresponds to a particular customer account and associating the captured mobile phone number with the particular customer account. For example, the validation of the customer may include analyzing entries in the service log to identify phone numbers, determining whether the identified phone numbers are mobile numbers or landline numbers, determining who the identified phone numbers belong to, and determining whether the identified person corresponds to an account in the customer database. If the captured mobile phone number is in the customer database, the customer using the mobile phone number may be validated against the corresponding customer account record to establish a confidence score. | 2012-07-05 |
| 20120169460 | Multiparty Controlled Remote Security Lock System - A multiparty controlled remote security lock is disclosed. The embodiments herein relate to security systems and, more particularly, to remotely controlled biometric based mechanisms in security systems. In order to operate the remote security lock at least one OC and a plurality of RCs are employed. Further, the OC is located at the site of the lock and the RCs may be located away from the site of the lock. The remote security lock employs 2-factor authentication mechanisms using smartcard access and biometric means. A method for randomized selection of a subset of controllers (RCs) who operate the lock is used. The randomization enhances the scalability of the system, while keeping the security strength of the system as that of choosing the full set of controllers for operating the lock. | 2012-07-05 |
| 20120169461 | ELECTRONIC PHYSICAL ACCESS CONTROL WITH REMOTE AUTHENTICATION - The system has an authorizing device, such as a cellular telephone, and a mechanism for receiving information related to a particular facility and the user's access rights based on the location of the authorizing device. The authorizing device is placed in proximity to a secured portal. The user is required to authenticate theirself to the authorizing device via biometric and/or a PIN. The authorizing device then sends a signal to a locking device associated with the secured portal. | 2012-07-05 |
| 20120169462 | METHOD AND APPARATUS FOR ACCESS AUTHENTICATION USING MOBILE TERMINAL - An access authentication method and apparatus in which access authentication is performed using positional data associated with access information data. | 2012-07-05 |
| 20120169463 | APPARATUS AND METHOD FOR AUTHENTICATING BIOMETRIC INFORMATION - A method for biometric authentication and a system using the same are provided. The biometric authentication system of the present invention separates pre-registered biometric information of a user into a plurality of separated biometric information, disperses them to a plurality of databases and manages them. Accordingly, when a user authentication process is needed, the biometric authentication system performs an authentication by obtaining the separated biometric information that are managed by a plurality of databases and composing registered biometric information. The present invention reduces the risk of leakage of biometric information of a user due to hacking or theft since it allows biometric information to be separated, disperse and managed, which conventionally is store as a single file on a server, a database or a security token. | 2012-07-05 |
| 20120169464 | BIOMETRIC AUTHENTICATION DEVICE, BIOMETRIC AUTHENTICATION SYSTEM, AND BIOMETRIC AUTHENTICATION METHOD - A biometric authentication device includes a photographing unit configured to photograph a biological body and acquire biological body information; an authentication unit configured to match registered biological body information that is registered in advance with the biological body information and perform authentication; a posture determination unit configured to determine steadiness of a posture of the biological body based on history of posture information relevant to the posture of the biological body when photographed; and an update determination unit configured to determine to update the registered biological body information when the posture determination unit determines that the posture of the biological body is steady. | 2012-07-05 |
| 20120169465 | Vehicle Apparatus Control System and Method Thereof - A vehicle apparatus control system is used to control at least one piece of vehicle equipment in a vehicle, and includes a data storage module, an image capture module, a face recognition module, and a control module. The data storage module stores a plurality of facial expression parameters therein. The face recognition module detects a face image from an image captured by the image capture module and determines a facial expression in the face image based on the facial expression parameters. The control module controls the vehicle equipment to enter into a first state based on the facial expression. When the facial expression is recognized as a sleeping facial expression, the control module controls the vehicle seat to move into a horizontal position and mutes a vehicle stereo. A vehicle apparatus control method for controlling at least one piece of vehicle equipment in a vehicle is also disclosed. | 2012-07-05 |
| 20120169466 | SYSTEM AND METHOD FOR TRANSMITTING MESSAGES RECEIVED FROM A PAGING NETWORK ON A PAGING DEVICE TO ELECTRONIC DEVICES - Systems, methods, and media are provided for transmitting a message received from a paging network on a paging device to wireless or other electronic devices. The paging device establishes a radio connection with the wireless device and transmits the received messages to the wireless device through the established radio connection. In response to receiving a message from the paging device, the wireless device sends an acknowledgment to the paging network that the message was received and displays the message. | 2012-07-05 |
| 20120169467 | PATIENT ALERT MANAGEMENT SYSTEM - A patient alert management system includes a remote alert monitor at a location, an alert management and reporting server, and a portable communications device. The remote alert monitor generates an alert in response to an internal patient care timer or receiving an alert from a patient care device at the location of the remote alert monitor and communicates the alert to the alert management and reporting server. The alert management and reporting server sends a message to the portable communications device including a description of the alert and the location. The portable communications device displays the description and location to a caregiver. The caregiver goes to the location and cancels the alert via the remote alert monitor. The remote alert monitor sends an alert cancellation to the alert management and reporting server in the alert management and reporting server cancels the alert in response to receiving the alert cancellation. | 2012-07-05 |
| 20120169468 | MULTIPLE RADIO FREQUENCY NETWORK NODE RFID TAG - In embodiments of the present invention improved capabilities are described for a Radio Frequency ID (RFID) tag that contains multiple Radio Frequency (RF) network nodes that provide enhanced memory capabilities, redundant functionality, and multiple frequency capabilities to the RFID tag using an inter-RF network node communication connection. The inter-RF network node communication may allow the coordination of RFID tag memory and functionality. | 2012-07-05 |
| 20120169469 | MULTIPLE RADIO FREQUENCY NETWORK NODE RFID TAG - In embodiments of the present invention improved capabilities are described for a Radio Frequency ID (RFID) tag that contains multiple Radio Frequency (RF) network nodes that provide enhanced memory capabilities, redundant functionality, and multiple frequency capabilities to the RFID tag using an inter-RF network node communication connection. The inter-RF network node communication may allow the coordination of RFID tag memory and functionality. | 2012-07-05 |
| 20120169470 | RFID SYSTEM FOR CHECKING MEDICAL ITEMS - A RFID system for checking medical items includes a processing unit; two RFID readers connected with the processing unit; at least an antenna connected to each of the RFID readers; and a plurality of RFID tags being respectively attached to a plurality of medical items. The RFID tags are configured to store identification codes that respectively and uniquely correspond to the medical items that the RFID tags are attached to. The RFID readers are configured to respectively read the identification codes of the medical items from the RFID tags through the antennas before and after a surgical operation and send the identification codes to the processing unit. The processing unit is configured to receive the identification codes and determine the completeness of the medical items based on the received identification codes. A method for checking medical items with the RFID system is also provided. | 2012-07-05 |
