| 27th week of 2012 patent applcation highlights part 16 |
| Patent application number | Title | Published |
|---|
| 20120168770 | HEAT DISSIPATION STRUCTURE OF CHIP - A heat dissipation structure of a chip in the field of microelectronics is provided. The heat dissipation structure includes a P-type superlattice layer and an N-type superlattice layer formed over an upper surface of the chip by oxidation isolation. The P-type superlattice and the N-type superlattice are isolated by silicon oxide. Through a contact hole the P-type superlattice is electrically connected to a metal layer that is applied with a low potential in the chip, and a metal layer to be connected with an external power source is formed over the P-type superlattice. Through a contact hole the N-type superlattice is electrically connected to a metal layer that is applied with a high-potential power source in the chip, and a metal layer to be connected with an external power source is formed over the N-type superlattice. The potential of the external power source connected with the P-type superlattice is lower than that of the external power source connected with the N-type superlattice. The present invention can achieve heat dissipation of the chip and meanwhile prevent the ambient heat from transferring into the chip, by using the feature that the superlattice has a low thermal conductivity and phonon-localization-like behavior. | 2012-07-05 |
| 20120168771 | SEMICONDUCTOR ELEMENT, HEMT ELEMENT, AND METHOD OF MANUFACTURING SEMICONDUCTOR ELEMENT - A semiconductor device is provided such that a reverse leak current is suppressed, and a Schottky junction is reinforced. The semiconductor device includes an epitaxial substrate formed by laminating a group of group-III nitride layers on a base substrate in such a manner that (0001) surfaces of said group-III nitride layers are substantially parallel to a substrate surface, and a Schottky electrode, in which the epitaxial substrate includes a channel layer formed of a first group-III nitride having a composition of In | 2012-07-05 |
| 20120168772 | PASSIVATION OF ALUMINUM NITRIDE SUBSTRATES - The present invention provides methods of protecting a surface of an aluminum nitride substrate. The substrate with the protected surface can be stored for a period of time and easily activated to be in a condition ready for thin film growth or other processing. In certain embodiments, the method of protecting the substrate surface comprises forming a passivating layer on at least a portion of the substrate surface by performing a wet etch, which can comprise the use of one or more organic compounds and one or more acids. The invention also provides aluminum nitride substrates having passivated surfaces. | 2012-07-05 |
| 20120168773 | SEMICONDUCTOR-ON-DIAMOND DEVICES AND ASSOCIATED METHODS - Semiconductor-on-diamond (SOD) substrates and methods for making such substrates are provided. In one aspect, a method of making an SOD substrate may include depositing a base layer onto a lattice-orienting silicon (Si) substrate such that the base layer lattice is substantially oriented by the Si substrate, depositing a semiconductor layer onto the base layer such that the semiconductor layer lattice is substantially oriented with respect to the base layer lattice, and disposing a layer of diamond onto the semiconductor layer. The base layer may include numerous materials, including, without limitation, aluminum phosphide (AlP), boron arsenide (BAs), gallium nitride (GaN), indium nitride (InN), and combinations thereof. Additionally, the method may further include removing the lattice-orienting Si substrate and the base layer from the semiconductor layer. In one aspect, the Si substrate may be of a single crystal orientation. | 2012-07-05 |
| 20120168774 | SILICON CARBIDE SUBSTRATE AND METHOD FOR MANUFACTURING SAME - A silicon carbide substrate and a method for manufacturing the silicon carbide substrate are obtained, each of which achieves reduced manufacturing cost of semiconductor devices using the silicon carbide substrate. A method for manufacturing a SiC-combined substrate includes the steps of: preparing a plurality of single-crystal bodies each made of silicon carbide (SiC); forming a collected body; connecting the single-crystal bodies to each other; and slicing the collected body. In the step, the plurality of SiC single-crystal ingots are arranged with a silicon (Si) containing Si layer interposed therebetween, so as to form the collected body including the single-crystal bodies. In the step, adjacent SiC single-crystal ingots are connected to each other via at least a portion of the Si layer, the portion being formed into silicon carbide by heating the collected body. In step, the collected body in which the SiC single-crystal ingots are connected to each other is sliced. | 2012-07-05 |
| 20120168775 | STRESS ENHANCED TRANSISTOR DEVICES AND METHODS OF MAKING - A transistor device includes a gate conductor spaced above a semiconductor substrate by a gate dielectric, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the channel region comprises undercut areas under the gate conductor; a stressed material embedded in the undercut areas of the channel region under the gate conductor; and epitaxially grown source and drain regions disposed in the recessed regions of the semiconductor substrate laterally adjacent to the stressed material. | 2012-07-05 |
| 20120168776 | LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - To prevent a point defect and a line defect in forming a light-emitting device, thereby improving the yield. A light-emitting element and a driver circuit of the light-emitting element, which are provided over different substrates, are electrically connected. That is, a light-emitting element and a driver circuit of the light-emitting element are formed over different substrates first, and then electrically connected. By providing a light-emitting element and a driver circuit of the light-emitting element over different substrates, the step of forming the light-emitting element and the step of forming the driver circuit of the light-emitting element can be performed separately. Therefore, degrees of freedom of each step can be increased, and the process can be flexibly changed. Further, steps (irregularities) on the surface for forming the light-emitting element can be reduced than in the conventional technique. | 2012-07-05 |
| 20120168777 | LED PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - An LED package structure includes: a carrier; at least a first protruding portion and a plurality of electrical contacts formed on the carrier; a plurality of LED chips disposed on the first protruding portion and on the carrier in a region free from the first protruding portion, respectively; a plurality of bonding wires electrically connecting the | 2012-07-05 |
| 20120168778 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An OLED display includes a substrate, a first electrode on the substrate, an organic emission layer on the first electrode, a second electrode on the organic emission layer, an insulating layer substantially covering the second electrode and having an opening that exposes a center portion of the second electrode, and a power supply electrically coupled with the second electrode through the opening of the insulating layer and configured to supply power to the second electrode. | 2012-07-05 |
| 20120168779 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND MANUFACTURING METHOD THEREOF - An organic light emitting diode display includes: a substrate; a display device formed on the substrate, and including a common power line and a common electrode; a sealing substrate attached to the substrate by a junction layer surrounding the display device, the sealing substrate sealing the display device with the substrate; a first conductor formed over an outer side, a lateral side, and an inner side of the sealing substrate, the first conductor being for supplying a first electrical signal to the common power line; a second conductor formed on the inner side, the lateral side, and the outer side of the sealing substrate, the second conductor being for supplying a second electrical signal to the common electrode; and a plurality of arranging members formed into the sealing substrate, the first conductor, and the second conductor, the arranging members being for arranging positions of the sealing substrate, the first conductor, and the second conductor. | 2012-07-05 |
| 20120168780 | RESIN FOR TRANSPARENT ENCAPSULATION MATERIAL, AND ASSOCIATED ENCAPSULATION MATERIAL AND ELECTRONIC DEVICE - A resin for an encapsulation material includes a first polysiloxane including hydrogen bound to silicon (Si—H) at its terminal end, and a second polysiloxane including an alkenyl group bound to silicon (Si-Vi) at its terminal end, wherein a ratio (Si—H/Si-Vi) of hydrogen bound to silicon (Si—H) in the first polysiloxane to the alkenyl group bound to silicon (Si-Vi) in the second polysiloxane is about 1 to about 1. | 2012-07-05 |
| 20120168781 | LIGHT-EMITTING-ELEMENT ENCAPSULATING COMPOSITION, LIGHT-EMITTING DIODE AND LIQUID-CRYSTAL DISPLAY DEVICE - An encapsulating composition for a light emitting element, a light emitting diode (LED) and a liquid crystal display device (LCD) are provided. A silicone-cured product included as a main ingredient and a conductivity-providing agent having excellent compatibility and capable of providing superior conductivity can be used to significantly reduce the surface resistivity of the silicone-cured product. Therefore, the encapsulating composition for a light emitting element, the LED and the LCD can be useful in solving the problems regarding attachment of a foreign substance such as dust due to static electricity, and degradation of transparency since the composition has low surface resistivity when used as a semiconductor encapsulation material for an LED, and also in providing a cured product having excellent properties such as light resistance, heat resistance, durability and optical transparency. | 2012-07-05 |
| 20120168782 | LIGHT EMITTING DIODE, LIGHT EMITTING DIODE LAMP, AND ILLUMINATING APPARATUS - Disclosed is a light-emitting diode, which has an infrared emission wavelength of 700 nm or more, excellent monochromatism characteristics, and high output and high efficiency and excellent humidity resistance. The light-emitting diode is provided with: a light-emitting section ( | 2012-07-05 |
| 20120168783 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device includes a substrate, a plurality of pixels on the substrate having a first region configured to emit light and a second region configured to transmit external light, a plurality of pixel circuit units, a plurality of first electrodes, a first organic layer on the plurality of first electrodes, a second organic layer on the first organic layer, the second organic layer including an emission layer, a third organic layer on the second organic layer, the third organic layer being positioned in the first region and outside a central portion of the second region, and a second electrode having a first portion only on the third organic layer. | 2012-07-05 |
| 20120168784 | Two-Transistor Pixel Array - A two-transistor (2T) pixel comprises a chemically-sensitive transistor (ChemFET) and a selection device which is a non-chemically sensitive transistor. A plurality of the 2T pixels may form an array, having a number of rows and a number of columns. The ChemFET can be configured in a source follower or common source readout mode. Both the ChemFET and the non-chemically sensitive transistor can be NMOS or PMOS device. | 2012-07-05 |
| 20120168785 | DISPLAY DEVICE - The present invention provides a display device using a copper wiring and having high display properties in which without preventing a higher aperture ratio of the pixel, coloring of a screen due to reflected light of external light produced within the display device can be prevented. The display device according to the present invention is a display device including a plurality of pixel regions, wherein each of the pixel regions includes a copper wiring containing copper or an alloy thereof, and a red-colored layer and a colored layer of another color; and an area of the copper wiring is smaller in the pixel region including the red-colored layer than in the pixel region including the colored layer of another color, the area of the copper wiring reflecting incident light entering from the display surface side of the display device. | 2012-07-05 |
| 20120168786 | Potted Optoelectronic Module Having a Plurality of Semiconductor Components and Method for Producing an Optoelectronic Module - An optoelectronic semiconductor component comprising: a main body ( | 2012-07-05 |
| 20120168787 | ORGANIC ELECTROLUMINESCENT DISPLAY DEVICE - An organic electroluminescent display device which satisfies all of chromatic purity, transmission factor, reduction in reflection, and reflected color in balance at low cost is provided. An organic electroluminescent (EL) display device includes: a main substrate; an organic light-emitting layer formed above the main substrate and including a red light-emitting layer which emits red light, a green light-emitting layer which emits green light, a blue light-emitting layer which emits blue light, and a bank which is a non-light emitting region; a first light-adjusting layer formed above the blue light-emitting layer and the bank, which selectively transmits the blue light and selectively absorbs the green light and the red light; and a second light-adjusting layer formed above the red light-emitting layer and the green light-emitting layer, which selectively absorbs the blue light and selectively transmits the green light and the red light. | 2012-07-05 |
| 20120168788 | Backlight Device and Display Device - It is an object to manufacture a highly reliable backlight device with less color unevenness and less luminance unevenness, and a high-performance and highly reliable display device including the backlight device, which can display a high quality image. A light emitting diode (LED) is used as a light source of a backlight device and thermoelectric elements are provided in a chassis for holding the light emitting diode so as to surround the light emitting diode (the thermoelectric elements are provided under the light emitting diode and on the four sides thereof). A temperature in the backlight device is adjusted by cooling and heating by the thermoelectric elements. | 2012-07-05 |
| 20120168789 | High-Transparent LED Display Module - A high-transparency LED display module, which comprises a transparent glass plate, and an LED luminous unit and a main driving unit which are lined linearly; the transparent glass plate is provided with lamp holes which are lined based on pixel pitch, and the lamp holes which are horizontally or vertically lined along the transparent glass plate are provided with wiring ducts which are vertical to the surface of the transparent glass plate; the LED luminous unit comprises a driving PCB board and an LED luminous bodies which are electrically connected with the PCB board; the driving PCB boards are inlaid in the wiring ducts of the transparent glass plate; the surface of the driving PCB board is vertical to the surface of the transparent glass plate; the positions of the LED luminous bodies correspond to the positions of the lamp holes; and the light of the LED luminous bodies is axially vertical to the surface of the transparent glass plate. In the invention, the main PCB board is horizontally installed on an organic glass plate, thus greatly reducing the blockage of the PCB board to the light and improving the transparency of the module. | 2012-07-05 |
| 20120168790 | DISPLAY DEVICE STRUCTURE AND MANUFACTURING METHOD THEREOF - A display device structure includes an active device, a passivation layer, a pixel electrode and a first conductive material. The passivation layer covers the active device and has a first through hole exposing a portion of the active device. The pixel electrode is disposed on the passivation layer, and the pixel electrode is a non-thin-film electrode constituted by a plurality of micro-conductive structures. The first conductive material is filled in the first through hole and electrically connected to the exposed active device. The pixel electrode is electrically connected to the first conductive material. | 2012-07-05 |
| 20120168791 | METHOD FOR PREVENTING ELECTROSTATIC BREAKDOWN, METHOD FOR MANUFACTURING ARRAY SUBSTRATE AND DISPLAY SUBSTRATE - An embodiment of the disclosed technology provides a method for preventing electrostatic breakdown during the manufacturing process of the array substrate. The method comprises: when forming a conductive pattern of a substrate, connecting conductive lines for forming the conductive pattern with a closed conductive ring on a same layer as the conductive lines in a peripheral region of the substrate, and wherein when electrostatic charges are generated over the metal line, the electrostatic charges are led to the closed conductive ring. | 2012-07-05 |
| 20120168792 | HETEROJUNCTION STRUCTURES OF DIFFERENT SUBSTRATES JOINED AND METHODS OF FABRICATING THE SAME - In one embodiment, a heterojunction structure includes a first substrate; a second substrate comprising an electrode pad, the second substrate joined to the first substrate by an adhesive layer interposed between the first and second substrates, the first substrate and the adhesive layer having a via hole penetrating therethrough to expose a region of the electrode pad; a connection electrode disposed in the via hole and contacting the electrode pad; and an insulation layer electrically insulating the connection electrode from the first substrate. One of the first and second substrates has a thermal expansion coefficient different than a thermal expansion coefficient of the other of the first and second substrates, and at least one of the adhesive layer or the insulation layer comprises an organic material. | 2012-07-05 |
| 20120168793 | LIGHT EMITTING CHIP AND METHOD FOR MANUFACTURING THE SAME - A light emitting chip includes a substrate, an epitaxial structure comprising a first semiconductor layer, a light emitting layer and a second semiconductor layer, a current conducting structure formed on a bottom side of the first semiconductor layer of the epitaxial structure, and heat conducting protrusions formed on a top side of the substrate. Each of the heat conducting protrusions includes a carbon nanotube layer vertically grown thereon. The heat conducting protrusions are embedded into the current conducting structure to thermally connect with the first semiconductor layer. A method for manufacturing the light emitting chip is also disclosed. | 2012-07-05 |
| 20120168794 | LIGHT-EMITTING DIODE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A light-emitting diode (LED) structure and a method for manufacturing the same. In one embodiment, the LED structure includes a carrying component, an LED chip, a first conductivity type electrode and a second conductivity type electrode. The carrying component includes a carrier, a sidewall disposed on the carrier and forms a carrying tank. The LED chip is fixed within the carrying tank and includes a first conductivity type semiconductor layer having a first region and a second region, an active layer and a second conductivity type semiconductor layer stacked in sequence. The LED chip further includes a second conductive finger disposed on the second semiconductor layer in the first region, and a first conductive finger disposed on the first semiconductor layer in the second region. The first electrode extends on the sidewall and the first conductive finger. The second electrode extends on the sidewall and the second conductive finger. | 2012-07-05 |
| 20120168795 | LIGHT EMITTING DIODE PACKAGE AND METHOD FOR MANUFACTURING SAME - A light emitting diode (LED) package and the manufacturing method thereof are provided. The LED package comprises a substrate, at least one LED die, a lens and an in-mold decoration film, wherein the LED die is fixed on the substrate; the lens is convexly molded on the substrate to encapsulate the LED die; and the in-mold decoration film has at least one phosphor layer disposed on the lens and a surface treatment layer disposed on the phosphor layer. | 2012-07-05 |
| 20120168796 | Light emitting diode display - An organic light emitting diode (OLED) display includes a substrate, a pixel electrode on the substrate, an organic light emitting member on the pixel electrode, a common electrode on the organic light emitting member, a thin film encapsulation member covering the common electrode, a black matrix on the thin film encapsulation member, and an upper protection film on the black matrix. The black matrix has a color filter at a location corresponding to the organic light emitting member. A sum of a thickness of the color filter and a distance between the color filter and the organic light emitting member is smaller than a width of the organic light emitting member. | 2012-07-05 |
| 20120168797 | LIGHT EMITTING DIODE CHIP AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a light emitting diode chip, comprising steps: providing a substrate with a first patterned blocking layer formed thereon; growing a first n-type semiconductor layer on the substrate between the constituting parts of first patterned blocking layer, and stopping the growth of the first n-type semiconductor layer before the first n-type semiconductor layer completely covers the first patterned blocking layer; removing the first patterned blocking layer, whereby a plurality of first holes are formed at position where the first patterned blocking layer is originally existed; continuing the growth of the first n-type semiconductor layer until the first holes are completely covered by the first n-type semiconductor layer; and forming an active layer and a p-type current blocking layer on the first n-type semiconductor layer successively. | 2012-07-05 |
| 20120168798 | LED PACKAGE - A light emitting device (LED) package is disclosed. The light emitting device package includes a light emitting device, a substrate on which the light emitting device is mounted in plural; and a lens mounted on the substrate so as to cover and seal the light emitting device and having an accommodating groove formed in a lower surface thereof contacting the substrate, the accommodating groove accommodating the light emitting device, and a concave portion formed in an upper surface thereof in such a manner as to be disposed at a position corresponding to the light emitting device, wherein the concave portion has a radius of curvature on an optical axis of the lens and is formed to be depressed from the upper surface to the lower surface. | 2012-07-05 |
| 20120168799 | LED LAMPS - A high power LED lamp has a GaN chip placed over an AlGaInP chip. A reflector is placed between the two chips. Each of the chips has trenches diverting light for output. The chip pair can be arranged to produce white light having a spectral distribution in the red to blue region that is close to that of daylight. Also, the chip pair can be used to provide an RGB lamp or a red-amber-green traffic lamp. The active regions of both chips can be less than 50 microns away from a heat sink. | 2012-07-05 |
| 20120168800 | LEAD FRAME FOR OPTICAL SEMICONDUCTOR DEVICE, METHOD OF PRODUCING THE SAME, AND OPTICAL SEMICONDUCTOR DEVICE - A lead frame for an optical semiconductor device, having a reflection layer ( | 2012-07-05 |
| 20120168801 | LIGHT EMITTING DEVICE AND PACKAGE STRUCTURE THEREOF - A light-emitting device package structure includes a carrier, at least one light-emitting device and a magnetic element. The magnetic element aids in enhancing overall luminous output efficiency. | 2012-07-05 |
| 20120168802 | WAFER FOR LED MOUNTING, METHOD FOR MANUFACTURING SAME, AND LED-MOUNTED STRUCTURE USING THE WAFER - Provided is a wafer for LED mounting having a small difference in thermal expansion coefficient from an LED and having excellent heat conductivity, a method for manufacturing the wafer for LED mounting, and an LED-mounted structure manufactured by using the wafer for LED mounting. The wafer for LED mounting ( | 2012-07-05 |
| 20120168803 | SEMICONDUCTOR LIGHT-EMITTING DIODE AND A PRODUCTION METHOD THEREFOR - Provided is a semiconductor light-emitting diode including a semiconductor layer having a light-emitting structure; and an ohmic electrode incorporating a nanodot layer, a contact layer, a diffusion-preventing layer and a capping layer on the semiconductor layer. The nanodot layer is formed on the N-polar surface of the semiconductor layer and is formed from a substance comprising at least one of Ag, Al and Au. Also provided is a production method therefor. In the ohmic electrode which has the multi-layer structure comprising the nanodot layer/contact layer/diffusion-preventing layer/capping layer in the semiconductor light-emitting diode of this type, the nanodot layer constitutes the N-polar surface of a nitride semiconductor and improves the charge-injection characteristics such that outstanding ohmic characteristics can be obtained. | 2012-07-05 |
| 20120168804 | Light Emitting Diode Package and Fabrication Method Thereof - A light emitting diode package and a fabrication method thereof are provided. The light emitting diode package comprises a lead frame, having a frame body and a conductive layer covering the frame body. A reflector has a first portion and a second portion sandwiching the lead frame, wherein the first portion has a depression to expose the lead frame, and a light emitting diode chip is disposed on the lead frame in the depression. The fabrication method comprises forming a frame body and forming a conductive layer covering the frame body to form a lead frame. A first portion and a second portion of a reflector are formed to sandwich the lead frame, wherein the first portion has a depression to expose the lead frame. A light emitting diode chip is disposed on the lead frame in the depression. | 2012-07-05 |
| 20120168805 | LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE - A light emitting device including a bonding layer; a barrier layer on the bonding layer; an adhesion layer on the barrier layer, in which the adhesion layer includes Pd, Au, and Sn; a reflective layer on the adhesion layer, in which the reflective layer includes Ag; an ohmic contact layer on the reflective layer, in which the ohmic contact layer includes Pt and Ag; a light emitting structure layer on the ohmic contact layer; and a passivation layer includes an insulating material on a side surface and a top surface of the light emitting structure layer. | 2012-07-05 |
| 20120168806 | Optical Semiconductor Device having Pre-Molded Leadframe with Window and Method Therefor - A semiconductor device is made by providing a semiconductor die having an optically active area, providing a leadframe or pre-molded laminated substrate having a plurality of contact pads and a light transmitting material disposed between the contact pads, attaching the semiconductor die to the leadframe so that the optically active area is aligned with the light transmitting material to provide a light transmission path to the optically active area, and disposing an underfill material between the semiconductor die and leadframe. The light transmitting material includes an elevated area to prevent the underfill material from blocking the light transmission path. The elevated area includes a dam surrounding the light transmission path, an adhesive ring, or the light transmission path itself can be the elevated area. An adhesive ring can be disposed on the dam. A filler material can be disposed between the light transmitting material and contact pads. | 2012-07-05 |
| 20120168807 | Tri-color LED module structure - A tri-color LED module structure includes an insulating base, four terminals, a tri-color LED chip, and a cover. The insulating base has a receiving recess. The four terminals do not contact with one another, and each of them includes an inserting portion and a touching portion which are connected with each other. The touching portion is received in the receiving recess; while the inserting portion extends out of the insulating base. The four terminals and the insulating base are an integrally formed structure. The tri-color LED chip is disposed in the receiving recess of the insulating base, with four pins of the tri-color LED chip in touch with the touching portions of the four terminals, respectively. Further, the cover covers on the receiving chamber of the insulating base. Thereby, an independent red-green-blue tri-color LED loop can be constituted, making color mixing become possible by controlling various voltage combination. | 2012-07-05 |
| 20120168808 | PACKAGE STRUCTURE - A package structure including a first substrate, a second substrate and a light emitting diode is provided. The first substrate has at least a first annular engaged portion. The second substrate is disposed above the first substrate and has at least a second annular engaged portion. The light emitting diode is disposed on the first substrate. The second annular engaged portion is infixed to the first annular engaged portion so as to form an airtight space. The light emitting diode is located in the airtight space. | 2012-07-05 |
| 20120168809 | OPTOELECTRONIC SEMICONDUCTOR BODY AND OPTOELECTRONIC SEMICONDUCTOR CHIP - An optoelectronic semiconductor body has a front face provided for the emission and/or reception of electromagnetic radiation, a rear face which lies opposite the front face and is provided for application onto a support plate, and an active semiconductor layer sequence which in the direction from the rear face to the front face includes a layer of a first conductivity type, an active layer and a layer of a second conductivity type in this sequence. | 2012-07-05 |
| 20120168810 | LEAD FRAME FOR OPTICAL SEMICONDUCTOR DEVICE, METHOD OF PRODUCING THE SAME, AND OPTICAL SEMICONDUCTOR DEVICE - A lead frame for an optical semiconductor device, having: a layer | 2012-07-05 |
| 20120168811 | NITRIDE-TYPE SEMICONDUCTOR ELEMENT AND PROCESS FOR PRODUCTION THEREOF - A nitride-based semiconductor device includes a p-type Al | 2012-07-05 |
| 20120168812 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device includes a lead frame, a semiconductor light-emitting element mounted on the top surface of the bonding region, and a case covering part of the lead frame. The bottom surface of the bonding region is exposed to the outside of the case. The lead frame includes a thin extension extending from the bonding region and having a top surface which is flush with the top surface of the bonding region. The thin extension has a bottom surface which is offset from the bottom surface of the bonding region toward the top surface of the bonding region. | 2012-07-05 |
| 20120168813 | LIGHT EMITTING DIODE WITH A TEMPERATURE DETECTING PATTERN AND MANUFACTURING METHOD THEREOF - A light emitting diode (LED) includes a substrate, a temperature detecting pattern, and a semiconductor structure. The temperature detecting pattern is formed on the substrate. Then the semiconductor structure is formed on the temperature detecting pattern and the substrate. The semiconductor structure includes an n-type semiconductor layer, a p-type semiconductor layer, and an active layer. Per above-mentioned structural design, the temperature detecting pattern directly integrated into the LED can measure the actual temperature of PN junction with high precision. | 2012-07-05 |
| 20120168814 | ADHESIVE COMPOSITION - An adhesive composition for flip-chip-mounting a chip component on a circuit board contains an alicyclic epoxy compound, an alicyclic acid anhydride curing agent, and an acrylic resin. The amount of the alicyclic acid anhydride curing agent is 80 to 120 parts by mass based on 100 parts by mass of the alicyclic epoxy compound, and the amount of the acrylic resin is 5 to 50 parts by mass based on 100 parts by mass of the total amount of the alicyclic epoxy compound, the alicyclic acid anhydride curing agent, and the acrylic resin. The acrylic resin is a resin obtained by copolymerization of 100 parts by mass of alkyl (meth)acrylate and 2 to 100 parts by mass of glycidyl methacrylate and having a water absorption rate of 1.2% or less. | 2012-07-05 |
| 20120168815 | ENCAPSULATION MATERIAL AND ELECTRONIC DEVICE PREPARED USING THE SAME - An encapsulation material and an electronic device, the encapsulation material including a resin, the resin including a first polysiloxane including hydrogen bonded with silicon (Si—H) at a terminal end thereof, and a second polysiloxane including an alkenyl group bonded with silicon (Si-Vi) at a terminal end thereof, a phosphor, and a density controlling agent, wherein a weight ratio of the density controlling agent to the phosphor is about 1.5:1 to about 10:1. | 2012-07-05 |
| 20120168816 | LIGHT EMITTING SEMICONDUCTOR DEVICE - A light emitting semiconductor device ( | 2012-07-05 |
| 20120168817 | LATERAL EXTENDED DRAIN METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (LEDMOSFET) HAVING A HIGH DRAIN-TO-BODY BREAKDOWN VOLTAGE (Vb), A METHOD OF FORMING AN LEDMOSFET, AND A SILICON-CONTROLLED RECTIFIER (SCR) INCORPORATING A COMPLEMENTARY PAIR OF LEDMOSFETS - Disclosed are embodiments of a lateral, extended drain, metal oxide semiconductor, field effect transistor (LEDMOSFET) having a high drain-to-body breakdown voltage. Discrete conductive field (CF) plates are adjacent to opposing sides of the drain drift region, each having an angled sidewall such that the area between the drain drift region and the CF plate has a continuously increasing width along the length of the drain drift region from the channel region to the drain region. The CF plates can comprise polysilicon or metal structures or dopant implant regions within the same semiconductor body as the drain drift region. The areas between the CF plates and the drain drift region can comprise tapered dielectric regions or, alternatively, tapered depletion regions within the same semiconductor body as the drain drift region. Also disclosed are embodiments of a method for forming an LEDMOSFET and embodiments of a silicon-controlled rectifier (SCR) incorporating such LEDMOSFETs. | 2012-07-05 |
| 20120168818 | METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE AND SEMICONDUCTOR DEVICE - Disclosed are a method which improves the performance of a semiconductor element, and a semiconductor element with improved performance. The method for forming a semiconductor element structure includes a heterojunction forming step in which a heterojunction is formed between a strained semiconductor layer ( | 2012-07-05 |
| 20120168819 | Semiconductor pillar power MOS - A novel semiconductor power transistor is presented. The semiconductor structure is simple and is based on a multi-gate vertical MOS configuration with multi semiconductor pillars, so that the control on the carrier transport is enhanced and the specific on-resistance per area is reduced. Furthermore, due to its particular geometry, the parasitic resistances due to the source/drain junctions, are also drastically reduced with respect to standard CMOS technologies. It offers the advantage of extremely lower on-resistance for the same silicon area while improving on its dynamic performances. The novel structure does not require Silicon On Insulator technologies and can be built using the standard Bulk CMOS process technology. This characteristic improves the thermal properties of the device which are extremely important in power applications. | 2012-07-05 |
| 20120168820 | JUNCTION FIELD EFFECT TRANSISTOR STRUCTURE WITH P-TYPE SILICON GERMANIUM OR SILICON GERMANIUM CARBIDE GATE(S) AND METHOD OF FORMING THE STRUCTURE - Disclosed are embodiments of a junction field effect transistor (JFET) structure with one or more P-type silicon germanium (SiGe) or silicon germanium carbide (SiGeC) gates (i.e., a SiGe or SiGeC based heterojunction JFET). The P-type SiGe or SiGeC gate(s) allow for a lower pinch off voltage (i.e., lower Voff) without increasing the on resistance (Ron). Specifically, SiGe or SiGeC material in a P-type gate limits P-type dopant out diffusion and, thereby ensures that the P-type gate-to-N-type channel region junction is more clearly defined (i.e., abrupt as opposed to graded). By clearly defining this junction, the depletion layer in the N-type channel region is extended. Extending the depletion layer in turn allows for a faster pinch off (i.e., requires lower Voff). P-type SiGe or SiGeC gate(s) can be incorporated into conventional lateral JFET structures and/or vertical JFET structures. Also disclosed herein are embodiments of a method of forming such a JFET structure. | 2012-07-05 |
| 20120168821 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device having a substrate including a major surface, a gate stack comprising a sidewall over the substrate and a spacer over the substrate adjoining the sidewall of the gate stack. The spacer having a bottom surface having an outer point that is the point on the bottom surface farthest from the gate stack. An isolation structure in the substrate on one side of the gate stack has an outer edge closest to the spacer. A strained material below the major surface of the substrate disposed between the spacer and the isolation structure having an upper portion and a lower portion separated by a transition plane at an acute angle to the major surface of the substrate. | 2012-07-05 |
| 20120168822 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device and a fabrication method of the semiconductor device, the semiconductor device including: a substrate; a nitride based compound semiconductor layer placed on the substrate and doped with a first transition metal atom; an aluminum gallium nitride layer (Al | 2012-07-05 |
| 20120168823 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present application discloses a semiconductor device and a method for forming the same. The method comprises: providing a first semiconductor layer and forming a first STI in the first semiconductor layer; determining a selected region in the first semiconductor layer, and making a portion of the first semiconductor layer in the selected region recessed; and in the selected region, epitaxially growing a second semiconductor layer on the first semiconductor layer, wherein the material of the second semiconductor layer is different from that of the first semiconductor layer. According to the present invention, a structure with a second semiconductor layer selectively epitaxially grown and embedded in the first semiconductor layer can be formed by a simple process, and defects generated during the epitaxial growth process can be further reduced. | 2012-07-05 |
| 20120168824 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device including a memory string including a plurality of memory cells coupled in series. The non-volatile memory device includes the memory string including a first semiconductor layer and a second conductive layer with a memory gate insulation layer therebetween, a first selection transistor comprising a second semiconductor layer coupled with one end of the first semiconductor layer, a second selection transistor comprising a third semiconductor layer coupled with the other end of the first semiconductor layer, and a fourth semiconductor layer contacting the first semiconductor layer in a region where the second conductive layer is not disposed. | 2012-07-05 |
| 20120168825 | Charged Coupled Device Module and Method of Manufacturing the Same - A charged coupled device (CCD) module fixed between a lens assembly and a main board having a first plate surface is disclosed. The CCD module comprises a hard PCB having a first surface and a second surface, a CCD component, and at least one fixed member. The first surface of the hard PCB faces the first plate surface of the main board. The CCD component facing the lens assembly is located on the second surface of the hard PCB. The fixed member is used for combining the hard PCB and the main board. The hard PCB and the fixed member can be used as a buffer to reduce possible damages to the CCD component and/or the main board. | 2012-07-05 |
| 20120168826 | ONE-TRANSISTOR PIXEL ARRAY - To reduce the pixel size to the smallest dimensions and simplest form of operation, a pixel may be formed by using only one ion sensitive field-effect transistor (ISFET). This one-transistor, or | 2012-07-05 |
| 20120168827 | SEMICONDUCTOR DEVICE HAVING A TRIPLE GATE TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction. | 2012-07-05 |
| 20120168828 | SEMICONDUCTOR DEVICE HAVING A TRIPLE GATE TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction. | 2012-07-05 |
| 20120168829 | MOS TRANSISTOR AND METHOD FOR FORMING THE SAME - The invention provides a MOS transistor and a method for forming the MOS transistor. The MOS transistor includes a semiconductor substrate; a gate stack on the semiconductor substrate, and including a gate dielectric layer and a gate electrode on the semiconductor substrate in sequence; a source region and a drain region, respectively at sidewalls of the gate stack sidewalls of the gate stack and in the semiconductor; sacrificial metal spacers on sidewalls of the gate stack sidewalls of the gate stack, and having tensile stress or compressive stress. This invention scales down the equivalent oxide thickness, improves uniformity of device performance, raises carrier mobility and promotes device performance. | 2012-07-05 |
| 20120168830 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment includes: a substrate; a first semiconductor layer formed on the substrate and having a strain; a second and a third semiconductor layers formed at a distance from each other on the first semiconductor layer, and having a different lattice constant from a lattice constant of the first semiconductor layer; a gate insulating film formed on a first portion of the first semiconductor layer, the first portion being located between the second semiconductor layer and the third semiconductor layer; and a gate electrode formed on the gate insulating film. At least one of outer surface regions of the second semiconductor layer and a second portion of the first semiconductor layer is a first silicide region, and at least one of outer surface regions of the third semiconductor layer and a third portion of the first semiconductor layer is a second silicide region, the second and third portions being located immediately below the second and third semiconductor layers respectively. | 2012-07-05 |
| 20120168831 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a non-volatile memory device includes: providing a substrate which includes a cell region where a plurality of memory cells are to be formed and a peripheral circuit region where a plurality of peripheral circuit devices are to be formed; forming the memory cells that are stacked perpendicularly to the substrate of the cell region; and forming a first conductive layer for forming a gate electrode of a selection transistor over the memory cells while forming the first conductive layer in the peripheral circuit region simultaneously, wherein the first conductive layer of the peripheral circuit region functions as a resistor body of at least one peripheral circuit device of the peripheral circuit devices. | 2012-07-05 |
| 20120168832 | ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD - Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (R | 2012-07-05 |
| 20120168833 | FORMATION OF FINFET GATE SPACER - Gate spacers are formed in FinFETS having a bottom portion of a first material extending to the height of the fins, and a top portion of a second material extending above the fins. An embodiment includes forming a fin structure on a substrate, the fin structure having a height and having a top surface and side surfaces, forming a gate substantially perpendicular to the fin structure over a portion of the top and side surfaces, for example over a center portion, forming a planarizing layer over the gate, the fin structure, and the substrate, removing the planarizing layer from the substrate, gate, and fin structure down to the height of the fin structure, and forming spacers on the fin structure and on the planarizing layer, adjacent the gate. | 2012-07-05 |
| 20120168834 | FIELD EFFECT TRANSISTOR (FET) AND METHOD OF FORMING THE FET WITHOUT DAMAGING THE WAFER SURFACE - Disclosed are a field effect transistor structure and a method of forming the structure. A gate stack is formed on the wafer above a designated channel region. Spacer material is deposited and anisotropically etched until just prior to exposing any horizontal surfaces of the wafer or gate stack, thereby leaving relatively thin horizontal portions of spacer material on the wafer surface and relatively thick vertical portions of spacer material on the gate sidewalls. The remaining spacer material is selectively and isotropically etched just until the horizontal portions of spacer material are completely removed, thereby leaving only the vertical portions of the spacer material on the gate sidewalls. This selective isotropic etch removes the horizontal portions of spacer material without damaging the wafer surface. Raised epitaxial source/drain regions can be formed on the undamaged wafer surface adjacent to the gate sidewall spacers in order to tailor source/drain resistance values. | 2012-07-05 |
| 20120168835 | ANTI-REFLECTION STRUCTURES FOR CMOS IMAGE SENSORS - Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package. | 2012-07-05 |
| 20120168836 | MULTILAYERED PHOTODIODE AND METHOD OF MANUFACTURING THE SAME - In a multilayered photodiode and a method of manufacturing the same, the multilayered photodiode comprises: a transparent substrate; a gate insulating film formed on the transparent substrate; a first metal layer formed on the gate insulating film; a semiconductor layer formed on the first metal layer so as to be in contact with the first metal layer; and a second metal layer formed on the semiconductor layer so as to be in contact with the semiconductor layer. The photodiode is vertically multilayered, and has a metal-insulator-metal (MIM) structure in which a P-N region is replaced by a metal, and in which a light-receiving region does not block incident light. | 2012-07-05 |
| 20120168837 | Ferroelectric Memory Electrical Contact - A ferroelectric apparatus includes a circuit having a first capacitor electrically coupled to a plate line via a top terminal connection of the first ferroelectric capacitor and to a storage node via a bottom terminal connection of the first ferroelectric capacitor. The circuit also includes a second ferroelectric capacitor electrically coupled to a second plate line via a second bottom terminal connection of the second ferroelectric capacitor and to the storage node via a second top terminal connection of the second ferroelectric capacitor. | 2012-07-05 |
| 20120168838 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment includes: a semiconductor layer; source and drain regions in the semiconductor layer; a magnetic metal semiconductor compound film on each of the source and drain regions, the magnetic metal semiconductor compound film including the same semiconductor as a semiconductor of the semiconductor layer and a magnetic metal; a gate insulating film on the semiconductor layer between the source region and the drain region; a gate electrode on the gate insulating film; a gate sidewall formed at a side portion of the gate electrode, the gate sidewall being made of an insulating material; a film stack formed on the magnetic metal semiconductor compound film on each of the source and drain regions, the film stack including a magnetic layer; and an oxide layer formed on the gate sidewall, the oxide layer containing the same element as an element in the film stack. | 2012-07-05 |
| 20120168839 | POWER DEVICE PACKAGE STRUCTURE - The disclosure relates to a power device package structure. By employing the metal substrate of the power device package structure serve as a bottom electrode of a capacitor, the capacitor is integrated into the power device package structure. A dielectric material layer and a upper metal layer sequentially disposed on the metal substrate. | 2012-07-05 |
| 20120168840 | RF-POWER DEVICE - An RF-power device includes a semiconductor substrate having a plurality of active regions arranged in an array. Each active region includes one or more RF-power transistors. The active regions are interspersed with inactive regions for reducing mutual heating of the RF-power transistors in separate active regions. The devices also includes at least one impedance matching component located in one of the inactive regions of the substrate. | 2012-07-05 |
| 20120168841 | Multiple Patterning Method - An integrated circuit memory comprises a set of lines each line having parallel X direction line portions in a first region and Y direction line portions in a second region. The second region is offset from the first region. The lengths of the X direction line portions are substantially longer than the lengths of the Y direction line portions. The X direction and Y direction line portions have respective first and second pitches with the second pitch being at least 3 times larger than the first pitch. Contact pickup areas are at the Y direction line portions. In some examples, the lines comprise word lines or bit lines. The memory can be created using multiple patterning methods to create lines of material and then the parallel X direction line portions and parallel Y direction line portions. | 2012-07-05 |
| 20120168842 | SPLIT GATE FLASH CELL AND METHOD FOR MAKING THE SAME - A method for forming a split gate flash cell device provides for forming floating gate transistors. Each floating gate transistor is formed by providing a floating gate transistor substructure including an oxide disposed over a polysilicon gate disposed over a gate oxide disposed on a portion of a common source. Nitride spacers are formed along sidewalls of the floating gate transistor substructure and cover portions of the gate oxide that terminate at the sidewalls. An isotropic oxide etch is performed with the nitride spacers intact. The isotropic etch laterally recedes opposed edges of the oxide inwardly such that a width of the oxide is less than a width of the polysilicon gate. An inter-gate dielectric is formed over the floating gate transistor substructure and control gates are formed over the inter-gate dielectric to form the floating gate transistors. | 2012-07-05 |
| 20120168843 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device includes a bit line formed over a substrate, an insulation layer formed over the bit line, a gate line crossing the bit line and formed over the insulation layer, and a channel layer formed on both sidewalls of the gate line and coupled to the bit line. | 2012-07-05 |
| 20120168844 | Nonvolatile semiconductor memory device - Provided is an electrically erasable and programmable nonvolatile semiconductor memory device having a tunnel region; the tunnel region and the peripheral of the tunnel region are dug down to be made lower, and a depletion electrode, to which an arbitral potential is given to deplete a part of the tunnel region through a depletion electrode insulating film, is arranged in the lowered drain region. | 2012-07-05 |
| 20120168845 | Nonvolatile semiconductor memory device - Provided is an electrically erasable and programmable nonvolatile semiconductor memory device having a small hole in a second conductivity-type drain region, a tunnel insulating film formed on the surface of the hole, and a protrusion extended from the floating gate electrode and arranged to fill the hole. Further a tunneling restriction region which is an electrically floating first conductivity type region arranged in a vicinity of the surface of the drain region around the hole to define the size of the tunnel region through which the tunnel current flows. | 2012-07-05 |
| 20120168846 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING ELEMENT ISOLATING REGION OF TRENCH TYPE - Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion. | 2012-07-05 |
| 20120168847 | MEMORY WITH EXTENDED CHARGE TRAPPING LAYER - A memory array includes a plurality of bit lines and a plurality of word lines, a gate region, and a charge trapping layer. The charge trapping layer is wider than a word line; the charge trapping layer is extended beyond the edge of the gate region to facilitate capturing and removing charges. | 2012-07-05 |
| 20120168848 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a channel structure extended in a first direction that includes a plurality of inter-layer dielectric layers and a plurality of channel layers alternately stacked over a substrate such that each inter-layer dielectric layer is adjacent to a corresponding one of the plurality of channel layers. A word line extends in a second direction crossing the first direction over the channel structure, and a gate electrode protrudes from the word line in a downward direction to contact a sidewall of the channel structure. A memory gate insulation layer is interposed between the gate electrode and the channel structure, where sidewalls of the channel layers contacting the gate electrode are protruded toward the gate electrode, compared with sidewalls of the inter-layer dielectric layers. | 2012-07-05 |
| 20120168849 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a substrate including a resistor layer having a resistance lower than that of a source line, channel structures including a plurality of inter-layer dielectric layers that are alternately staked with a plurality of channel layers over the substrate, and the source line configured to contact sidewalls of the channel layers, where a lower end of the source line contacts the resistor layer. | 2012-07-05 |
| 20120168850 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a channel protruding in a vertical direction from a substrate, a plurality of interlayer dielectric layers and gate electrode layers which are alternately stacked over the substrate along the channel, and a memory layer formed between the channel and a stacked structure of the interlayer dielectric layers and gate electrode layers. Two or more gate electrode layers of the plurality of gate electrode layers are coupled to an interconnection line to form a selection transistor. | 2012-07-05 |
| 20120168851 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device including a memory cell configured to store data and a resistor element provided around the memory cell. The memory cell includes a charge storage layer provided above a substrate, a first semiconductor layer formed on a top surface of the charge storage layer via an insulating layer, and a first low resistive layer formed on a top surface of the first semiconductor layer and having resistance lower than that of the first semiconductor layer. The resistor element includes a second semiconductor layer formed on the same layer as the first semiconductor layer, and a second low resistive layer formed on the same layer as the first low resistive layer and on a top surface of the second semiconductor layer, having resistance lower than that of the second semiconductor layer. | 2012-07-05 |
| 20120168852 | NONVOLATILE MEMORY DEVICES - A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the memory cell transistors. Second impurity layers are formed at boundaries between a channel and a drain region of the string selection transistor and between a channel and a source region of the ground selection transistor. The second impurity layers are doped with the same conductivity type impurities as the first impurity layers and have a higher impurity concentration than the first impurity layers. | 2012-07-05 |
| 20120168853 | SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE - A semiconductor non-volatile memory (NVM) device, comprising: a semiconductor substrate; a three-layer stack structure of medium layer-charge trapping layer-medium layer disposed on the semiconductor substrate; a gate disposed above the three-layer stack structure; a source and a drain disposed in the semiconductor substrate at either side of the three-layer stack structure; wherein the charge trapping layer is a dielectric layer containing one or more discrete compound clusters formed by atomic layer deposition (ALD) method. | 2012-07-05 |
| 20120168854 | SEMICONDUCTOR DEVICE AND METOD FOR FORMING THE SAME - A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a first junction region formed at the bottom of a vertical pillar, a bit line formed below the first junction region, and an insulation film formed below the bit line. As a result, the 4F2-sized semiconductor device is provided and the bit line is configured in the form of a laminated structure of a conductive layer and a polysilicon layer, so that bit line resistance is reduced. In addition, the semiconductor device reduces ohmic contact resistance by forming silicide between the conductive layer and the polysilicon layer, and includes an insulation film at a position between the semiconductor substrate and the bit line, resulting in reduction of bit line capacitance. Therefore, the sensing margin of the semiconductor device is increased and the data retention time is also increased. | 2012-07-05 |
| 20120168855 | NANOWIRE TRANSISTOR WITH SURROUNDING GATE - One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The pillar has a sublithographic thickness. A transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein. | 2012-07-05 |
| 20120168856 | TRENCH-TYPE SEMICONDUCTOR POWER DEVICES - The present invention relates to a semiconductor device. The device comprises a semiconductor substrate. A semiconductor drift region is on the semiconductor substrate. The semiconductor drift region comprises a semiconductor region of a first conduction type and a semiconductor region of a second conduction type. The semiconductor region of the first conduction type and the semiconductor region of the second conduction type form a superjunction structure. A high-K dielectric is on the semiconductor substrate. The high-K dielectric is adjacent to the semiconductor region of the second conduction type. An active region is on the semiconductor drift region. A trench gate structure is on the high-K dielectric, the trench gate structure being adjacent to the active region. The semiconductor region of the second conduction type is formed by shallow angle ion implantation, thus its width is narrow and its concentration is high. | 2012-07-05 |
| 20120168857 | Memory structure having a floating body and method for fabricating the same - A memory structure having a floating body is provided, which includes a substrate including an active area and an isolation structure surrounding the active area, a first source/drain region in the substrate in the active area, a first floating body in the substrate above the first source/drain region, a second floating body on the first floating body, a second source/drain region on the second floating body, and a trench-type gate structure in the substrate and beside the first floating body. A method of fabricating a memory structure having a floating body is also provided. | 2012-07-05 |
| 20120168858 | NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a non-volatile memory device includes providing a substrate with a cell region where a plurality of memory cells that are stacked vertically are to be formed and a peripheral circuit region where a peripheral circuit device is to be formed. Forming a gate structure where an inter-layer dielectric layer and a gate electrode layer are alternately stacked over the substrate of the cell region and the peripheral circuit region. Forming a first trench that isolates the gate electrode layers in one direction by selectively etching the gate structure of the cell region and forming a trench by selectively etching the gate structure corresponding to a contact formation region of the peripheral circuit region. | 2012-07-05 |
| 20120168859 | VERTICAL TRANSISTOR MANUFACTURING METHOD AND VERTICAL TRANSISTOR - A method is disclosed of manufacturing a vertical transistor which comprises providing a substrate including a vertical stack of regions including a source region separated from a drain region by a channel region; forming a trench in said substrate, said trench at least partially extending into said vertical stack of regions; lining said trench with a stack comprising a gate dielectric liner, an etch protection layer and a further insulating layer; filling the remainder of the trench with a shield electrode material; exposing a top portion of the shield electrode material by removing the further insulating layer to a first depth in said trench; forming a inter electrode dielectric on the exposed shield electrode material; removing the etch protection layer to the first depth from said trench; and forming a gate electrode in said trench between the inter electrode dielectric liner and the exposed portion of the gate dielectric liner. | 2012-07-05 |
| 20120168860 | TRANSISTOR AND METHOD FOR FORMING THE SAME - The invention provides a method for forming a transistor, which includes: providing a substrate, a semiconductor layer being formed on the substrate; forming a dummy gate structure on the semiconductor layer; forming a source region and a drain region in the substrate and the semiconductor layer and at opposite sides of the dummy gate structure; forming an interlayer dielectric layer on the semiconductor layer; removing the dummy gate structure for forming an opening in the interlayer dielectric layer; non-crystallizing the semiconductor layer exposed in the opening for forming a channel layer; annealing the channel layer so that the channel layer and the substrate have same crystal orientation; and forming a metal gate structure in the opening, the metal gate being formed on the channel layer. Saturation current of the transistor is raised, and the performance of a semiconductor device is promoted. | 2012-07-05 |
| 20120168861 | POWER TRANSISTOR WITH INCREASED AVALANCHE CURRENT AND ENERGY RATING - A field-effect transistor involves a drain electrode, a drift region, a body region, a source region, a gate insulator layer, and a gate electrode. The drift region is disposed above the drain electrode. The body region extends down into the drift region from a first upper semiconductor surface. The source region is ladder-shaped and extends down in the body region from a second upper semiconductor surface. The first and second upper semiconductor surfaces are substantially planar and are not coplanar. A first portion of the body region is surrounded laterally by a second portion of the body region. The second portion of the body region and the drift region meet at a body-to-drift boundary. The body-to-drift boundary has a central portion that is non-planar. A gate insulator layer is disposed over the source region and a gate electrode is disposed over the gate insulator. | 2012-07-05 |
| 20120168862 | HIGH-VOLTAGE METAL-OXIDE-SEMICONDUCTOR DEVICE - A high-voltage MOS transistor includes a gate overlying an active area of a semiconductor substrate; a drain doping region pulled back away from an edge of the gate by a distance L; a first lightly doped region between the gate and the drain doping region; a source doping region in a first ion well; and a second lightly doped region between the gate and the source doping region. | 2012-07-05 |
| 20120168863 | Semiconductor Structure and Method for Manufacturing the Same - Semiconductor structure and methods for manufacturing the same are disclosed. In one embodiment, the semiconductor device is formed on an SOI substrate comprising an SOI layer, a buried insulating layer, a buried semiconductor layer and a semiconductor substrate from top to bottom, and comprises: source/drain regions formed in the SOI layer; a gate formed on the SOI layer, wherein the source/drain regions are located at both sides of the gate; a back gate region formed by a portion of the buried semiconductor layer which is subjected to resistance reduction; and a first isolation structure and a second isolation structure which are located at both sides of the source/drain regions and extend into the SOI substrate; wherein the first isolation structure and the second isolation structure laterally adjoin the SOI layer at a first side surface and a second side surface respectively; the first isolation structure laterally adjoins the buried semiconductor layer at a third side surface; and the third side surface is located between the first side surface and the second side surface. | 2012-07-05 |
| 20120168864 | SELF-ALIGNED WELL IMPLANT FOR IMPROVING SHORT CHANNEL EFFECTS CONTROL, PARASITIC CAPACITANCE, AND JUNCTION LEAKAGE - A transistor device includes a patterned gate structure formed over a substrate, the patterned gate structure including a gate conductor, a gate dielectric layer and sidewall spacers; and a doped well implant formed in the substrate, the well implant being self-aligned with the patterned gate structure. | 2012-07-05 |
| 20120168865 | Transistor and Method for Manufacturing the Same - The invention relates to a transistor and a method for manufacturing the transistor. The transistor according to an embodiment of the invention may comprise: a substrate which comprises at least a back gate of the transistor, an insulating layer and a semiconductor layer stacked sequentially, wherein the back gate of the transistor is used for adjusting the threshold voltage of the transistor; a gate stack formed on the semiconductor layer, wherein the gate stack comprises a gate dielectric and a gate electrode formed on the gate dielectric; a spacer formed on sidewalls of the gate stack; and a source region and a drain region located on both sides of the gate stack, respectively, wherein the height of the gate stack is lower than the height of the spacer. The transistor enables the height of the gate stack to be reduced and therefore the performance of the transistor is improved. | 2012-07-05 |
| 20120168866 | STRUCTURE, METHOD AND SYSTEM FOR COMPLEMENTARY STRAIN FILL FOR INTEGRATED CIRCUIT CHIPS - A structure, method and system for complementary strain fill for integrated circuit chips. The structure includes a first region of an integrated circuit having multiplicity of n-channel and p-channel field effect transistors (FETs); a first stressed layer over n-channel field effect transistors (NFETs) of the first region, the first stressed layer of a first stress type; a second stressed layer over p-channel field effect transistors (PFETs) of the first region, the second stressed layer of a second stress type, the second stress type opposite from the first stress type; and a second region of the integrated circuit, the second region not containing FETs, the second region containing first sub-regions of the first stressed layer and second sub-regions of the second stressed layer. | 2012-07-05 |
| 20120168867 | PROTECTION ELEMENT AND SEMICONDUCTOR DEVICE HAVING THE PROTECTION ELEMENT - Disclosed herein is a protection element for protecting a circuit element. The protection element includes source and drain areas created in a semiconductor layer, a gate created on the semiconductor layer, sandwiching a gate insulation film between the gate and the semiconductor layer, a source electrode connected to the surface of the source area and electrically connected to the ground, a drain electrode connected to the surface of the drain area and used for receiving a surge input, and a diode connected between the source electrode and the gate. | 2012-07-05 |
| 20120168868 | MULTI-GATE FIELD-EFFECT TRANSISTOR WITH ENHANCED AND ADAPTABLE LOW-FREQUENCY NOISE - A field-effect transistor has an extra gate above a shallow trench isolation (STI) to enhance and to adapt the low-frequency noise induced by an STI-silicon interface. By changing the voltage applied to the STI gate, the field-effect transistor is able to adapt its low-frequency noise over four decades. The field-effect transistor can be fabricated with a standard CMOS logic process without additional masks or process modification. | 2012-07-05 |
| 20120168869 | SEMICONDUCTOR DEVICE, AND ITS MANUFACTURING METHOD - The present invention provides a high breakdown voltage transistor that eases an electric field concentration caused between a gate and a drain. | 2012-07-05 |
