| 27th week of 2013 patent applcation highlights part 67 |
| Patent application number | Title | Published |
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| 20130173894 | SHARING VIRTUAL FUNCTIONS IN A SHARED VIRTUAL MEMORY BETWEEN HETEROGENEOUS PROCESSORS OF A COMPUTING PLATFORM - A computing platform may include heterogeneous processors (e.g., CPU and a GPU) to support sharing of virtual functions between such processors. In one embodiment, a CPU side vtable pointer used to access a shared object from the CPU | 2013-07-04 |
| 20130173895 | METHOD AND APPARATUS FOR IMPROVING THE EFFICIENCY OF INTERRUPT DELIVERY AT RUNTIME IN A NETWORK SYSTEM - Processor affinity of an application/thread may be used to deliver an interrupt caused by the application/thread to a best processor at runtime. The processor to which the interrupt is delivered may either run the target application/thread or be located in the same socket as the processor that runs the target application/thread. The processor affinity of the application/thread may be pushed down at runtime to a network device, a chipset, a memory control hub (“MCH”), or an input/output hub (“IOH”), which will facilitate delivery of the interrupt using that affinity information. | 2013-07-04 |
| 20130173896 | METHODS AND APPARATUSES FOR DEFERRED OBJECT CUSTOMIZATION - A method and apparatus to record one or more customization messages in a storage are described. Each customization message may include one or more predicates specifying applicability of the customization message for a plurality of objects. An operation on the objects may be performed to generate a configuration of a device in response to receiving an event. The configuration may include the objects. Each customization message may be selectively applied to the objects in the configuration to customize the configuration. An object may be updated via the customization message if the predicates match the object in the configuration. The device may be configured via the customized configuration. | 2013-07-04 |
| 20130173897 | COMPUTER SYSTEM - A computer system including a configuration unit and a plurality of computers is provided. The configuration unit sends login information and key information to a basic input/output system (BIOS) setting unit in each of the computers to simultaneously configure and check the BIOS settings of the computers. | 2013-07-04 |
| 20130173898 | SECURE BOOT OF A DATA BREAKOUT APPLIANCE WITH MULTIPLE SUBSYSTEMS AT THE EDGE OF A MOBILE DATA NETWORK - A secure boot is provided for a breakout system having multiple subsystems at the edge of a mobile data network. The secure boot utilizes two trusted platform modules (TPM) to secure multiple subsystems. Further described is utilizing a first TPM to boot a service processor and then utilizing a second TPM to secure boot two additional subsystems. Booting of the final subsystem is accomplished in a two step process which first loads a boot loader and verifies the boot loader, and then second loads an operating system load image and verifies the operating system code. | 2013-07-04 |
| 20130173899 | Method for Secure Self-Booting of an Electronic Device - The present invention relates to a method for a self-boot of an electronic device, wherein an external component is accessible through an interface of the electronic device ( | 2013-07-04 |
| 20130173900 | KEY TRANSMISSION METHOD AND DEVICE OF A VIRTUAL MACHINE UNDER FULL DISK ENCRYPTION DURING PRE-BOOT - The disclosure provides a key transmission method and device of a virtual machine under full disk encryption during pre-boot. The method includes: pre-booting the virtual machine, where the virtual machine is in a full disk encryption state; during the pre-boot, establishing, by the virtual machine, a transmission channel with a cloud platform, where the cloud platform is configured to provide a key; requesting, by the virtual machine, the key from the cloud platform through the transmission channel, and receiving the key sent by the cloud platform; and decrypting, by the virtual machine, an operation system by using the key, and booting the operation system. In embodiments of the present disclosure, key transmission may be implemented during a pre-boot phase of the virtual machine, so as to boot the virtual machine. | 2013-07-04 |
| 20130173901 | MULTI-PROCESSOR COMPUTER SYSTEMS AND METHODS - Multi-processor computer systems and methods are provided. A multi-processor computer system can include a plurality of communicatively coupled processors ( | 2013-07-04 |
| 20130173902 | SPLIT DEEP POWER DOWN OF I/O MODULE - I/O logic can be separated into critical and non-critical portions, with the non-critical portions being powered down during processor idle. The I/O logic is separated into gate logic and ungated logic, where the ungated logic continues to be powered during a processor deep sleep state, and the gated logic is powered off during the deep sleep state. A power control unit can trigger the shutting down of the I/O logic. | 2013-07-04 |
| 20130173903 | UNIFIED NETWORK ARCHITECTURE HAVING STORAGE DEVICES WITH SECURE BOOT DEVICES - A unified computer network may be created between network devices, such as storage devices, servers, and client computing system through multiple protocols and multiple connections. Each of the connections, regardless of different protocols or physical connections, may employ secure communications links through a secure boot device. For example, a secure communications link may be created through a fibre channel over Ethernet (FCoE) protocol. | 2013-07-04 |
| 20130173904 | SECURE DATA COMMUNICATIONS WITH NETWORK BACK END DEVICES - Devices located on a back end of a web application in a private cloud may establish secure communications to other back end devices or client devices with a secure boot device integrated in the back end device. The secure boot device enables the back end component to cryptographically split data and encrypt data for transmission to other devices through a secure communications link. The secure communications link may improve security on private cloud networks. Further the secure communications link may improve security to allow back end devices to be located remote to other back end devices. | 2013-07-04 |
| 20130173905 | TRANSMITTING TERMINAL, RECEIVING TERMINAL, ID NUMBERING DEVICE, AND KEY TRANSMISSION METHOD - Provided is a transmitting terminal capable of sharing an encryption key among a number of specific apparatuses using fewer resources and securely. A transmitting terminal ( | 2013-07-04 |
| 20130173906 | CLONING STORAGE DEVICES THROUGH SECURE COMMUNICATIONS LINKS - New storage devices located remote to old storage devices may be cloned through a secure data communications link established with a secure boot device located in the storage device. The secure communications link cryptographically splits data and encrypts the data for transmission over unsecure public network through the secure communications link. The cloning process may be completed between the new storage device and the old storage device with little or no involvement from other devices. | 2013-07-04 |
| 20130173907 | PKI GATEWAY - A PKI gateway allows an enterprise to maintain a limited number of PKI protocol interfaces while servicing every standard and proprietary PKI protocol used by a customer of the enterprise. The PKI gateway listens for a PKI management request, adds contextual information needed by the certificate authority, translates the request into the appropriate protocol, and executes the request. | 2013-07-04 |
| 20130173908 | Hash Table Organization - Disclosed are various embodiments for improving hash table utilization. A key corresponding to a data item to be inserted into a hash table can be transformed to improve the entropy of the key space and the resultant hash codes that can generated. Transformation data can be inserted into the key in various ways, which can result in a greater degree of variance in the resultant hash code calculated based upon the transformed key. | 2013-07-04 |
| 20130173909 | KEY ENCRYPTION SYSTEM, METHOD, AND NETWORK DEVICES - A network includes encryption devices at customer sites and transport devices provide transport functionality for encrypted data for transmission across networks. A method of controlling access to a first plurality of functions of the encryption devices and access to a second plurality functions of the transport devices is disclosed. The method involves providing a customer with access to at least some of the first plurality of functions and providing a network service provider with access to at least some of the second plurality of functions. The method also involves providing the network service provider with restricted access to a first subset of the first plurality of functions and/or providing the network service provider with restricted access to a second subset of the second plurality of functions. This allows the customer and the service provider to share access to hardware resources such as the encryption devices and the transport devices. | 2013-07-04 |
| 20130173910 | METHOD FOR SHARING SECRET VALUES BETWEEN SENSOR NODES IN MULTI-HOP WIRELESS COMMUNICATION NETWORK - A method for sharing a secret key between a source node and a destination node includes (a) adding, at each forward intermediate node, a secret key between the forward intermediate node and a node before the forward intermediate node to the secret key sharing request message; (b) generating a shared secret key between the source node and the destination node from the secret key between the forward intermediate node and the node before the forward intermediate node added in the secret key sharing request message; (c) adding, at each backward intermediate node, a secret key between the backward intermediate node and a node before it to the secret key sharing response message; and (d) generating the shared secret key between the destination node and the source node from the secret key between the backward intermediate node and the node before it added in the secret key sharing response message. | 2013-07-04 |
| 20130173911 | TASTE-BASED AUTHENTICATION TO SECURELY SHARE DATA - Examples are disclosed for transforming a multi-dimensional attribute value for a taste related to an area of interest for a user of a computing device and encrypting or decrypting a ciphertext using the transformed multi-dimensional attribute value in order to securely share data with another computing device. | 2013-07-04 |
| 20130173912 | DIGITAL RIGHT MANAGEMENT METHOD, APPARATUS, AND SYSTEM - A digital right management method, including: generating, by a first user equipment having access right to shared digital contents, a common public key based on one or more public keys of one or more second user equipments intended to share the digital contents, respectively; encrypting, by the first user equipment, a key of the digital contents with the common public key to generate a ciphertext of the key of the digital contents; generating, by the first user equipment, from the ciphertext a new authorization certificate corresponding to the digital contents; and transmitting, by the first user equipment, the new authorization certificate and the digital contents to the second user equipments to instruct the second user equipments to share the digital contents in accordance with the new authorization certificate. | 2013-07-04 |
| 20130173913 | SECURE MECHANISMS TO ENABLE MOBILE DEVICE COMMUNICATION WITH A SECURITY PANEL - A method of arming or disarming a building security system includes transferring an electronic security credential file from an authorizing environment to a mobile computing device. The electronic security credential file is read by the mobile computing device to extract authentication data. The authentication data is transmitted from the mobile computing device and received at the building security system. Within the building security system, the authentication data is used to verify that a user of the mobile computing device is authorized to communicate with the building security system. The mobile computing device is enabled to communicate with the building security system only if the electronic security credential file has been used to verify that a user of the mobile computing device is authorized to communicate with the building security system. | 2013-07-04 |
| 20130173914 | Method for Certificate-Based Authentication - A method is disclosed for certificate-based authentication, in which a first subscriber authenticates himself to a second subscriber using a digital certificate associated to the first subscriber. The certificate specifies requirement(s) and the fulfillment of a requirement is ensured by a third subscriber. Within the framework of the authentication by the second subscriber, a validity condition is checked, and the certificate is classified as valid if the validity condition is fulfilled, based on the issue and/or absence of issue of the requirement(s) specified in the certificate by the third subscriber. Requirements may be used to restrict the validity of the certificate. The validity of a certificate can thereby be controlled in a simple and flexible manner without explicitly defining the validity in the certificate. The method can be used for authentication in any technical field, e.g., to authentication subscribers in the form of components of an automation system. | 2013-07-04 |
| 20130173915 | SYSTEM AND METHOD FOR SECURE NEWORK LOGIN - Systems and methods for providing an expedited login process that is relatively fast and that still provides a reasonable level of security and a reasonable method for mitigating compromised login information are described. In one configuration, a web server sends an anonymous unique machine readable login identifier code to a browser display of a client computer. A server account holding user then uses his smartphone to scan the code and send a message including the login identifier code and a smartphone identifier code to the server. The server obtains the identity of the user and authenticates the user by determining possession of the smartphone using the smartphone identifier. The server then uses the login identifier code to log the user into the server and into the user account at the client computer. | 2013-07-04 |
| 20130173916 | SECURE STORAGE SYSTEM FOR DISTRIBUTED DATA - The present invention relates to a system for distributed data storage that ensures the safety of the user data. In particular, the system of the present invention provides that the data stored in a cloud storage service are encrypted and their cryptographic keys are created from a remote device. In the context of the present invention, cloud is a set of servers that form an online service over the Internet, these servers are invisible to the user of the service pretending they form only a single server, thus forming a “cloud servers”. These keys will be divided and stored in cloud storage part and part on other devices. | 2013-07-04 |
| 20130173917 | SECURE SEARCH AND RETRIEVAL - A method and apparatus is disclosed herein for secure search and retrieval. In one embodiment, the method comprises receiving an encrypted, permuted search tree with nodes that have been permuted and encrypted, the encrypted permuted search tree having been encrypted with a first private encryption key; receiving, at a server, a query from a client, the query comprising a set of keywords, wherein each query term is encrypted with the first private encryption key; performing a search using the query, including performing an oblivious matching keyword test in which an evaluation occurs at each node of the tree to determine if one or more matches exist; and returning results based on a match of keywords for each document, the results including one or more encrypted leaf nodes of the tree, the encrypted leaf nodes encrypted with the first private encryption key. | 2013-07-04 |
| 20130173918 | DATA EXCHANGE TECHNOLOGY - A data exchange adaptor that synchronizes data between an enterprise system operated by a company and a cloud-based system operated by a third party other than the company. The data exchange adaptor enables exchange of data between the enterprise system and the cloud-based system and controls storage and retrieval of data at the enterprise system and the cloud-based system. The data exchange adaptor also performs transport level security for communications that exchange data between the enterprise system and the cloud-based system and access level security for data stored to the enterprise system and the cloud-based system. The data exchange adaptor further schedules synchronization of data between the enterprise system and the cloud-based system and allows the enterprise system to retain control over the synchronization of data between the enterprise system and the cloud-based system. | 2013-07-04 |
| 20130173919 | Method and System for Activation of Local Content with Legacy Streaming Systems - A method and system for activation of local content with legacy streaming systems are disclosed. In one embodiment, a storage device stores encrypted content. The encrypted content can be preloaded or downloaded into the storage device. To consume the content, a host device using the storage device receives a stream of data from a network. The host device then derives a key from the received stream of data and decrypts the encrypted content using the key derived from the received stream of data. Other embodiments are possible, and each of the embodiments can be used alone or together in combination. | 2013-07-04 |
| 20130173920 | SYSTEM AND METHOD FOR AUTOMATICALLY VERIFYING STORAGE OF REDUNDANT CONTENTS INTO COMMUNICATION EQUIPMENTS, BY DATA COMPARISON - A method is intended for verifying storage of contents into communication equipments connected to at least one communication network. This method consists, when a first communication equipment stores a content and wants to verify that this content is still stored into a second communication equipment: i) in transmitting a first request, comprising at least an identifier of this content and first data representative of this content and requiring verification of the storage of this content into the second communication equipment, to an auxiliary communication equipment acting as an interface between the communication network and the second communication equipment, ii) in transmitting a second request, comprising at least the content identifier, to the second communication equipment, to require transmission of second data representative of the content to the auxiliary communication equipment, and in triggering a timeout having a chosen duration, and iii) if the auxiliary communication equipment has received the second data before expiration of this timeout, in comparing these received second data, possibly after having processed them, to the received first data, and in transmitting a message representative of the result of this comparison to the first communication equipment. | 2013-07-04 |
| 20130173921 | SYSTEM AND METHOD FOR USING A STREAMING PROTOCOL - An initialization vector (IV) is employed to decrypt a block of a stream that has been encrypted with Cypher Block Chaining (CBC) encryption, without requiring decryption of previous blocks within the stream. For example, a listener who accesses a distribution point to retrieve encrypted content authenticates himself to an application server that regulates access to encrypted content on the distribution point, and responsively receives a key. The listener then requests access to a reference point within the encrypted content stream somewhere after its beginning (e.g., using preview clips). The distribution point relates the reference point to a corresponding block of the encrypted stream, and identifies an IV previously used for encryption of that block. The distribution point provides the associated encrypted block of content and the IV to the listener to enable mid-stream rendering of the encrypted content, without requiring the listener to decrypt previous blocks within the encrypted stream. | 2013-07-04 |
| 20130173922 | METHOD FOR CERTIFICATE-BASED AUTHENTICATION - A first subscriber authenticates himself to a second subscriber with a certificate associated to the first subscriber. The certificate specifies one or several characteristics, which have to be fulfilled by the second subscriber. In the course of the authentication, it is verified using the certificate whether the second subscriber fulfills the characteristics, wherein a criterion required for successful authentication is that the second subscriber fulfills the characteristics(s). Characteristics of the second subscriber are verified in the framework of the authentication process, the second subscriber representing the authenticator with respect to whom the authentication is carried out. In this way, certificates for authentication dedicated communication links between two communication partners can be determined. The method can be used for any subscribers in a communication network, e.g., representing components of an automation system, such as, for example, control devices, field devices, sensors, actuators and the like. | 2013-07-04 |
| 20130173923 | METHOD AND SYSTEM FOR DIGITAL CONTENT SECURITY COOPERATION - A method for digital content security cooperation, including: creating, by a first content possessing device, a cooperation content packet of digital contents and transmitting the created cooperation content packet to at least one of a second content possessing device or a first content cooperating device, wherein the cooperation content packet includes an attribute data block and a content data block; and performing, by the first content cooperating device receiving the cooperation content packet, privilege verification according to the cooperation content packet, and after the privilege verification is passed, updating the information in the content data block in the cooperation content packet, and transmitting the cooperation content packet including the updated information to at least one of a second content cooperating device or the first content possessing device. | 2013-07-04 |
| 20130173924 | METHOD AND APPARATUS OF CIPHER COMMUNICATION FOR MANAGEMENT FRAME USING QUALITY OF SERVICE MECHANISM IN WIRELESS LOCAL AREA NETWORK SYSTEM - A method of cipher communication for management frame performed by station in wireless local area network system is provided. The method includes obtaining a first pseudonoise code sequence (PN) for a plaintext Medium Access Control (MAC) protocol data unit (MPDU), constructing an additional authentication data (AAD) by using fields in a header of the plaintext MPDU, constructing a Nonce value from the PN, an Address 2 and a Priority field in the header of the plaintext MPDU, generating a encrypted MPDU from the plaintext MPDU by using a temporal key, the AAD, and the Nonce value, and transmitting the encrypted MPDU to a peer station, wherein the plaintext MPDU is a management frame including a sequence number field, the sequence number field including access category field indicating category of data included in the plaintext MPDU, and the Nonce value includes a priority field matched with the access category field. | 2013-07-04 |
| 20130173925 | Systems and Methods for Fingerprint-Based Operations - A method for operating a system based on fingerprint scanning inputs includes receiving, by a fingerprint sensor, a fingerprint input and providing, from a processor coupled with the fingerprint sensor, fingerprint feature data representing features of the fingerprint input. The method also includes executing a first command, by the processor, if comparing the fingerprint feature data with at least a portion of stored fingerprint data results in a first match reflecting that the fingerprint input occurred in a first direction and executing a second command that is different from the first command, by the processor, if comparing the fingerprint feature data with the at least a portion of the stored fingerprint data results in a second match reflecting that the fingerprint input occurred in a second direction. | 2013-07-04 |
| 20130173926 | Method, Apparatus and Applications for Biometric Identification, Authentication, Man-to-Machine Communications and Sensor Data Processing - Applications, algorithms and technologies are disclosed for machine-to-machine communications, biometric identification and sensor data fusion. Applications include authentication, e-commerce and energy management. Algorithms include biometric signature generation and identification, as well as data fusion methods. Technologies include biometric and environmental sensing and identification. Advantages of the invention include more robust person authentication, greater immunity to theft of personal property and information, and enhanced building energy management. | 2013-07-04 |
| 20130173927 | SECURE REGISTRATION-FREE FINGERPRINT AUTHENTICATION METHOD AND SYSTEM BASED ON LOCAL FEATURES - A secure registration-free fingerprint authentication method based on local structures comprising: extracting descriptor features and local structure features of fingerprint minutiae from an input fingerprint image; conducting quantization and feature selection with respect to the features of the fingerprint minutiae; and encrypting the selected features and then decrypting the encrypted features to obtain the fingerprint image. The method adopts local features for fingerprint authentication, thus avoiding the complex registration in encryption domain. The method lowers the risk of the fingerprint authentication being attacked and improves security. | 2013-07-04 |
| 20130173928 | CRYPTOGRAPHIC DEVICE WITH RESISTANCE TO DIFFERENTIAL POWER ANALYSIS AND OTHER EXTERNAL MONITORING ATTACKS - Techniques usable by devices to encrypt and decrypt sensitive data to in a manner that provides security from external monitoring attacks. The encrypting device has access to a base secret cryptographic value (key) that is also known to the decrypting device. The sensitive data are decomposed into segments, and each segment is encrypted with a separate encryption key derived from the base key and a message identifier to create a set of encrypted segments. The encrypting device uses the base secret cryptographic value to create validators that prove that the encrypted segments for this message identifier were created by a device with access to the base key. The decrypting device, upon receiving an encrypted segments and validator(s), uses the validator to verify the message identifier and that the encrypted segment are unmodified, then uses a cryptographic key derived from the base key and message identifier to decrypt the segments. | 2013-07-04 |
| 20130173929 | CRYPTOGRAPHIC PROCESSING SYSTEM, KEY GENERATION DEVICE, ENCRYPTION DEVICE, DECRYPTION DEVICE, CRYPTOGRAPHIC PROCESSING METHOD, AND CRYPTOGRAPHIC PROCESSING PROGRAM - The object is to provide a secure functional encryption scheme having many cryptographic functions. An access structure is constituted by applying the inner-product of attribute vectors to a span program. The access structure has a degree of freedom in design of the span program and design of the attribute vectors, thus having a large degree of freedom in design of access control. A functional encryption process is implemented by imparting the access structure to each of a ciphertext and a decryption key. | 2013-07-04 |
| 20130173930 | ADDING OR REPLACING DISKS WITH RE-KEY PROCESSING - In a network of multiple storage devices, a storage device may become faulty and need to be replaced or additional capacity may need to be added through additional storage devices. When the storage devices communicate through a secure communications link using an encryption key for cryptographically splitting data, replacement or new storage devices may be re-keyed using an encryption key from an existing or prior storage device on the secure data network. After the storage device is re-keyed, the new or replacement storage device may continue to function on the secure data network without requiring changes to clients accessing the secure data network. | 2013-07-04 |
| 20130173931 | Host Device and Method for Partitioning Attributes in a Storage Device - A host device and method for partitioning attributes in a storage device are provided. In one embodiment, a host device is provided that is in communication with a storage device storing a table associating logical address ranges with an encryption key and read/write permissions. The host device sends a request to the storage device to add a column to the table and then sends a request to the storage device to add an attribute to a cell of the added column to the table associated with a particular logical address range. The table and commands can be those compatible with the Trusted Computing Group's (TCG's) Opal standard. | 2013-07-04 |
| 20130173932 | Systems and Methods for Decimation Based Over-Current Control - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system. In some such systems and methods, the operation of one or more calibration circuits is modified when it is determined that too many data processing circuits are active. | 2013-07-04 |
| 20130173933 | PERFORMANCE OF A POWER CONSTRAINED PROCESSOR - Provided is a method for improving performance of a processor. The method includes computing utilization values of components within the processor and determining a maximum utilization value based upon the computed utilization values. The method also includes comparing (i) the maximum utilization value with a first threshold and (ii) differences between the computed utilization values and a second threshold. | 2013-07-04 |
| 20130173934 | MOTHERBOARD - A motherboard includes a central processing unit (CPU), a drive, and a voltage-state display system to display a voltage mode of the CPU. The voltage-state display system includes a power management chip, a first transistor, a second transistor, a first light emitting diode (LED), and a second LED. A first phase output terminal of the power management chip is connected to the first LED through the first transistor. A second phase output terminal of the power management chip is connected to the second LED through the second transistor. The LEDs indicate the voltage mode of the CPU. | 2013-07-04 |
| 20130173935 | POWER CONTROL METHOD AND APPARATUS FOR ARRAY PROCESSOR - Provided is an apparatus and method for controlling power to a reconfigurable array processor. The method may determine one or more function units (FUs) as activation function units (FUs) and deactivation FUs among a plurality of FUs included in the reconfigurable array processor. The processor may interrupt power supplied to the deactivation FUs. | 2013-07-04 |
| 20130173936 | POWER DISTRIBUTION INSIDE CABLE - Circuits, methods, and apparatus that provide for the powering of active components in connector inserts at each end of a cable may in various ways. For example, where a host is coupled to a device that is not self-powered, the host may provide power for circuitry at each end of the cable. In various embodiments of the present invention, the device may request higher voltage from the host, such that more power can be delivered. In these cases, the device may regulate the voltage received from the host to a lower voltage, and then provide the lower voltage to circuitry at one or both ends of the cable. Where the host is connected to a device that is self-powered, the host and the self-powered device may power their respective connector insert circuits. | 2013-07-04 |
| 20130173937 | EXPANDABLE ETHERNET POWER SUPPLY DEVICE - An expandable Ethernet power supply device includes a network line, a power sourcing equipment (PSE), a DC power inputting terminal and a power outputting terminal. A PoE outputting port is inserted into network equipment. An Ethernet connector is connected to a network data source. A DC power is inputted to the DC power inputting terminal and managed by the PSE, and then providing demanded working voltage of the network equipment and transmitting network data. The power outputting terminal is provided for connecting to the DC power inputting terminal of another Ethernet power supply device and demanded working voltage of more network equipment. | 2013-07-04 |
| 20130173938 | DATA PROCESSING DEVICE AND PORTABLE DEVICE HAVING THE SAME - A data processing device includes a plurality of central processing unit (CPU) cores; a plurality of first switches connected between a power line and each of the plurality of CPU cores, respectively; a power management unit; and a dynamic voltage/frequency scaling control circuit configured to scale at least one of a voltage and a frequency of a clock signal which are supplied to each of the CPU cores according to a control of the power management unit, wherein the power management unit is configured to decrease at least one of the voltage and the frequency which are supplied to each of the CPU cores and generate each of first control signals controlling a switching operation of each of the plurality of first switches, according to a control of one of the CPU cores. | 2013-07-04 |
| 20130173939 | Modular Combined Optical Data Network and Independent DC Power Distribution System - This invention relates to a modular combined optical data and electrical power distribution network and related system. More particularly the invention relates to a system for bi directional high-speed distribution of data and the universal transmission of significant quantities of electrical power using composite cabling which is adapted for connection to a plurality of peripheral components and devices. Previous data networks, particularly in domestic environments, for example for controlling personal computers, laptops and peripherals such as printers and scanners required dedicated power supplies and resulted in a tangled mass of wires and cabling often seen as clutter and sometimes posing safety hazards. The invention overcomes this prob- lem by providing a relatively low voltage continual power bus, in the foim of a dual or multi-core wire, which typically carries up to 100-200 Watts per node and which is also capable of carrying high volumes of data traffic typically in excess of 1 GBit/sec. The invention comprises: a data bus and an electrical conductor encased within a sleeving, the data bus defining a path for data and the conductor defming an electrical path. The sleeving is shaped and dimensioned so as to be capable of receiving junction connectors which, in use pierce the sleeving, so as to provide simultaneous connection to the data bus and electrical path. This is combined with intelligent power and data circuitry. | 2013-07-04 |
| 20130173940 | SYSTEM AND METHOD FOR AUTO-DISCOVERY AND MAPPING OF NETWORKED MODULES - A method of performing automated discovery and mapping of the topology of a network is provided, wherein the networked modules include discovery and mapping-enabled modules and standard modules that are not discovery and mapping-enabled and wherein the network connections include both data connections and power connections. The method comprises the following steps: a) powering up all discovery and mapping-enabled modules on the network with current trips set to maximum level; b) powering up all standard modules; c) determining what modules are on the network; d) determine the topology of the network, including where the modules are connected within the network; e) using the determined topology to determine power requirements for the modules on the network; and f) adjusting the power distribution on the network to accommodate the identified power needs of the network. | 2013-07-04 |
| 20130173941 | Controlling Temperature Of Multiple Domains Of A Multi-Domain Processor - In one embodiment, the present invention includes a method for determining, in a controller of a multi-domain processor, whether a temperature of a second domain of the multi-domain processor is greater than a sum of a throttle threshold and a cross-domain margin, and if so, reducing a frequency of a first domain of the multi-domain processor by a selected amount. In this way, a temperature of the second domain can be allowed to reduce, given a thermal coupling of the domains. Other embodiments are described and claimed. | 2013-07-04 |
| 20130173942 | FAST PLATFORM HIBERNATION AND RESUMPTION OF COMPUTING SYSTEMS - Secure fast platform hibernation and resumption for computing systems. An embodiment of an apparatus includes a processor to operate according to an operating system, the processor to transition the apparatus to a first reduced power state in response to a request, the transition to the first reduced power state including the processor to store context data for the apparatus in a volatile system memory, and logic to transition the apparatus to a second reduced power state, the logic to write the context data from the volatile system memory to a nonvolatile memory for the transition to the second reduced power state, wherein the logic is to implement one or more security measures for the writing of the context data into the nonvolatile memory. | 2013-07-04 |
| 20130173943 | IMAGE FORMING APPARATUS, SYSTEM ON CHIP UNIT AND DRIVING METHOD THEREOF - An image forming apparatus connected to a host apparatus includes a first memory; a second memory; a USB interface to receive a USB control signal or a USB data signal from the host apparatus; a first CPU to perform an operation using the first memory in a normal mode and being deactivated if the normal mode is converted into a power saving mode; and a second CPU to perform an operation using the second memory in the power saving mode. In the image forming apparatus, if the USB data signal is input in the power saving mode, the second CPU activates the first CPU to convert the power saving mode into the normal mode, and if the USB control signal is input in the power saving mode, the second CPU retains the power saving mode and performs an operation corresponding to the USB control signal using the second memory. | 2013-07-04 |
| 20130173944 | REDUCING POWER CONSUMPTION OF MEMORY - Described embodiments provide for a memory system having a transparent source bias (TSB) circuit. A monitor in the memory system monitors a process, temperature, and/or a leakage current of the memory. The system determines whether at least one of the monitored process, temperature, and leakage current reaches a corresponding threshold. The threshold is set based on a power budget of the memory. If the corresponding threshold is reached, the TSB is disabled and the memory operates at a relatively high speed. If the corresponding threshold is not reached, the TSB is enabled and the memory operates at a relatively law speed. | 2013-07-04 |
| 20130173945 | CONTROL METHOD, CONTROL DEVICE AND TERMINAL - A control method, a control apparatus and a terminal are provided according to embodiments of the present invention. The method includes: receiving a trigger event; determining from the trigger event whether the terminal enters a limited operation mode in which at least one component of the terminal is unusable; generating a first control instruction when it is determined that the terminal enters the limited operation mode; and controlling to turn off power supply to the at least one component terminal according to the first control instruction. With the present invention, it is possible to switch the terminal system between a limited operation mode and a normal operation mode in terms of hardware, thereby saving power and satisfying the low-carbon environmental preservation requirements. | 2013-07-04 |
| 20130173946 | CONTROLLING POWER CONSUMPTION THROUGH MULTIPLE POWER LIMITS OVER MULTIPLE TIME INTERVALS - Methods and apparatus relating to controlling power consumption through multiple power limits over multiple time intervals are described. In one embodiment, the level of power consumption by a computing device component (e.g., a processor or one of its processor cores) is modified based on a determined power limit value. The power limit value may be determined based on rolling power consumption averages over multiple time intervals and their comparison against multiple corresponding power limits. Other embodiments are also disclosed and claimed. | 2013-07-04 |
| 20130173947 | DEVICE AND METHOD FOR CALCULATING BATTERY USABLE TIME PERIOD FOR MOBILE STATION - A device includes a retrieval unit that retrieves information regarding usage conditions including operating time periods indicating extents of utilizing corresponding plural functions included in a mobile station by a user; a storing unit that stores, for each of operating mode of the mobile station, average consumed current values for the corresponding plural functions; a calculating unit that calculates, for each of the operating modes, a battery usable time period by calculating an added value, the added value being obtained by adding a product of the average consumed current value for one of the functions and the operating time period of the one of the functions over the plural functions, and by dividing a capacity value of a battery included in the mobile station by the added value; and a display unit that displays the battery usable time periods to the user. | 2013-07-04 |
| 20130173948 | Frequency And Voltage Scaling Architecture - A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the invention relate to techniques to divide a microprocessor into clock domains and control the frequency and operating voltage of each clock domain independently of the others. | 2013-07-04 |
| 20130173949 | HS-CAN BUS CLOCK RECOVERY USING A TRACKING OSCILLATOR CIRCUIT - A method for recovering a clock frequency of a CAN bus, the method including: receiving a data signal, wherein the data signal includes at least one state transition; detecting the state transition; and adjusting a frequency of a clocking signal generated by an oscillator circuit, wherein the frequency is adjusted when the state transition is detected and adjusting the frequency is for recovering the clock frequency of the CAN bus. | 2013-07-04 |
| 20130173950 | METHOD AND APPARATUS FOR COMMUNICATING TIME INFORMATION BETWEEN TIME AWARE DEVICES - According to one embodiment, an apparatus includes a first processing unit operating according to a first clock, a second processing unit operating according to a second clock running separately from the first clock, and a synchronization controller coupled to the first communication unit and the second communication unit. The synchronization controller is configured to (i) cause the first communication unit to generate a first indication of time at which the first processing unit transmits a signal to the second processing unit, according to the first clock, (ii) cause the second processing unit to generate a second indication of time at which the second processing unit receives the signal, according to the second clock, and (iii) determine an offset between the first clock and the second clock based on the first indication of time and the second indication of time. | 2013-07-04 |
| 20130173951 | CONTROLLING COMMUNICATION OF A CLOCK SIGNAL TO A PERIPHERAL - A method of communicating in an electronic system or apparatus is disclosed. The method includes using a processor to communicate with a peripheral. The method further includes using the peripheral to request a clock signal. The method also includes selectively control communication of the clock signal to the peripheral in response to the request. | 2013-07-04 |
| 20130173952 | ELECTRONIC DEVICE AND METHOD FOR LOADING FIRMWARE - An electronic device includes an internal storage module, a baseboard management controller (BMC) and a port. The internal storage module stores a first firmware and a boot application. The port connects to an external storage for storing a second firmware which is a backup of the first firmware. After the electronic device is powered on, the BMC runs the boot application to load the first firmware from the internal storage module. If the first firmware fails to load, the BMC copies the second firmware from the external storage to the internal storage module to replace the first firmware. | 2013-07-04 |
| 20130173953 | METHOD AND APPARATUS FOR RESTORING A CONNECTION THROUGH A PROVIDER NETWORK UPON REQUEST - A method and related apparatus are provided for restoring a connection through a provider network (PN). In particular, a connection is established along a path (P | 2013-07-04 |
| 20130173954 | METHOD OF MANAGING BAD STORAGE REGION OF MEMORY DEVICE AND STORAGE DEVICE USING THE METHOD - A method of managing a bad storage region of a memory device may include detecting a bad page of a selected data block that has failed in one of a program operation, a read operation, and an erase operation on the memory device; and performing a mapping process so that the detected bad page is excluded from a storage region to which data is to be programmed, wherein remaining pages of the selected data block excluding the bad page are allowed to be used as a storage region in a garbage collection operation. | 2013-07-04 |
| 20130173955 | DATA PROTECTION IN A RANDOM ACCESS DISK ARRAY - A disk array memory system comprises: a plurality of disks in a disk array for storage of content data and parity data in stripes, content data in a same stripe sharing parity bits of said parity data, each disk having a spare disk capacity including at least some of a predefined array spare capacity, said array spare capacity providing a dynamic space reserve over said array to permit data recovery following a disk failure event; a cache for caching content data prior to writing to said disk array; and a controller configured to select a stripe currently having a largest spare stripe capacity, for a current write operation of data from said cache, thereby to write all said data of said current write operation on a same stripe, thereby to maximize sharing of parity bits per write operation and minimize separate parity write operations. | 2013-07-04 |
| 20130173956 | USING PARITY DATA FOR CONCURRENT DATA AUTHENTICATION, CORRECTION, COMPRESSION, AND ENCRYPTION - A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data. | 2013-07-04 |
| 20130173957 | Peripheral Component Interconnect Express Root Port Mirroring - An information handling system includes a peripheral component interconnect express root complex, a basic input output system, and a root complex mirroring block. The peripheral component interconnect express root complex includes a plurality of peripheral component interconnect express ports. The basic input output system is in communication with the peripheral component interconnect express root complex, and is configured to detect a peripheral component interconnect express adaptor configuration, and to set a peripheral component interconnect express mirroring setting based on the peripheral component interconnect express adaptor configuration. The root complex mirroring block is in communication with the basic input output system, and is configured to mirror data between a first peripheral component interconnect express adaptor and a second peripheral component interconnect express adaptor based on the peripheral component interconnect express mirroring setting. | 2013-07-04 |
| 20130173958 | Extending Cache In A Multi-Processor Computer - Methods, apparatuses, and computer program products of extending cache in a multi-processor computer are provided. Embodiments include detecting, by a donor processor, nonuse of a donor processor's cache; broadcasting to one or more processors in the multi-processor computer, by the donor processor, a donor-ready message indicating the donor processor's cache is available for ownership transferment; receiving from a first requesting processor, by the donor processor, a first ownership-request message requesting ownership of the donor processor's cache by the first requesting processor; transmitting to the first requesting processor, by the donor processor, an ownership-grant message indicating an intention of the donor processor to transfer ownership of the donor processor's cache to the first requesting processor; and receiving from the first requesting processor, by the donor processor, an ownership-claim message indicating that the first requesting processor intends to claim ownership of the donor processor's cache. | 2013-07-04 |
| 20130173959 | HOME/BUILDING FAULT ANALYSIS SYSTEM USING RESOURCE CONNECTION MAP LOG AND METHOD THEREOF - Provided are a home/building fault analysis system and method using a resource connection map log which compares and analyzes a previous integrated resource state and a current resource state using resource connection map logging information based on a standard resource management model when a fault is generated, provides state information of the resource in which information having high association with a fault resource is mainly changed, and performs an effective fault analysis and process by restoring to the previous resource state, as necessary. According to the prevent invention, when the fault is generated, a synthetic state of resources within a home/building as well as a state of an individual resource may be known from the resource connection map. | 2013-07-04 |
| 20130173960 | Method for Checking an Installation Location of a Component and Automation Component - A method for checking an installation location of a component in a failsafe automation system, wherein the components are connected to one another in series and uniquely defined addresses are continuously assigned from a first component to successor components, wherein, after the assignment of addresses to the components, a switching device is operated in the components such that a signal transit time measurement is performed incrementally with a test signal for each successor component, and wherein the test signal is emitted and re-received and the installation location of the successor component is check based on the time difference. | 2013-07-04 |
| 20130173961 | MEMORY-LEAK IDENTIFICATION - A memory-leak source in a data structure can be identified by counting insertions into the data structure and deletions from the data structure for locations in the execution path of a computer program. These insertion and deletion values can be used to identify at least one location as a memory-leak source that corresponds to an imbalance between insertions and deletions during the execution of the computer program. | 2013-07-04 |
| 20130173962 | Test Execution Spanning Cloud and Local Devices - A test system for a managed cloud computing environment may have a management system that may recruit devices in the cloud and outside the cloud to perform a test on a cloud based application. Each device may execute an agent that connects the device to several cloud services for messaging, data collection, and executable code storage. The management system may identify and gather the devices, then cause the devices to execute a test by sending commands through the messaging service. The devices may access executable code for the specific tasks of a test through the code storage service, and as the devices complete tasks for the test, the devices may publish results in the data collection service. The test system enables any type of scenario to be implemented, including operations that can only be performed inside and outside the managed cloud environment. | 2013-07-04 |
| 20130173963 | DYNAMIC TESTING OF NETWORKS - Service providers strive to maintain networks with high levels of availability and performance. To maintain the networks, the service providers measure performance and perform network diagnostics. Measuring performance and performing network diagnostics typically involves manual verification of functionality or performing individual tests between user agents. Service providers who maintain networks and service providers who use networks can dynamically run tests with operations of a signaling protocol (e.g., session initiation protocol) to diagnose network problems and determine appropriate responses. An agent manager can coordinate the dynamic tests across multiple user agents to gather more information to increase problem diagnosis accuracy. | 2013-07-04 |
| 20130173964 | METHOD OF MANAGING FAILURE, SYSTEM FOR MANAGING FAILURE, FAILURE MANAGEMENT DEVICE, AND COMPUTER-READABLE RECORDING MEDIUM HAVING STORED THEREIN FAILURE REPRODUCING PROGRAM - A failure management device includes a stored position obtainer that obtains stored position data that represents a position at which failure data is generated by an information processing apparatus when a failure is occurring; a failure data obtainer that obtains the failure data generated by the information processing apparatus from a memory device, communicably connected to the information processing apparatus and the failure management device, on the basis of the stored position data; and a configuration controller that changes, on the basis of the failure data obtained by the failure data obtainer, a configuration of the failure management device so as to conform to that of the information processing apparatus. This configuration makes it possible to easily reproduce the failure occurred in the information processing apparatus and consequently, a reproducing test can be accomplished efficiently. | 2013-07-04 |
| 20130173965 | FAULT TRACING SYSTEM AND METHOD FOR REMOTE MAINTENANCE - Provided is a fault tracing system and method for remote maintenance. The fault tracing method includes detecting faults by receiving error events or fault diagnosis request messages, generating transactions for the detected faults, tracing the faults according to the transactions, and notifying a client terminal or user of the fault diagnosis results. Accordingly, it is possible to accurately trace a fault even in a home/building network environment complicatedly consisting of various resources. | 2013-07-04 |
| 20130173966 | MEMORY CONTROLLER AND MEMORY ACCESS SYSTEM - A controller section outputs a first signal and a second signal holding a phase relationship with the first signal. The second signal is received by a memory I/F section via a FIFO memory of an error detecting section. The memory I/F section performs timing adjustment for the first and second signals, outputs the first and second signals after the timing adjustment to a memory, and loops back the second signal. A data comparator compares the looped-back second signal with the original second signal outputted from the FIFO memory and corresponding to the looped-back signal. | 2013-07-04 |
| 20130173967 | HARD MEMORY ARRAY FAILURE RECOVERY UTILIZING LOCKING STRUCTURE - A technique for managing hard failures in a memory system employing a locking is disclosed. An error count is maintained for units of memory within the memory system. When the error count indicates a hard failure, the unit of memory is locked out from further use. An arbitrary set of error counters are assigned to record errors resulting from access to the units of memory. Embodiments of the present invention advantageously enable a system to continue reliable operation even after one or more internal hard memory failures. Other embodiments advantageously enable manufacturers to salvage partially failed devices and deploy the devices as having a lower-performance specification rather than discarding the devices, as would otherwise be indicated by conventional practice. | 2013-07-04 |
| 20130173968 | DYNAMIC LINK LIBRARY INTEGRITY CHECKING FOR HANDHELD MEDICAL DEVICES - A method of checking the integrity of a dynamic link library (DLL) file called by an application being executed on a handheld medical device is described. The method includes loading a DLL from a read only memory (ROM) to a random access memory (RAM) beginning at a fixed location in the RAM. The DLL includes a first routine for performing a safety critical function of the handheld medical device and a second routine for performing a cyclical redundancy check (CRC) once the DLL is loaded to the RAM. The method includes selectively executing the first routine from the RAM. The method includes selectively executing the second routine from the RAM including: calculating a check value based on the DLL; comparing the check value with a predetermined check value; and indicating that an error is present when the check value is different than the predetermined check value. | 2013-07-04 |
| 20130173969 | TRANSMISSION DEVICE, TRANSMISSION SYSTEM, AND FAULT NOTIFICATION METHOD - A link failure information transmission unit | 2013-07-04 |
| 20130173970 | MEMORY DEVICE WITH BACKGROUND BUILT-IN SELF-TESTING AND BACKGROUND BUILT-IN SELF-REPAIR - A memory device with background built-in self-testing (BBIST) includes a plurality of memory blocks; a memory buffer to offload data from one of the plurality of memory blocks temporarily; and a memory block stress controller to control a stress test applied to the one of the memory blocks when the data is temporarily offloaded on the memory buffer. The stress test tests for errors in the one of the plurality of the memory blocks. | 2013-07-04 |
| 20130173971 | BOUNDARY SCAN CHAIN FOR STACKED MEMORY - A boundary scan chain for stacked memory. An embodiment of a memory device includes a system element and a memory stack including one or more memory die layers, each memory die layer including input-output (I/O) cells and a boundary scan chain for the I/O cells. A boundary scan chain of a memory die layer includes a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including a first scan logic multiplexer a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and a decoder to provide command signals to the boundary scan chain. | 2013-07-04 |
| 20130173972 | SYSTEM AND METHOD FOR SOLID STATE DISK FLASH PLANE FAILURE DETECTION - A system and method for early detection and reporting of an impending NAND Flash device plane failure. Each time that a data unit is retrieved from a NAND Flash array the number of bits in error and the memory location associated with the errors is observed. if the number of bits in error or the error rate for a memory location exceeds a threshold of the number of bits in error per data, retrieval, or number of bits in error per data unit per unit time, a NAND Flash plane failure Patrol Read operation is performed at the memory location, regardless of where in the cycle the Patrol Read function is in a scrub of the overall NAND Flash device. The NAND Flash plane failure Patrol Read is repeated for a number of cycles on the NAND Flash plane in question. | 2013-07-04 |
| 20130173973 | DEVICE - A device includes memory banks, each having a plurality of memory cells with respective error data output circuits. Each of the error data output circuits outputs first to M-th (M is an integer of 2 or more) error data according to first to M-th data retrieved from first to M-th memory cell groups selected from its corresponding memory bank. A test control circuit has first error data synthesis circuits and second to (M+1)-th error data synthesis circuits, each of which synthesizes the first to M-th error data from a corresponding error data output circuit and outputs the synthesized data as first test data. Each of the error data synthesis circuits synthesizes m-th (m is an integer of from 1 to M) error data from the error data output circuits and outputs the synthesized data as (m+1)-th test data. | 2013-07-04 |
| 20130173974 | COMPUTER MEMORY TEST STRUCTURE - A method and apparatus for a computer memory test structure. An embodiment of a method for testing of a memory board includes testing a memory of the memory board, where testing the memory including use of a built-in self-test structure to provide a first test pattern for the memory. The method further includes testing an IO (input output) interface of the memory with a host, where testing of the IO interface includes use of the built-in self-test structure to provide a second test pattern for the IO interface. | 2013-07-04 |
| 20130173975 | METHOD OF TESTING FLASH MEMORY - A method of testing a flash memory is applied to retrieve the flash memory available by picking up a defective flash memory. The flash memory includes at least a block, a page, and a cell. The method comprises inputting a test command into the flash memory to execute at least one of write, read, or compare of the flash memory. After the test command is executed, the states of the block, page, and cell in the flash memory may be obtained. The states are marked in a flash memory distribution list to allow a controller to access at least one of the normal block, page, and cell from the list. Thus, in the method, the normal block, page, and cell may be obtained. | 2013-07-04 |
| 20130173976 | Scan Test Circuitry with Delay Defect Bypass Functionality - An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells. The scan test circuitry further comprises scan delay defect bypass circuitry comprising a plurality of multiplexers arranged within said at least one scan chain. At least a given one of the multiplexers is configured to allow a corresponding one of the scan cells to be selectively bypassed in a scan shift configuration of the scan cells responsive to a delay defect associated with that scan cell. A delay defect bypass controller may be used to generate a bypass control signal for controlling the multiplexer between at least a first state in which the corresponding scan cell is not bypassed and a second state in which the corresponding scan cell is bypassed. | 2013-07-04 |
| 20130173977 | HIGH DENSITY FLIP-FLOP WITH ASYNCHRONOUS RESET - A master/slave latch includes an input stage, a master latch, a slave latch, and receives an asynchronous clear signal. The input stage is arranged to alternately pass or block a data input signal in response to a clock signal and a gated clock signal. The gated clock signal is the inverse of the clock signal when the asynchronous clear signal is not asserted, and the gated clock signal is not active when the asynchronous clear signal is asserted. The master latch receives and latches the passed data signal in a latched state, clears the latched state in response to the asynchronous clear signal being asserted, and generates a master latch output signal. The slave latch receives and latches the master latch output signal in a latched state. The cleared latched state is passed to the slave latch in response to the asynchronous clear signal being asserted. | 2013-07-04 |
| 20130173978 | MULTIPLE INPUT AND/OR OUTPUT DATA FOR BOUNDARY SCAN NODES - A boundary scan node of a boundary scan chain for testing an associated node of core logic core logic includes a first boundary scan cell having an input that is coupled to a first data output of the core logic. A second boundary scan cell having an output is coupled to a first data input of the core logic. A programmable series connection is arranged to selectively couple an output of the first boundary scan cell to an input of the second boundary scan cell when the boundary scan node is arranged in an internal test mode for the core logic. Test stimulus can be written to the boundary scan node using a data register clock and test results can be read from the boundary scan node using the data register clock. | 2013-07-04 |
| 20130173979 | HIGH PERFORMANCE COMPACTION FOR TEST RESPONSES WITH MANY UNKNOWNS - A circuit arrangement for controlling the masking of test and diagnosis data with X values of an electronic circuit with N scan paths, wherein the test data are provided on insertion into the N scan paths by a decompressor with m inputs and N outputs (m| 2013-07-04 | |
| 20130173980 | SWITCHING CONVERTER WITH PULSE SKIPPING MODE AND CONTROL METHOD THEREOF - The present invention provides a switching converter with pulse skipping mode. The switching converter comprises a switching circuit having at least one switch, a controller and a feedback circuit. The controller comprises an error amplifying circuit, a logic circuit, a ramp signal generator and a pulse skipping circuit. The error amplifying circuit generates a compensation signal based on comparing the feedback signal with a reference signal. The logic circuit generates a control signal to control the ON and OFF switching of the at least one switch based on the compensation signal. The ramp signal generator generates a ramp signal. The pulse skipping circuit generates a pulse skipping signal based on the compensation signal, the ramp signal and a threshold voltage. The logic circuit skips one or more switching pulses of the control signal in accordance with the pulse skipping signal. | 2013-07-04 |
| 20130173981 | NON-BINARY QC-LDPC CODE DECODING DEVICE AND ASSOCIATED METHOD - A non-binary quasi-cyclic (QC) low-density parity-check (LDPC) code decoding device comprises a first barrel-shifter, a routing network and a second barrel-shifter. The first barrel-shifter uses a constraint h′v′+h″v″=hv to shift q−1 elements of an input by j | 2013-07-04 |
| 20130173982 | METHOD OF DECODING LDPC CODE FOR PRODUCING SEVERAL DIFFERENT DECODERS USING PARITY-CHECK MATRIX OF LDPC CODE AND LDPC CODE SYSTEM INCLUDING THE SAME - Provided are a method of decoding an LDPC code for producing several different decoders using a parity-check matrix of the LDPC code, and an LDPC code system including the same. The system includes: an LDPC encoder outputting an LDPC codeword through a channel; a first LDPC decoder decoding the LDPC codeword received through the channel, and when the decoding has failed in a second LDPC decoder, decoding the LDPC codeword according to original parity check matrix of the LDPC codeword, using soft information newly generated after the decoding is ended in the second LDPC decoder; and the second LDPC decoder, when the decoding has failed in the first LDPC decoder, receiving the soft information on each bit from the first LDPC, and decoding the LDPC codeword according to a new parity-check matrix produced from the parity-check matrix of the LDPC codeword using the received soft information on each bit. | 2013-07-04 |
| 20130173983 | GENERATION OF PROGRAM DATA FOR NONVOLATILE MEMORY - A method generating program data to be stored in a nonvolatile memory device comprises randomizing the program data, and processing the randomized program data to reduce a frequency of at least one data state among the randomized program data. | 2013-07-04 |
| 20130173984 | FORWARD ERROR CORRECTION (FEC) CONVERGENCE BY CONTROLLING RELIABILITY LEVELS OF DECODED WORDS IN A SOFT FEC DECODER - A system receives a first word on which to perform error correction; identifies combinations in which encoded bits, within the first word, can be inverted; generates candidate words based on the first word and the combinations; decodes the candidate words; determines distances between the decoded words and the first word; selects, as a second word, one of the decoded words associated with a shortest distance; compares the second word to the first word to identify errors within the first word; generates a value to cause a reliability level of the first word to increase when a quantity of the errors is less than a threshold; generates another value to cause a reliability level of the first word to decrease when the quantity of the errors is not less than the threshold; and outputs a third word based on the first word, and the value or the other value. | 2013-07-04 |
| 20130173985 | METHOD OF READING DATA FROM STORAGE DEVICE, ERROR CORRECTION DEVICE AND STORAGE SYSTEM INCLUDING ERROR CORRECTION CODE DECODER - Methods of reading data from storage devices may include reading data stored in the storage device using normal read voltages; performing a first low density parity check (LDPC) decoding based on the read data; generating reliability bits of each of read bits according to the decoding result, the read bits being bits of the read data; and performing a second low density parity check (LDPC) decoding based on the read data and the reliability bits to perform a first error correction on the read data. | 2013-07-04 |
| 20130173986 | MEMORY CONTROLLER, DATA STORAGE DEVICE, AND MEMORY CONTROLLING METHOD - A memory controller includes a first error detection code generator for generating a first error detection code for data received from a host, a controller to write the data and the first error detection code to nonvolatile memory and to read the data and the first error detection code from the nonvolatile memory, an error detector to perform an error detection based on the data and the first error detection code that are read from the nonvolatile memory, a second error detection code generator to generate a second detection error code based on the data read from the nonvolatile memory, and a mismatch code generator to generate a mismatch code signaling the presence of an error in the data, wherein either the second error detection code or the mismatch code is selected based on the error detection and sent to the host. | 2013-07-04 |
| 20130173987 | Method and Apparatus for Dispersed Storage Memory Device Utilization - A method begins with a processing module receiving data for storage. The method continues with the processing module determining storage metadata regarding storage requirements of the data. When the storage metadata includes a first type of storage mode, the method continues with the processing module determining a first error coding dispersal storage function; identifying first memory of DSN memory; encoding the data in accordance with the first error coding dispersal storage functions; and outputting the first encoded data slices to the first memory for storage therein. When the storage metadata includes a second type of storage mode, the method continues with the processing module determining a second error coding dispersal storage function; identifying second memory of a dispersed storage network (DSN) memory; encoding the data in accordance with the second error coding dispersal storage functions; and outputting the second encoded data slices to the second memory for storage therein. | 2013-07-04 |
| 20130173988 | Mixed Domain FFT-Based Non-Binary LDPC Decoder - Various embodiments of the present invention are related to methods and apparatuses for decoding data, and more particularly to methods and apparatuses for decoding data in a mixed domain FFT-based non-binary LDPC decoder. For example, in one embodiment an apparatus includes a message processing circuit operable to process variable node messages and check node messages in a log domain, and a check node calculation circuit in the low density parity check decoder operable to perform a Fast Fourier Transform-based check node calculation in a real domain. The message processing circuit and the check node calculation circuit perform iterative layer decoding. | 2013-07-04 |
| 20130173989 | MEMORY SYSTEM CONTROLLER HAVING SEED CONTROLLER USING MULTIPLE PARAMETERS - In a memory system, a memory controller includes a randomizer and a seed controller. The seed controller provides a seed to the randomizer and includes; a first register block performing a first cyclic shift operation using a first parameter related to the nonvolatile memory device, a second register block performing a second cyclic shift operation using a second parameter related to the nonvolatile memory device, and a seed generating block generating the seed from the first and second cyclic shift results. | 2013-07-04 |
| 20130173990 | HIGH-THROUGHPUT ITERATIVE DECODING'S DEFECT SCAN IN RETRY MODE OF STORAGE SYSTEM CHANNEL - The present disclosure includes systems and techniques relating to decoding signals produced within a storage device. A described technique includes retrieving a first codeword from a storage medium, decoding the first codeword, performing a retry process when the decoding was not successful, and retrieving one or more second codewords from the storage medium during the retry process to at least maintain a drive throughput. The retry process can include identifying one or more data chunks within the first codeword having potential defects, generating an erasure mask based on the one or more data chunks, applying, based on a window, one or more erasures within one or more different regions of the first codeword based on one or more corresponding regions of the erasure mask to produce one or more versions of the first codeword, and decoding the one or more versions of the first codeword. | 2013-07-04 |
| 20130173991 | Facilitating Error Detection And Recovery In A Memory System - The disclosed embodiments relate to a system for accessing a data word in a memory. During operation, the system receives a request to access a data word, wherein the request includes a physical address for the data word. Next, the system translates the physical address into a mapped address, wherein the translation process spreads out the data words and intersperses groups of consecutive error information between groups of consecutive data words. Finally, the system uses the mapped address to access the data word and corresponding error information for the data word from the memory. | 2013-07-04 |
| 20130173992 | MEMORY CONTROL DEVICE AND MEMORY CONTROL METHOD - A memory control device includes a CPU, a flash ROM that records therein first information having undergone an error-correction coding process and second information not having undergone an error-correction coding process, an address line switch that switches between a first path that connects an address bus to the ROM so that the CPU can read the first information and a second path that connects the address bus to the ROM so that the second information can be erased, written, and read, a decoder that performs error correction on the first information and performs decoding, and a second switch that switches between a third path that connects the decoder to the data bus so that information decoded by the decoder is transmitted to the data bus and a fourth path that connects the ROM to the data bus so that the second information can be erased, written, and read. | 2013-07-04 |
| 20130173993 | DECODING APPARATUS AND DECODING METHOD - A control device ( | 2013-07-04 |
