| 27th week of 2013 patent applcation highlights part 66 |
| Patent application number | Title | Published |
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| 20130173794 | SYSTEMS AND METHODS FOR CONNECTING AN AUDIO CONTROLLER TO A HIDDEN AUDIO NETWORK - An example multimedia playback device is connected to a network that is configured to not provide an indicator of existence absent a command from the multimedia playback device. The example playback device is to initiate a connection phase for a device to connect to the hidden network based on a user action at the playback device. The example playback device is to reveal a network access point in a connection phase and authenticate the wireless device with the audio network for limited connectivity to the network during the connection phase. The example playback device is to disconnect the wireless device from the audio network and accept a connection of the wireless device to the audio network in an operational phase, the connection enabled using information provided to the wireless device during the connection phase and without the limited connectivity provided in the connection phase. | 2013-07-04 |
| 20130173795 | DNS Package in a Partitioned Network - A Domain Name System (“DNS”) package and a method for providing domain name resolution services in a partitioned network are disclosed. The system may include one or more built-in root name servers; one or more built-in top level domain (“TLD”) name servers; and a recursive name server. The recursive name server may be configured to query the one or more built-in root name servers during domain name resolution. Moreover, the one or more built-in root name servers may be configured to provide a network address corresponding to one of the built-in TLD name servers in response to a domain name resolution query sent by the recursive name server. | 2013-07-04 |
| 20130173796 | SYSTEMS AND METHODS FOR MANAGING A MEDIA CONTENT QUEUE - Systems and methods for managing media content in accordance with various embodiments of the present invention are provided. A future time is identified during which a mobile device access to a network will be limited. Media content is automatically selected for transmission to the mobile device based on an environment of the mobile device at the future time. The selected content is transmitted to the mobile device for storage in a memory of the mobile device. In some embodiments, media content may be automatically selected from a media content queue for transmission to the mobile device. The selected content may be transmitted without receiving a request from the mobile device. | 2013-07-04 |
| 20130173797 | CLOUD BASED CUSTOMER PREMISES EQUIPMENT - Network (cloud) based customer premises equipment may receive, over a broadband access circuit, layer 2 traffic from an access device at a customer premises; provide dynamic host configuration protocol (DHCP) services for computing devices at the customer premises, the DHCP services providing Internet Protocol (IP) addresses to the computing devices at the customer premises; and provide network address translation (NAT) services for the computing devices at the customer premises. | 2013-07-04 |
| 20130173798 | Computer Implemented Methods And Apparatus For Providing Access To An Online Social Network - Disclosed are systems, apparatus, methods, and computer-readable storage media for providing alerts in an online social network. In some implementations, the online social network is specific to an organization having one or more internal users and one or more external users. An indication of an action associated with providing data to the online social network is received from a computing device. A group associated with the indication of the action is identified. It is determined that the identified group includes the one or more external users. Responsive to determining that the identified group includes the one or more external users, an instruction to display an alert notification is provided at the computing device. | 2013-07-04 |
| 20130173799 | ENRICHMENT, MANAGEMENT OF MULTIMEDIA CONTENT AND SETTING UP OF A COMMUNICATION ACCORDING TO ENRICHED MULTIMEDIA CONTENT - An enrichment of multimedia content, management of multimedia content and setting up of a communication according to enriched multimedia content. A multimedia content enrichment method comprising an association of at least one identifier of a first user with multimedia content during management of said content by a communication terminal of said first user, said association allowing a second user having access to said multimedia content to request setting up of a communication between a communication terminal of said second user and a communication terminal of said first user by using one of said at least one identifier(s) of said first user. | 2013-07-04 |
| 20130173800 | TRANSMISSION MANAGEMENT APPARATUS, TRANSMISSION SYSTEM, AND COMPUTER-READABLE RECORDING MEDIUM - An apparatus includes a storage unit configured to store therein, in association with one another, group identification information for identifying groups to which transmission terminals each belong, transmission terminal identification information for identifying the terminals belonging to the respective groups, and display information to be displayed on the transmission terminals belonging to the groups. The apparatus also includes an acquiring unit configured to acquire the group identification information of a certain group and a change instruction for the display information; a changing unit configured to change the display information associated with the group identification information in the storage unit based on the change instruction; and a transmitting unit configured to transmit the display information associated with the certain group in the storage unit and changed to the terminal identified by the transmission terminal identification information associated with the group identification information of the certain group in the storage unit. | 2013-07-04 |
| 20130173801 | SYSTEMS AND METHODS FOR MANAGING PREFERRED CLIENT CONNECTIVITY TO SERVERS VIA MULTI-CORE SYSTEM - The present application is directed towards systems and methods for providing a cookie by an intermediary device comprising a plurality of packet processing engines executing on a corresponding plurality of cores, the cookie identifying a session of a user that was redirected responsive to a service exceeding a response time limit. The cookie may be generated with identifiers based off a name of a virtual server managing a service of a server, and a name of a policy associated with the virtual server. Each packet processing engine of the plurality of packet processing engines may interpret cookies generated by other packet processing engines due to the name of the virtual server and name of the policy, and may provide preferred client connectivity based on cookies included in requests for access to a service. | 2013-07-04 |
| 20130173802 | METHOD AND SYSTEM FOR DETERMINING ALLOCATION OF CLIENTS TO SERVERS - This invention relates to assignment of mobile clients (such as mobile telephones or software agents) to mainly stationary servers (such as mobile network base stations or computer servers) with the objective of reducing or minimizing the number of active servers. Once the number of users of a server drops below a specified level, the server may be deactivated resulting in power and efficiency savings. Preferably the method of the invention operates dynamically and during run time. In certain embodiments, the method can accept trade-offs in the quality of service or the number of active servers. In an embodiment of the invention, servers are arranged to “compete” with adjacent servers for their clients. This competition may be in a self-amplifying manner such that with the effect that more “popular” servers are more likely to succeed thus resulting in servers which are below a utilization threshold and can therefore be switched off. | 2013-07-04 |
| 20130173803 | DYNAMIC THROTTLING OF ACCESS TO COMPUTING RESOURCES IN MULTI-TENANT SYSTEMS - Systems, methods, and media for method for managing requests for computing resources are provided herein. Methods may include dynamically throttling requests for computing resources generated by one or more tenants within a multi-tenant system, such as a cloud. In some embodiments, the present technology may dynamically throttle I/O operations for a physical storage media that is accessible by the tenants of the cloud. The present technology may dynamically throttle I/O operations to ensure fair access to the physical storage media for each tenant within the cloud. | 2013-07-04 |
| 20130173804 | System and Method for Providing Effective Resource Reusability Management in a Virtualized Environment - A virtual system management server includes an infrastructure manager, a workload manager, and a system director. The infrastructure manager manages a computing resource of a virtualized environment and determines a utilization of the computing resource. The workload manager allocates the computing resource to a workload and launches the workload on the virtualized environment. The system director receives the utilization from the infrastructure manager, determines that the utilization is less than a utilization threshold, and directs the workload manager to reclaim a portion of the computing resource from the workload in response to determining that the utilization is less than the utilization threshold. | 2013-07-04 |
| 20130173805 | EXTENDED ADDRESS VOLUME (EAV) ALLOCATION VERIFICATION - In one embodiment, a system includes a first storage including track-managed storage and cylinder-managed storage, logic adapted for receiving a request to allocate a target data set on the first storage, logic adapted for determining a size of a source data set on a second storage, wherein data from the source data set will be copied to the target data set, logic adapted for comparing the determined size of the source data set to a break point value to determine if the target data set is to be stored to the track-managed storage or the cylinder-managed storage of the first storage, logic adapted for receiving the data from the source data set, and logic adapted for storing the data from the source data set to the target data set in either track-managed storage or cylinder-managed storage of the first storage based on the comparison. | 2013-07-04 |
| 20130173806 | LOAD-BALANCING CLUSTER - A load-balancing cluster includes a switch having ports; and servers connected to at least some of the ports. The servers are each addressable by the same virtual Internet Protocol (VIP) address. A first server of the plurality of servers establishing a Transmission Control Protocol (TCP) connection with a client computer, and, in response to a resource request received by the first server from the client computer for a particular resource, if the first server does not have a copy of the particular resource it queries one or more peers regarding the particular resource. Based at least in part on responses from the peers, the first server either: obtains the particular resource from a peer; or migrates the TCP connection to a peer; or serves the particular resource to the client request through a second server. | 2013-07-04 |
| 20130173807 | ENERGY SERVICE DELIVERY PLATFORM - A resource management client apparatus (client, | 2013-07-04 |
| 20130173808 | APPARATUS AND METHOD FOR PROVIDING MIXED CONTENT BASED ON CLOUD COMPUTING - There are provided a concept of mixing and synchronizing a plurality of pieces of content and of providing mixed content to an N-screen terminal, a method for overcoming limitations of a mobile terminal using a thin-client technique based on cloud computing and an apparatus for providing mixed content based on cloud computing. The apparatus for providing mixed content based on cloud computing includes a content server configured to, in response to a content request, execute a piece of content and provide content execution results, a content access middleware configured to allocate one or more virtual terminals to the content server, receive the content execution results from the content server and synchronize the content execution results, and a virtual convergence gateway server configured to receive the synchronized content execution results, generate mixed content and provide the mixed content to the user terminal using a split-screen method and a multi-screen method. | 2013-07-04 |
| 20130173809 | FAULT TOLERANCE AND MAINTAINING SERVICE RESPONSE UNDER UNANTICIPATED LOAD CONDITIONS - A system and method is disclosed for allocating servers across a large number of applications and for providing a predictable and consistent service response under conditions where the use of the service and associated loads is driven by unknown factors. The invention provides fault tolerance within an application through multiple resources per application and fault tolerance across applications by limiting the overlap in resources between applications. The computational load on the service may include both individual processing time due to the complexity of a single request and the number of requests. Complexity may be unpredictable because the service is self-provisioned and may allow service users to create an arbitrary sequence of compound processing steps. The number of requests may vary due to a variety of events, including daily, seasonal, or holidays, or factors driven more directly by the user of the service, such as sales, advertising, or promotions. The invention throttles server loads to provide managed degradation of application processing. The system has application in personalization, behavioral targeting, Internet retailing, personalized search, email segmentation and ad targeting, to name but a few applications. | 2013-07-04 |
| 20130173810 | System and Method of Enabling a Multi-Chassis Virtual Switch for Virtual Server Network Provisioning - A multi-chassis server system has several chassis, each including a chassis management controller (CMC) and a blade server with a blade management controller (BMC) and a virtual switch (VS). The first CMC establishes management sessions with the second CMC and the first BMC. The second CMC establishes a management session with the second BMC. A switch path on a virtual switch is provided via a management session to the first CMC and another switch path on another virtual switch is provided via a management session to the second chassis management controller and by another management session to the first CMC. The switch paths are aggregated into a chassis management controller virtual switch on the first chassis management controller. | 2013-07-04 |
| 20130173811 | NETWORK SYSTEM OF HOME APPLIANCE AND NETWORK SETUP METHOD OF THE SAME - A network system of a home appliance configured to set up a network of the home appliance by using a terminal, and a network set-up method of the same, after converting a home appliance having built with a WIFI module into an AP to enable the terminal to be connected to an AP home appliance, the information stored at the terminal is transmitted to the AP home appliance, and thus the WIFI may be set up without a separate manipulation of a user at the time of setting up the WIFI of the home appliance without adding an input/output apparatus such as a display apparatus or an interface, the set-up value of the AP, the device information, and the device authentication key may be changed, and thus is safer from hack attacks, an AP is not needed to be provided, and thus a cost-related advantage may be obtained. | 2013-07-04 |
| 20130173812 | SIP TRANSFER IN A BACK-TO-BACK USER AGENT (B2BUA) ENVIRONMENT - The system generates a change in the SIP INVITE message during a call transfer. Here, a user relation element involved in the call can change the header information in the message to include the endpoint view of the transferring party. Thus, the INVITE message is redirected to the transferring party's user relation element, which can interpret the received message and “unravel” the B2BUAs in the existing call path. The system includes changes in the user relation element to effect the message change and interpret the message once received. Changes to the user relation element forgo the need to change the communication endpoints. | 2013-07-04 |
| 20130173813 | SYSTEM AND METHOD FOR ENDPOINT HANDOFF IN A HYBRID PEER-TO-PEER NETWORKING ENVIRONMENT - A system and method for endpoint handoff in a hybrid peer-to-peer networking environment are provided. In one example, the method includes logging into the peer-to-peer network by a first endpoint. The first endpoint directly notifies a second endpoint that the second endpoint is to transfer an active communication session existing between the second endpoint and a third endpoint from the second endpoint to the first endpoint. The first endpoint receives session parameters associated with the active communication session directly from the second endpoint and directly notifies the third endpoint that the first endpoint is online. The first endpoint then re-establishes the active communication session with the third endpoint using the session parameters. | 2013-07-04 |
| 20130173814 | SESSION ESTABLISHING DEVICE, SESSION ESTABLISHING METHOD, AND RECORDING MEDIUM - A session establishing device includes a storage that stores therein establishment-finished information and under-establishment information in a manner associated with each other with respect to each session used by a terminal unit; an information determining unit that, when having received a session start request from a terminal unit, determines whether under-establishment information corresponding to the session indicates not in the process of establishment when there is a not-yet-established session; an assignment control unit that, when the under-establishment information corresponding to the session indicates not in the process of establishment, assigns the session to the terminal unit which issued the session start request; and an information registering unit that, when the session has been assigned to the terminal unit, registers session identifying information and terminal identifying information in a manner associated with the session and changes content of the under-establishment information corresponding to the session to in the process of establishment. | 2013-07-04 |
| 20130173815 | Selectively processing cookies in a proxy - An intermediary (such as a web reverse proxy), which is located between a web browser and one or more backend applications, manages cookies that are provided by the backend applications and returned to the web browser during a user session. The intermediary decides which cookies should be sent to the browser and which cookies should be stored therein. Preferably, this determination is made in an automated manner by examining the response for any cookie-dependent code (e.g., scripting) included in the response. | 2013-07-04 |
| 20130173816 | DATA DISTRIBUTION SYSTEM AND APPARATUS THEREOF - The invention relates to a system, apparatus and method for the distribution of digital data signals, which are received at a receiving means, to be sent to a plurality of locations downstream therefrom, in an efficient manner. The received data is received in a first format such as an RF format with a plurality of different components and is then changed in format, in one embodiment to an optical format. The data path is also split to allow a plurality of data paths to be defined which allow the data to be transmitted along the plurality of data paths to each of the downstream locations. | 2013-07-04 |
| 20130173817 | Transmission of Content Fragments - Some aspects of the disclosure relate to transmitting content over a network. For example, a device may determine that it is missing a content fragment from its cache, and may send a request for the content fragment. A network device may be configured to respond to such requests by transmitting the content fragment. In some instances, this may allow receiving devices to acquire the missing content fragment without the need to transmit a request for content. | 2013-07-04 |
| 20130173818 | DEVICE FOR PROVIDING A REAL-TIME LIVE VIDEO DATA STREAM FILE AND METHOD THEREOF - A device providing a real-time live video data stream file includes a memory, a processor, and a buffer. The memory stores a first video file. The processor is used for receiving a first access command generated by a Universal Plug and Play client device for accessing the first video file, and converting an original real-time video data stream to a real-time video data stream file with a predetermined format according to the first access command. The buffer is used for storing the real-time video data stream file temporarily. Therefore, the real-time video data stream file stored in the buffer can be accessed and played by the Universal Plug and Play client device. | 2013-07-04 |
| 20130173819 | SYSTEM AND METHOD FOR PROVIDING AND TRANSMITTING CONDENSED STREAMING CONTENT - A stream condense unit coupled to a streaming server and a client player is provided. The stream condense unit includes a streaming data input unit, a stream content analysis unit, a frame timestamp adjust unit, and a streaming data output unit. The streaming data input unit is configured to receive a plurality of streaming content groups sent by the streaming server. The stream content analysis unit is configured to receive the plurality of streaming content groups, execute a content analysis to get importance scores of the source streaming contents. The frame timestamp adjust unit is configured to receive the condensed stream and adjust a timestamp of each frame in the condensed stream. The streaming data output unit is configured to receive the condensed stream and attach content identifying labels and tables to the condensed stream, and send the condensed stream to the client player to display. | 2013-07-04 |
| 20130173820 | Duplicating Switch for Streaming Data Units to a Terminal - Streaming to a terminal by using a duplicating switch to receive a stream of data units, using the duplicating switch to store content from the stream, using the duplicating switch to generate a second stream that incorporates the content that was stored and address information corresponding to more than one terminal whose addressing information was not part of the first stream, and using the duplicating switch to make the second stream of data units available to two or more terminals. | 2013-07-04 |
| 20130173821 | Duplicating Switch for Streaming Data Units to a Terminal - Streaming to a terminal by using a duplicating switch to receive a stream of data units, using the duplicating switch to store content from the stream, using the duplicating switch to generate a second stream that incorporates the content that was stored and address information corresponding to more than one terminal whose addressing information was not part of the first stream, and using the duplicating switch to make the second stream of data units available to two or more terminals. | 2013-07-04 |
| 20130173822 | METHOD OF IMPLEMENTING CONTENT-CENTRIC NETWORK (CCN) USING INTERNET PROTOCOL (IP)-BASED NETWORK IN GATEWAY, AND GATEWAY - A method of implementing a Content-Centric Network (CCN) using an Internet Protocol (IP)-based network, and a gateway that may implement such a method, are provided. A method of implementing a CCN using an IP-based network may involve: determining an application protocol and a packet type corresponding to the application protocol of an IP-based network, the application protocol being included in an IP packet of an IP-based network, and generating a content name corresponding to the IP packet, based on the application protocol and the packet type. | 2013-07-04 |
| 20130173823 | DIAMETER ROUTE LEARNING - Various exemplary embodiments relate to a method and related network node including one or more of the following: receiving a message at the network device; constructing a route key based on the message, wherein the route key comprises at least one value carried by the message; determining whether the network device stores a previous route record associated with the route key; and if the network device does not store a previous route record associated with the route key, generating a new route record based on the route key, and provisioning a new route based on the new route record into a routing table of the network device. | 2013-07-04 |
| 20130173824 | PATH FINDING SYSTEM, COMPUTER, CONTROL METHOD, AND PROGRAM - Each node configuring a network performs a process to finding a path in an autonomously and distributed manner without knowing information of the entire network. A computer functioning as a node configuring a network includes: an adjacent-node communication unit that acquires a provisional pressure value and an approximate pressure value of an adjacent node adjacent to the node itself from the adjacent node; an approximate-pressure-value calculation unit that calculates an approximate pressure value of the node itself using a pipe diameter value and the length of each link connected to the node itself, the provisional pressure value of the adjacent node, and a previously given source or sink flux of the node itself; a flux value calculation unit that calculates a flux flowing through each link using the pipe diameter value, the length, the approximate pressure value of the adjacent node, and the approximate pressure value of the node itself; and a pipe diameter value updating unit that updates the pipe diameter value using the flux flowing through each link, the pipe diameter value, and a function representing a feature of slime mold, wherein calculation of the approximate pressure value, calculation of the flux, and updating of the pipe diameter value are iteratively performed at least until the pipe diameter value converges. | 2013-07-04 |
| 20130173825 | PROVIDING PRIVACY ENHANCED RESOLUTION SYSTEM IN THE DOMAIN NAME SYSTEM - An apparatus and a non-transitory computer-readable medium may perform a method of minimizing the disclosure of a domain name contained in a DNS query. The method may include: determining a first label and a second label associated with a domain name included in a DNS query; querying a first nameserver for the first label without revealing the second label to the first nameserver; receiving a response from the first nameserver directing a resolver to a second nameserver; and querying the second nameserver for the first label and the second label. | 2013-07-04 |
| 20130173826 | METHOD OF PROVIDING TIMING INFORMATION USING MMT SIGNALING LAYER SIGNALING FOR SYNCHRONIZING MMT PACKET STREAMS IN MMT HYBRID DELIVERY SERVICE AND METHOD OF SYNCHRONIZING MMT PACKET STREAMS IN MMT HYBRID DELIVERY SERVICE - A method for providing timing information for synchronizing between packet streams each transported from a first server and a second server under environment of a hybrid delivery service is provided. When the first server transports a first media entity and the second server transports a second media entity, timing information for synchronizing a second packet including a second media entity with a first packet including a first media entity in the second server is generated in response to a transport request for the second media entity from a client and the timing information and the second packet including the second media entity is provided to the client from the second server. | 2013-07-04 |
| 20130173827 | METHOD, DEVICE, AND SYSTEM FOR STARTING PLUG-IN TYPE APPARATUS - Embodiments of the present invention disclose a method, a device, and a system for starting a plug-in type apparatus. In the embodiments of the present invention, the method includes: receiving an inquiry command sent by a host; determining, according to the inquiry command, whether a plug-in type apparatus exists; when the plug-in type apparatus does not exist, sending a media change command to the host; and when the plug-in type apparatus exists, sending a media ok command to the host, so that the plug-in type apparatus performs data exchange with the host. With the solution, not only a compatibility problem of the plug-in type apparatus may be alleviated and an identification rate of the plug-in type apparatus may be improved, but also startup time of the plug-in type apparatus may be shortened greatly. | 2013-07-04 |
| 20130173828 | REMOTE DATA CONCENTRATOR - A remote data concentrator (RDC) for an avionics network, the RDC comprising an input/output interface (I/O) for connection to one or more input/output devices, and a network interface for connection to a remote processor, wherein the RDC is operable to provide communication between the input/output device(s) and the remote processor, and wherein the RDC further comprises a set of instructions for autonomously driving an output device connected to the I/O. Also, an avionics network including the RDC; an aircraft including the RDC; and a method of operating the RDC. | 2013-07-04 |
| 20130173829 | SYSTEM AND METHOD FOR PROTECTING DATA STORED ON A REMOVABLE DATA STORAGE DEVICE - A system for protecting data stored in a memory of a removable data storage device is provided. The system includes a personal electronic device, a removable solid state data storage device operatively coupled to the personal electronic device, and a circuit configured to protect data stored in a memory of the data storage device in response to detecting impending removal of the data storage device from the personal electronic device. | 2013-07-04 |
| 20130173830 | Synchronization of Data Delivery in Control Systems - An enhanced synchronized communication device within a control system may allow output data delivered to various input/output (I/O) devices to be synchronized to the time at which the output data has been generated by a programmable logic controller (PLC). In this scheme, a central processing unit (CPU) associated with the PLC may generate and transmit output data to the enhanced synchronized communication device. When the output data arrives at the enhanced synchronized communication device, the enhanced synchronized communication device may associate the output data to a trigger mechanism (e.g., the application trigger feature of Common Industrial Protocol, etc.) for immediately triggering the transfer of the output data to the I/O devices. This process may remove possible jitter associated with output data delivery in control systems. | 2013-07-04 |
| 20130173831 | PROTECTING CIRCUIT FOR BASIC INPUT OUTPUT SYSTEM CHIP - A protecting circuit for a basic input output system (BIOS) chip of a computer includes a platform controller hub (PCH), an inverting circuit connected to the PCH, a BIOS socket to connect the BIOS chip, and a controlling circuit connected between the inverting circuit and the BIOS socket. The PCH outputs a first signal or a second signal, and a third signal. The inverting circuit outputs an inverted signal with a level contrary to the first or second signal. The controlling circuit receives the first or second signal and the inverted signal, to output a processing signal to the BIOS socket, thereby controlling write-protection states of the BIOS chip. | 2013-07-04 |
| 20130173832 | SWITCH FABRIC HAVING A SERIAL COMMUNICATIONS INTERFACE AND A PARALLEL COMMUNICATIONS INTERFACE - A switch fabric is disclosed that includes a serial communications interface and a parallel communications interface. The serial communications interface is configured for connecting a plurality of slave devices to a master device in parallel to transmit information between the plurality of slave devices and the master device, and the parallel communications interface is configured for separately connecting the plurality of slave devices to the master device to transmit information between the plurality of slave devices and the master device, and to transmit information between individual ones of the plurality of slave devices. The parallel communications interface may comprise a dedicated parallel communications channel for each one of the plurality of slave devices. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch. | 2013-07-04 |
| 20130173833 | SWITCH APPARATUS SWITCHING BETWEEN BASIC INPUT OUTPUT SYSTEM CHIP AND DIAGNOSTIC CARD - A switch apparatus which can switch between two different booting chips includes a first connector, a platform controller hub (PCH) chip, a first basic input output system (BIOS) chip, a switch circuit, and a diagnostic card. The diagnostic card includes a second connector operable to be plugged into the first connector, and a second BIOS chip. When the switch circuit receives a high level control signal from the second BIOS chip, the switch circuit outputs a high level switch signal to first and second trapping pins of the PCH chip, to select the second BIOS chip to bootstrap the motherboard. When the switch circuit does not receive a high level control signal, the switch circuit outputs a low level signal to the first and second trapping pins of the PCH chip, to select the first BIOS chip to bootstrap the motherboard. | 2013-07-04 |
| 20130173834 | METHODS AND APPARATUS FOR INJECTING PCI EXPRESS TRAFFIC INTO HOST CACHE MEMORY USING A BIT MASK IN THE TRANSACTION LAYER STEERING TAG - Methods and apparatus are provided for implementing transaction layer processing (TLP) hint (TPH) protocols in the context of the peripheral component interconnect express (PCIe) base specification. The method allows an endpoint function associated with a PCI Express device to configure a steering tag header in the open systems interconnect (OSI) transaction layer to identify a particular processing resource that the requester desires to target, such as a specific processor or cache location within the execution core. A bit mask may be implemented by the hardware or operating system, for example, by embedding the bit mask in the steering tag header. The bit mask provides administrative oversight of the steering tag header configuration, to thereby mitigate unintended denial of service attacks or cache misses occasioned by aggressive steering tag configuration strategies employed by endpoint functions. | 2013-07-04 |
| 20130173835 | Controlling HDMI Devices Via Intelligent Emulation of Consumer Electronics Control (CEC) Protocol - Disclosed are various embodiments of a Consumer Electronics Control (CEC) bridge. In one embodiment, a CEC bridge includes an HDMI interface, a network interface, a processor, and code executable by the processor. The code includes logic that emulates a CEC command directed to any of a cluster of remote HDMI devices, wherein none of the remote HDMI devices are coupled to the device through the HDMI interface. | 2013-07-04 |
| 20130173836 | USB KEY DEVICE AND METHOD FOR REALIZING INTELLIGENT CARD COMMUNICATION USING USB INTERFACE - A USB key device and method for realizing the intelligent card communication using the USB interface are provided. The USB key device includes: a USB interface ( | 2013-07-04 |
| 20130173837 | METHODS AND APPARATUS FOR IMPLEMENTING PCI EXPRESS LIGHTWEIGHT NOTIFICATION PROTOCOLS IN A CPU/MEMORY COMPLEX - Methods and apparatus are provided for implementing a lightweight notification (LN) protocol in the PCI Express base specification which allows an endpoint function associated with a PCI Express device to register interest in one or more cachelines in host memory, and to request an LN notification message from the CPU/memory complex when the content of a registered cacheline changes. The LN notification message can be unicast to a single endpoint using ID-based routing, or broadcast to all devices on a given root port. The LN protocol may be implemented in the CPU complex by configuring a queue or other data structure in system memory for LN use. An endpoint registers a notification request by setting the LN bit in a “read” request of an LN configured cacheline. | 2013-07-04 |
| 20130173838 | BRIDGE BETWEEN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS INTERFACE AND A UNIVERSAL SERIAL BUS 3.0 DEVICE - A bridge includes a Peripheral Component Interconnect Express interface supporting at least two lanes, an Extensible Host Controller Interface, and a Universal Serial Bus 3.0 root hub. The Peripheral Component Interconnect Express interface is used for coupling to a host. Each lane of the at least two lanes provides a highest data transmission speed. The Extensible Host Controller Interface is coupled to the Peripheral Component Interconnect Express interface for storing data transmitted by the Peripheral Component Interconnect Express interface. The Universal Serial Bus 3.0 root hub includes a first controller and a second controller. The first controller and the second controller are used for controlling data transmission of four ports, and a highest data transmission speed provided by each port of the four ports is not more than the highest data transmission speed provided by the lane. | 2013-07-04 |
| 20130173839 | SWITCH DISK ARRAY, STORAGE SYSTEM AND DATA STORAGE PATH SWITCHING METHOD - A disk array for a storage system that includes a dual controller disk array and a server includes a disk frame and two controller nodes. Each controller node includes a switch, where a port of the switch is connected to a port of a switch of a peer controller node. Each controller node is configured to detect whether the peer controller node is invalid through the port. When it has been detected that the peer controller node is invalid, a local controller node enables the peer controller node to send, through the port of the switch of the peer controller node, received data from the server to a port of a switch of the local controller node. | 2013-07-04 |
| 20130173840 | COMMUNICATIONS CONTROL SYSTEM WITH A SERIAL COMMUNICATIONS INTERFACE AND A PARALLEL COMMUNICATIONS INTERFACE - A communications control system is disclosed that includes a serial communications interface and a parallel communications interface for coupling a plurality of input/output modules with a control module. The serial communications interface is configured for connecting the plurality of input/output modules to the control module in parallel to transmit information between the plurality of input/output modules and the control module, and the parallel communications interface is configured for separately connecting the plurality of input/output modules to the control module to transmit information between the plurality of input/output modules and the control module, and to transmit information between individual ones of the plurality of input/output modules. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch. | 2013-07-04 |
| 20130173841 | CONVENIENT, FLEXIBLE, AND EFFICIENT MANAGEMENT OF MEMORY SPACE AND BANDWIDTH - A device may receive a request to read data from or write data to a memory that includes a number of memory banks. The request may include an address. The device may perform a mapping operation on the address to map the address from a first address space to a second address space, identify one of the memory banks based on the address in the second address space, and send the request to the identified memory bank. | 2013-07-04 |
| 20130173842 | Adaptive Logical Group Sorting to Prevent Drive Fragmentation - A method and system are disclosed for controlling the storage of data in a storage device to reduce fragmentation. The method may include a controller of a storage device receiving data for storage in non-volatile memory and determining if a threshold amount of data has been received. When the threshold amount of data is received, the non-volatile memory is scanned for sequentially numbered logical groups of data previously written in noncontiguous locations in the non-volatile memory. When a threshold amount of such sequentially numbered logical groups is found, the controller re-writes the sequentially numbered logical groups of data contiguously into a new block. The system may include a storage device with a controller configured to perform the method noted above, where the thresholds for scanning the memory for fragmented data and removing fragmentation by re-writing the fragmented data into new blocks may be fixed or variable. | 2013-07-04 |
| 20130173843 | WRITE BANDWIDTH MANAGEMENT FOR FLASH DEVICES - Embodiments of the present invention provide a flash memory device write-access management amongst different virtual machines (VMs) in a virtualized computing environment. In one embodiment, a virtualized computing data processing system can include a host computer with at least one processor and memory and different VMs executing in the host computer. The system also can include a flash memory device coupled to the host computer and accessible by the VMs. Finally, a flash memory controller can manage access to the flash memory device. The controller can include program code enabled to compute a contemporaneous bandwidth of requests for write operations for the flash memory device, to allocate a corresponding number of tokens to the VMs, to accept write requests to the flash memory device from the VMs only when accompanied by a token and to repeat the computing, allocating and accepting after a lapse of a pre-determined time period. | 2013-07-04 |
| 20130173844 | SLC-MLC Wear Balancing - A method and system for SLC-MLC Wear Balancing in a flash memory device is disclosed. The flash memory device includes a single level cell (SLC) portion and a multi-level cell (MLC) portion. The age of the SLC portion and the MLC portion may differ, leading potentially to one portion wearing out before the other. In order to avoid this, a controller is configured to receive an age indicator from one or both of the SLC portion and the MLC portion, determine, based on the age indicator, whether to modify operation of the SLC portion and/or the MLC portion, and in response to determining to modifying operation, modify the operation of the at least one of the SLC portion or the MLC portion. The modification of the operation may thus balance wear between the SLC and MLC portions, thereby potentially extending the life of the flash memory device. | 2013-07-04 |
| 20130173845 | Command Aware Partial Page Programming - A method and system for partial page programming in a storage device is disclosed. An amount of data for partial page programming is determined. The amount may include host data (such as host data in a host command sent from a host device) and/or binary cache index data. The write step, used for partial page programming, is dynamically set based on the determined amount of data for partial page programming. In this way, the write step for partial page programming is dynamic rather than fixed. Further, dynamically setting the write step may reduce the number of programming steps for storing the host data in the host command and may reduce padding when partial page programming, thereby leaving less invalid data inside a block. | 2013-07-04 |
| 20130173846 | Controller and Method for Memory Aliasing for Different Flash Memory Types - A controller and method for memory aliasing for different flash memory types are presented. In one embodiment, a controller is presented having one or more interfaces through which to communicate with a plurality of memory dies, wherein at least one of the memory dies is of a different memory type than the other memory dies. The controller also has an interface through which to communicate with a host, wherein the interface only supports commands for a single memory types. The controller further contains a processor that is configured to receive a logical address and a command from the host, determine which memory die is associated with the logical address, and translate the command received from the host to a form suitable for the memory type of the memory die associated with the logical address. | 2013-07-04 |
| 20130173847 | Metablock Size Reduction Using on Chip Page Swapping Between Planes - Methods and systems are disclosed herein for storing data in a memory device. Data for multiple pages is written in parallel using plane interleaving. For example, in a four plane write, a first set of four pages are written in the following sequence: 0, 1, 2, 3. A second set of four pages, after plane interleaving, are written in the following sequent: 7, 4, 5, 6. After writing the data, the pages of written data are read, page swapped if necessary, and then written into another portion of memory (such as MLC). | 2013-07-04 |
| 20130173848 | Controller and Method for Using a Transaction Flag for Page Protection - A controller is presented having one or more interfaces through which to communicate with a plurality of memory dies with multi-level memory cells and an interface through which to communicate with a host. The controller also contains a processor that is configured to receive a command from the host to program data in a plurality of lower pages and a plurality of upper pages of the multi-level memory cells. The controller detects an indication from the host that indicates which previously-programmed lower pages from a previous program command are at risk of being corrupted by the programming of the upper pages from the received program command. Prior to programming the upper pages, the controller backs up the previously-programmed lower pages from the previous program command that are at risk of being corrupted but not the lower pages of data programmed by the received program command. | 2013-07-04 |
| 20130173849 | WRITE BANDWIDTH MANAGEMENT FOR FLASHDEVICES - Embodiments of the present invention provide a flash memory device write-access management amongst different virtual machines (VMs) in a virtualized computing environment. In one embodiment, a virtualized computing data processing system can include a host computer with at least one processor and memory and different VMs executing in the host computer. The system also can include a flash memory device coupled to the host computer and accessible by the VMs. Finally, a flash memory controller can manage access to the flash memory device. The controller can include program code enabled to compute a contemporaneous bandwidth of requests for write operations for the flash memory device, to allocate a corresponding number of tokens to the VMs, to accept write requests to the flash memory device from the VMs only when accompanied by a token and to repeat the computing, allocating and accepting after a lapse of a pre-determined time period. | 2013-07-04 |
| 20130173850 | METHOD FOR MANAGING ADDRESS MAPPING INFORMATION AND STORAGE DEVICE APPLYING THE SAME - Methods and devices for managing address mapping information are disclosed. In one example, a method for managing address mapping information may include writing address mapping recovery information on a user data area of a storage medium in an initially set size unit, the address mapping recovery information being generated in response to a write operation, storing the address mapping recovery information without being written on the storage medium in a non-volatile memory device when an abnormal power off occurs in a storage device, and updating the address mapping information related to the storage device based on the address mapping recovery information stored in the non-volatile memory device and the storage medium when power is applied to the storage device. | 2013-07-04 |
| 20130173851 | NON-VOLATILE STORAGE DEVICE, ACCESS CONTROL PROGRAM, AND STORAGE CONTROL METHOD - An access control program is executed by a specific electronic device first connected to the non-volatile storage device to associate with the specific electronic device to be given full access to the storage, executed by the specific electronic device to set the specific electronic device associated with the non-volatile storage device to a first mode permitting full access to the storage, executed by an arbitrary electronic device connected to the non-volatile storage device to judge whether the arbitrary electronic device is the specific electronic device associated with the non-volatile storage device by performing certification; and executed by the arbitrary electronic device connected to the non-volatile storage device to perform mode setting. | 2013-07-04 |
| 20130173852 | MEMORY SYSTEM - According to the embodiments, a memory system includes a plurality of memory chips, I/O signal lines, CE signal lines, and a control unit. The plurality of memory chips is divided to a plurality of first groups. The first plurality of memory chips for each first group is divided to a plurality of second groups. Each of the I/O signal lines is commonly connected to the memory chips for each first group. Each of the CE lines is commonly connected to the memory chips for each second group. The control unit specifies one of the second groups using the CE signal line, and transmits a reset command to one of the I/O signal lines which is connected to the specified second group, at activation. Each of the memory chips belonging to the specified second group executes reset processing at respective timings after receiving the reset command. | 2013-07-04 |
| 20130173853 | MEMORY-EFFICIENT CACHING METHODS AND SYSTEMS - Caching systems and methods for managing a cache are disclosed. One method includes determining whether a cache eviction condition is satisfied. In response to determining that the cache eviction condition is satisfied, at least one Bloom filter registering keys denoting objects in the cache is referenced to identify a particular object in the cache to evict. Further, the identified object is evicted from the cache. In accordance with an alternative scheme, a bit array is employed to store recency information in a memory element that is configured to store metadata for data objects stored in a separate cache memory element. This separate cache memory element stores keys denoting the data objects in the cache and further includes bit offset information for each of the keys denoting different slots in the bit array to enable access to the recency information. | 2013-07-04 |
| 20130173854 | METHOD FOR MANAGING DATA IN STORAGE DEVICE AND MEMORY SYSTEM EMPLOYING SUCH A METHOD - A method for managing data in a storage device includes: receiving a logical page from a host and calculating an actual time stamp of the logical page; finding a block of the storage device in which the logical page is stored and detecting a time stamp of the block and a page offset of the logical page stored in the block; calculating an approximate time stamp of the logical page stored in the block using the time stamp of the block and the page offset; and determining that the logical page is in a first state if the difference between the actual time stamp and the approximate time stamp is smaller than a threshold value, and determining that the logical page is in a second state different from the first state if the difference between the actual time stamp and the approximate time stamp is larger than the threshold value. | 2013-07-04 |
| 20130173855 | METHOD OF OPERATING STORAGE DEVICE INCLUDING VOLATILE MEMORY AND NONVOLATILE MEMORY - For a storage device including a volatile memory and a nonvolatile memory, an operating method includes partitioning the volatile memory into volatile memory blocks in response to a first control command, and then performing a data read operation, a data write operation, or a data migration operation by using at least one of the volatile memory blocks. | 2013-07-04 |
| 20130173856 | DATA STORAGE DEVICE, MEMORY SYSTEM, AND COMPUTING SYSTEM USING NONVOLATILE MEMORY DEVICE - Provided is a data storage device including two or more data storage areas including may have two or more (heterogeneous) types of nonvolatile memory cells. At least one of the data storage areas includes a plurality of memory blocks that are sequentially selected, and metadata are stored in the currently selected memory block. The memory blocks can be sequentially used and metadata can be stored in a uniformly-distributed manner throughout the data storage device. Therefore, separate merging and wear-leveling operations are unnecessary. Thus, it is possible to improve the lifetime and writing performance of a data storage device having two or more heterogeneous nonvolatile memories. | 2013-07-04 |
| 20130173857 | FLASH MEMORY DEVICE WITH MULTI-LEVEL CELLS AND METHOD OF WRITING DATA THEREIN - In one aspect, a method of writing data in a flash memory system is provided. The flash memory system forms an address mapping pattern according to a log block mapping scheme. The method includes determining a writing pattern of data to be written in a log block, and allocating one of SLC and MLC blocks to the log block in accordance with the writing pattern of the data. | 2013-07-04 |
| 20130173858 | Method for Scheduling Memory Refresh Operations Including Power States - A method for performing refresh operations on a rank of memory devices is disclosed. After the completion of a memory operation, a determination is made whether or not a refresh backlog count value is less than a predetermined value and the rank of memory devices is being powered down. If the refresh backlog count value is less than the predetermined value and the rank of memory devices is being powered down, an Idle Count threshold value is set to a maximum value such that a refresh operation will be performed after a maximum delay time. If the refresh backlog count value is not less than the predetermined value or the rank of memory devices is not in a powered down state, the Idle Count threshold value is set based on the slope of an Idle Delay Function such that a refresh operation will be performed accordingly. | 2013-07-04 |
| 20130173859 | Logically Partitioning Remote Virtual Library Extensions for Use in Disaster Recovery of Production Data - Systems and methods that make use of logical partitions of a second tier of disk storage at a disaster recovery (DR) site remote from a production site as part of a DR setup to advantageously reduce disruption to production site data production operations during DR procedures while providing for the substantially immediate recall or retrieval of data previously migrated to the remote second tier of disk storage. | 2013-07-04 |
| 20130173860 | NEAR NEIGHBOR DATA CACHE SHARING - Parallel computing environments, where threads executing in neighboring processors may access the same set of data, may be designed and configured to share one or more levels of cache memory. Before a processor forwards a request for data to a higher level of cache memory following a cache miss, the processor may determine whether a neighboring processor has the data stored in a local cache memory. If so, the processor may forward the request to the neighboring processor to retrieve the data. Because access to the cache memories for the two processors is shared, the effective size of the memory is increased. This may advantageously decrease cache misses for each level of shared cache memory without increasing the individual size of the caches on the processor chip. | 2013-07-04 |
| 20130173861 | NEAR NEIGHBOR DATA CACHE SHARING - Parallel computing environments, where threads executing in neighboring processors may access the same set of data, may be designed and configured to share one or more levels of cache memory. Before a processor forwards a request for data to a higher level of cache memory following a cache miss, the processor may determine whether a neighboring processor has the data stored in a local cache memory. If so, the processor may forward the request to the neighboring processor to retrieve the data. Because access to the cache memories for the two processors is shared, the effective size of the memory is increased. This may advantageously decrease cache misses for each level of shared cache memory without increasing the individual size of the caches on the processor chip. | 2013-07-04 |
| 20130173862 | METHOD FOR CLEANING CACHE OF PROCESSOR AND ASSOCIATED PROCESSOR - A method for cleaning a cache of a processor includes: generating a specific command according to a request, wherein the specific command includes an operation command, a first field and a second field; obtaining an offset and a starting address according to the first field and the second field; selecting a specific segment from the cache according to the starting address and the offset; and cleaning data stored in the specific segment. | 2013-07-04 |
| 20130173863 | Memory Management Among Levels Of Cache In A Memory Hierarchy - Methods, apparatus, and product for memory management among levels of cache in a memory hierarchy in a computer with a processor operatively coupled through two or more levels of cache to a main random access memory, caches closer to the processor in the hierarchy characterized as higher in the hierarchy, including: identifying a line in a first cache that is preferably retained in the first cache, the first cache backed up by at least one cache lower in the memory hierarchy, the lower cache implementing an LRU-type cache line replacement policy; and updating LRU information for the lower cache to indicate that the line has been recently accessed. | 2013-07-04 |
| 20130173864 | SEMICONDUCTOR DEVICE INCLUDING ROW CACHE REGISTER - Disclosed herein is a device that includes a memory cell array having a plurality of pages, a row cache register, and an array control circuit. The array control circuit is configured to: select one of the pages as a selected page to form an electrical path between the selected page and the row cache register in response to a first command with a row address; cut the electrical path between the selected page and the row cache register; and form the electrical path again between the selected page and the row cache register in response to a second command without the row address. | 2013-07-04 |
| 20130173865 | REGISTER FILE ORGANIZATION TO SHARE PROCESS CONTEXT FOR HETEROGENEOUS MULTIPLE PROCESSORS OR JOINT PROCESSOR - A register file organization is used to support multiple accesses from more than one processor or pipeline. This shared register file is organized for a multiple processor device that includes a high performance (HP) and a low power (LP) core. The shared register file includes separate HP and LP storage units coupled to separate HP and LP write and read ports. | 2013-07-04 |
| 20130173866 | Optimized Approach to Parallelize Writing to a Shared Memory Resource - Reducing contentions between processes or tasks that are trying to access shared resources is described herein. According to embodiments of the invention, a method of writing a set of data associated with a task to a memory resource is provided. The method includes calculating the amount of memory required to write said data to the memory resource and updating an expected end marker to reflect the amount of memory required to write the data to the memory resource. A flag is then set to an incomplete state, and the data is written to the memory resource. The flag can be set to a complete state and an end marker is updated. The end marker indicates the end of the data stored in the memory resource. | 2013-07-04 |
| 20130173867 | INFORMATION PROCESSING APPARATUS AND UNAUTHORIZED ACCESS PREVENTION METHOD - An information processing apparatus includes nodes having a first node and a second node each of which includes a processor and a memory in which at least a part of area is set as a shared memory area, and an interconnect that connects the nodes. The first node transmits communication data to be transmitted to the second node by attaching identification information used for accessing a memory in the second node. The second node determines whether or not an access to the shared memory area in the memory in the second node is permitted on the basis of the identification information that is attached to the communication data transmitted from the first node and identification information stored in a storing unit and used for controlling permission to access, from another node, the shared memory area in the memory in the second node. | 2013-07-04 |
| 20130173868 | Generation of Activation List for Memory Translation and Memory Access Protection in Industrial Ethernet Standard - The invention relates to an EtherCAT fieldbus system, a master and a slave for the system and a method. The slave is configured to be coupled to the EtherCAT fieldbus. A first configurable memory of the slave stores a first activation list indicating for consecutive bytes of data of an EtherCAT datagram a corresponding fieldbus memory management information or synchronization management information. | 2013-07-04 |
| 20130173869 | Increasing Functionality Of A Reader-Writer Lock - In one embodiment, the present invention includes a method for accessing a shared memory associated with a reader-writer lock according to a first concurrency mode, dynamically changing from the first concurrency mode to a second concurrency mode, and accessing the shared memory according to the second concurrency mode. In this way, concurrency modes can be adaptively changed based on system conditions. Other embodiments are described and claimed. | 2013-07-04 |
| 20130173870 | BIDIRECTIONAL SHIFT REGISTER AND THE DRIVING METHOD THEREOF - A bidirectional shift register includes a first register circuit and a second register circuit. The first register circuit includes a first register stage and a first output buffer stage with n numbers of scanning signal output ends. The first register stage is electrically coupled to a third voltage source. The first output buffer stage is electrically coupled to a second voltage source and a first voltage source. The second register circuit has a similar circuit structure to the first register circuit; wherein the first register circuit and the second register circuit each use n+1 numbers clock signal lines, and the n is a positive integer. | 2013-07-04 |
| 20130173871 | Memory Systems and Methods for Dividing Physical Memory Locations Into Temporal Memory Locations - Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical addresses. This data masking divides the physical address locations into two or more temporal subsets of the physical address locations, effectively increasing the number of uniquely addressable locations in a given module. Reading temporal addresses in write order can introduce undesirable read latency. Some embodiments reorder read data to reduce this latency. | 2013-07-04 |
| 20130173872 | Abstracting Programmatic Representation of Data Storage Systems - Providing for a paradigm shift in block-level abstraction for storage devices is described herein. At a block-level, storage is characterized as a variable size data record, rather than a fixed size sector. In some aspects, the variable size data record can comprise a variable binary key-data pair, for addressing and identifying a variable size block of data, and for dynamically specifying the size of such block in terms of data storage. By changing the key or data values, the location, identity or size of block-level storage can be modified. Data records can be passed to and from the storage device to facilitate operational commands over ranges of such records. Block-level data compression, space management and transactional operations are provided, mitigating a need of higher level systems to characterize underlying data storage for implementation of such operations. | 2013-07-04 |
| 20130173873 | Method and Apparatus for Performing Mapping Within a Data Processing System Having Virtual Machines - In an environment in which a processor operates a hypervisor and multiple guest partitions operating under the hypervisor's control, it is desirable to allow a guest partition access to a physical memory device without decreasing system performance. Accordingly, a conversion instruction for converting a logical address to a real address, i.e., an LTOR instruction, executable from a guest partition, is added to the processor. Upon the guest partition's execution of the conversion instruction with the logical address specified, the processor converts the logical address to an encrypted real address, and returns it to the guest partition. The guest partition is then able to pass the encrypted real address to an accelerator that converts the encrypted real address to a real address in order to access the memory device using the real address. | 2013-07-04 |
| 20130173874 | System and Method for Pre-interleaving Sequential Data - A method and system for operating a memory device in programming mode is disclosed. The memory device includes a programming mode and a normal mode. The memory device in programming mode increases the number of physical planes that can be programmed in parallel than can be programmed in normal mode. In this way, the memory device may be programmed more quickly at various times of operation of the memory device (such as during manufacturing). The host system may send rearranged data to the memory device in programming mode with the rearranged data accounting for the increased number of physical planes programmed in parallel. | 2013-07-04 |
| 20130173875 | METHOD OF MANAGING STORAGE REGION OF MEMORY DEVICE, AND STORAGE APPARATUS USING THE METHOD - A method of managing a storage region of a memory device, and a storage apparatus using the method. In the method, data blocks are arranged in an order of performing writing on the memory device; a frequency of updating data in a logical page to be written is determined, based on whether an invalid physical page is present in a block within a window size that is initially set based on a most recently written data block from among the arranged data blocks, in response to a write request, and the data in the logical page is stored in a storage region of the memory device classified according to the determined frequency, according to the determined frequency. | 2013-07-04 |
| 20130173876 | METHOD AND APPARATUS FOR SYNCHRONIZATION IN PRIMARY-BACKUP REPLICATION SCHEMES - A primary-backup replication capability is disclosed. A primary process and a backup process participate in a synchronization process configured to synchronize state information of the primary and backup processes. The synchronization process operates in periods of time referred to as epochs. During the current epoch, the primary process computes state update information representing changes to the state information of the primary process since a previous epoch, and also buffers output messages generated during the current epoch in an associated output buffer dedicated for use in the current epoch. The primary process initiates a new epoch independent of receiving, from the backup process, a state update acknowledgement for the previous epoch. The output messages buffered for the current epoch are released from the associated output buffer after the primary process receives a state update acknowledgment for the current epoch and all output buffers of all previous epochs are empty. | 2013-07-04 |
| 20130173877 | INFORMATION PROCESSING DEVICE, DATA MANAGEMENT METHOD, AND STORAGE DEVICE - According to an aspect of the present invention, provided is an information processing device including a first storage unit and a processor. The processor sets, in an external device, device identification information of the information processing device. The processor stores a duplicate copy of data stored in the first storage unit in a second storage unit included in the external device. The processor invalidates, in response to an instruction for invalidating data, the data stored in the first storage unit. The processor restores the duplicate copy stored in the second storage unit on the first storage unit at a time of start-up of the information processing device after the invalidation when the external device is connected to the information processing device and the device identification information is set in the external device. | 2013-07-04 |
| 20130173878 | SOURCE-TARGET RELATIONS MAPPING - A data preservation function is provided which, in one embodiment, includes indicating by a map, usage of a particular map extent range by a relationship between a source extent range of storage locations on a source storage device containing data to be preserved in the source extent range, and a target extent range mapped to the map particular extent range. In another aspect, in response to receipt of a data preservation command, a data preservation operation is performed including determining whether a map indicates availability of a map extent range mapped to the identified target extent range. Upon determining that a particular map indicates availability of a map extent range mapped to the identified target extent range, a relationship between the identified source extent range and the identified target extent range is established. Other features and aspects may be realized, depending upon the particular application. | 2013-07-04 |
| 20130173879 | On-Vehicle Apparatus, And Method And Computer Program For Transmitting Positional Information - At every first prescribed timing, a positional information piece is generated. Each generated positional information piece represents a position of a vehicle which occurs at the corresponding first prescribed timing. Each generated positional information piece is written into one of storage areas in a storage device. At every second prescribed timing, positional information pieces in the storage areas are sent to a positional information collecting apparatus, and new positional information pieces are allowed to be written into the storage areas in which the sent positional information pieces are stored. In the event that sending the positional information pieces in the storage areas to the positional information collecting apparatus is impossible, a new positional information piece or pieces are allowed to be written into one or more of the storage areas which store a positional information piece or pieces having not been sent yet. | 2013-07-04 |
| 20130173880 | DEDICATED LARGE PAGE MEMORY POOLS - Dedicated large page memory pools are provided to, at least in part, facilitate access to large pages. The large page memory is managed by: establishing multiple large page memory pools, each large page memory pool of the multiple large page memory pools including a number of large pages; and dedicating each large page memory pool of the multiple large page memory pools to a respective processor of multiple processors of the computing environment, wherein processors of the multiple processors can concurrently access pages from the respective large page memory pools of the multiple large page memory pools. | 2013-07-04 |
| 20130173881 | CIRCUIT FOR SETTING A PLURALITY OF BLOCKS AS AN IN-SYSTEM PROGRAMMING AREA AND A DATA BUFFER AREA AND METHOD THEREFORE - A method for setting a plurality of blocks as an in-system programming area and a data buffer area includes generating a plurality of select signals; setting some blocks of the plurality of blocks as blocks of the in-system programming area and other blocks of the plurality of blocks as blocks of the data buffer area according to the plurality of select signals. | 2013-07-04 |
| 20130173882 | INSTRUCTION FETCH TRANSLATION LOOKASIDE BUFFER MANAGEMENT TO SUPPORT HOST AND GUEST O/S TRANSLATIONS - A translation lookaside buffer (TLB) configured for use in a multiple operating system environment includes a plurality of storage locations, each storage location being configured to store a page translation entry configured to relate a virtual address range to a physical address range, each page translation entry having an address space identifier (ASID) associated with an operating system. The TLB also includes flush logic configured to receive a TLB flush request from an operating system having an operating system ASID and flush only TLB page translation entries having a stored ASID that matches the operating system ASID. | 2013-07-04 |
| 20130173883 | APPLICATION PROCESSOR AND A COMPUTING SYSTEM HAVING THE SAME - An application processor includes a system memory unit, peripheral devices, a control unit and a central processing unit (CPU). The system memory unit includes one page table. The peripheral devices share the page table and perform a DMA (Direct Memory Access) operation on the system memory unit using the page table, where each of the peripheral devices includes a memory management unit having a translation lookaside buffer. The control unit divides a total virtual address space corresponding to the page table into sub virtual address spaces, assigns the sub virtual address spaces to the peripheral devices, respectively, allocates and releases a DMA buffer in the system memory unit, and updates the page table, where at least two of the sub virtual address spaces have different sizes from each other. The CPU controls the peripheral devices and the control unit. The application processor reduces memory consumption. | 2013-07-04 |
| 20130173884 | PROGRAMMABLE DEVICE FOR SOFTWARE DEFINED RADIO TERMINAL - A programmable device suitable for software defined radio terminal is disclosed. In one aspect, the device includes a scalar cluster providing a scalar data path and a scalar register file and arranged for executing scalar instructions. The device may further include at least two interconnected vector clusters connected with the scalar cluster. Each of the at least two vector clusters provides a vector data path and a vector register file and is arranged for executing at least one vector instruction different from vector instructions performed by any other vector cluster of the at least two vector clusters. | 2013-07-04 |
| 20130173885 | Processor and Methods of Adjusting a Branch Misprediction Recovery Mode - A processor core includes a fetch control unit for fetching instructions and placing the instructions into an instruction queue and includes a branch predictor for controlling the fetch control unit to speculatively fetch at least one instruction subsequent to an unresolved branch instruction. The processor further includes a controller configured to dispatch instructions from the instruction queue and, in response to a branch misprediction of an unresolved control instruction, to apply a selected one of a checkpointing-based recovery mode and a commit-time-based recovery mode. | 2013-07-04 |
| 20130173886 | Processor with Hazard Tracking Employing Register Range Compares - Systems and methods for tracking data hazards in a processor. The processor comprises a pipelined architecture configured to execute a first instruction and a second instruction, wherein the second instruction is older than the first instruction. At least one of the first and second instructions comprises at least one operand expressed as a range of registers. Hazard detection logic is configured to compare the first instruction and the second instruction to determine if there is a data hazard, prior to expanding the second instruction. | 2013-07-04 |
| 20130173887 | PROCESSOR SIMULATION ENVIRONMENT - In a method of simulating a processor system by running code that simulates the system on a host processor, code is translated at run time to a form required by the host processor. All instructions are mapped to a native instruction set of the host using two or more different code dictionaries: the translated instructions are mapped to multiple and different dictionaries dependent on the execution privilege level or mode of the simulated processor. If an instruction is encountered during runtime that changes the mode of the processor the code dictionary is switched to use the dictionary associated with the new mode. The different modes require different instruction mappings to the native instruction set of the host using different models that more accurately represent the behaviour of the system code and hardware in the system being simulated. | 2013-07-04 |
| 20130173888 | Processor for Executing Wide Operand Operations Using a Control Register and a Results Register - A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers. | 2013-07-04 |
| 20130173889 | PARALLEL PROCESSING SYSTEM FOR COMPUTING PARTICLE INTERACTIONS - A parallel processing system for computing particle interactions includes a plurality of computation nodes arranged according to a geometric partitioning of a simulation volume. Each computation node has storage for particle data. This particle data is associated with particles in a region of the geometrically partitioned simulation volume. The parallel processing system also includes a communication system having links interconnecting the computation nodes. Each of the computation nodes includes a processor subsystem. These processor subsystems cooperate to coordinate computation of the particle interactions in a distributed manner. | 2013-07-04 |
| 20130173890 | METHOD OF, AND APPARATUS FOR, STREAM SCHEDULING IN PARALLEL PIPELINED HARDWARE - A method of generating a hardware design for a stream processor. The method includes defining a graph representing a processing operation designating processes to be implemented in hardware as part of the stream processor. The graph represents the processing operation in the time domain as a function of clock cycles and includes at least one data path. At least one stream offset object is provided located at a particular point in the data path. The stream offset object is operable to access, for a particular clock cycle and for the particular point in the data path, data values from a clock cycle different from the particular clock cycle | 2013-07-04 |
| 20130173891 | CONVERT FROM ZONED FORMAT TO DECIMAL FLOATING POINT FORMAT - Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location. | 2013-07-04 |
| 20130173892 | CONVERT TO ZONED FORMAT FROM DECIMAL FLOATING POINT FORMAT - Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location. | 2013-07-04 |
| 20130173893 | HARDWARE COMPILATION AND/OR TRANSLATION WITH FAULT DETECTION AND ROLL BACK FUNCTIONALITY - Hardware compilation and/or translation with fault detection and roll back functionality are disclosed. Compilation and/or translation logic receives programs encoded in one language, and encodes the programs into a second language including instructions to support processor features not encoded into the original language encoding of the programs. In one embodiment, an execution unit executes instructions of the second language including an operation-check instruction to perform a first operation and record the first operation result for a comparison, and an operation-test instruction to perform a second operation and a fault detection operation by comparing the second operation result to the recorded first operation result. In some embodiments, an execution unit executes instructions of the second language including commit instructions to record execution checkpoint states of registers mapped to architectural registers, and roll-back instructions to restore the registers mapped to architectural registers to previously recorded execution checkpoint states. | 2013-07-04 |
