| 27th week of 2013 patent applcation highlights part 46 |
| Patent application number | Title | Published |
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| 20130171786 | NON-VOLATILE MEMORY (NVM) AND LOGIC INTEGRATION - A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A metal select gate of the NVM cell is formed over an NVM work function setting metal, the NVM work function setting metal is on a high-k dielectric, and a metal logic gate of a logic transistor is similarly formed over work function setting and high-k dielectric materials. The logic transistor is formed while portions of the metal select gate of the NVM cell are formed. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region using nanocrystals and a metal control gate over a portion of the metal select gate and a portion of the charge storage region over the substrate. The charge storage region is etched to be aligned to the metal control gate. | 2013-07-04 |
| 20130171787 | METHOD FOR FABRICATING NON-VOLATILE MEMORY DEVICE - A method for fabricating a non-volatile memory device includes alternately stacking a plurality of inter-layer dielectric layers and a plurality of sacrificial layers over a substrate, forming at least a channel hole that exposes the substrate by selectively etching the inter-layer dielectric layers and the sacrificial layers, forming a protective layer on sidewalls of the sacrificial layers that are exposed through the channel hole, sequentially forming a memory layer and a channel layer on the sidewalls of the channel hole, forming slit holes that penetrate through the inter-layer dielectric layers and the sacrificial layers on both sides of the channel hole, removing the sacrificial layers that are exposed through the slit holes, removing the protective layer, and forming gate electrodes in space from which the sacrificial layers and the protective layer are removed. | 2013-07-04 |
| 20130171788 | NON-VOLATILE MEMORY DEVICE HAVING VERTICAL STRUCTURE AND METHOD OF MANUFACTURING THE SAME - According to an example embodiment, a non-volatile memory device includes a semiconductor layer pattern on a substrate, a plurality of gate patterns and a plurality of interlayer insulating layer patterns that are alternately stacked along a side wall of the semiconductor layer pattern, and a storage structure between the plurality of gate patterns and the semiconductor layer pattern. The semiconductor layer pattern extends in a vertical direction from the substrate. The gate patterns are recessed in a direction from a side wall of the interlayer insulating layer patterns opposing the side wall of the semiconductor layer pattern. A recessed surface of the gate patterns may be formed to be vertical to a surface of the substrate. | 2013-07-04 |
| 20130171789 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes providing a substrate having a first gate structure and a second gate structure formed thereon; blanketly forming a seal layer covering the first gate structure and the second gate structure on the substrate; performing a first ion implantation to form first light-doped drains (LDDs) in the substrate respectively at two sides of the first gate structure; and performing a second ion implantation to form second LDDs in the substrate respectively at two sides of the second gate structure; wherein at least one of the first ion implantation and the second ion implantation is performed to penetrate through the seal layer. | 2013-07-04 |
| 20130171790 | Methods of Manufacturing Semiconductor Devices and Transistors - Methods of manufacturing semiconductor devices and transistors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece comprising a plurality of fins, and forming a semiconductive material over a top surface of the plurality of fins. An etch stop layer is formed over the semiconductive material, and an insulating material is disposed over the etch stop layer. The insulating material and a portion of the etch stop layer are removed from over the plurality of fins. Forming the semiconductive material or forming the etch stop layer are controlled so that removing the portion of the etch stop layer does not remove the etch stop layer between a widest portion of the semiconductive material over the plurality of fins. | 2013-07-04 |
| 20130171791 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURE METHOD - A semiconductor device has: a low concentration drain region creeping under a gate electrode of a MIS type transistor; a high concentration drain region having an impurity concentration higher than the low concentration drain region and formed in the low concentration drain region spaced apart from the gate electrode; and an opposite conductivity type region of a conductivity type opposite to the drain region formed in the low concentration drain region on a surface area between the high concentration drain region and the gate electrode, the opposite conductivity type region and low concentration drain region forming a pn junction. | 2013-07-04 |
| 20130171792 | Methods for Semiconductor Regrowth - A treatment is performed on a surface of a first semiconductor region, wherein the treatment is performed using process gases including an oxygen-containing gas and an etching gas for etching the semiconductor material. An epitaxy is performed to grow a second semiconductor region on the surface of the first semiconductor region. | 2013-07-04 |
| 20130171793 | METHODS OF FORMING SEMICONDUCTOR DEVICES USING ELECTROLYZED SULFURIC ACID (ESA) - A method of forming a semiconductor device may include forming a metal layer on a silicon portion of a substrate, and reacting the metal layer with the silicon portion to form a metal silicide. After reacting the metal layer, unreacted residue of the metal layer may be removed using an electrolyzed sulfuric acid solution. More particularly, a volume of sulfuric acid in the electrolyzed sulfuric acid solution may be in the range of about 70% to about 95% of the total volume of the electrolyzed sulfuric acid solution, a concentration of oxidant in the electrolyzed acid solution may be in the range of about 7 g/L to about 25 g/L, and a temperature of the electrolyzed sulfuric acid solution may be in the range of about 130 degrees C. to about 180 degrees C. | 2013-07-04 |
| 20130171794 | EPITAXIAL EXTENSION CMOS TRANSISTOR - A pair of horizontal-step-including trenches are formed in a semiconductor layer by forming a pair of first trenches having a first depth around a gate structure on the semiconductor layer, forming a disposable spacer around the gate structure to cover proximal portions of the first trenches, and by forming a pair of second trenches to a second depth greater than the first depth. The disposable spacer is removed, and selective epitaxy is performed to form an integrated epitaxial source and source extension region and an integrated epitaxial drain and drain extension region. A replacement gate structure can be formed after deposition and planarization of a planarization dielectric layer and subsequent removal of the gate structure and laterally expand the gate cavity over expitaxial source and drain extension regions. Alternately, a contact-level dielectric layer can be deposited directly on the integrated epitaxial regions and contact via structures can be formed therein. | 2013-07-04 |
| 20130171795 | TRENCH SILICIDE CONTACT WITH LOW INTERFACE RESISTANCE - An electrical structure is provided that includes a dielectric layer present on a semiconductor substrate and a via opening present through the dielectric layer. | 2013-07-04 |
| 20130171796 | METHODS OF FABRICATING TRENCH GENERATED DEVICE STRUCTURES - Methods for fabricating device structures, such as bipolar transistors and diodes. The method includes forming a trench extending through stacked semiconductor and insulator layers and into an underlying semiconductor substrate. The trench may be at least partially filled with a sacrificial plug containing a dopant with a conductivity type opposite to the conductivity type of the semiconductor substrate. Dopant is transported outwardly from the sacrificial plug into the semiconductor substrate surrounding the trench to define a doped region of the second conductivity type in the semiconductor substrate. A first contact is formed that extends through the semiconductor and insulator layers to a portion of the semiconductor substrate outside of the doped region. A second contact is formed that extends through the semiconductor and insulator layers to the doped region. | 2013-07-04 |
| 20130171797 | METHOD FOR FORMING MULTI-COMPONENT LAYER, METHOD FOR FORMING MULTI-COMPONENT DIELECTRIC LAYER AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method of forming a multi-component dielectric layer on the surface of a substrate by atomic layer deposition includes injecting a cocktail source of a plurality of sources at least having a cyclopentadienyl ligand, wherein the cocktail source is adsorbed on a surface of a substrate by injecting the cocktail source, performing a first purge process to remove a non-adsorbed portion of the cocktail source, injecting a reactant to react with the adsorbed cocktail source, wherein a multi-component layer is formed by the reaction between the reactant and the absorbed cocktail source, and performing a second purge process to remove reaction byproducts and an unreacted portion of the reactant. | 2013-07-04 |
| 20130171798 | METHOD OF MANUFACTURING PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE - A method of manufacturing a phase-change random access memory device. The method includes forming a word line on a semiconductor substrate, forming a switching element material and a hard mask material on the word line, etching the switching element material and the hard mask material to form a hole exposing the word line, forming an insulating material on a sidewall and a bottom of the hole, removing the hard mask material; and forming a heater material on the switching element material. The hard mask material has different etch selectivity from the insulating material. | 2013-07-04 |
| 20130171799 | CURRENT STEERING ELEMENT AND NON-VOLATILE MEMORY ELEMENT INCORPORATING CURRENT STEERING ELEMENT - A current steering element ( | 2013-07-04 |
| 20130171800 | Method of Forming Top Electrode for Capacitor and Interconnection in Integrated Passive Device (IPD) - A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer. | 2013-07-04 |
| 20130171801 | SEMICONDUCTOR DEVICES HAVING NITRIDED GATE INSULATING LAYER AND METHODS OF FABRICATING THE SAME - Semiconductor devices, and methods of fabricating the same, include forming device isolation regions in a substrate to define active regions, forming gate trenches in the substrate to expose the active regions and device isolation regions, conformally forming a preliminary gate insulating layer including silicon oxide on the active regions exposed in the grate trenches, nitriding the preliminary gate insulating layer using a radio-frequency bias having a frequency of about 13.56 MHz and power between about 100 W and about 300 W to form a nitrided preliminary gate insulating layer including silicon oxynitride, forming a gate electrode material layer on the nitride preliminary gate insulating layer, partially removing the nitrided preliminary gate insulating layer and the gate electrode material layer to respectively form a gate insulating layer and a gate electrode layer, and forming a gate capping layer on the gate electrode layer to fill the gate trenches. | 2013-07-04 |
| 20130171802 | FULL WAFER PROCESSING BY MULTIPLE PASSES THROUGH A COMBINATORIAL REACTOR - Overlapping combinatorial processing can offer more processed regions, better particle performance and simpler process equipment. In overlapping combinatorial processing, one or more regions are processed in series with some degrees of overlapping between regions. In some embodiments, overlapping combinatorial processing can be used in conjunction with non-overlapping combinatorial processing and non-combinatorial processing to develop and investigate materials and processes for device processing and manufacturing. | 2013-07-04 |
| 20130171803 | METHOD FOR FABRICATING AN ISOLATION STRUCTURE - A method of fabricating an isolation structure including forming a trench in a top surface of a substrate and partially filling the trench with a first oxide, wherein the first oxide is a pure oxide. Partially filling the trench includes forming a liner layer in the trench and forming the first oxide over the liner layer using silane and oxygen precursors at a pressure less than 10 milliTorr (mTorr) and a temperature ranging from about 500° C. to about 1000° C. The method further includes producing a solid reaction product in a top portion of the first oxide. The method further includes sublimating the solid reaction product by heating the substrate in a chamber at a temperature from 100° C. to 200° C. and removing the sublimated solid reaction product by flowing a carrier gas over the substrate. The method further includes filling the trench with a second oxide. | 2013-07-04 |
| 20130171804 | METHOD FOR MANUFACTURING ELECTRONIC COMPONENT - Provided is a method for manufacturing electronic component improved in chip-holding efficiency, pickup efficiency and contamination resistance in a well-balanced manner, the method comprising a semi-cured adhesive layer-forming step of forming a semi-cured adhesive layer on the rear face of a wafer, a fixing step of fixing the semi-cured adhesive layer of the wafer on a ring frame with a cohesive sheet, a dicing step of dicing the wafer into semiconductor chips, a UV-irradiating step of irradiating ultraviolet ray, and a pick-up step of picking up the chips and semi-cured adhesive layers from the cohesive layer, wherein the cohesive sheet has a cohesive layer of a cohesive agent having a particular composition formed on one face of its base film. | 2013-07-04 |
| 20130171805 | GaN Epitaxy With Migration Enhancement and Surface Energy Modification - Methods and apparatus for depositing thin films incorporating the use of a surfactant are described. Methods and apparatuses include a deposition process and system comprising multiple isolated processing regions which enables rapid repetition of sub-monolayer deposition of thin films. The use of surfactants allows the deposition of high quality epitaxial films at lower temperatures having low values of surface roughness. The deposition of Group III-V thin films such as GaN is used as an example. | 2013-07-04 |
| 20130171806 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - Provided is a three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device includes a substrate that has a cell array region including a pair of sub-cell regions and a strapping region interposed between the pair of sub-cell regions. A Plurality of sub-gates are sequentially stacked on the substrate in each of the sub-cell regions, and interconnections are electrically connected to extensions of the stacked sub-gates, respectively, which extend into the strapping region. Each of the interconnections is electrically connected to the extensions of the sub-gate which are disposed in the pair of the sub-cell regions, respectively, and which are located at the same level. | 2013-07-04 |
| 20130171807 | METHODS OF FABRICATING A SEMICONDUCTOR DEVICE INCLUDING DUAL TRANSISTORS - Provided are a semiconductor device having dual transistors, and methods of fabricating a semiconductor device, including sequentially forming an insulating layer and a polysilicon layer on a substrate having a first region and a second region, forming a first mask to cover the polysilicon layer on the second region, injecting at least one n-type impurity into the polysilicon layer on the first region to form an N-region, injecting nitrogen into the N-region, forming a second mask to cover the N-region, and injecting at least one p-type impurity into the polysilicon layer on the second region to form a P-region. | 2013-07-04 |
| 20130171808 | DOUBLE-SIDED REUSABLE TEMPLATE FOR FABRICATION OF SEMICONDUCTOR SUBSTRATES FOR PHOTOVOLTAIC CELL AND MICROELECTRONICS DEVICE MANUFACTURING - This disclosure presents manufacturing methods and apparatus designs for making TFSSs from both sides of a re-usable semiconductor template, thus effectively increasing the substrate manufacturing throughput and reducing the substrate manufacturing cost. This approach also reduces the amortized starting template cost per manufactured substrate (TFSS) by about a factor of 2 for a given number of template reuse cycles. | 2013-07-04 |
| 20130171809 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device has a substrate that includes a cell array region and a dummy pattern region surrounding the cell array region. The cell array region includes a cell structure having a plurality of cell active pillars extending in a vertical direction from the cell array region of the substrate and includes cell gate patterns and cell gate interlayer insulating patterns alternately stacked on the substrate. The cell gate patterns and cell gate interlayer insulating patterns have sides facing the cell active pillars. The dummy pattern region includes a damp-proof structure. | 2013-07-04 |
| 20130171810 | METHODS OF FABRICATING SEMICONDUCTOR DEVICE USING HIGH-K LAYER FOR SPACER ETCH STOP AND RELATED DEVICES - Methods of fabricating a semiconductor device, and related devices, include forming a gate electrode on a substrate, forming a first buffer layer, a second buffer layer and a third buffer layer on side surfaces of the gate electrode and on the substrate near the gate electrode, forming a spacer covering the side surfaces of the gate electrode on the third buffer layer, the third buffer layer on the substrate being exposed, exposing the second buffer layer on the substrate by removing the exposed third buffer layer, exposing the first buffer layer on the substrate by removing the exposed second buffer layer, forming deep junction in the substrate using the spacer as a mask, and removing the spacer. The third buffer layer is a material layer having a higher dielectric constant than the second buffer layer. The spacer includes a material layer different than the third, second and first buffer layers. | 2013-07-04 |
| 20130171811 | METHOD FOR MANUFACTURING COMPOUND SEMICONDUCTOR - In a method for manufacturing a compound semiconductor, a silicon oxide film is formed in an upper part of a substrate made of silicon. Subsequently, a base layer made of single crystal silicon to which ions are implanted is formed by performing ion implantation to a region of the substrate below the silicon oxide film and performing a thermal process. Then, the base layer is exposed by removing the silicon oxide film. Finally, a GaN layer is formed on the base layer. | 2013-07-04 |
| 20130171812 | SELF-ALIGNED PATTERNING WITH IMPLANTATION - A method of fabricating a plurality of features of a semiconductor device includes providing a dielectric layer over a silicon layer, and etching the dielectric layer and the silicon layer to form a plurality of first apertures in the dielectric layer and the silicon layer, wherein adjacent apertures of the plurality of first apertures are set apart by a first pitch. The method further includes etching a plurality of second apertures in the dielectric layer, each aperture of the plurality of second apertures having a greater width than and centered about a respective aperture of the plurality of first apertures, implanting a plurality of dopants into the silicon layer aligned through the plurality of second apertures in the dielectric layer, wherein doped portions of the silicon layer are set apart by a second pitch less than the first pitch, and removing undoped portions of the silicon layer. | 2013-07-04 |
| 20130171813 | FIELD EFFECT TRANSISTOR DEVICE AND FABRICATION - A method for forming a field effect transistor (FET) device includes forming a dielectric layer on a substrate, forming a first metal layer on the dielectric layer, removing a portion of the first metal layer to expose a portion of the dielectric layer, forming a second metal layer on the dielectric layer and the first metal layer, and removing a portion of the first metal layer and the second metal layer to define a boundary region between a first FET device and a second FET device. | 2013-07-04 |
| 20130171814 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes: forming a conductive film on a semiconductor substrate; patterning the conductive film in a memory region to form a first gate electrode; after forming the first gate electrode, forming a mask film above each of the conductive film in a logic region and the first gate electrode; removing the mask film in the logic region; forming a first resist film above the mask film left in the memory region and above the conductive film left in the logic region; and forming a second gate electrode in the logic region by etching the conductive film using the first resist film as a mask. | 2013-07-04 |
| 20130171815 | MANUFACTURING METHOD OF FLASH MEMORY STRUCTURE WITH STRESS AREA - In a manufacturing method of a flash memory structure with a stress area, a better stress effect can be achieved by controlling the manufacturing process of a tunneling oxide layer formed in a gate structure and contacted with a silicon substrate, so that an L-shaped spacer (or a first stress area) and a contact etch stop layer (or a second stress area) of each L-shaped spacer are formed between two gate structures and aligned towards each other to enhance the carrier mobility of the gate structure, so as to achieve the effects of improving a read current, obtaining the required read current by using a lower read voltage, reducing the possibility of having a stress-induced leakage current, and enhancing the data preservation of the flash memory. | 2013-07-04 |
| 20130171816 | APPARATUS AND METHOD FOR PLACING SOLDER BALLS - A system and process for forming a ball grid array on a substrate includes defining a plurality of openings in a resist layer on the substrate, and forming a plurality of openings in the resist layer, each positioned over a contact pad of the substrate. Flux is then deposited in the openings, and solder balls are positioned in each opening with the flux. Solder bumps are formed by reflowing the solder balls in the respective openings. The resist layer is then removed, leaving an array of solder bumps on the substrate. The flux can be deposited by depositing a layer of flux, then removing the flux, except a portion that remains in each opening. Solder balls can be positioned by moving a ball feeder across the resist layer and dropping a solder ball each time an aperture in the ball feeder aligns with an opening in the resist layer. | 2013-07-04 |
| 20130171817 | STRUCTURE AND METHOD FOR REDUCING VERTICAL CRACK PROPAGATION - A semiconductor device and a method of fabricating the same, includes vertically stacked layers on an insulator. Each of the layers includes a first dielectric insulator portion, a first metal conductor embedded within the first dielectric insulator portion, a first nitride cap covering the first metal conductor, a second dielectric insulator portion, a second metal conductor embedded within the second dielectric insulator portion, and a second nitride cap covering the second metal conductor. The first and second metal conductors form first vertically stacked conductor layers and second vertically stacked conductor layers. The first vertically stacked conductor layers are proximate the second vertically stacked conductor layers, and at least one air gap is positioned between the first vertically stacked conductor layers and the second vertically stacked conductor layers. An upper semiconductor layer covers the first vertically stacked conductor layers, the air gap and the second plurality of vertically stacked conductor layers. | 2013-07-04 |
| 20130171818 | Method of Manufacturing A Semiconductor Device - In a method of forming an ohmic layer of a DRAM device, the metal silicide layer between the storage node contact plug and the lower electrode of a capacitor is formed as the ohmic layer by a first heat treatment under a first temperature and an instantaneous second heat treatment under a second temperature higher than the first temperature. Thus, the metal silicide layer has a thermo-stable crystal structure and little or no agglomeration occurs on the metal silicide layer in the high temperature process. Accordingly, the sheet resistance of the ohmic layer may not increase in spite of the subsequent high temperature process. | 2013-07-04 |
| 20130171819 | METHODS FOR INTEGRATION OF METAL/DIELECTRIC INTERCONNECTS - Described herein are methods for copper/low-k dielectric material integration. The methods involve depositing and curing a low-k dielectric material and depositing a mask on the low-k dielectric material. A via is patterned in the low-k dielectric material and a trench is patterned in the low-k dielectric material. After the via or trench is patterned, a portion of the low-k material is backfilled with a backfill material. The trench and via are filled with copper, then the mask and the copper filling the via are removed. After a first pre-CLN, the backfill material is removed. This creates a robust copper/porous low-k dielectric material interconnect. | 2013-07-04 |
| 20130171820 | METHODS FOR THREE-DIMENSIONAL INTEGRATED CIRCUIT THROUGH HOLE VIA GAPFILL AND OVERBURDEN REMOVAL - Presented are methods and systems for fabricating three-dimensional integrated circuits having large diameter through-hole vias. One embodiment of the present invention provides a method of processing a wafer having holes for through-hole vias. The method comprises plating a gapfill metal on the wafer. The method also comprises chemically or electrochemically deplating a portion of the overburden metal. The method further comprises using chemical mechanical planarization to planarize the gapfill metal and to remove the remaining overburden metal. Another embodiment of the present invention is an integrated system comprising a process chamber for containing the wafer, a plating component integrated with the process chamber, and a deplating component integrated with the process chamber. The plating component is configured to electrochemically plate a gapfill metal onto the wafer to a least partially fill the holes. The deplating component is configured to chemically or to electrochemically remove a portion of the overburden metal formed by the plating component. | 2013-07-04 |
| 20130171821 | METHOD OF FABRICATING METAL CONTACT USING DOUBLE PATTERNING TECHNOLOGY AND DEVICE FORMED THEREBY - Metal contacts are formed within a string overhead area using a double patterning technology (DPT) process thereby allowing for the reduction of a string overhead area and a concomitant reduction in the chip size of a semiconductor device. A first mask pattern is formed by etching a first mask layer, the first mask pattern including a first opening formed in a cell region and a first hole formed in a peripheral region. A first sacrificial pattern is formed on the first mask pattern and the exposed first insulating layer of the cell region using a double patterning technology process. Contact holes are formed by exposing the target layer by etching the first insulating layer using the first mask pattern and the first sacrificial pattern as an etch mask. Metal contacts are then formed in the contact holes. | 2013-07-04 |
| 20130171822 | TUNGSTEN FEATURE FILL WITH NUCLEATION INHIBITION - Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. In certain embodiments, the substrate can be biased during selective inhibition. Process parameters including bias power, exposure time, plasma power, process pressure and plasma chemistry can be used to tune the inhibition profile. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3-D integration using through-silicon vias. | 2013-07-04 |
| 20130171823 | CMP Slurry Composition and Polishing Method Using the Same - A CMP slurry composition includes metal oxide particles, a diisocyanate compound, and deionized water. The CMP slurry composition is capable of selectively controlling polishing speed of a wafer surface having a convex portion and a concave portion, such that primary polishing and secondary polishing can be performed rapidly while stopping polishing of the nitride layer upon the secondary polishing. | 2013-07-04 |
| 20130171824 | PROCESS FOR CHEMICALLY MECHANICALLY POLISHING SUBSTRATES CONTAINING SILICON OXIDE DIELECTRIC FILMS AND POLYSILICON AND/OR SILICON NITRIDE FILMS - CMP process for substrates containing silicon oxide dielectric films and polysilicon and/or silicon nitride films comprising the steps of (1) contacting the substrate with an aqueous composition containing (A) abrasive particles which are positively charged when dispersed in an aqueous medium having a pH in the range of from 3 to 9; (B) a water-soluble or water-dispersible linear or branched alkylene oxide homopolymer or copolymer; and (C) a water-soluble or water-dispersible polymer selected from (c1) aliphatic and cycloaliphatic poly(N-vinylamide) homopolymers and copolymers, (c2) homopolymers and copolymers of acrylamide monomers of the general formulas I and II: H | 2013-07-04 |
| 20130171825 | PHOTORESIST PATTERN TRIMMING METHODS - Provided are methods of trimming photoresist patterns. The methods involve coating a photoresist trimming composition over a photoresist pattern, wherein the trimming composition includes a matrix polymer, a thermal acid generator and a solvent, the trimming composition being free of cross-linking agents. The coated semiconductor substrate is heated to generate an acid in the trimming composition from the thermal acid generator, thereby causing a change in polarity of the matrix polymer in a surface region of the photoresist pattern. The photoresist pattern is contacted with a developing solution to remove the surface region of the photoresist pattern. The methods find particular applicability in the formation of very fine lithographic features in the manufacture of semiconductor devices. | 2013-07-04 |
| 20130171826 | SEMICONDUCTOR DEVICE PRODUCTION METHOD AND RINSE - The present invention provides a semiconductor device production method and a rinse used in the production method. The method includes: a sealing composition application process in which a semiconductor sealing layer is formed by applying, to at least a portion of a surface of a semiconductor substrate, a semiconductor sealing composition that includes a resin having a cationic functional group and a weight average molecular weight of from 2,000 to 600,000, wherein a content of sodium and a content of potassium are 10 mass ppb or less on an elemental basis, respectively; and, subsequently, a rinsing process in which the surface of the semiconductor substrate on which the semiconductor sealing layer has been formed is rinsed with a rinse having a pH at 25° C. of 6 or lower. | 2013-07-04 |
| 20130171827 | METHOD AND APPARATUS FOR MANUFACTURING THREE-DIMENSIONAL-STRUCTURE MEMORY DEVICE - A method for manufacturing a memory device having a vertical structure according to one embodiment of the present invention comprises: a step for alternatingly laminating one or more insulation layers and one or more sacrificial layers on a substrate; a step for forming a penetration hole for penetrating the insulation layer and the sacrificial layer; a step for forming a pattern for filling up the penetration hole; a step for forming an opening for penetrating the insulation layer and the sacrificial layer; and a step for removing the sacrificial layer by supplying an etchant through the opening, wherein the step for laminating the insulation layer includes a step for depositing a first silicon oxide film by supplying to the substrate at least one gas selected from the group consisting of SiH | 2013-07-04 |
| 20130171828 | PROCESSING LIQUID FOR SUPPRESSING PATTERN COLLAPSE OF MICROSTRUCTURE, AND METHOD FOR PRODUCING MICROSTRUCTURE USING SAME - There are provided a processing liquid for suppressing pattern collapse of a microstructure formed of polysilicon which includes at least one compound selected from the group consisting of pyridinium halides containing an alkyl group having 12, 14 or 16 carbon atoms, and water; and a method for producing a microstructure using the processing liquid. | 2013-07-04 |
| 20130171829 | Titanium-Nitride Removal - A chemical solution that removes undesired metal hard mask yet remains selective to the device wiring metallurgy and dielectric materials. The present invention decreases aspect ratio by selective removal of the metal hard mask before the metallization of the receiving structures without adverse damage to any existing metal or dielectric materials required to define the semiconductor device, e.g. copper metallurgy or device dielectric. Thus, an improved aspect ratio for metal fill without introducing any excessive trapezoidal cross-sectional character to the defined metal receiving structures of the device will result. | 2013-07-04 |
| 20130171830 | METHOD FOR REMOVING GERMANIUM SUBOXIDE - A method for removing germanium suboxide between a germanium (Ge) substrate and a dielectric layer made of metal oxide includes causing a supercritical fluid composition that includes a supercritical carbon dioxide fluid and an oxidant to diffuse into the germanium suboxide such that metal residues in the dielectric layer, the germanium suboxide and the oxidant are subjected to a redox reaction so as to reduce the germanium suboxide into germanium. | 2013-07-04 |
| 20130171831 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - A substrate processing apparatus includes a substrate holding unit configured to hold a substrate; a first processing liquid nozzle configured to supply a first processing liquid to a peripheral portion of the substrate; a second processing liquid nozzle configured to supply a second processing liquid, the temperature of which is lower than that of the first processing liquid, to the peripheral portion of the substrate; a first gas supply port configured to supply a first gas at a first temperature to a first gas supplied place on the peripheral portion of the substrate; and a second gas supply port configured to supply a second gas at a second temperature lower than the first temperature to a place closer to the center in the radial direction as compared to the first gas supplied place with respect to the substrate. | 2013-07-04 |
| 20130171832 | Enhanced Isolation For Combinatorial Atomic Layer Deposition (ALD) - An apparatus and method for delivering fluids to a semiconductor chamber for combinatorial processing is provided. In some embodiments the apparatus is comprised of a showerhead assembly having a plurality of processing sectors separated by a purge member. The processing sectors are configured to receive one or more processing fluids for combinatorial processing on a substrate. The processing sectors are isolated by a purge fluid conveyed through the purge member. The purge member is configured to selectively control the profile of the purge fluid to enhance isolation of the processing fluids within each sector. The profile of the purge fluid is manipulated by selectively controlling the shape and/or density of the purge curtain, independently between each processing sector. | 2013-07-04 |
| 20130171833 | METHODS AND APPARATUS FOR WETTING PRETREATMENT FOR THROUGH RESIST METAL PLATING - Disclosed are pre-wetting apparatus designs and methods. In some embodiments, a pre-wetting apparatus includes a degasser, a process chamber, and a controller. The process chamber includes a wafer holder configured to hold a wafer substrate, a vacuum port configured to allow formation of a subatmospheric pressure in the process chamber, and a fluid inlet coupled to the degasser and configured to deliver a degassed pre-wetting fluid onto the wafer substrate at a velocity of at least about 7 meters per second whereby particles on the wafer substrate are dislodged and at a flow rate whereby dislodged particles are removed from the wafer substrate. The controller includes program instructions for forming a wetting layer on the wafer substrate in the process chamber by contacting the wafer substrate with the degassed pre-wetting fluid admitted through the fluid inlet at a flow rate of at least about 0.4 liters per minute. | 2013-07-04 |
| 20130171834 | IN-SITU DEPOSITION OF FILM STACKS - Disclosed herein are methods of forming a film stack which may include the plasma accelerated deposition of a silicon nitride film formed from the reaction of nitrogen containing precursor with silicon containing precursor, the plasma accelerated substantial elimination of silicon containing precursor from the processing chamber, the plasma accelerated deposition of a silicon oxide film atop the silicon nitride film formed from the reaction of silicon containing precursor with oxidant, and the plasma accelerated substantial elimination of oxidant from the processing chamber. Also disclosed herein are process station apparatuses for forming a film stack of silicon nitride and silicon oxide films which may include a processing chamber, one or more gas delivery lines, one or more RF generators, and a system controller having machine-readable media with instructions for operating the one or more gas delivery lines, and the one or more RF generators. | 2013-07-04 |
| 20130171835 | COMPOSITION FOR WATER-REPELLENT TREATMENT OF SURFACE, AND METHOD FOR WATER-REPELLENT TREATMENT OF SURFACE OF SEMICONDUCTOR SUBSTRATE USING SAME - The purpose of the present invention to provide: a composition which can be used for water-repellent treating of the entire surface of a semiconductor substrate having a pattern formed by laminating a Si-containing insulating layer and a metal layer, at one time; and a method for water-repellent treatment of the semiconductor substrate surface using the composition. | 2013-07-04 |
| 20130171836 | METHOD FOR SURFACE TREATMENT ON A METAL OXIDE AND METHOD FOR PREPARING A THIN FILM TRANSISTOR - Embodiments of the present invention provide a method for surface treatment on a metal oxide and a method for preparing a thin film transistor. The method for surface treatment on a metal oxide comprises: utilizing plasma to perform a surface treatment on a device to be processed; the plasma comprises a mixture gas of an F-based gas and O | 2013-07-04 |
| 20130171837 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A substrate having a recess is provided. A decoupled plasma nitridation process is performed to nitride the surface of the recess for forming a nitrogen containing liner on the surface of the recess. A nitrogen containing annealing process is then performed on the nitrogen containing liner. | 2013-07-04 |
| 20130171838 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF PROCESSING SUBSTRATE, SUBSTRATE PROCESSING APPARATUS, AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM - Provided is a method of manufacturing a semiconductor device capable of forming a nitride layer having high resistance to hydrogen fluoride at low temperatures. The method includes forming a nitride film on a substrate by performing a cycle a predetermined number of times, the cycle including supplying a source gas to the substrate, supplying a plasma-excited hydrogen-containing gas to the substrate, supplying a plasma-excited or thermally excited nitriding gas to the substrate, and supplying at least one of a plasma-excited nitrogen gas and a plasma-excited rare gas to the substrate. | 2013-07-04 |
| 20130171839 | C-RICH CARBON BORON NITRIDE DIELECTRIC FILMS FOR USE IN ELECTRONIC DEVICES - A carbon-rich carbon boron nitride dielectric film having a dielectric constant of equal to, or less than 3.6 is provided that can be used as a component in various electronic devices. The carbon-rich carbon boron nitride dielectric film has a formula of C | 2013-07-04 |
| 20130171840 | CONNECTOR SYSTEMS WITH MAGNETIC RETAINING MEANS - Connector systems ( | 2013-07-04 |
| 20130171841 | TEST DEVICE FOR TESTING USB SOCKETS - A test device includes a load module, an input module, an output module, a switching module, and a control module. The load module includes a light electrical load and a heavy electrical load. The input module includes at least one input connector switchably connected to the light load and the heavy load. The output module includes at least one output connector switchably connected to one of the at least one input connector. The switching module is configured to switch a connection between the input connector and the load module, and the connection between the at least one output connector and the at least one input connector. The control module is configured to control the switching module to switch the connections. | 2013-07-04 |
| 20130171842 | SOCKET FOR ELECTRIC PARTS - A socket for electric parts which is dawn sized. The socket of the present invention comprises a socket body to accommodate an electric part, plural contact pins disposed to a peripheral edge of the socket body, a latch rotatably located on the socket body so as to positioned above the contact pins, which presses an upper part of the electric part when the latch is closed and is in a state the electric part can be accommodated and taken out when the latch is opened, an operating member which is vertically movably disposed in the socket body and comprises an operating portion for opening constituted so as to press down an operation portion to be operated for opening formed to a central portion in a width direction of the latch and rotate the latch in an opening direction when the operating member moves downward. | 2013-07-04 |
| 20130171843 | BUS BAR FOR POWER DISTRIBUTION ON A PRINTED CIRCUIT BOARD - A bus bar distributes power to a plurality of electronic components supported on a printed circuit board. One embodiment of the bus bar comprises a plurality of compressible contact pads made from an electronically conductive polymer, spaced along the bus bar for contacting conductive contacts that are coupled to a power domain or individual electronic component. The pads may be secured to the bus bar and the conductive traces using an electronically conductive epoxy adhesive. Rivets may then be used to secure the bus bar to the printed circuit board and compress the pads, which conform to the printed circuit board to make a reliable electrical connection with the conductive traces. The bus bar further comprises a plurality of current sense points disposed adjacent to the pads for measuring the amount of current provided to each power domain. | 2013-07-04 |
| 20130171844 | ELECTRIC CONNECTOR CAGE - An electric connector cage is disclosed. In order to achieve an accurate positioning of a spring member with respect to a cage body and make operations such as welding easy to perform, the electric connector cage includes the cage body and a grounding spring member to be fixed to a distal end portion of the cage body, and includes one or more sets of a positioning recess formed at the distal end portion of the cage body and a positioning projection formed to engage a distal end portion of the spring member corresponding to the recess. | 2013-07-04 |
| 20130171845 | HOUSING FOR COMPUTER SYSTEM AS WELL AS COMPUTER SYSTEM WITH SUCH A HOUSING - A housing for a computer system which can be opened at least on a first housing wall for access into the housing and wherein, on a second housing wall, an opening for an external connector plug is arranged, the housing having a covering fixture to cover the opening for the connector plug, wherein the covering fixture is operable by the first housing wall such that the opening for the external connector plug is covered at least partially when the housing is opened, and the opening for the external connector plug is not covered when the housing is closed. | 2013-07-04 |
| 20130171846 | USB DEVICE WITH A CAP - An electronic device, which may be a USB device, includes a body part that is removably connected to a cap. The body part includes a connector for plugging the device into a host computing device. The cap includes a lever part and a main part. The lever part of the cap is attached to the main part and pivots at least partially around a pivot axis. The lever part includes an anchor part on one side of the pivot axis and an unlock part on the other side of the pivot axis. The anchor part includes a hook that engages a cavity in the body part when the cap is connected to the body part. Depressing the unlock part of the cap causes the lever to pivot around the pivot axis thereby disengaging the hook from the first cavity, and thereby releasing the cap from the body part. | 2013-07-04 |
| 20130171847 | LEAKAGE PROTECTION SOCKET WITH INTEGRATED BAFFLE LOCKING MECHANISM - A power outlet may comprise an enclosure with at least one plug jack, a reset button comprising at least one integrally formed extension latch arm, the extension latch arm comprising at least one positioning pin, and at least one baffle configured to selectively block at least a portion of the plug jack, the baffle comprising an outer wall comprising a face, a pin slit, and a leg. The extension latch arm positioning pin is configured to selectively press against the outer wall face when the extension latch arm is in an upward position. The extension latch arm positioning pin is configured to selectively enter the outer wall pin slit when the extension latch arm is in a downward position. | 2013-07-04 |
| 20130171848 | SURFACE CONTACT CARD HOLDER FOR ELECTRONIC DEVICE - A surface contact card holder includes a housing, a tray and two elastic members positioned between the tray and the housing. The housing includes a support plate and defines an opening. The support plate defines a through hole. The tray is slidable and receivable in the housing from the opening and the tray is configured for carrying a surface contact card therein. The tray includes a tray body and a cantilever arm extending from the tray body. The cantilever arm includes a protruding portion releasbly latched in the through hole. When the protruding portion is pressed to release the tray, the tray is automatically slid out of the opening under the elastic force of the elastic members to allow insertion and removal of the surface contact card from the housing. | 2013-07-04 |
| 20130171849 | ADJUSTABLE ELECTRICAL BUSWAY JOINT - An adjustable busway joint for coupling two longitudinally aligned busway sections is disclosed. The adjustable joint has a first plurality of electrically conductive splice plates defining a splice plate adjustment slot, and a second plurality of electrically conductive splice plates defining an aperture, wherein each splice plate of the second plurality of splice plates is disposed to overlap a portion of a corresponding splice plate of the first plurality of splice plates to form an electrical joint, and wherein the aperture is sized and disposed to overlap at least a portion of the first splice plate adjustment slot. The joint additionally has a first clamping member disposed through the splice plate adjustment slot and the aperture such that the first and said second pluralities of splice plates are operably movable with respect each other between a first compressed position and a second extended position. | 2013-07-04 |
| 20130171850 | ADJUSTABLE ELECTRICAL BUSWAY JOINT - An adjustable length busway joint for coupling a first and a second busway section, the first and second busway sections being longitudinally offset, is disclosed. The busway joint includes a first plurality of splice plates and a second plurality of splice plates disposed to overlap to form an electrical joint. The first and said second pluralities of splice plates are arranged for a longitudinal movement with respect each other between a first compressed position and a second extended position. The busway joint further includes a third plurality of splice plates. Each splice plate of the second plurality of splice plates overlaps a portion of a corresponding splice plate of the third plurality of splice plates to form an electrical joint. The third and second pluralities of splice plates are arranged for a longitudinal movement with respect each other between a third compressed position and a fourth extended position. | 2013-07-04 |
| 20130171851 | HOUSING FOR A COMPUTER SYSTEM AND A COMPUTER SYSTEM WITH SUCH A HOUSING - A housing for a computer system which can be opened at at least one first housing wall for access into the housing and an opening for an external connecting plug is disposed at a second housing wall and where 1) the housing has a locking device to lock the first housing wall and prevent opening of the housing, the locking device is disposed at the opening for an external connecting plug and is actuatable via an external connecting plug so that the first housing wall is locked when an external connecting plug is inserted into the opening and the first housing wall is unlocked if no external connecting plug is inserted into the opening. | 2013-07-04 |
| 20130171852 | MULTI-INTERFACE - A line replaceable unit (LRU) for an integrated modular avionics (IMA) architecture, the LRU comprising at least one input/output interface and a plurality of connectors, wherein each connector includes at least one pin and each connector is adapted for connection to a single segregated wire route bundle, and wherein hardware of one interface is electrically connected within the LRU to one or more pins of each of at least two of the connectors. Also, an IMA architecture including the LRU, and an aircraft including the LRU or the IMA architecture. | 2013-07-04 |
| 20130171853 | CONNECTOR - A connector includes a connector housing having a cavity, a male terminal having a protruded portion, a sealing ring receiving recess included in the connector housing, a sealing ring arranged in the sealing ring receiving recess, and a retainer mounted in the connector housing and pressing the sealing ring from a front side of the protruded portion of the male terminal. The male terminal is housed in the cavity in a way that the protruded portion protrudes from the connector housing. The sealing ring receiving recess is located at a position corresponding to a base section of the male terminal that is on a side from which the protruded portion protrudes. The male terminal passes through the sealing ring such that it seals a space between the male terminal and an inner surface of the sealing ring receiving recess. The retainer includes an engagement portion engaged with the male terminal. | 2013-07-04 |
| 20130171854 | Waterproof Connector and Waterproof Connector Mounting Structure and Mounting Method - A waterproof connector is provided for ensuring an appropriate intimate contact state to a sealing member without impairing easy assembly. The connector includes a housing that holds at least one contact for establishing an electrical connection with a mating connector; and a ring-shaped sealing member mounted on the housing, the sealing member having a front face and a rear face; at least a first and a second guide portion provided adjacent to each of both faces of the sealing member, the guide portions guiding the housing when being mounted to a case. | 2013-07-04 |
| 20130171855 | SOCKET FOR ELECTRIC PARTS - A socket for electric parts which is dawn sized. The socket of the present invention comprises a socket body to accommodate an electric part, plural contact pins disposed to a peripheral edge of the socket body, a latch rotatably located on the socket body so as to positioned above the contact pins, which presses an upper part of the electric part when the latch is closed and is in a state the IC socket can be accommodated and taken out when the latch is opened, an operating member which is vertically movably disposed in the socket body and comprises an operating portion for closing constituted so as to press upward an operation portion to be operated for dosing formed to both side end portion of the latch and rotate the latch in an closing direction when the operating member moves upward. | 2013-07-04 |
| 20130171856 | ELECTRICAL CONNECTOR - An electrical connector includes an elongated insulating housing defining a number of passageways and power terminals received in corresponding passageways. The passageways are arranged side by side along a longitudinal direction of the insulating housing. Each power terminal has a first terminal and a second terminal oppositely arranged beside the first terminal. The first terminal has a first contacting portion, a first fixing portion extending towards the second terminal, and a first connecting portion connecting the first contacting portion and the first fixing portion. The second terminal has a second contacting portion oppositely arranged beside the first contacting portion of the first terminal. A curved intermediate region is formed between the first connecting portion and the first contacting portion of the first terminal. A width of the first fixing portion is larger than a distance between the first contacting portion and the second contacting portion. | 2013-07-04 |
| 20130171857 | Electrical Connector - The invention relates to an electrical connector having a first contact housing, a second contact housing, and a lock housing. The first contact housing includes a housing protrusion disposed on a rear end portion thereof, and the second contact housing is positioned over the first contact housing. The lock housing includes a base portion positioned across the second contact housing and a deformable lock arm extending from the base portion toward the first contact housing. The deformable lock arm includes an engaging protrusion facing the first contact housing and is deformable by the first contact housing when not engaged with the housing protrusion. | 2013-07-04 |
| 20130171858 | DETACHABLE LID - A method and apparatus for mounting a semiconductor is disclosed. First, the semiconductor is mounted into the bracket of a lid while the lid is detached from a frame. Once the semiconductor has been loaded into the lid/bracket assembly, the loaded lid is mounted onto the frame. The lid is then locked in place on the frame by rotating a locking lever into a closed locked position. | 2013-07-04 |
| 20130171859 | THIN CONNECTOR RECEPTACLE HOUSINGS - Structures, methods, and apparatus that provide connector receptacles that have a reduced tendency to scratch and otherwise mar connector inserts, have an aesthetically-pleasing appearance, have an improved tactile response when inserts are inserted, or are very thin or have a low profile. Various examples reduce scratches and wear by utilizing domes, cylinders, balls, or other structures as finger contacts in a connector receptacle. Another example provides aesthetically-pleasing connector receptacle enclosures by forming receptacle enclosures using the same type of material, or material having the same or similar color or texture, as is used for enclosing the electronic device that includes the receptacle. Another example provides an aesthetically-pleasing receptacle enclosure by forming receptacle enclosures that are, in part or in whole, contiguous or formed with the housing. Another example provides a super-thin connector receptacle by removing fingers and portions of a shell along one or more sides. | 2013-07-04 |
| 20130171860 | CONNECTOR MOUNTING APPARATUS - A connector mounting apparatus includes a receiving bracket for receiving a connector, and a front panel. The receiving bracket includes two hooks and a positioning tab. The front panel includes a front panel body. The front panel body defines two securing holes and a positioning cutout. The two securing holes are engaged by the two hooks to prevent the receiving bracket from moving along a first direction. The front panel includes a resilient arm. The positioning tab is received in the positioning cutout. The resilient arm is adjacent to the positioning cutout to prevent the positioning tab from moving along a second direction. The resilient arm is pressed to enable the positioning tab to be moved out of the positioning cutout along the second direction. The two hooks disengage from the two securing holes when the two hooks move along the second direction. | 2013-07-04 |
| 20130171861 | SOCKET FOR ELECTRIC PARTS - A socket for electric parts which is dawn sized. The socket of the present invention comprises a socket body, contact pins to conduct to an electric part, a latch rotatably located on the socket body so as to positioned above the contact pins, which presses the electric part when the latch is closed and is in a state the electric part can be accommodated and taken out when the latch is opened, and an operating member vertically movably disposed in the socket body and comprises an operating portion for opening constituted so as to press down an operation portion to be operated for opening formed to the latch and rotate the latch in an opening direction when the operating member descends. A outermost position of the latch is disposed on an inside of outermost portion of the contact pins when the latch is opened to an outermost position. | 2013-07-04 |
| 20130171862 | ANTI-MISINSERTION STRUCTURE OF SOCKET CONNECTOR - An anti-misinsertion structure of a socket connector includes a pivot clasped to both sides of the top of an insulating base of the socket connector and two connecting arms extended horizontally from both sides of the pivot. Each connecting arm has a guide piece extended horizontally from an end of each connecting arm, a stop piece formed at the bottom of the connecting arm and proximate to the guide piece of the connecting arm, a downwardly tilted first guide bevel formed at the bottom of the guide piece, a position limit surface defined on a side of the guide piece and proximate to the stop piece, an upwardly tilted second guide bevel formed at the bottom of the stop piece, and a stop surface defined on a side of the stop piece and proximate to the guide piece and perpendicular to the position limit surface of the guide piece. | 2013-07-04 |
| 20130171863 | EDGE CONNECTOR - An edge connector is to accept a memory card therein, the memory card having two opposite side surfaces, each provided with a plurality of terminal contacts. The edge connector includes an insulated body formed with a reception chamber; a plurality of first and second terminals mounted on the insulated body, each having a fixing section extending into the reception chamber and a transmission section integrally formed with, bent relative to the fixing section and extending into the reception chamber in order to form a card slot therebetween. The transmission section of the first terminal has a scratching corner protruding into the card slot, wherein, forcibly insertion of the memory card into the card slot causes the scratching corner to scratch away of an oxidized layer formed on the terminal contacts of the memory card, thereby enhancing electrical connection between the memory card and the first and second terminals. | 2013-07-04 |
| 20130171864 | CABLE WITH MULTIPLE, PHYSICALLY SELECTABLE CONNECTORS - An electronic cable is provided. The electronic cable includes a cable extending between a first end and a second end. A first electronic connection extends from the first end of the cable. A plurality of physically selectable electronic connections extend from the second end of the cable. | 2013-07-04 |
| 20130171865 | ELECTRICAL CORD REEL WITH REMOVEABLE CORD - An electrical cord can include a cord segment with an electrical connector. The connector can connect to a spool member of an electrical cord reel to form an electrical connection between the electrical cord and the electrical cord reel. The spool can have a recess that engages and/or mates with the connector. When the connector is in the recess, at least a portion of the connector can be flush with a cylinder surface of the spool. The connector can be secured in the recess with one or more fasteners (e.g., screws). The connector and recess can have members that act as the primary load bearing members when spooling and unspooling the electrical cord to inhibit the application of loads on the electrical connection during rotation of the spool member. | 2013-07-04 |
| 20130171866 | ELECTRICAL CORD WITH WEAR RING - An electrical cord can include a cord segment with a receptacle. The receptacle can have a surface and apertures that accept a plug to form an electrical connection between the plug and wires of the electrical cord. A wear ring can be on the receptacle. The wear ring can be at least as large as the receptacle in a transverse cross-section. The wear ring can inhibit or prevent at least a portion of the surface from contacting a ground surface when the receptacle is on the ground surface or is dragged along the ground surface. | 2013-07-04 |
| 20130171867 | BIOMETRIC BELT CONNECTOR - A belt connector for electrically connecting an electrode belt to a biometric device to be carried on a human or animal body. The belt connector is made from one single piece which can be economically manufactured in order to function as a single-use consumable, to be used with a matching biometric device. The connector comprises a molded plastic frame having a shaped circular or semi-circular hole with radial flexibility to function as a female snap button fastener for receiving and fastening on the front side of the frame a male snap protrusion. The belt connector further comprises fastening means for fastening to the frame a belt end of said electrode belt, and a member adjacent to said snap fastener hole to engage an electrode wire end electrically connected to said belt such that said end is in contact with said hole and comes in electrical contact with a conducting male snap fastener inserted in said hole. The belt connector and belt is configured such that a person wearing the belt under operation is insulated from current running through the belt, in order to meet existing standards for medical devices. | 2013-07-04 |
| 20130171868 | Ground Spring with Strain Relief - A ground spring for receiving a ground end of a high-frequency test probe is described. The ground spring includes a generally annular base portion, and a number of elongated spring fingers extending from the base portion. The fingers extend generally radially inwardly from the base portion and have inner end faces that together define a substantially circular opening in a center portion of the ground spring. Each of the fingers have a tapered shape including a wider base portion end and a narrower inner end portion Each of the fingers has a longitudinal axis that is aslant relative to a reference line extending from the center of the ground spring to a center of the base portion of each finger. BMA connectors including the ground spring and test and measurement devices are also described. | 2013-07-04 |
| 20130171869 | Coaxial Connector with Grommet Biasing for Enhanced Continuity - A compressible F-connector and method for interconnection with coaxial cable that includes a biasing grommet for promoting electrical continuity despite inadequate nut tightening. Each connector has a rigid nut, a post penetrating the nut, a tubular body, and an end cap. The conductive post coaxially extends through the connector, linking the nut and body. A post end penetrates the coaxial cable. Each connector body comprises a frontal annular groove in which is seated a biasing grommet with projections extending from one or both grommet ends that bias the nut to insure mechanical and electrical contact with the post. In one embodiment of the invention the projections are semicircular. In alternative embodiments the projections may be triangular or square, and projections on one grommet end may be radially offset from projections on the opposite end. | 2013-07-04 |
| 20130171870 | Coaxial Connector with Internal Nut Biasing Systems for Enhanced Continuity - A compressible, F-connector for interconnection with coaxial cable that includes at least one biasing system for promoting electrical continuity, despite inadequate nut tightening. Each connector has a rigid nut, a post penetrating the nut, a tubular body, and an end cap. The conductive post coaxially extends through the connector, linking the nut and body. A post end penetrates the coaxial cable. Biasing systems emanating from the body pressure the nut. The biasing systems comprise pistons or bearings yieldably biased by springs seated within radially spaced-apart bores in the connector body that are pressured outwardly of the body towards the nut. Yieldable pressure applied to the nut by the biasing systems insures mechanical and electrical contact between the nut and the post. | 2013-07-04 |
| 20130171871 | SHIELDED MULTI-POLE ELECTRICAL CONNECTOR - A high-power, shielded, multi-pole electrical connector and method for installing such a connector are disclosed. The connector has separate structure for connecting each line of a multi-pole connector, with this structure housed within an electrically conductive outer shell. The inner connections are electrically insulated and shielded from the outer shell. A shielding trap is used to provide electrical contact between the outer shell of the connector and a shielding layer of a shielded electrical supply cable. The inner structure may be a male-female type or a lug-type connection. In a typical arrangement, a three-pole connector is used to provided a shielded connection to each of three power lines within a shielded cable. | 2013-07-04 |
| 20130171872 | SHIELD CONNECTOR - An inner terminal connected to a terminal of a core wire and provided with an electric connecting portion electrically connected with a mating terminal is received in an inner housing. The inner housing is incorporated into an outer terminal. The outer terminal is mated with a mating connector in such a state as that the shield member is connected to the outer terminal and the electric connecting portion of the inner terminal is positioned in the outer terminal. The outer terminal has the same configuration as that of an outer terminal of the mating connector, thus making the outer terminals sharable between male and female connectors. | 2013-07-04 |
| 20130171873 | SHIELD CONNECTOR - An inner terminal is provided with a crimp barrel portion with which a terminal of a core wire is connected and an electric connecting portion to be electrically connected with a mating terminal. The inner terminal is received in an insulation inner housing. The inner housing is set into a terminal body portion. An outer terminal is provided with a shield member connecting portion with which a shield member is connected and a cylindrical portion in which the electric connecting portion of the inner terminal is positioned, the cylindrical portion mated with a mating connector. An impedance adjusting portion is provided between the electric connecting portion and the crimp barrel portion of the inner terminal. | 2013-07-04 |
| 20130171874 | CONNECTOR HAVING FILTERING MODULE - The connector contains a port member, a base board electrically connected to the port member, and a filtering module electrically connected to the base board. The filtering module contains a number of vertically stacked circuit boards. There are a number of layout areas on each circuit board. Between a pair of adjacent circuit boards, an amorphous ring core is configured correspondingly to each layout area. Through the conduction between the amorphous ring core and the circuits in the layout areas, the amorphous ring cores are capable of filtering. The connector does not require manual winding, and have advantages such as stable quality and reduced production time. | 2013-07-04 |
| 20130171875 | UNIVERSAL SERIAL BUS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed are a universal serial bus (USB) memory device having a 5 pin USB connector which may be directly used for a portable terminal and a method of manufacturing the same. The USB memory device includes: at least one 5 pin USB connector; a memory to write data received from the 5 pin USB connector or reading out stored data to transmit the data to the 5 pin USB connector; and a controller electrically connected to the 5 pin USB connector and the memory to control data transmission between the 5 pin USB connector and the memory, wherein the 5 pin USB connector comprises a power terminal, a ground terminal, a D+ terminal, a D− terminal, and an ID terminal, and the ID terminal is connected to the ground terminal so that the 5 pin USB connector is grounded. | 2013-07-04 |
| 20130171876 | COAXIAL ELECTRICAL CONNECTOR AND COAXIAL ELECTRICAL CONNECTOR ASSEMBLY - A coaxial electrical connector having a shorter height and improved retention strength against mating and removal with a simple structure is provided. A connector mounting portion P | 2013-07-04 |
| 20130171877 | HIGH-VOLTAGE COUPLING DEVICE - The present invention relates to an electric coupler for high-voltage DIN C type cells comprising a voltage divider, a condenser and two terminal contacts and wherein the condenser is elongated and its ends are in contact with the two terminals of the coupling device, occupying an axis parallel to the imaginary central axis of the connector passing through the two contacts and wherein the resistances of the divider are aligned and parallel to the mentioned axis of the zig-zag device. As a result of this arrangement the insulation can be assured and the field distributions of both systems are compatible with one another and with those of the DIN C connector. | 2013-07-04 |
| 20130171878 | CONNECTOR ASSEMBLY - A connector assembly includes an input/output device, a motherboard, at least one first cable, a first connector connected to the motherboard, a signal increasing connector located between the at least one first USB input/output connector and the first connector, and a power supply cable connected to the signal increasing connector and the motherboard The an input/output device includes at least one first USB input/output connector. The signal increasing connector divides the at least one cable into a first portion and a second portion. The first portion is connected to the signal increasing connector and the at least one first USB input/output connector, and the second portion is connected to the signal increasing connector and the first connector. | 2013-07-04 |
| 20130171879 | CHARGER WITH REMOVABLE CAP - A charger includes a housing defining a receiving cavity, two through holes defined in the housing communicating with the receiving cavity, two slots defined in the housing, a fuse and a spring member received in the receiving cavity, a cap movably coupled to the housing, and an anode contact. The anode contact abuts between the spring member and the fuse engaging with the cap. A hooks engages in the through holes to prevent the cap from detaching from the housing, being disengageable from the through holes when pushed by a pin inserted into the through holes allowing the spring member to push the cap to move until the hooks engage in the slots. The cap is rotated a predetermined angel until the hooks are slidably received in a receiving grooves, thereby allowing the cap to be detachable from the housing through the opening. | 2013-07-04 |
| 20130171880 | Mounting Socket For Mobile Phone - A card mounting socket for a mobile phone having a reduced size and reduced number of parts. The card mounting socket having a body and a separate casing. The body housing includes a first receiving section, a second receiving section and an inner wall. The first receiving section is provided with a pair of guides positioned on both sides thereof and a first card terminal disposed along a major surface of the first receiving section. The second receiving section includes a second card terminal disposed along a major surface of the second receiving section. The inner wall extends perpendicular from the first receiving section to the second receiving section such that the second receiving section is stepped with respect to the first receiving section. The separate casing is secured to an upper portion of the body and separates the first receiving section from the second receiving section. | 2013-07-04 |
| 20130171881 | CONNECTOR BLOCK ASSEMBLY UTILIZING A SINGLE OUTPUT AND ASSOCIATED METHOD OF USE - A connector block assembly that includes two or more input terminals for receiving electrical input voltage, a single electrical conductor output that is electrically connected to two or more input terminals, an insulator base; wherein the plurality of input terminals for receiving electrical input voltage are mounted within the insulator base and the single electrical conductor output are transversely mounted either within the insulator base or to the outside of the outer insulator so that the single electrical conductor output is at an angle of about seventy degrees to about one hundred-ten degrees in relationship to the two or more input terminals with a variation of angles between these two values. The optimal embodiment is being a single electrical conductor output being substantially perpendicular at an angle of about ninety degrees in relationship to the plurality of input terminals. | 2013-07-04 |
| 20130171882 | HDMI AUDIO-VIDEO SIGNAL SWITCHING DEVICE - An HDMI audio-video signal switching device comprises two housing bodies and a conductively connecting circuit board. Each of the housing bodies has an assembling end and a plugged end. The conductively connecting circuit board is a circuit board formed, at each end thereof corresponding to a positioning slot of each housing body, with a plugging projection sheet. Each plugging projection sheet has conductively connecting terminals. A portion of the conductively connecting circuit board between the two plugging projection sheets is set in the positioning slot, such that each plugging projection sheet and conductively connecting terminals thereon are allowed to pass through the positioning slot and then extend into a plugged hole, as well as the assembling ends of the two housing bodies are allowed to be butted and assembled together. Thereby, a more simplified structure is introduced for the HDMI audio-video signal switching device. | 2013-07-04 |
| 20130171883 | POWER SUPPLY PLUG STRUCTURE - A power supply plug structure includes a hollow housing, at least two conductive poles, at least two wire connecting members and at least two snap rings. The housing includes a base body. The base body defines an opening. The conductive pole includes a main body and an insertion body connected with the main body. The main body passes through the base body, and is exposed out of the housing. The insertion body is received in the housing. The wire connecting members sleeve on the conductive poles and are positioned outside of the housing. The snap ring sleeves on the main body as the main body is exposed out of the housing and also clamps the main body to hold each conductive pole on the housing. | 2013-07-04 |
| 20130171884 | MULTIPLE-USE ELECTRICAL CONNECTOR - An electric connector comprising a housing, a tongue module, a plurality of first terminals, a plurality of second terminals and the terminals assembled in the housing and tongue, and a metal shell assembled in the housing. The tongue module is assembled in the housing, and those first terminals disposed in the tongue module by insert molding. Each first terminal has an extended part buried in the tongue module. The lower surface of the tongue module has a plurality of second terminal receiving slots between those first terminals. The pitch between the two adjacent first terminals is greater than the width of the second terminal receiving slot. The upper surface of the tongue module has a plurality of the terminal receiving slots. | 2013-07-04 |
| 20130171885 | SHIELDED ELECTRICAL CONNECTOR WITH GROUND PINS EMBEDED IN CONTACT WAFERS - An electrical connector assembly includes a receptacle and a plug. The receptacle includes a housing defining two vertical stacked mating slots and a plurality of wafers loaded in the housing. Each wafer includes an upper pair and a lower pair of contacting portions, the upper pairs and the lower pairs of the wafers expose to the slots respectively. Each of the wafers further defines a ground contact with a contacting portion between the upper pair and lower pair of the contacting portions. The plurality of wafers includes pairs of differential signal wafers and ground wafers which are arranged in an alternating sequence in the connecting housing. The plug includes two card edges and a ground plate with a row of contacting pin between the card edges. The contacting pins of the ground plate touch with pairs of ground contacts formed with two adjacent ground contacts in two adjacent wafers. | 2013-07-04 |
