27th week of 2013 patent applcation highlights part 21 |
Patent application number | Title | Published |
20130169282 | DETECTION CIRCUITS FOR BATTERIES - A detection circuit includes a sensing unit, a signal reference source, and a detecting unit. The sensing unit provides a sensed signal by sensing an input signal representing a status of a battery. The signal reference source comprises a reference node and determines a signal reference at the reference node, and receives and is biased by the sensed signal at the same reference node to generate a trigger signal indicative of a difference between the sensed signal and the signal reference. The detecting unit is coupled to the signal reference source and generates an output signal according to the trigger signal to indicate an abnormal condition is present in the battery. | 2013-07-04 |
20130169283 | ACCURATE MEASUREMENT OF EXCESS CARRIER LIFETIME USING CARRIER DECAY METHOD - A method is described for accurate measuring of the excess carrier lifetime on a semiconductor sample from the carrier decay after termination of the excitation pulse imposed on the steady-state carrier excitation. The method includes determining a quality of decay parameter using progressing segments in each carrier decay; establishing an accurate lifetime measurement multiparameter domain for experimental variables whereby the quality of decay parameter falls within prescribed limits from the ideal exponential decay value of QD=1; and determining an excess carrier lifetime for the semiconductor sample based on experimental measurement conditions within the domain and the quality of decay value within the predetermined range indicative of an accurate excess carrier lifetime measurement. | 2013-07-04 |
20130169284 | UTILITY GROUND DETECTION - In an embodiment, a missing utility ground detection circuit includes a pair of balanced resistors each connected to receive utility voltage from a different one of a pair of utility power lines, the balanced resistors being connected together at a summing node to be capable of summing the voltages from the pair of utility power lines. It includes an unbalance resistor connected to shunt voltage from one of the utility power lines. It has a summing amplifier with an input coupled to the summing node and to a reference voltage, and an input coupled to a second reference voltage. It has an averaging circuit connected at the output of the summing amplifier. A comparator is provided having an input connected to the averaging circuit an input connected to a threshold voltage. | 2013-07-04 |
20130169285 | LEAKAGE CURRENT SENSOR FOR SUSPENSION TYPE INSULATOR - A sensor apparatus for detecting leakage current in a suspension-type insulator of an electrical power system is disclosed. The sensor apparatus includes a housing having a leakage current sensor contained therein, a door pivotally connected to the housing and adapted to move between an open position where a grounded end fitting of the insulator is received by the sensor apparatus and a closed position, and a clamping mechanism connected to the housing. The leakage current sensor is adapted to detect a leakage current along the insulator. The clamping mechanism is adapted to clamp the sensor apparatus to the grounded end fitting of the insulator. | 2013-07-04 |
20130169286 | LEAKAGE CURRENT SENSOR FOR POST TYPE INSULATOR - A sensor apparatus for detecting leakage current in a post-type insulator of an electrical power system includes: a sensor unit having a housing, the sensor unit including: a sensor assembly operable to generate an analog signal proportional to a received leakage current; an electronics module operable to covert the analog signal to a digital value; and a communications system operable to wirelessly transmit the digital value to an external receiver; a collection band adapted to be connected to an exterior surface of the insulator; and a transfer lead interconnecting the sensor assembly and the collection band, the transfer lead operable to transfer leakage current from the insulator from the collection band to the sensor assembly. | 2013-07-04 |
20130169287 | METHOD AND DEVICE FOR DETERMINING THE STATE OF AN ELECTRICALLY CONTROLLED VALVE - The invention relates to a method ( | 2013-07-04 |
20130169288 | APPARATUS AND METHOD FOR DETECTING FAILURE OF SWITCHING DEVICE IN INVERTER - Disclosed is an apparatus and method for detecting failure of a switching device in an inverter, the method including detecting a maximum value and a minimum value of a phase current inputted into a motor from synchronous angle information of the motor through a switching device in a predetermined leg of the inverter unit, and detecting failure of the switching device of the leg through an asymmetry ratio of the phase current. | 2013-07-04 |
20130169289 | METHOD AND APPARATUS FOR TESTING IN FIELD WIND TURBINES - A method for testing in field a wind turbine. The wind turbine being configured for providing power at a given rated voltage and at a rated frequency of 50 or 60 Hz; the method comprising connecting the wind turbine to an electric grid of a given rated voltage and of a rated frequency of 50 or 60 Hz through a conversion device that allows the adaptation of the features of the electric grid at the wind turbine side of said conversion device to the conditions requested by the tests to be performed to the wind turbine; that adaptation including the adaptation of the rated frequency of the electric grid to the rated frequency of the wind turbine, when they are different, so that identical tests to wind turbines configured for different rated frequencies can be performed in the same site. | 2013-07-04 |
20130169290 | APPARATUS AND METHOD TO DETECT A SERIES ARC FAULT OF AN ELECTRICAL CIRCUIT - An apparatus is for a power circuit providing an alternating current to a load. The apparatus includes a high frequency current sensor structured to cooperate with the power circuit to provide a high frequency current signal. A voltage zero crossing detector is structured to cooperate with the power circuit to provide a voltage zero crossing signal. A high pass filter is structured to provide a filtered current signal from the high frequency current signal. A threshold comparator is structured to provide an output when the filtered current signal exceeds a predetermined value. A processor is structured to receive the voltage zero crossing signal and the output of the threshold comparator and output a trip signal in response to undesired series arcing by detecting an unsymmetrical high frequency signal for a predetermined number of cycles. | 2013-07-04 |
20130169291 | Capacitive Measurement System with Increased Robustness Against Electro-magnetic Interference - A method for capacitive sensing comprises the steps of tagging a transmitting signal by modulating a sub-carrier on said signal using state of the art modulation techniques; demodulating said subcarrier out of useful/received signal to prove validity of said signal. | 2013-07-04 |
20130169292 | METHOD OF ANALYZING COUPLING EFFECT BETWEEN SIGNAL LINES IN AN INTEGRATED CIRCUIT - second signal lines are selected among neighboring signal lines near a first signal line, such that the second signal lines have valid coupling capacitances with respect to the first signal line. Test signal patterns of the first signal line and the second signal lines are selected among real signal patterns according to a function of the integrated circuit. At least one of a coupling noise and a coupling transition delay of the first signal line is calculated based on the test signal patterns. | 2013-07-04 |
20130169293 | Carbon Nanotube High Temperature Length Sensor - A sensor assembly includes a carbon nanotube bundle and a controller. The carbon nanotube bundle is integrated into a host material and extends along a predetermined dimension of the host material. The controller is configured to control transmission of radio frequency energy through the carbon nanotube bundle to determine a round trip time between transmission and reception of the radio frequency energy at a proximal end of the carbon nanotube bundle responsive to reflection of the radio frequency energy at a distal end of the carbon nanotube bundle. | 2013-07-04 |
20130169294 | DEVICES AND METHODS HAVING CAPACITANCE SENSE STRUCTURE FORMED OVER HOUSING SURFACE - A capacitance sensing system can include at least a first conductive pattern formed on a first surface of a housing of an electronic device; and a capacitance sensing circuit electrically connected to the first conductive pattern. | 2013-07-04 |
20130169295 | LEAKAGE CURRENT COMPENSATION CIRCUIT - Circuitry is described for compensating leakage currents in capacitive sensing circuits. A single active leakage compensation circuit may sense a representative leakage current and drive a plurality of output transistors, each of which provides a compensating current to a respective capacitive sensing circuit. The leakage compensation circuit may sense current flow through a device substantially equivalent to a device exhibiting leakage current in a capacitive sensing circuit, and in response, provide a signal to drive one or more output transistors to supply approximately equivalent currents to a plurality of circuit nodes. For embodiments having multiple similar capacitive sensors and capacitive sensing circuits, only one transistor need be added to each capacitive sensing circuit to compensate for leakage current. | 2013-07-04 |
20130169296 | IMPEDANCE ANALYZER - An impedance analyzer includes: a control voltage generating unit for generating a control voltage that has a predetermined amplitude value; a measuring unit operable to provide an output current, which has an amplitude value corresponding to that of the control voltage, for flowing through first and second body portions of a biological target, and to generate a measurement voltage that has an amplitude value corresponding to a difference between voltages at the first and second body portions attributed to flow of the output current therethrough; and a calculating module operable to determine an electrical impedance between the first and second body portions according to a predetermined adjustment value and the amplitude value of the measurement voltage. | 2013-07-04 |
20130169297 | METHOD FOR MEASURING AN ELECTRICAL CURRENT AND APPARATUS FOR THIS PURPOSE - A method for measuring an electrical current with the aid of a field effect transistor inserted into a current path and an apparatus for implementing the method. A control voltage is applied between the gate and source of the transistor in such a way that the voltage drop between the drain and source at the transistor in the current path remains within a specifiable range. The voltage drop and the control voltage are determined. With these two values, and with a known relationship between the drain-source current, the drain-source voltage and the gate-source voltage the value of the current of interest can now be determined. | 2013-07-04 |
20130169298 | TRANSFORMER WINDING RESISTANCE TESTER TEST PROBE AND METHOD - A test probe has a probe portion, a current source lead attachment portion and a voltage sense lead attachment portion. The test probe includes two conductive halves secured together with an electrically insulating material disposed between the halves electrically insulating them from each other. Each half has an âLâ shape including a probe portion and a test lead attachment portion extending perpendicularly outwardly from the probe portion, and provides the test probe with an overall âTâ shape. The conductive halves can be made of copper-beryllium. Methods of providing and using the test probe can include uncoupling a male coupling member of a power cable connector of a loadbreak bushing assembly from a female coupling member of the loadbreak bushing and inserting the rod-shaped probe portion into the female coupling member. | 2013-07-04 |
20130169299 | POSITIONING DEVICE FOR TESTING RESISTANCE OF CAMERA MODULE - A positioning device includes a positioning mechanism, a contacting mechanism located in the positioning mechanism, and a connecting mechanism located adjacent to an end of the positioning mechanism. The positioning mechanism includes a receiving member, a positioning member received in the receiving member, and a cover rotatable connected to the receiving member. The receiving member defines two sliding grooves. The cover defines two driving grooves corresponding to the two sliding grooves, each of the two driving grooves forms a driving surface, and the sliding block includes a slanted surface corresponding to the driving surface. When the cover is rotated to cover the receiving member, the driving surface resists with the slanted surface to drive the sliding block to move towards the positioning groove until the first contacting member contacts one testing point of the camera module. | 2013-07-04 |
20130169300 | MULTI-CHIP PROBER, CONTACT POSITION CORRECTION METHOD THEREOF, AND READABLE RECORDING MEDIUM - Three axial coordinate positions and the rotational position of electrode pads of chips to be inspected on a moving platform are controlled in such a manner that the electrode pads will correspond to the tip position of a plurality of probes, a large number of probes of a probe card, and electrode pads of a large number of chips, whose positional accuracy after being cut is uneven, can be positioned with accuracy, thus largely increasing the number of chips for simultaneous contact, and thus increasing the efficiency for the test. | 2013-07-04 |
20130169301 | Probes With Programmable Motion - The elongated body of an electrically conductive contact probe can be disposed in a guide hole and can include a patterned region for engaging and riding on a contact region of an inner sidewall of the guide hole as the elongated body moves in the guide hole in response to a force on a tip of the probe. As the patterned region rides the contact region, the tip moves in a lateral pattern that is a function of the surface(s) of the patterned region. | 2013-07-04 |
20130169302 | SYSTEM AND ADAPTER FOR TESTING PACKAGED INTEGRATED CIRCUIT CHIPS - High precision connectivity for a device under test (DUT) in an electronic test system at reduced cost and superior performance characteristics is provided by incorporating an appropriate contact structure into a printed circuit board (PCB) of the electronic test system. Alternatively, a superior adapter that is formed on the basis of highly precise volume production techniques, for example using well-established semiconductor materials and related manufacturing techniques, is provided to support high precision connectivity. | 2013-07-04 |
20130169303 | ELECTRONIC DEVICE TESTING APPARATUS - There is provided an electronic device testing apparatus which can effectively use a space in an electronic device handling apparatus since a preciser is not necessary. | 2013-07-04 |
20130169304 | PITCH CHANGING APPARATUS, ELECTRONIC DEVICE HANDLING APPARATUS, AND ELECTRONIC DEVICE TESTING APPARATUS - There is provided a pitch changing apparatus which can change a pitch of DUTs when the DUTs are transferred between trays by a shuttle revolving system. | 2013-07-04 |
20130169305 | WIRING BOARD AND PROBE CARD USING THE SAME - A wiring board | 2013-07-04 |
20130169306 | Light Source Evaluation Device and Solar Cell Evaluation Device - With a light source evaluation device | 2013-07-04 |
20130169307 | CONTACT RESISTANCE TEST STRUCTURE AND METHOD SUITABLE FOR THREE-DIMENSIONAL INTEGRATED CIRCUITS - A contact resistance test structure, a method for fabricating the contact resistance test structure and a method for measuring a contact resistance while using the contact resistance test structure are all predicated upon two parallel conductor lines (or multiples thereof) that are contacted by one perpendicular conductor line absent a via interposed there between. The test structure and related methods are applicable within the context of three-dimensional integrated circuits. | 2013-07-04 |
20130169308 | LCR TEST CIRCUIT STRUCTURE FOR DETECTING METAL GATE DEFECT CONDITIONS - A test structure for an integrated circuit device includes a series inductor, capacitor, resistor (LCR) circuit having one or more inductor elements, with each inductor element having at least one unit comprising a first segment formed in a first metal layer, a second segment connecting the first metal layer to a semiconductor substrate beneath the first metal layer, and a third segment formed in the semiconductor substrate; and a capacitor element connected in series with each inductor element, the capacitor element defined by a transistor gate structure including a gate electrode as a first electrode, a gate dielectric layer, and the semiconductor substrate as a second electrode. | 2013-07-04 |
20130169309 | METHOD OF DETECTING INSTABILITY IN ISLANDED ELECTRICAL SYSTEMS - Systems and methods for evaluating the stability of an islanded electrical system (off-grid) using high-speed frequency measurements of the electrical signal supplied by an alternate power source in the islanded electrical system. Additional inputs may include status signals from an automatic transfer switch, a generator, and loads within the islanded electrical system. The high-speed frequency measurements have a resolution sufficient to enable analysis of any combination of the frequency magnitude (e.g., sudden increase), frequency slew rate (e.g., frequency rate of change), frequency rate of recovery (e.g., frequency recovery time), or frequency oscillations (e.g., frequency ringing around the nominal value before settling) to indicate the presence of an actual or impending instability of the islanded electrical system. The frequency referred to herein corresponds to the frequency at which an alternating current supplied by the alternate power source is cycling. | 2013-07-04 |
20130169310 | TESTING CIRCUIT FOR DC-DC CONVERTER - Provided is a testing circuit capable of testing functionality of various DC-DC converters without an inductor. According to the present invention, various electronic elements forming the testing circuit for a DC-DC converter are converted in the same kinds of elements or different elements in one-to-one or one-to-two or more correspondence to electronic elements forming a typical DC-DC converter. When the conversion is performed, the electronic values of the elements may be properly scaled to test the DC-DC converter without consuming high power. Therefore, various problems of the related art are minimized. | 2013-07-04 |
20130169311 | ADAPTIVE BUFFER - An embodiment of a buffer for a transmission line, a circuit including such a buffer, a high-speed data link, and a low-voltage differential signaling (LVDS) system. | 2013-07-04 |
20130169312 | SYSTEM AND METHOD FOR REDUCING INPUT CURRENT SPIKE FOR DRIVE CIRCUITRY - A circuit includes a plurality of logic gates and a drive circuit. The plurality of logic gates are coupled between a first supply node and a second supply node. Each logic gate has at least one input and consumes a short circuit current during a logic state transition. The drive circuit is coupled to the inputs of the plurality of logic gates to deliver a copy of an input signal to each logic gate, wherein the input signal copies arrive at the inputs of the logic gates at substantially different times. The circuit may be incorporated in a touch screen panel and a display. | 2013-07-04 |
20130169313 | HIGH-SPEED FREQUENCY DIVIDER ARCHITECTURE - A high speed clock frequency divider circuit is provided that uses a first shift register loop-back circuit and a second shift-register loop-back circuit to shift a predetermined array of bits therethrough. The first shift register loop-back circuit is clocked on a rising clock edge of an input clock signal, while the second shift register loop-back signal is clocked on a negative edge of the input clock signal. The outputs of the first and second loop-back shift registers are ORed to provide a 50% duty cycle output clock signal. | 2013-07-04 |
20130169314 | METHODS AND CIRCUITS FOR ADJUSTING PARAMETERS OF A TRANSCEIVER - Methods and circuits for analyzing a signal and adjusting parameters of an equalizer for a signal. The signal is received at a receiver over a channel wherein the signal has a wave form. The signal is equalized at an equalizer using an adjustable parameter for the equalization. Data points from the signal are sampled between upper and lower limits of a threshold at an error sampler. A performance metric of the signal is computed based on a statistical density of the data points from the signal between the upper and lower limits of the threshold. | 2013-07-04 |
20130169315 | METHOD FOR ENCODER FREQUENCY-SHIFT COMPENSATION - A method for encoder frequency-shift compensation includes determining frequency values of an input encoder signal, determining repeatable frequency-shifts of the frequency values and generating a frequency-shift compensated clock using the repeatable frequency-shifts. A frequency-shift compensated clock includes a synthesizer configured to generate a frequency-shift compensated clock signal using repeatable frequency shifts and encoder clock signals. | 2013-07-04 |
20130169316 | TRI-STATE CONTROL FOR A LINE DRIVER - A tri-state control mechanism can be implemented for a line driver of a transmitter unit to switch the output impedance of the transmitter unit between a low impedance state in the transmit mode and a high impedance state in the receive mode while minimizing turn-off glitch. It may be determined whether a communication device comprising the transmitter unit is configured in a transmit operating mode or a receive operating mode. If the communication device is configured in the receive operating mode, a first bias voltage can be generated to bias output transistors of the line driver circuit in a sub-threshold state. If the communication device is configured in the transmit operating mode, a second bias voltage can be generated to bias output transistors of the line driver circuit in a saturation state. | 2013-07-04 |
20130169317 | OUTPUT DRIVER - An output driver includes, inter alia: a code generation unit disposed between a first node and a second node and configured to generate pull-up codes, according to a voltage difference between the first node and an output node, pull-down codes, according to a voltage difference between the output node and the second node, and a driving unit configured to drive the output node in response to a pull-up signal and a pull-down signal to generate output data, wherein a voltage level of the output data is controlled by a driving force which is set according to a combination of the pull-up and pull-down codes. | 2013-07-04 |
20130169318 | GATE-STRESS TEST CIRCUIT WITHOUT TEST PAD - A high side driver circuit includes a driver stage having an input, an output, a first power terminal and a second power terminal, a transistor having a first power terminal, a second power terminal, and a control terminal coupled to the output of the driver stage, and a switch coupled between the second power terminal of the driver stage and the second power terminal of the transistor. | 2013-07-04 |
20130169319 | SIGNAL PROCESSING CIRCUIT, DRIVER CIRCUIT, AND DISPLAY DEVICE - A signal processing circuit of the present invention includes: a first input terminal; a second input terminal; a third input terminal; a first node; a second node; an output terminal; a resistor; a first signal generating section which (i) is connected to the first node, a third input terminal, and the output terminal and (ii) includes a bootstrap capacitor; and a second signal generating section which is connected to the second node, a first power supply, and the output terminal. The first node becomes active in a case where the first input terminal becomes active. The second node becomes active in a case where the second input terminal becomes active. The output terminal is connected to the first power supply via the resistor. With the configuration, it is possible to have an improvement in operational stability of the signal processing circuit. | 2013-07-04 |
20130169320 | GATE DRIVER WITH DIGITAL GROUND - Various exemplary embodiments relate to gate driver circuitry that compensate for parasitic inductances. Input buffers in the gate driver are grounded to an exposed die pad. Grounding may involve either a downbond or conductive glue. | 2013-07-04 |
20130169321 | INTEGRATED CIRCUIT (IC), ADAPTIVE POWER SUPPLY USING IC CHARACTERISTICS AND ADAPTIVE POWER SUPPLY METHOD ACCORDING TO IC CHARACTERISTICS, ELECTRONIC DEVICE INCLUDING THE SAME AND MANUFACTURING METHOD OF IC - Embodiments disclose an integrated circuit (IC) including a power input unit, which receives power from an external power supply, a core, which is driven by the power input through the power input unit, and a controller, which determines characteristics of the core and controls the external power supply to supply the power according to the determined characteristics. | 2013-07-04 |
20130169322 | EFFICIENT REDUCTION OF ELECTROMAGNETIC EMISSION IN LIN DRIVER - A Local Interconnect Network (LIN) driver circuit employs a charging/discharging current applied to the gate of a driver transistor coupled to an LIN bus. The charging current includes a constant charging current and an additional soft charging current, whereas the discharging current includes a constant discharging current and an additional soft discharging current. As a result of the soft charge/discharge components, there is a significant reduction in electromagnetic emission on the LIN bus. | 2013-07-04 |
20130169323 | ADAPTIVE NON-POSITIVE INDUCTOR CURRENT DETECTOR (ANPICD) - Systems and methods are disclosed to detect current for an output load with an inductor. The system includes a high side power transistor a low side power transistor coupled to the high side power transistor; and a controller coupled to the high and low side power transistors. | 2013-07-04 |
20130169324 | FULLY INTEGRATED CIRCUIT FOR GENERATING A RAMP SIGNAL - A fully integrated ramp generator circuit includes a first current generator that sources current to first capacitor through a first transistor that is gate controlled by the complement of a periodic signal. The ramping voltage stored on the first capacitor is buffered to an output node as a ramp output signal. A second transistor couples the output node to the first current generator and is gate controlled by the periodic signal. The periodic signal is generated at the output of a flip-flop that receives an input clock signal and reset signal. The reset signal is generated by a comparator circuit operable to compare the voltage on a second capacitor to a reference. The second capacitor is charged by a second current source and discharged by a third transistor that is gate controlled by the periodic signal. | 2013-07-04 |
20130169325 | SYSTEMS AND METHODS OF SIGNAL SYNCHRONIZATION FOR DRIVING LIGHT EMITTING DIODES - System and method for signal synchronization. The system includes a first selection component, a first signal generator, a second signal generator and a first gate drive component. The first selection component is configured to receive a first mode signal and generate a first selection signal based on at least information associated with the first mode signal. The first signal generator is configured to, if the first selection signal satisfies one or more first conditions, receive a first input signal and generate at least a first clock signal based on at least information associated with the first input signal. Furthermore, the first gate drive component is configured to, if the first selection signal satisfies the one or more first conditions, receive at least the first clock signal and output a first drive signal to a first switch. | 2013-07-04 |
20130169326 | GATED VOLTAGE-CONTROLLED OSCILLATOR AND CLOCK AND DATA RECOVERY CIRCUIT - A gated voltage-controlled oscillator receives a gating signal and outputs an oscillating signal having a frequency corresponding to the gating signal. The gated voltage-controlled oscillator includes a delay unit, having a first terminal and a second terminal, and a multiplexer, having a first input terminal, a second input terminal, a select terminal and an output terminal. The first input terminal and the select terminal are coupled to the gating signal. The second input terminal is coupled to the first terminal of the delay unit. The output terminal outputs the oscillating signal and is coupled to the second terminal of the delay unit. The delay unit delays the oscillating signal and outputs the delayed oscillating signal into the second input terminal. The multiplexer outputs a signal of the first input terminal or the second input terminal according to the gating signal. | 2013-07-04 |
20130169327 | Charge-to-Digital Timer - The charge-to-digital timer apparatus and method disclosed herein estimates the elapsed time between two signals, e.g., a start signal and a stop signal. To that end, at least a capacitive load is charged with a known current to generate a load voltage. Subsequently, a first voltage is ramped in a plurality of discrete voltage steps associated with a plurality of known capacitances until the ramped voltage satisfies a predetermined criterion relative to a second voltage. The elapsed time is determined from the discrete voltage steps, one of the first and second voltages, the known current, and the known capacitive load. | 2013-07-04 |
20130169328 | CDR CIRCUIT, RECEPTION CIRCUIT, AND ELECTRONIC DEVICE - An apparatus includes an integration circuit that integrates values of one of a data center and a data edge of input data, based on clock signals, a sampling circuit that samples another at the data center and a data edge of the input data, based on clock signals, a first determination circuit that determines a data value of an integration value of the integration circuit, a second determination circuit that determines a data value of a sampling value of the sampling circuit, a phase detection circuit that detects phase information of the input data, based on a data value determined by the first determination circuit and the second determination circuit, and a phase adjusting circuit that adjusts a phase of a reference clock so as to track a phase of the input data, in accordance with the phase information, so as to output as the clock signals. | 2013-07-04 |
20130169329 | METHOD FOR LOCKING A DELAY LOCKED LOOP - A method and apparatus for synchronizing a delay line to a reference clock includes a delay line that receives a clock input signal based on a reference clock and outputs a delay edge signal according to a control adjustment. An injector receives a first rise edge of the reference clock and in response to a first trigger, sends the clock input signal to the delay line. A synchronizer determines that the rise edge has passed through the delay line, and in response, sends the injector a second trigger to send a next single fall edge of the clock input signal to the delay line. A charge pump determines a timing difference between the delay edge signal and a reference edge signal sent from the injector. The charge pump sends the control signal to the delay line to adjust the delay setting of the delay line based on the timing difference. | 2013-07-04 |
20130169330 | DUTY CYCLE CONTROLLING CIRCUIT, DUTY CYCLE ADJUSTING CELL, AND DUTYCYCLE DETECTING CIRCUIT - A duty cycle controlling circuit for adjusting duty cycle of a target clock signal to a desired value, comprises: a first duty cycle adjusting cell, for receiving a first duty cycle control signal to adjust duty cycle of an input clock signal to generate a first output clock signal as the target clock signal; and a duty cycle detecting module, for generating the first duty cycle control signal according to the first output clock signal. | 2013-07-04 |
20130169331 | APPARATUS - An embodiment of a circuit includes a data latch and a plurality of cascaded latches, wherein a first of the plurality of cascaded latches is configured to receive a first signal from the data latch and each subsequent cascaded latch is configured to receive a data output signal of a preceding cascaded latch, and an error-detection circuit configured to receive the respective data output signals and detect error in operation of the cascaded latches based thereon. | 2013-07-04 |
20130169332 | Family of Multiplexer/Flip-Flops with Enhanced Testability - A multibit combined multiplexer and flip-flop circuit has a plurality of bit circuits. Each bit circuit includes and input section, a flip-flop section and a per bit control section. The input sections have inputs for plural of input signals and corresponding input pass gates. The outputs of the input pass gates are connected to the input of the flip-flop section. Each per bit control section includes an inverter for each input terminal. There is a combined control section receiving a clock signal and a control signals for selection of only one of the input signals. The combined control section include a logical AND for each input signal combining the clock signal and the selection signal. The output of each logical AND is connected to the input of a corresponding inverter of each per bit control circuit. The input pass gate are controlled by a corresponding logical AND and said corresponding inverter. | 2013-07-04 |
20130169333 | FRONT-END MODULE HAVING LOW INSERTION LOSS - One object is to provide a front-end module with a shared output terminal wherein an input impedance is readily matched and an insertion loss is suppressed. In accordance with one aspect, the front-end module | 2013-07-04 |
20130169334 | INTERPOLATION CIRCUIT AND INTERPOLATION SYSTEM - An interpolation circuit, includes a bias generating module, a load module consisting of a current source sub-module and a load resistance sub-module, first and second clock control modules, and an output module. The first clock control module includes a first input sub-module, a first source terminal negative feedback sub-module, a first multiplex switch sub-module and a first multiplex current sink sub-module. The bias generating module includes first, second and third FETs, and a bias current terminal. The current source sub-module includes fourth and fifth FETs. The load resistance sub-module includes first and second resistors. The first input sub-module includes sixth and seventh FETs. The first source terminal negative feedback sub-module includes a third resistor and a first capacitor. The first multiplex switch sub-module includes first and second groups of switches. The first multiplex current sink sub-module includes first and second groups of FETs. An interpolation system is further provided. | 2013-07-04 |
20130169335 | DELAY LINES, METHODS FOR DELAYING A SIGNAL, AND DELAY LOCK LOOPS - Locked loops, delay lines, delay circuits, and methods for delaying signals are disclosed. An example delay circuit includes a delay line including a plurality of delay stages, each delay stage having an input and further having a single inverting delay device, and also includes a two-phase exit tree coupled to the delay line and configured to provide first and second output clock signals responsive to clock signals from inputs of the delay stages of the plurality of delay stages. Another example delay circuit includes a delay line configured to provide a plurality of delayed clock signals, each of the delayed clock signals having a delay relative to a previous delayed clock signal equal to a delay of a single inverting delay device. The example delay circuit also includes a two-phase exit tree configured to provide first and second output clock signals responsive to the delayed clock signals. | 2013-07-04 |
20130169336 | ELECTRONIC DEVICE - When operational clocks are output to a plurality of connecting sections, magnetic waves caused by the rising and falling of each clock have a large effect on the surrounding area. Therefore, provided is an electronic device comprising a plurality of connecting sections that are respectively connected to a plurality of external devices having the same frequencies for operational clocks used to communicate signals; and a clock output section that outputs, respectively to the connecting sections, operational clocks that are phase-shifted relative to each other. The clock output section outputs operational clocks with inverse phases to two of the connecting sections. | 2013-07-04 |
20130169337 | PHASE DIFFERENCE QUANTIZATION CIRCUIT, DELAY VALUE CONTROL CIRCUIT THEREOF, AND DELAY CIRCUIT - A delay value control circuit of a phase difference quantization circuit, wherein the phase difference quantization circuit has first to N | 2013-07-04 |
20130169338 | CLOCK GENERATOR AND METHOD OF GENERATING CLOCK SIGNAL - A clock generator utilized for providing a clock signal includes: a first oscillator and a switching circuit. The switching circuit is coupled to the first oscillator and a second oscillator, and utilized for receiving a first oscillating signal generated from the first oscillator and a second oscillating signal generated from the second oscillator, and selecting one of the first oscillating signal and the second oscillating signal as the clock signal according to a status signal. | 2013-07-04 |
20130169339 | LEVEL SHIFTING CIRCUIT AND SEMICONDUCTOR DEVICE USING THE SAME - A level shifting circuit includes a first circuit, a second circuit and an output voltage controlling circuit. The first circuit is coupled to an input node, an output node and a first supply voltage node and configured to pull an output voltage at the output node toward the first supply voltage in accordance with an input voltage applied to the input node. The second circuit is coupled to the first circuit, the output node and the second supply voltage node and configured to pull the output voltage toward the second supply voltage in accordance with the input voltage from the first circuit. The output voltage controlling circuit is coupled to the output node and configured to control the output voltage within a range narrower than a range from the first voltage to the second voltage. | 2013-07-04 |
20130169340 | CAPACITIVE TOUCH SENSOR INTERFACE - A technique includes charging and discharging a capacitive sensor of a display. The technique includes regulating currents that are associated with the charging and discharging based at least in part on a reference time interval and determining a capacitance sensed by the capacitive sensor based at least in part on the regulating. | 2013-07-04 |
20130169341 | DETECTING RESPONSES OF MICRO-ELECTROMECHANICAL SYSTEM (MEMS) RESONATOR DEVICE - A system for detecting responses of a MEMS resonator device includes first and second signal sources, a signal divider and a frequency mixer. The first signal source provides a first signal and the second signal source provides a second signal that electrostatically drives the MEMS resonator device, causing mechanical vibration. The signal divider divides the first signal into a probe signal and a local oscillator (LO) signal, the probe signal being applied to the MEMS resonator device and reflected by a capacitance of the MEMS resonator device. A reflection coefficient is modulated onto the reflected probe signal at the mechanical resonance frequency by variations in the capacitance induced by the mechanical vibration of the MEMS resonator device. The frequency mixer mixes the reflected probe signal and the LO signal and outputs an intermediate frequency (IF) signal, which represents modulation of the reflection coefficient, providing an image of the mechanical vibration. | 2013-07-04 |
20130169342 | DEVICE AND METHOD FOR REMOVING HARMONIC COMPONENTS - An apparatus of a Harmonic Rejection Mixer (HRM) for removing a harmonic component and an operating method thereof are provided. The HRM includes a Local Oscillator (LO), at least one frequency converter, at least two mixers, at least one phase converter, and a combiner. The LO generates an LO signal. The at least one frequency converter multiplies the LO signal using different variables to provide the same to at least two mixers. The at least two mixers convert a frequency band of an input signal using the LO signal provided from the LO and the at least one frequency converter. The at least one phase converter controls a phase of an output signal of at least one other mixer excluding one of the at least two mixers. The combiner combines an output signal of the one mixer with an output signal of the at least one phase converter. | 2013-07-04 |
20130169343 | USING INTERRUPTED THROUGH-SILICON-VIAS IN INTEGRATED CIRCUITS ADAPTED FOR STACKING - In an integrated circuit (IC) adapted for use in a stack of interconnected ICs, interrupted through-silicon-vias (TSVs) are provided in addition to uninterrupted TSVs. The interrupted TSVs provide signal paths other than common parallel paths between the ICs of the stack. This permits IC identification schemes and other functionalities to be implemented using TSVs, without requiring angular rotation of alternate ICs of the stack. | 2013-07-04 |
20130169344 | CASCODE DRIVE CIRCUITRY - A drive circuit includes a switching transistor having a design maximum voltage V | 2013-07-04 |
20130169345 | ELECTRONIC RELAY, ELECTRONIC SYSTEM AND METHOD FOR SWITCHING A POWER CURRENT - The invention relates to an electronic relay with
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20130169346 | SWITCH CIRCUIT - A switch circuit includes: first, second, and third input-output terminals; a first switching element connected between the first and second input-output terminals; a second switching element connected between the third input-output terminal and a grounding point; a third switching element connected between the first and third input-output terminals; a fourth switching element connected between the second input-output terminal and the grounding point; a first control voltage applying terminal connected to control terminals of the first and second switching elements; a second control voltage applying terminal connected to control terminals of the third and fourth switching elements; first and second resistors connected between the control terminals of the first and second switching elements and the first control voltage applying terminal, respectively; and first and second diodes connected in parallel with the first and second resistors, respectively, and having cathodes connected to the first control voltage applying terminal. | 2013-07-04 |
20130169347 | Temperature Management Circuit, System on Chip Including the Same and Method of Managing Temperature - In managing temperature in a system on chip (SOC), a main temperature signal is generated using a main sensor, where the main temperature signal is a signal having a value corresponding to a main temperature of the SOC. Subsidiary temperature signals are generated using subsidiary sensors, where the subsidiary temperature signals are pulse signals having frequencies corresponding to subsidiary temperatures of subsidiary blocks in the SOC, respectively. An operation of the SOC is controlled based upon the main temperature signal and the subsidiary temperature signals. | 2013-07-04 |
20130169348 | SAR Control Using Capacitive Sensor and Transmission Duty Cycle Control in a Wireless Device - A wireless device for providing specific absorption rate (SAR) control comprising a wireless transmitter, a capacitance sensor, and a processor coupled to the wireless transmitter and the capacitance sensor, wherein the processor is configured to receive a first capacitance measurement from the capacitance sensor, estimate a relative proximity of a human body to the apparatus based on the measurement, determine a target transmission time for the wireless transmitter within a time period based on the estimate, and switch off the wireless transmitter for a portion of the time period if a transmission time of the wireless transmitter during the time period exceeds the target transmission time. | 2013-07-04 |
20130169349 | ANTI-FUSE CIRCUIT - An anti-fuse circuit includes: a first fuse unit including a first anti-fuse which is determined to be short-circuited if the first anti-fuse in a programmed state and determined not to be short-circuited if the first anti-fuse in a non-programmed state, and configured to generate an output signal according to a state of the anti-fuse and a restoration signal; and a second fuse unit including a second anti-fuse, and configured to activate the restoration signal when the second anti-fuse is in the programmed state in case where the first anti-fuse is in the programmed state. | 2013-07-04 |
20130169350 | SENSING SUPPLY VOLTAGE SWINGS WITHIN AN INTEGRATED CIRCUIT - An integrated circuit comprising a plurality of sensors configured to sense variations in supply voltage levels at points within the integrated circuit is disclosed. The plurality of sensors are distributed across the integrated circuit and have transistor devices such that process variations in the transistor devices within the sensors are such that a sensing result will have a random voltage offset that has a predetermined probability of lying within a pre-defined voltage offset range. The integrated circuit is configured to transmit results from multiple ones of the plurality of sensors to processing circuitry such that the variations in the supply voltage levels can be determined with a voltage offset range that is reduced compared to the pre-defined voltage offset range. | 2013-07-04 |
20130169351 | TRANSISTOR OPERATING METHOD - A transistor operating method is applicable to a transistor including a first gate, a first gate insulating layer, a semiconductor layer, a source, a drain, a second gate insulating layer and a second gate. The transistor operating method includes: grounding the first gate and the source, applying a negative bias to the second gate and applying a positive bias to the drain, so that the transistor acts as an optical detector; alternatively, grounding the source, grounding or floating the second gate, applying a bias to the first gate and applying a positive bias to the drain, so that the transistor acts as a pixel switch. | 2013-07-04 |
20130169352 | BOOSTING CIRCUIT OF CHARGE PUMP TYPE AND BOOSTING METHOD - A boosting circuit includes an input terminal to which a power voltage is applied, a first capacitor connected to the input terminal, second and third capacitors, a first circuit including a first switch through which one end of the first capacitor is connected to one end of the second capacitor, and a second switch through which another end of the first capacitor is connected to another end of the second capacitor, a second circuit including a third switch through which the one end of the first capacitor is connected to the other end of the second capacitor, and a fourth switch through which the one end of the second capacitor is connected to one end of the third capacitor, the other end of the first capacitor being connected to another end of the third capacitor, and a fifth switch through which the one end of the first capacitor is connected to the one end of the third capacitor. | 2013-07-04 |
20130169353 | INTERNAL VOLTAGE GENERATION CIRCUIT - An internal voltage generation circuit includes a pumping voltage generation unit configured to generate a pumping voltage when a first internal voltage has a lower level than a first reference voltage or a second internal voltage has a lower level than a second reference voltage, and a select transmission unit configured to selectively transmit the pumping voltage as the first internal voltage or the second internal voltage. | 2013-07-04 |
20130169354 | INTERNAL VOLTAGE GENERATION CIRCUIT - An internal voltage generation circuit includes a comparison signal generation unit configured to compare an internal voltage with first and second reference voltages and generate first and second comparison signals; a transfer unit configured to transfer the first comparison signal as a pull-up signal in response to the second comparison signal, transfer the second comparison signal as a pull-down signal in response to the first comparison signal, transfer a power supply voltage as the pull-up signal when the second comparison signal is enabled and transfer a ground voltage as the pull-down signal when the first comparison signal is enabled; and a driving unit configured to drive a node in response to the pull-up signal and the pull-down signal and generate the internal voltage. | 2013-07-04 |
20130169355 | Integrated Circuit Device - An integrated circuit device includes: a first chip including a first substrate and a main circuit formed on said first chip; a second chip stacked on the first substrate and including a second substrate that is independent from the first substrate, and a protective circuit for protecting the main circuit; and a conductive channel unit extending from the protective circuit and electrically connected to the main circuit. | 2013-07-04 |
20130169356 | SWITCHING POWER AMPLIFIER AND METHOD OF CONTROLLING THE SAME - A switching power amplifier having a pulse width modulation (PWM) signal generation unit that converts an input audio signal into a PWM signal with a predetermined carrier frequency, a correction unit that corrects the difference between an audio signal included in the PWM signal and a negative feedback output audio signal to generate a corrected PWM signal, a low pass filter that removes a high-frequency component from the corrected PWM signal, a frequency modulation unit that modulates the corrected PWM signal so that the corrected PWM signal has a switching frequency different from the carrier frequency of the input PWM signal to generate a modulated PWM signal, and a power amplification unit that amplifies a power of the modulated PWM signal. | 2013-07-04 |
20130169357 | RF Power Amplifier Circuit With Mismatch Tolerance - A radio frequency (RF) power amplifier system adjusts the supply voltage provided to a power amplifier (PA) adaptively, responsive to the measured or estimated power of the RF output signal of the PA. The RF PA system includes a power amplifier (PA) which receives and amplifies an RF input signal to generate an RF output signal at a level suitable for transmission to an antenna. A PA supply voltage controller generates a supply voltage control signal, which is used to control the supply voltage to the final stage of the PA. The supply voltage control signal is generated responsive to the measured or estimated power of the PA RF output signal, and also may be responsive to a parameter indicative of impedance mismatch experienced at the PA output. By controlling this supply voltage to the RF PA, the efficiency of the PA is improved. | 2013-07-04 |
20130169358 | High Speed Power Supply System - A power supply system includes a high-speed power supply providing a first output, operating in conjunction with an externally supplied DC source or low frequency power supply which provides a second output. A frequency blocking power combiner circuit combines the first and second outputs to generate a third output in order to drive a load, while providing frequency-selective isolation between the first and second outputs. A feedback circuit coupled to the combined, third output compares this combined, third output with a predetermined control signal and generates a control signal for controlling the high-speed power supply, based on a difference between the third output and the predetermined control signal. The feedback circuit does not control the DC source or the low frequency power supply, but controls only the high-speed power supply. | 2013-07-04 |
20130169359 | Power Distortion-Based Servo Control Systems For Frequency Tuning RF Power Sources - A radio frequency system includes a power amplifier that outputs a radio frequency signal to a matching network via a transmission line between the power amplifier and the matching network. A sensor monitors the radio frequency signal and generates first sensor signals based on the radio frequency signal. A distortion module determines a first distortion value according to at least one of (i) a sinusoidal function of the first sensor signals and (ii) a cross-correlation function of the first sensor signals. A first correction circuit (i) generates a first impedance tuning value based on the first distortion value and a first predetermined value, and (ii) provides feedforward control of impedance matching performed within the matching network including outputting the first impedance tuning value to one of the power amplifier and the matching network. | 2013-07-04 |
20130169360 | APPARATUS - According to an embodiment, an apparatus includes: a first node configured to receive a data input signal of a data latch; a second node configured to receive a data output signal of the data latch; process and hold circuitry configured to process a difference between a value of the data input signal received at the first node and a value of the data output signal received at the second node and hold respective values at the first and second nodes responsive to the difference; and comparison circuitry configured to compare the value held at the first node and a value of the data output signal of the data latch; wherein the process and hold circuitry is configured to be biased toward the signal received at one of the first node and the second node. | 2013-07-04 |
20130169361 | Multi-Stage Fully Differential Amplifier with Controlled Common Mode Voltage - Disclosed are systems and methods to achieve a low noise, fully differential amplifier with controlled common mode voltages at each stage output but without the requirement of a common mode feedback loop. Common mode voltages are adjusted by adjusting the currents flowing through the load impedances (bias currents) wherein the currents are derived from one or more voltage-to-current converters based on an impedance that matches to the load impedances of the stages of the amplifier. The amplifier invented is primarily used for amplification of low frequency signals. The amplifier has one or more gain stages applying only one conduction type of transistors of an IC technology that has the lowest transition frequency between 1/f noise and white noise to achieve a low chopping or autozeroing frequency. | 2013-07-04 |
20130169362 | INPUT CLAMPING STRUCTURE FOR SOUND QUALITY IMPROVEMENT IN CAR-RADIO CLASS-AB POWER AMPLIFIER DESIGN - A clamping circuit for a class AB amplifier includes a reference voltage circuit, four NPN Darlington transistors having inputs coupled to the reference voltage circuit, and outputs for providing four clamped voltages, and a split NPN Darlington transistor having an input coupled to the reference voltage circuit, and four separate outputs for providing four AC ground voltages. | 2013-07-04 |
20130169363 | Body Biasing Device and Operational Amplifier thereof - A body biasing device for an amplifier which has a P-type differential pair and outputs an output signal at an output node according to a differential input signal pair is disclosed. The body biasing device includes a detection unit coupled to the operational amplifier for detecting a detected voltage related to the differential input signals and accordingly outputting a control signal; and a selection unit coupled to the detection unit and the operational amplifier for outputting a body bias to the P-type differential pair according to the control signal. | 2013-07-04 |
20130169364 | Amplifier and Transceiver Including the Amplifier - An amplifier and a transceiver including the amplifier are provided. The amplifier includes an input terminal; a first transistor of a first conductivity and a second transistor of a second conductivity, each transistor comprising a source terminal, a gate terminal and a drain terminal respectively, the source terminal of the first transistor being coupled to the source terminal of the second transistor, and the gate terminal of the first transistor and the gate terminal of the second transistor being coupled to the input terminal; and an output terminal coupled to the drain terminal of the first transistor and the drain terminal of the second transistor. | 2013-07-04 |
20130169365 | AUTOMATIC GAIN CONTROL FEEDBACK AMPLIFIER - Disclosed is an automatic gain control feedback amplifier that can arbitrarily control a gain even when a difference in input signal is large. The automatic gain control feedback amplifier includes: an amplification circuit unit configured to amplify voltage input from an input terminal and output the amplified voltage to an output terminal; a feedback circuit unit connected between the input terminal and the output terminal and including a feedback resistor unit of which a total resistance value is determined by one or more control signals and a feedback transistor connected to the feedback resistor unit in parallel; and a bias circuit unit configured to supply predetermined bias voltage to the feedback transistor. | 2013-07-04 |
20130169366 | DOHERTY AMPLIFIER AND SEMICONDUCTOR DEVICE - A Doherty amplifier includes a carrier amplifier including a first FET, the first FET having a plurality of gate electrodes, and a peaking amplifier including a second FET, the second FET having a plurality of gate electrodes, a gate-to-gate interval of the gate electrodes of the second FET being shorter than a gate-to-gate interval of the first FET. | 2013-07-04 |
20130169367 | ACTIVE CIRCULATOR - An active circulator for a microwave system. The microwave system includes at least one front-end arrangement. Each front-end arrangement includes a power amplifier function arranged to deliver an amplified output signal via a circulator function to an antenna in a transmit mode. A low noise amplifier function is arranged to amplify an input signal from the antenna via the circulator function in a receive mode. The circulator function is arranged to direct a signal flow between the transmit and receive modes. Each front-end arrangement includes one active circulator. The active circulator includes the power amplifier function, the low noise amplifier function and the circulator function of directing a signal flow. The functions integrated into one module. Also, a method to manufacture the active circulator. | 2013-07-04 |
20130169368 | Method and Apparatus of a Resonant Oscillator Separately Driving Two Independent Functions - Capacitive adjustment in an RCL resonant circuit is typically performed by adjusting a DC voltage being applied to one side of the capacitor. One side of the capacitor is usually connected to either the output node or the gate of a regenerative circuit in an RCL resonant circuit. The capacitance loading the resonant circuit becomes a function of the DC voltage and the AC sinusoidal signal generated by the resonant circuit. By capacitively coupling both nodes of the capacitor, a DC voltage can control the value of the capacitor over the full swing of the output waveform. In addition, instead of the RCL resonant circuit driving a single differential function loading the outputs, each output drives an independent single ended function; thereby providing two simultaneous operations being determined in place of the one differential function. | 2013-07-04 |
20130169369 | METHODS AND APPARATUS FOR SELF-TRIM CALIBRATION OF AN OSCILLATOR - In one general aspect, an apparatus can include a reference oscillator counter circuit configured to produce a reference oscillator count value based on a reference oscillator signal, and a target oscillator counter circuit configured to produce a target oscillator count value based on a target oscillator signal where the target oscillator signal has a frequency targeted for calibration against a frequency of the reference oscillator signal. The apparatus can include a difference circuit configured to calculate a difference between the reference oscillator counter value and the target oscillator counter value, and a summation circuit configured to define a trim code based on only a portion of bit values from the difference. | 2013-07-04 |
20130169370 | FREQUENCY JITTER CIRCUIT AND METHOD - An oscillator generates a clock signal according to a voltage, a current and a capacitance, and a frequency jitter circuit and method use a random number to modulate the voltage, the current or the capacitance, or a count value to modulate the capacitance, to jitter the frequency of the clock signal. | 2013-07-04 |
20130169371 | SPIN TRANSFER OSCILLATOR - A spin transfer oscillator including a magnetic stack including at least two magnetic layers, at least one of the two magnetic layers is an oscillating layer that has variable direction magnetization and a current supply device configured to cause the flow of a current of electrons perpendicularly to the plane of the magnetic stack. The magnetic stack includes a device to generate inhomogeneities of current at the level of the surface of the oscillating layer and the intensity of the current supplied by the supply device is selected such that the magnetization of the oscillating layer has a consistent magnetic configuration, the magnetic configuration oscillating as a whole at the same fundamental frequency. | 2013-07-04 |
20130169372 | PULSE GENERATOR AND SEMICONDUCTOR INTEGRATED CIRCUIT - A pulse generator includes an oscillation circuit that generates a burst signal oscillated for ultrawideband band and a generation circuit that generates a trigger signal that causes oscillation by the oscillation circuit to be started. | 2013-07-04 |
20130169373 | Method and Apparatus of Capacitively Coupling an Adjustable Capacitive Circuit in a VCO - Capacitive adjustment in an RCL resonant circuit is typically performed by adjusting a DC voltage being applied to one side of the capacitor. One side of the capacitor is usually connected to either the output node or the gate of a regenerative circuit in an RCL resonant circuit. The capacitance loading the resonant circuit becomes a function of the DC voltage and the AC sinusoidal signal generated by the resonant circuit. By capacitively coupling both nodes of the capacitor, a DC voltage can control the value of the capacitor over the full swing of the output waveform. In addition, instead of the RCL resonant circuit driving a single differential function loading the outputs, each output drives an independent single ended function; thereby providing two simultaneous operations being determined in place of the one differential function. | 2013-07-04 |
20130169374 | VOLTAGE CONTROLLED OSCILLATOR - Voltage controlled oscillators are disclosed. The voltage controlled oscillator includes an inductive circuit, a cross-coupled N-type transistor pair, and a cross-coupled P-type transistor pair. The inductive circuit includes two inductive windings stacked together, and is configured to generate a pair of differential resonance signals. The cross-coupled N-type transistor pair is coupled in series with the inductive circuit, and configured to receive the pair of differential resonance signals to generate a first oscillation signal. The cross-coupled P-type transistor pair is coupled in series with the inductive circuit, and configured to receive the pair of differential resonance signals to generate a second oscillation signal. The first oscillation signal and second oscillation signal include substantially the same frequency and are out-of-phase to each other. The first oscillation and second oscillation signal have substantially the same frequency which is twice that of the pair of the differential resonance signals. | 2013-07-04 |
20130169375 | BROADBAND BALUN - For broadband applications of a balun in a magnetic field, the balun includes at least three line transformers each having two transformer sides. At least two transformer sides of the balun that belong to different line transformers of the at least three line transformers are embodied for the same voltage drop at least in terms of magnitude. The at least two transformer sides of the balun are also embodied with an identical number of turns. Two transformer sides connected in parallel are replaced by a single coil, with the result that the balun may be produced from a five-wire structure. | 2013-07-04 |
20130169376 | DIFFERENTIAL MODE AMPLIFIER DRIVING CIRCUIT - There is provided a differential mode amplifier driving circuit, including: a first port having one end connected to a single signal; a second port having one end connected to a differential signal; a first transmission line having one end grounded; and a third port having one end connected to the first transmission line and the other end connected to the differential signal. | 2013-07-04 |
20130169377 | HIGH FREQUENCY SIGNAL COMBINER - A high-frequency signal combiner comprises at least one first bridge coupler ( | 2013-07-04 |
20130169378 | APPARATUS HAVING DOUBLE PHASE-MATCHED CONFIGURATION FOR REDUCING MAGNITUDE OF INTERMODULATION PRODUCTS - An apparatus includes: a first apparatus port receiving a first signal having a first frequency; a second apparatus port outputting the first signal having the first frequency; a first passive device connected between the first and second apparatus ports; a second passive device connected between the first and second apparatus ports; a plurality of phase shifters each providing a corresponding phase shift, wherein at least one of the phase shifters provides its phase shift in a first signal path between the first and second apparatus ports through the first passive device, and wherein at least another phase shifter provides its phase shift in a second signal path between the first and second apparatus ports through the second passive device. The phase shifts are selected to cancel an upper or lower intermodulation product between the first signal and a second signal having a second frequency received at the second apparatus port. | 2013-07-04 |
20130169379 | MICROSTRIP MANIFOLD COUPLED MULTIPLEXER - A multiplexer includes a microstrip manifold, and a filter bank having at least two output filters. The multiplexer channelizes an input radio frequency (RF) band of electromagnetic energy into a set of output channels by way of the filter bank. The microstrip manifold has an input port that receives an input RF signal, and at least two output ports. The microstrip manifold distributes the input RF signal to each output port, each said output port being coupled to a respective one of the at least two output filters. The multiplexer may be an input multiplexer for a spacecraft communications payload system. | 2013-07-04 |
20130169380 | NOISE FILTER AND TRANSMISSION DEVICE - A noise filter can reliably reject an in-phase component included in a differential signal without generating anti-resonance at a target frequency reject and, a transmission device including such a noise filter. | 2013-07-04 |
20130169381 | COMMON MODE FILTER AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a common mode filter and a method of manufacturing the same. In order to implement a common mode filter with low shrinkage, high substrate sintered density, and high strength, the present invention provides a common mode filter including: a lower substrate; an insulating layer having a conductor pattern inside and provided on the lower substrate; an upper substrate provided on the insulating layer; and a ferrite core made of ferrite and provided in the center of the insulating layer, the lower substrate, and the upper substrate by penetrating the insulating layer, the lower substrate, and the upper substrate, and a method of manufacturing the same. | 2013-07-04 |