| 27th week of 2013 patent applcation highlights part 16 |
| Patent application number | Title | Published |
|---|
| 20130168782 | MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) STRUCTURES AND DESIGN STRUCTURES - Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming at least one fixed electrode on a substrate. The method further includes forming a Micro-Electro-Mechanical System (MEMS) beam with a varying width dimension, as viewed from a top of the MEMS beam, over the at least one fixed electrode. | 2013-07-04 |
| 20130168783 | MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) CAPACITIVE OHMIC SWITCH AND DESIGN STRUCTURES - A micro-electro-mechanical system (MEMS), methods of forming the MEMS and design structures are provided. The method comprises forming a coplanar waveguide (CPW) comprising a signal electrode and a pair of electrodes on a substrate. The method comprises forming a first sacrificial material over the CPW, and a wiring layer over the first sacrificial material and above the CPW. The method comprises forming a second sacrificial material layer over the wiring layer, and forming insulator material about the first sacrificial material and the second sacrificial material. The method comprises forming at least one vent hole in the insulator material to expose portions of the second sacrificial material, and removing the first and second sacrificial material through the vent hole to form a cavity structure about the wiring layer and which exposes the signal line and pair of electrodes below the wiring layer. The vent hole is sealed with sealing material. | 2013-07-04 |
| 20130168784 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package includes: a chip having a first portion and a second portion disposed on the first portion, wherein the second portion has at least a through hole therein for exposing a portion of the first portion, and the first portion and/or the second portion has a MEMS; and an etch stop layer formed between the first portion and the second portion and partially exposed through the through hole of the second portion. The invention allows an electronic element to be received in the through hole so as for the semiconductor package to have integrated functions of the MEMS and the electronic element. Therefore, the need to dispose the electronic element on a circuit board as in the prior art can be eliminated, thereby saving space on the circuit board. | 2013-07-04 |
| 20130168785 | SENSOR AND METHOD OF MANUFACTURE THEREOF - A pressure sensor having a structure, which includes a supporting body, a circuit arrangement and at least one circuit support. The circuit arrangement includes circuit components, amongst which detection means for generating electrical signals representing a quantity to be detected. The at least one circuit support is connected to the supporting body and has a surface, formed on which is a plurality of said circuit components, amongst which electrically conductive paths, where the circuit support is laminated on the first face of the supporting body. | 2013-07-04 |
| 20130168786 | MAGNETIC SHIFT REGISTER WITH PINNING STRUCTURE - A magnetic shift register includes a first supporting layer, a second supporting layer, a first pinning material layer, and at least one magnetic memory track. The first supporting layer has trenches on a first surface extending along a first direction. The second supporting layer is filled in the trenches, wherein the first support layer and the second support layer have at least a portion substantially equal in height. The first pinning material layer is disposed between the first supporting layer and the second supporting layer, wherein a plurality of end surfaces of the first pinning material layer are exposed on the first surface. The magnetic memory track extending along a second direction on the first surface is disposed over the first support layer, the first pinning material layer, and the second support layer, wherein the second direction is not the same or perpendicular to the first direction. | 2013-07-04 |
| 20130168787 | MAGNETIC SENSOR - A magnetic sensor suitable for sensing an external magnetic field includes a magnetic tunnel junction (MTJ) device. The MTJ device is used to sense an out-of-plane (Z-axis) component of the external magnetic field at a perpendicular direction to the MTJ device. The MTJ device includes a first pinned magnetic layer, a tunnel layer and a magnetic sensing layer. The first pinned magnetic layer has a pinned magnetization perpendicular to the first pinned magnetic layer. The tunnel layer is disposed on the first pinned magnetic layer. The magnetic sensing layer is disposed on the tunnel layer. The magnetic sensing layer has a critical thickness to be at a superparamagnetic range, in which an out-of-plane (Z-axis) magnetic sensitivity is larger than an in-plane (X-axis, Y-axis) magnetic sensitivity. The first pinned magnetic layer, the tunnel layer and the magnetic sensing layer are stacked in a forward sequence or a reverse sequence. | 2013-07-04 |
| 20130168788 | TUNNELING MAGNETO-RESISTOR REFERENCE UNIT AND MAGNETIC FIELD SENSING CIRCUIT USING THE SAME - A tunneling magneto-resistor reference unit for sensing a magnetic field includes a first MTJ (magnetic tunneling junction) device and a second MTJ device connected in parallel. The first MTJ device has a first pinned layer having a first pinned magnetization at a pinned direction, and a first free layer having a first free magnetization parallel to the pinned direction in a zero magnetic field. The second MTJ device has a second pinned layer having a second pinned magnetization at the pinned direction, and a second free layer having a second free magnetization anti-parallel to the pinned direction in a zero magnetic field. Major axes of the first and second MTJ devices have an angle of 45 degrees to a direction of an external magnetic field when sensed. | 2013-07-04 |
| 20130168789 | LOCALIZED SURFACE PLASMON RESONANCE SENSOR USING CHALCOGENIDE MATERIALS AND METHOD FOR MANUFACTURING THE SAME - A localized surface plasmon resonance sensor may include a localized surface plasmon excitation layer including a chalcogenide material. The chalcogenide material may include: a first material including at least one of selenium (Se) and tellurium (Te); and a second material including at least one of germanium (Ge) and antimony (Sb). The localized surface plasmon excitation layer may be prepared by forming a thin film including the chalcogenide material and crystallizing the thin film to have a predetermined pattern by irradiating laser on the thin film. | 2013-07-04 |
| 20130168790 | ORGANIC PHOTOELECTRIC CONVERSION ELEMENT AND IMAGE ELEMENT - An organic photoelectric conversion element comprises: a pair of electrodes; an organic photoelectric conversion layer arranged between the pair of electrodes; and an positive hole blocking layer arranged between one of the pair of electrodes and the organic photoelectric conversion layer, wherein an ionization potential of the positive hole blocking layer is larger than a work function of the adjoining electrode by 1.3 eV or more, and wherein an electron affinity of the positive hole blocking layer is equal to or larger than that of the adjoining organic photoelectric conversion layer. An electron blocking layer may be arranged between the other one of the pair of electrodes and the organic photoelectric conversion layer, wherein its electron affinity is smaller than a work function of the adjoining electrode by 1.3 eV or more, and its ionization potential is equal to or smaller than that of the adjoining organic photoelectric conversion layer. | 2013-07-04 |
| 20130168791 | Quantum Efficiency Back Side Illuminated CMOS Image Sensor And Package, And Method Of Making Same - An image sensor device (and method of making same) that includes a substrate with front and back opposing surfaces, a plurality of photo detectors formed at the front surface, and a plurality of contact pads formed at the front surface which are electrically coupled to the photo detectors. A cavity is formed into the back surface. A plurality of secondary cavities are formed into a bottom surface of the cavity such that each secondary cavity is disposed over one of the photo detectors. Absorption compensation material having light absorption characteristics that differ from those of the substrate is disposed in the secondary cavities. A plurality of color filters are each disposed in the cavity or in one of the secondary cavities and over one of the photo detectors. The plurality of photo detectors are configured to produce electronic signals in response to light incident through the color filters. | 2013-07-04 |
| 20130168792 | Three Dimensional Architecture Semiconductor Devices and Associated Methods - Semiconductor devices having three dimensional (3D) architectures and methods form making such devices are provided. In one aspect, for example, a method for making a semiconductor device can include forming a device layer on a front side of a semiconductor layer that is substantially defect free, bonding a carrier substrate to the device layer, processing the semiconductor layer on a back side opposite the device layer to form a processed surface, and bonding a smart substrate to the processed surface. In some aspects, the method can also include removing the carrier substrate from the semiconductor layer to expose the device layer. | 2013-07-04 |
| 20130168793 | AVALANCHE PHOTODIODE - An APD is provided with the semi-insulating substrate, a first mesa having a first laminate constitution in which a p-type electrode layer, a p-type light absorbing layer, a light absorbing layer with a low impurity concentration, a band gap inclined layer, a p-type electric field control layer, an avalanche multiplier layer, an n-type electric field control layer, and an electron transit layer with a low impurity concentration are stacked in this order on a surface of the semi-insulating substrate, a second mesa having an outer circumference provided inside an outer circumference of the first mesa as viewed from the laminating direction and having a second laminate constitution in which an n-type electrode buffer layer and an n-type electrode layer are stacked in this order on a surface on the electron transit layer side, and a depletion control region that is provided in layers on the second mesa side relative to the p-type electric field control layer, formed in an encircling portion provided inside an outer circumference of the first mesa and encircling an outer circumference of the second mesa, and prevents the encircling portion of the p-type electric field control layer from being depleted when bias is applied. | 2013-07-04 |
| 20130168794 | Seamless Multi-Poly Structure and Methods of Making Same - A sensor array is integrated onto the same chip as core logic. The sensor array uses a first polysilicon and the core logic uses a second polysilicon. The first polysilicon is etched to provide a tapered profile edge in the interface between the sensor array and the core logic regions to avoid an excessive step. Amorphous carbon can be deposited over the interface region without formation of voids, thus providing for improved manufacturing yield and reliability. | 2013-07-04 |
| 20130168795 | Color Image Sensing - An apparatus including a plurality of sensor elements, configured in an arrangement having a repeating pattern of sensor elements, the plurality of sensor elements including first monochromatic sensor elements configured to sense visible light of a first color; second monochromatic sensor elements configured to sense visible light of a second color; and panchromatic sensor elements configured to sense visible light of at least the first color and the second color, wherein the majority of the plurality of sensor elements are panchromatic sensor elements. | 2013-07-04 |
| 20130168796 | PHOTODIODE ARRAYS AND METHODS OF FABRICATION - Photodiode arrays and methods of fabrication are provided. One photodiode array includes a silicon wafer having a first surface and an opposite second surface. The photodiode array also includes a plurality of refilled conductive vias through the silicon wafer, wherein the refilled conductive vias have a doping type different than the doping type of the substrate, and an interface between the refilled conductive vias and the substrate form diode junctions. The photodiode array further includes a patterned doped layer on the first surface overlapping the refilled conductive vias, wherein the patterned doped layer defines an array of photodiodes. | 2013-07-04 |
| 20130168797 | METHOD AND STRUCTURE FOR USING DISCONTINUOUS LASER SCRIBE LINES - A thin film photovoltaic device includes a substrate and a first conductive layer coupled to the substrate. The first conductive layer includes at least one first groove extending through a first portion of the first conductive layer to a portion of the substrate. The device also includes at least one semiconductor layer coupled to a remaining portion of the first conductive layer and the portion of the substrate. The at least one semiconductor layer includes a plurality of non-overlapping vias, each via extending through a portion of the at least one semiconductor layer to a portion of the first conductive layer. The device further includes a second conductive layer coupled to a remaining portion of the at least one semiconductor layer and portions of the first conductive layer. The second conductive layer includes at least one second groove extending through a portion of the second conductive layer to a portion of the at least one semiconductor layer. | 2013-07-04 |
| 20130168798 | CHIP PACKAGE STRUCTURE - A first back surface of a first chip faces toward a carrier. A first active surface of the first chip has first pads and a first insulting layer thereon. A second chip is disposed on the first chip and electrically connected to the carrier. A second active surface of the second chip faces toward the first active surface. The second active surface has second pads and a second insulting layer thereon. Bumps connect the first and second pads. First and second daisy chain circuits are respectively disposed on the first and second insulting layers. Hetero thermoelectric device pairs are disposed between the first and second chips and connected in series by the first and second daisy chain circuits, and constitute a circuit with an external device. First and second heat sinks are respectively disposed on a second surface of the carrier and a second back surface of the second chip. | 2013-07-04 |
| 20130168799 | SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films | 2013-07-04 |
| 20130168800 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device that includes first and second isolation patterns disposed on a substrate. Alternately stacked interlayer insulating patterns and a conductive patterns are disposed on a surface of the substrate between the first and second isolation patterns. A support pattern penetrates the conductive patterns and the interlayer insulating patterns and has a smaller width than the first and second isolation patterns. First and second vertical structures are disposed between the first isolation and the support pattern and penetrate the conductive patterns and the interlayer insulating patterns. A second vertical structure is disposed between the second isolation pattern and the support pattern and penetrates the conductive patterns and the interlayer insulating patterns. A distance between top and bottom surfaces of the support pattern is greater than a distance between a bottom surface of the support pattern and the surface of the substrate. | 2013-07-04 |
| 20130168801 | METHOD OF FORMING ISOLATION AREA AND STRUCTURE THEREOF - The instant disclosure relates to a method of forming an isolation area. The method includes the steps of: providing a substrate having a first type of ion dopants, where the substrate has a plurality of trenches formed on the cell areas and the isolation area between the cell areas of the substrate, with the side walls of the trenches having an oxidation layer formed thereon and the trenches are filled with a metallic structure; removing the metallic structure from the trenches of the isolation area; implanting a second type of ions into the substrate under the trenches of the isolation area; and filling all the trenches with an insulating structure, where the trenches of the isolation area are filled up fully by the insulating structure to form a non-metallic isolation area. | 2013-07-04 |
| 20130168802 | SOI STRUCTURES WITH REDUCED METAL CONTENT - Methods for producing silicon on insulator structures with a reduced metal content in the device layer thereof are disclosed. Silicon on insulator structures with a reduced metal content are also disclosed. | 2013-07-04 |
| 20130168803 | Semiconductor-On-Insulator Devices and Associated Methods - Semiconductor-on-insulator (SOI) devices and associated methods are provided. In one aspect, for example, a method for making a SOI device can include forming a device layer on a front side of a semiconductor layer, bonding a first substrate to the front side of the device layer, processing the semiconductor layer on a back side opposite the device layer to form a processed surface, and bonding a second substrate to the processed surface. In some aspects, the method can further include removing the first substrate from the front side to expose the device layer. In one aspect, forming the device layer can include forming optoelectronic circuitry at the front side of the semiconductor layer. | 2013-07-04 |
| 20130168804 | STRESS-GENERATING STRUCTURE FOR SEMICONDUCTOR-ON-INSULATOR DEVICES - A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region. | 2013-07-04 |
| 20130168805 | Packages with Passive Devices and Methods of Forming the Same - A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A Post-Passivation Interconnect (PPI) line is disposed over the passivation layer and electrically coupled to the metal pad. An Under-Bump Metallurgy (UBM) is disposed over and electrically coupled to the PPI line. A passive device includes a portion at a same level as the UBM. The portion of the passive device is formed of a same material as the UBM. | 2013-07-04 |
| 20130168806 | ELECTRICAL FUSE STRUCTURE AND METHOD OF FABRICATING SAME - A high programming efficiency electrical fuse is provided utilizing a dual damascene structure located atop a metal layer. The dual damascene structure includes a patterned dielectric material having a line opening located above and connected to an underlying via opening. The via opening is located atop and is connected to the metal layer. The dual damascene structure also includes a conductive feature within the line opening and the via opening. Dielectric spacers are also present within the line opening and the via opening. The dielectric spacers are present on vertical sidewalls of the patterned dielectric material and separate the conductive feature from the patterned dielectric material. The presence of the dielectric spacers within the line opening and the via opening reduces the area in which the conductive feature is formed. As such, a high programming efficiency electrical fuse is provided in which space is saved. | 2013-07-04 |
| 20130168807 | INTERCONNECT STRUCTURE CONTAINING VARIOUS CAPPING MATERIALS FOR ELECTRICAL FUSE AND OTHER RELATED APPLICATIONS, AND DESIGN STRUCTURE THEREOF - A structure and design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure. | 2013-07-04 |
| 20130168808 | MEMS POWER INDUCTOR WITH MAGNETIC LAMINATIONS FORMED IN A CRACK RESISTANT HIGH ASPECT RATIO STRUCTURE - Magnetic laminations are formed in the openings of a first non-conductive structure, which is formed in the opening of a second non-conductive structure that has a maximum aspect ratio that is less than the maximum aspect ratio of the first non-conductive structure. The second non-conductive structure is more crack resistant than the first non-conductive structure, and thereby protects the first non-conductive structure and the magnetic laminations from environmental contaminants. | 2013-07-04 |
| 20130168809 | STRUCTURE AND METHOD FOR A TRANSFORMER WITH MAGNETIC FEATURES - The present disclosure provides a semiconductor device. The semiconductor device includes a first inductor formed on a first substrate; a second inductor formed on a second substrate and conductively coupled with the first inductor as a transformer; and a plurality of micro-bump features configured between the first and second substrates. The plurality of micro-bump features include a magnetic material having a relative permeability substantially greater than one and are configured to enhance coupling between the first and second inductors. | 2013-07-04 |
| 20130168810 | INTEGRATED CIRCUITS INCLUDING INDUCTORS - An integrated circuit includes a substrate having a surface and an inductor disposed over the surface of the substrate. The inductor includes a first conductive line disposed over the surface and first conductive structures disposed over and electrically coupled with the first conductive line. The inductor includes second conductive structures disposed over and electrically coupled with the first conductive structures. The inductor includes a second conductive line disposed over and electrically coupled with the second conductive structures. The inductor includes third conductive structures disposed over and electrically coupled with the first conductive line and at least one fourth conductive structure disposed over and electrically coupled with the third conductive structures. The inductor includes a third conductive line disposed over and electrically coupled with the at least one fourth conductive structure, the third conductive line extending substantially parallel to the second conductive line. | 2013-07-04 |
| 20130168811 | CAPACITOR HAVING MULTI-LAYERED ELECTRODES - The instant disclosure relates to a capacitor having multi-layered electrodes. The capacitor includes a dielectric layer having a first surface and a second surface oppositely arranged, a first electrode formed on the first surface, and a second electrode formed on the second surface. At least one of the first and second electrodes having a low band gap material layer formed on the dielectric layer and a conducting layer formed on the low band gap material layer. The band gap of the low band gap material layer is lower than the band gap of the conducting layer. | 2013-07-04 |
| 20130168812 | MEMORY CAPACITOR HAVING A ROBUST MOAT AND MANUFACTURING METHOD THEREOF - A manufacturing method for memory capacitor having a robust moat, comprising the steps of: providing a substrate; forming a patterned sacrificial layer on the substrate having a moat to separate a cell area and a peripheral area; forming a supporting layer on the sacrificial layer and filling the moat to form a annular member, wherein the supporting layer and the sacrificial layer arranged in alignment to form a stack structure; forming a plurality row of capacitor trenches on the substrate, wherein the capacitor trenches are formed at intervals in the stack structure; and forming a conducting layer on the supporting layer and covering the substrate and the inner surface of the stack structure defining the capacitor trenches. | 2013-07-04 |
| 20130168813 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A semiconductor device includes a semiconductor substrate; a first insulating film that is formed over the semiconductor substrate; a capacitor that is formed over the first insulating film and is formed by sequentially stacking a lower electrode, a capacitor dielectric film, and an upper electrode; a second insulating film that is formed over the capacitor and has a hole including the entire region of the upper electrode in plan view; and a conductor plug that is formed in the hole and contains tungsten. | 2013-07-04 |
| 20130168814 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a semiconductor device and a method for manufacturing the same, a mesh shaped lower electrode of a peripheral region is used as a reservoir capacitor to increase the size of a region contacting a dielectric film, such that Cs deterioration is minimized. An exemplary semiconductor device may include a line-type storage node contact plug formed over a semiconductor substrate, a mesh shaped lower electrode formed over the storage node contact plug, and a dielectric film and an upper electrode formed over the lower electrode. | 2013-07-04 |
| 20130168815 | TEMPERATURE SWITCH WITH RESISTIVE SENSOR - The present disclosure is directed to a device and a method for forming a precision temperature sensor switch with a Wheatstone bridge configuration of four resistors and a comparator. When the temperature sensor detects a temperature above a threshold, the switch will change states. The four resistors in the Wheatstone bridge have the same resistance, with three of the resistors having a low temperature coefficient of resistance and the fourth resistor having a high temperature coefficient of resistance. As the temperature increases, the resistance of the fourth resistor will change. The change in resistance of the fourth resistor will change a voltage across the bridge. The voltage across the bridge is coupled to the comparator and compares the voltage with the threshold temperature, such that when the threshold temperature is exceeded, the comparator switches the output off. | 2013-07-04 |
| 20130168816 | RESISTOR AND FABRICATION METHOD THEREOF - The present invention provides a structure of a resistor comprising: a substrate having an interfacial layer thereon; a resistor trench formed in the interfacial layer; at least a work function metal layer covering the surface of the resistor trench; at least two metal bulks located at two ends of the resistor trench and adjacent to the work function metal layer; and a filler formed between the two metal bulks inside the resistor trench, wherein the metal bulks are direct in contact with the filler. | 2013-07-04 |
| 20130168817 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first insulating layer (interlayer insulating layer), a resistive element that is disposed over the first insulating layer (interlayer insulating layer) and at least a surface layer of which is a TaSiN layer, and an interlayer insulating layer disposed over the first insulating layer (interlayer insulating layer) and the resistive element. Multiple via plugs having ends coupled to the TaSiN layer are disposed in the interlayer insulating layer. | 2013-07-04 |
| 20130168818 | DESIGN STRUCTURE, STRUCTURE AND METHOD OF LATCH-UP IMMUNITY FOR HIGH AND LOW VOLTAGE INTEGRATED CIRCUITS - Design structures, structures and methods of manufacturing structures for providing latch-up immunity for mixed voltage integrated circuits. The structure includes a diffused N-Tub structure embedded in a P-wafer and provided below a retrograde N-well to a non-isolated CMOS logic. | 2013-07-04 |
| 20130168819 | Fin-like BJT - A bipolar junction transistor (BJT) formed using a fin field-effect transistor (FinFET) complimentary metal-oxide-semiconductor (CMOS) process flow is provided. The BJT includes an emitter fin, a base fin, and a collector fin formed on a substrate. The base fin encloses the emitter fin and collector fin encloses the emitter fin. In some embodiments, the emitter fin, base fin, and collector fin have a square shape when viewed from above and are concentric with each other. | 2013-07-04 |
| 20130168820 | POWER SIGE HETEROJUNCTION BIPOLAR TRANSISTOR (HBT) WITH IMPROVED DRIVE CURRENT BY STRAIN COMPENSATION - A power SiGe heterojunction bipolor transistor (HBT) with improved drive current by strain compensation and methods of manufacture are provided. A method includes adding carbon in a continuous steady concentration in layers of a device including a subcollector layer, a collector layer, a base buffer layer, a base layer, and an emitter buffer layer. | 2013-07-04 |
| 20130168821 | SOI LATERAL BIPOLAR TRANSISTOR HAVING MULTI-SIDED BASE CONTACT AND METHODS FOR MAKING SAME - A Bipolar Junction Transistor with an intrinsic base, wherein the intrinsic base includes a top surface and two side walls orthogonal to the top surface, and a base contact electrically coupled to the side walls of the intrinsic base. In one embodiment an apparatus can include a plurality of Bipolar Junction Transistors, and a base contact electrically coupled to the side walls of the intrinsic bases of each BJT. | 2013-07-04 |
| 20130168822 | SELF ALIGNED STRUCTURES AND DESIGN STRUCTURE THEREOF - Vertical bipolar junction structures, methods of manufacture and design structures. The method includes forming one or more sacrificial structures for a bipolar junction transistor (BJT) in a first region of a chip. The method includes forming a mask over the one or more sacrificial structures. The method further includes etching an opening in the mask, aligned with the one or more sacrificial structures. The method includes forming a trench through the opening and extending into diffusion regions below the one or more sacrificial structures. The method includes forming a base region of the BJT by depositing an epitaxial material in the trench, in contact with the diffusion regions. The method includes forming an emitter contact by depositing a second epitaxial material on the base region within the trench. The epitaxial material for the emitter region is of an opposite dopant type than the epitaxial material of the base region. | 2013-07-04 |
| 20130168823 | SYSTEMS AND METHODS FOR BACKSIDE THRESHOLD VOLTAGE ADJUSTMENT - Described herein are semiconductor devices with a threshold voltage (V | 2013-07-04 |
| 20130168824 | P-DOPED SILICON LAYERS - The invention relates to a process for producing p-doped silicon layers, especially those silicon layers which are produced from liquid silane-containing formulations. The invention further relates to a substrate coated with a p-doped silicon layer. The invention additionally relates to the use of particular dopants based on boron compounds for p-doping of a silicon layer. | 2013-07-04 |
| 20130168825 | FABRICATION OF IONIC LIQUID ELECTRODEPOSITED CU-SN-ZN-S-SE THIN FILMS AND METHOD OF MAKING - A semiconductor thin-film and method for producing a semiconductor thin-films comprising a metallic salt, an ionic compound in a non-aqueous solution mixed with a solvent and processing the stacked layer in chalcogen that results in a CZTS/CZTSS thin films that may be deposited on a substrate is disclosed. | 2013-07-04 |
| 20130168826 | LASER SYSTEM WITH POLARIZED OBLIQUE INCIDENCE ANGLE AND ASSOCIATED METHODS - Novel laser processed semiconductor materials, systems, and methods associated with the manufacture and use of such materials are provided. In one aspect, for example, a method of processing a semiconductor material can include providing a semiconductor material and irradiating a target region of the semiconductor material with a beam of laser radiation to form a laser treated region. The laser radiation is irradiated at an angle of incidence relative to the semiconductor material surface normal of from about 5° to about 89°, and the laser radiation can be at least substantially p-polarized. | 2013-07-04 |
| 20130168827 | DESIGN METHOD OF WIRING LAYOUT, SEMICONDUCTOR DEVICE, PROGRAM FOR SUPPORTING DESIGN OF WIRING LAYOUT, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a design method of layout formed by a sidewall method is provided. The method includes: preparing a base pattern on which a plurality of first patterns extending in a first direction and arranged at a first space in a second direction intersecting the first direction and a plurality of second patterns extending in the first direction and arranged at a center between the first patterns, respectively, are provided; and drawing a connecting portion which extends in the second direction and connects two neighboring first patterns sandwiching one of the second patterns, and separating the one of the second patterns into two patterns not contacting the connecting portion. | 2013-07-04 |
| 20130168828 | THROUGH-HOLE FORMING METHOD AND INKJET HEAD - A through-hole forming method includes steps of forming a first impurity region ( | 2013-07-04 |
| 20130168829 | PHENOLIC RESIN COMPOSITION, AND METHODS FOR MANUFACTURING CURED RELIEF PATTERN AND SEMICONDUCTOR - Provided is a photopolymer composition for a semiconductor element surface protective film or an interlayer insulating film, in which a solution of the photopolymer composition comprises 100 parts by mass of (A) a phenolic resin having a biphenyldiyl structure in a main chain of the resin; 1 to 30 parts by mass of (B) a photo acid-generating agent; and 1 to 60 parts by mass of (C) a compound that can be reacted with ingredient (A) by means of an acid generated from the photo acid-generating agent or heat. | 2013-07-04 |
| 20130168830 | SEMICONDUCTOR WAFER PLATING BUS - A semiconductor wafer includes a die, an edge seal, a bond pad, a plating bus, and trace. The die is adjacent to a saw street. The edge seal is along a perimeter of the die and includes a conductive layer formed in a last interconnect layer of the die. The bond pad is formed as part of metal deposition layer above the last interconnect layer or part of the last interconnect layer. The plating bus is within the saw street. The trace is connected to the bond pad and to the plating bus (1) over the edge seal, insulated from the edge seal, and formed in the metal deposition layer or (2) through the edge seal and insulated from the edge seal. | 2013-07-04 |
| 20130168831 | LASER BEAM MACHINING METHOD AND SEMICONDUCTOR CHIP - An object to be processed | 2013-07-04 |
| 20130168832 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device is provided such that a penetrating via with a conductive material embedded through a medium of an insulating film is formed in a through hole of a p-type semiconductor substrate. The semiconductor device includes an n-type well on an upper section of the p-type semiconductor substrate in the vicinity of the penetrating via, an electrode connected to the n-type well, and the electrode connected to the p-type semiconductor substrate in the vicinity of the electrode. | 2013-07-04 |
| 20130168833 | METHOD FOR ENHANCING GROWTH OF SEMIPOLAR (Al,In,Ga,B)N VIA METALORGANIC CHEMICAL VAPOR DEPOSITION - A method for enhancing growth of device-quality planar semipolar nitride semiconductor thin films via metalorganic chemical vapor deposition (MOCVD) by using an (Al,In,Ga)N nucleation layer containing at least some indium. Specifically, the method comprises loading a substrate into a reactor, heating the substrate under a flow of nitrogen and/or hydrogen and/or ammonia, depositing an In | 2013-07-04 |
| 20130168834 | III-V COMPOUND SEMICONDUCTOR MATERIAL PASSIVATION WITH CRYSTALLINE INTERLAYER - The present disclosure reduces and, in some instances, eliminates the density of interface states in III-V compound semiconductor materials by providing a thin crystalline interlayer onto an upper surface of a single crystal III-V compound semiconductor material layer to protect the crystallinity of the single crystal III-V compound semiconductor material layer's surface atoms prior to further processing of the structure. | 2013-07-04 |
| 20130168835 | HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE AND METHOD OF FORMING - A semiconductor structure and a method of forming the same. In one embodiment, a method of forming a silicon-on-insulator (SOI) wafer substrate includes: providing a handle substrate; forming a high resistivity material layer over the handle substrate, the high resistivity material layer including one of an amorphous silicon carbide (SiC), a polycrystalline SiC, an amorphous diamond, or a polycrystalline diamond; forming an insulator layer over the high resistivity material layer; and bonding a donor wafer to a top surface of the insulator layer to form the SOI wafer substrate. | 2013-07-04 |
| 20130168836 | SOI STRUCTURES HAVING A SACRIFICIAL OXIDE LAYER - Methods for producing silicon on insulator structures with a reduced metal content in the device layer thereof are disclosed. Silicon on insulator structures with a reduced metal content are also disclosed. | 2013-07-04 |
| 20130168837 | ESD PROTECTION DEVICE - An ESD protection device includes a semiconductor substrate including input/output electrodes and a rewiring layer located on the top surface of the semiconductor substrate. An ESD protection circuit is provided in the top layer of the semiconductor substrate, and the input/output electrodes are connected to the ESD protection circuit. The rewiring layer includes interlayer wiring lines, in-plane wiring lines, and post-shaped electrodes. First ends of the interlayer wiring lines provided in the thickness direction are connected to the input/output electrodes provided on the top surface of the semiconductor substrate and the second ends are connected to first ends of the in-plane wiring lines extending in the plane direction. The distance between the centers of the first and second post-shaped electrodes is larger than the distance between the centers of the first and second input/output electrodes. | 2013-07-04 |
| 20130168838 | INSERTS FOR DIRECTING MOLDING COMPOUND FLOW AND SEMICONDUCTOR DIE ASSEMBLIES - Flow diverting structures for preferentially impeding, redirecting or both impeding and redirecting the flow of flowable encapsulant material, such as molding compound, proximate a selected surface or surfaces of a semiconductor die or dice during encapsulation are disclosed. Flow diverting structures may be included in or associated with one or more portions of a lead frame, such as a paddle, tie bars, or lead fingers. Flow diverting structures may also be inserted into a mold in association with semiconductor dice carried on non-lead frame substrates, such as interposers and circuit boards, to preferentially impede, redirect or both impede and redirect the flow of molding compound flowing between and over the semiconductor dice. | 2013-07-04 |
| 20130168839 | APPARATUS FOR INTEGRATED CIRCUIT PACKAGING - Apparatuses are disclosed, such as those involving integrated circuit packaging. In one embodiment, a chip package includes: an encapsulation having a top surface and a bottom surface facing away from the top surface. The package further includes a leadframe including a plurality of leads. Each of the leads includes an exposed portion exposed through one of edges of the bottom surface of the encapsulation. The exposed portion has a length. At least one of exposed portions positioned along one of the edges of the bottom surface of the encapsulation has a length different from other exposed portions along the edge. The package can also include a dummy pad exposed through a corner of the bottom surface. The configuration can enhance solder joint reliability of the package when the package is attached to a printed circuit board. | 2013-07-04 |
| 20130168840 | SEMICONDUCTOR INTEGRATED DEVICE WITH MECHANICALLY DECOUPLED ACTIVE AREA AND RELATED MANUFACTURING PROCESS - A semiconductor integrated device is provided with: a die having a body of semiconductor material with a front surface, and an active area arranged at the front surface; and a package having a support element carrying the die at a back surface of the body, and a coating material covering the die. The body includes a mechanical decoupling region, which mechanically decouples the active area from mechanical stresses induced by the package; the mechanical decoupling region is a trench arrangement within the body, which releases the active area from an external frame of the body, designed to absorb the mechanical stresses induced by the package. | 2013-07-04 |
| 20130168841 | Programmable Interposer with Conductive Particles - An exemplary implementation of the present disclosure includes a programmable interposer having top and bottom interface electrodes and conductive particles interspersed within the programmable interposer. The conductive particles are capable of forming an aligned configuration between the top and bottom interface electrodes in response to application of an energy field to the programmable interposer so as to electrically connect the top and bottom interface electrodes. The conductive particles can have a conductive outer surface. Also, the conductive particles can be spherical. The conductive particles can be within a bulk material in an interface layer in the programmable interposer, and the bulk material can be cured to secure programmed paths between the top and bottom interface electrodes. | 2013-07-04 |
| 20130168842 | INTEGRATED CIRCUIT PACKAGES HAVING REDISTRIBUTION STRUCTURES - A semiconductor package includes a semiconductor chip stack disposed between first and second leads near first and second sides of the package and including a plurality of semiconductor chips, and a redistribution structure disposed on the semiconductor chip stack. At least one semiconductor chip of the semiconductor chip stack includes a plurality of first chip pads disposed near or closer to a third side of the package. The redistribution structure includes a first redistribution pad disposed near or closer to the first side and electrically connected to the first lead, a second redistribution pad disposed near or closer to the second side and electrically connected to the second lead, and a third redistribution pad disposed near or closer to the third side and electrically connected to a first one of the first chip pads and the first redistribution pad. | 2013-07-04 |
| 20130168843 | EMBEDDED HEAT SPREADER FOR PACKAGE WITH MULTIPLE MICROELECTRONIC ELEMENTS AND FACE-DOWN CONNECTION - A microelectronic package includes a substrate, first and second microelectronic elements, and a heat spreader. The substrate has terminals thereon configured for electrical connection with a component external to the package. The first microelectronic element is adjacent the substrate and the second microelectronic element is at least partially overlying the first microelectronic element. The heat spreader is sheet-like, separates the first and second microelectronic elements, and includes an aperture. Connections extend through the aperture and electrically couple the second microelectronic element with the substrate. | 2013-07-04 |
| 20130168844 | METAL INJECTION MOLDED HEAT DISSIPATION DEVICE - A heat dissipation device is provided. The heat dissipation device includes an integrated heat spreader and a base plate coupled to the integrated heat spreader, wherein the base plate comprises a plurality of metal pellets to dissipate heat from the integrated heat spreader. | 2013-07-04 |
| 20130168845 | SEMICONDUCTOR MODULE - A semiconductor module includes a semiconductor device, a first conductive member, a second conductive member, a cylinder, and a cover. The first conductive member is in contact with a first electrode of the semiconductor device. The second conductive member is in contact with a second electrode of the semiconductor device. The cylinder encompasses the semiconductor device and is fixed to the first conductive member, and a first thread groove is formed on the cylinder. A second thread groove is formed on the cover. The cover is fixed to the cylinder by an engagement of the second thread groove with the first thread groove. The semiconductor device and the second conductive member are fixed by being sandwiched between the first conductive member and the cover. The second conductive member includes a portion extending from inside to outside the cylinder by penetrating an outer peripheral wall of the cylinder. | 2013-07-04 |
| 20130168846 | UNDERFILL PROCESS AND MATERIALS FOR SINGULATED HEAT SPREADER STIFFENER FOR THIN CORE PANEL PROCESSING - A method of making a microelectronic package, and a microelectronic package made according to the method. The method includes: bonding and thermally coupling a plurality of IC dies to an IHS panel to yield a die-carrying IHS panel, and mounting the die-carrying IHS panel onto a substrate panel including a plurality of package substrates by mounting perimeter ribs of the IHS panel to a corresponding pattern of sealant on the substrate panel and by mounting each of the plurality of dies to a corresponding one of the plurality of package substrates to yield a combination including the die-carrying IHS panel mounted to the substrate panel. Other embodiments are also disclosed and claimed. | 2013-07-04 |
| 20130168847 | ANISOTROPIC CONDUCTIVE FILM AND ELECTRONIC DEVICE INCLUDING THE SAME - An electronic device includes an anisotropic conductive film as a connection material, the anisotropic conductive film being formed from an anisotropic conductive film-forming composition. The anisotropic conductive film-forming composition includes a polycyclic aromatic ring-containing epoxy resin, a fluorene epoxy resin, nano silica and conductive particles. | 2013-07-04 |
| 20130168848 | PACKAGED SEMICONDUCTOR DEVICE AND METHOD OF PACKAGING THE SEMICONDUCTOR DEVICE - The mechanisms of forming a molding compound on a semiconductor device substrate to enable fan-out structures in wafer-level packaging (WLP) are provided. The mechanisms involve covering portions of surfaces of an insulating layer surrounding a contact pad. The mechanisms improve reliability of the package and process control of the packaging process. The mechanisms also reduce the risk of interfacial delamination, and excessive outgassing of the insulating layer during subsequent processing. The mechanisms further improve planarization end-point. By utilizing a protective layer between the contact pad and the insulating layer, copper out-diffusion can be reduced and the adhesion between the contact pad and the insulating layer may also be improved. | 2013-07-04 |
| 20130168849 | Fully Molded Fan-Out - A method for manufacturing a device package may include constructing a spacer element coupled with a surface of a semiconductor die unit, where the spacer element is configured to create a gap between the semiconductor die unit and a surface of a carrier, and encapsulating the semiconductor die unit within a mold compound, where the encapsulating includes introducing the mold compound into the gap. | 2013-07-04 |
| 20130168850 | SEMICONDUCTOR DEVICE HAVING A THROUGH-SUBSTRATE VIA - Semiconductor devices are described that include a via that extends only partially through the substrate. Through-substrate vias (TSV) furnish electrical interconnectivity to electronic components formed in the substrates. In implementations, the semiconductor devices are fabricated by first bonding a semiconductor wafer to a carrier wafer with an adhesive material. The semiconductor wafer includes an etch stop disposed within the wafer (e.g., between a first surface a second surface of the wafer). One or more vias are formed through the wafer. The vias extend from the second surface to the etch stop. | 2013-07-04 |
| 20130168851 | BUMP STRUCTURE AND ELECTRONIC PACKAGING SOLDER JOINT STRUCTURE AND FABRICATING METHOD THEREOF - A bump structure includes a substrate, a pad, an electrode and a protruding electrode. The pad is disposed on the substrate. The electrode is formed by a first metal material and disposed on the pad. The protruding electrode is formed by a second metal material and disposed on the electrode, wherein a cross-sectional area of the protruding electrode is less than a cross-sectional area of the electrode. | 2013-07-04 |
| 20130168852 | MEMS Devices and Methods of Forming Same - A microelectromechanical system (MEMS) device may include a MEMS structure over a first substrate. The MEMS structure comprises a movable element. Depositing a first conductive material over the first substrate and etching trenches in a second substrate. Filling the trenches with a second conductive material and depositing a third conductive material over the second conductive material and the second substrate. Bonding the first substrate and the second substrate and thinning a backside of the second substrate which exposes the second conductive material in the trenches. | 2013-07-04 |
| 20130168853 | PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME - Disclosed herein are a package substrate and a method of fabricating the same. The method of fabricating the package substrate includes preparing a base substrate, forming a metal material layer surrounding an entire surface of the base substrate, forming sacrificial patterns on partial regions of the base substrate on which the metal material layer is formed, forming pads contacting lateral surfaces of the sacrificial patterns, forming a gold plating layer on upper surfaces of the pads, and removing the sacrificial patterns and removing portions of the metal material layer to form a conductive layer that remains on partial regions so as to contact lower surfaces of the pads. | 2013-07-04 |
| 20130168854 | Semiconductor Package with a Bridge Interposer - There are disclosed herein various implementations of semiconductor packages including a bridge interposer. One exemplary implementation includes a first active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The semiconductor package also includes a second active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The second portion of the first active die and the second portion of the second active die include solder balls mounted on a package substrate, and are configured to communicate electrical signals to the package substrate utilizing the solder balls and without utilizing through-semiconductor vias (TSVs). | 2013-07-04 |
| 20130168855 | Methods and Apparatus for Package On Package Devices with Reduced Strain - Methods and apparatus for package on package structures. A structure includes a first integrated circuit package including at least one integrated circuit device mounted on a first substrate, a plurality of package on package connectors extending from a bottom surface and arranged in a pattern of one or more rows proximal to an outer periphery of the first substrate; and a second integrated circuit package including at least another integrated circuit device mounted on a second substrate and a plurality of lands on an upper surface coupled to the plurality of package on package connectors, and a plurality of external connectors extending from a bottom surface of the second substrate; wherein the pattern of the external connectors is staggered from the pattern of the package on package connectors so that the package on package connectors are not in vertical alignment with the external connectors. Methods for forming structures are disclosed. | 2013-07-04 |
| 20130168856 | Package on Package Devices and Methods of Packaging Semiconductor Dies - Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a bottom packaged die having solder balls disposed on the top surface thereof and a top packaged die having metal stud bumps disposed on a bottom surface thereof. The metal stud bumps include a bump region and a tail region coupled to the bump region. Each metal stud bump on the top packaged die is coupled to one of the solder balls on the bottom packaged die. | 2013-07-04 |
| 20130168857 | MOLDED INTERPOSER PACKAGE AND METHOD FOR FABRICATING THE SAME - The invention provides a molded interposer package and a method for fabricating the same. The molded interposer package includes a plurality of metal studs. A molding material encapsulates the metal studs leaving the bottom surfaces of the metal studs exposed. A first chip is disposed on the molding material, connecting to the top surfaces of the metal studs. A plurality of solder balls connects and contacts to the bottom surfaces of the metal studs. | 2013-07-04 |
| 20130168858 | EMBEDDED WAFER LEVEL BALL GRID ARRAY BAR SYSTEMS AND METHODS - A bar formed from a reconstituted wafer and containing one or more conductive material filled voids is used to electrically and physically connect the top and bottom packages in a package-on-package (PoP) package. The bar is disposed in the fan out area of the lower package forming the PoP package. | 2013-07-04 |
| 20130168859 | POSITIVE PHOTOSENSITIVE RESIN COMPOSITION, METHOD OF CREATING RESIST PATTERN, AND ELECTRONIC COMPONENT - The positive-type photosensitive resin composition according to the present invention comprises an alkali-soluble resin having a phenolic hydroxyl group, a compound that produces an acid by light, a thermal crosslinking agent, and a silane compound having at least one functional group selected from an epoxy group and a sulfide group. | 2013-07-04 |
| 20130168860 | Semiconductor Package with Ultra-Thin Interposer Without Through-Semiconductor Vias - There are disclosed herein various implementations of semiconductor packages including an interposer without through-semiconductor vias (TSVs). One exemplary implementation includes a first active die situated over an interposer. The interposer includes an interposer dielectric having intra-interposer routing traces. The first active die communicates electrical signals to a package substrate situated below the interposer utilizing the intra-interposer routing traces and without utilizing TSVs. In one implementation, the semiconductor package includes a second active die situated over the interposer, the second active die communicating electrical signals to the package substrate utilizing the intra-interposer routing traces and without utilizing TSVs. Moreover, in one implementation, the first active die and the second active die communicate chip-to-chip signals through the interposer. | 2013-07-04 |
| 20130168861 | ELECTRICALLY CONDUCTIVE DEVICE AND MANUFACTURING METHOD THEREOF - An electrically conductive device and a manufacturing method thereof are provided. According to the method, a protein tube portion and a conductor penetrating through the protein tube portion are formed on a graphene layer, and the conductor is in electrical contact with the graphene layer. A dummy dielectric material layer surrounding the protein tube portion can be formed on the graphene layer for support. The graphene layer can be protected from damage during the formation of the protein tube portion and the conductor because no etching process is employed in the formation. The method can facilitate the application of graphene in semiconductor devices as conductive interconnects. | 2013-07-04 |
| 20130168862 | METHOD OF MANUFACTURING BARRIER LAYER PATTERNS OF A SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE OF BARRIER LAYER PATTERNS OF SEMICONDUCTOR MEMORY DEVICE - A method of manufacturing a semiconductor memory and a structure of the semiconductor memory device, where the semiconductor memory device includes a material layer and a barrier layer. The barrier layer has a structure in which a horizontal cross-section of an upper portion thereof is larger than that of a lower portion thereof so that a fine pattern may be formed on the material layer using the barrier layer pattern without a structural damage or collapse in etching the underlying material layer. | 2013-07-04 |
| 20130168863 | ENHANCED DIFFUSION BARRIER FOR INTERCONNECT STRUCTURES - Alternative methods of fabricating an interconnect structure in which an enhanced diffusion barrier including an in-situ formed metal nitride liner formed between an interconnect dielectric material and an overlying metal diffusion barrier liner are provided. In one embodiment, at least one opening is formed into an interconnect dielectric material. A nitrogen enriched dielectric surface layer is formed within exposed surfaces of the interconnect dielectric material utilizing thermal nitridation. A metal diffusion barrier liner is the formed. During and/or after the formation of the metal diffusion barrier liner, a metal nitride liner forms in-situ in a lower region of the metal diffusion barrier liner. A conductive material is then formed on the metal diffusion barrier liner. The conductive material, the metal diffusion barrier liner and the metal nitride liner that are located outside of the at least one opening are removed to provide a planarized structure. | 2013-07-04 |
| 20130168864 | METHOD FOR PRODUCING ULTRA-THIN TUNGSTEN LAYERS WITH IMPROVED STEP COVERAGE - A tungsten nucleation film is formed on a surface of a semiconductor substrate by alternatively providing to that surface, reducing gases and tungsten-containing gases. Each cycle of the method provides for one or more monolayers of the tungsten film. The film is conformal and has improved step coverage, even for a high aspect ratio contact hole. | 2013-07-04 |
| 20130168865 | SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films | 2013-07-04 |
| 20130168866 | CHIP-ON-LEAD PACKAGE AND METHOD OF FORMING - In one embodiment, a chip-on-lead package structures includes an electronic chip having opposing major surfaces. One major surface of the electronic chip is attached to first and second leads. The one major surface is electrically connected to the first lead, and electrically isolated from the second lead. The other major surface where active device are formed may be electrically connected to the second lead. | 2013-07-04 |
| 20130168867 | METHOD FOR FORMING METAL LINE IN SEMICONDUCTOR DEVICE - A method for forming a metal line in a semiconductor device and an associated apparatus. The method includes at least one of (1) Depositing a metal line layer and a metal contact layer over a semiconductor substrate. (2) Patterning the metal contact layer and the metal line layer to form a primarily formed contact portion and a lower metal line. (3) Patterning the primarily formed contact portion to form a secondarily formed contact portion. (4) Forming an insulating film on the semiconductor substrate including the secondarily formed contact portion and the lower metal line. (5) Planarizing the insulating film such that the secondarily formed contact portion is exposed. (6) Forming an upper metal line over the planarized insulating film to be in electrical contact with the secondarily formed contact portion. | 2013-07-04 |
| 20130168868 | SEMICONDUCTOR STACK STRUCTURE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor stack structure mainly includes: singulating a wafer of a first specification into a plurality of chips; rearranging the chips into a second specification of a wafer so as to stack the chips on a substrate of the second specification through a plurality of blocks; forming a redistribution layer on the chips; and performing a cutting process to obtain a plurality of semiconductor stack structures. Therefore, the present invention allows a wafer of a new specification to be processed by using conventional equipment without the need of new factory buildings or equipment. As such, chip packages can be timely supplied to meet the replacement speed of electronic products. | 2013-07-04 |
| 20130168869 | Metal Layout of an Integrated Power Transistor and the Method Thereof - The present disclosure discloses a metal layout of an integrated power transistor. The metal layout comprises a 1 | 2013-07-04 |
| 20130168870 | DEVICE AND METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE - A method for manufacturing an electronic interconnect device is described, the method comprising: providing an electronic members each having one or more electrical contacts on a first member side thereof; providing a carrier having a carrier base and having sets of one or more electrically conductive projections on a surface of the carrier base; attaching the electronic members with the corresponding contacts thereof to the respective set of projections to thereby electrically connect the one or more electrical contacts of the respective chip with the corresponding one or more electrically conductive projections of the respective set; encapsulating exposed portions of the electronic member with an encapsulating material to form an encapsulation. | 2013-07-04 |
| 20130168871 | SEMICONDUCTOR PACKAGE WITH PACKAGE ON PACKAGE STRUCTURE - A semiconductor package of a package on package structure reducing an overall thickness of the package and simplifying design complexity of wiring paths is provided. The package includes a first package including a first substrate and a first semiconductor chip portion mounted thereon, a second package disposed on the first package and including a second substrate and a second semiconductor chip portion mounted thereon, and a connection member connecting the first and second substrates. The second semiconductor chip portion includes at least one semiconductor chip including a group of chip pads corresponding to one channel, and the group of chip pads is concentrated on a first edge of the semiconductor chip. An intellectual property core corresponding to the one channel is formed on an edge of the first semiconductor chip portion and the IP core corresponds to the edge on which the group of chip pads is concentrated. | 2013-07-04 |
| 20130168872 | VIA ARRANGEMENT AND SEMICONDUCTOR DEVICE WITH THE VIA ARRANGEMENT - A semiconductor device may include a first line of vias including a first via and a second via immediately adjacent to the first via. The semiconductor device may further include a second line of vias arranged immediately adjacent to and parallel to the first line of vias, the second line of vias including a third via immediately adjacent to the first via and the second via, the second line of vias further including a fourth via immediately adjacent to the third via, the first via, and the second via. The shortest distance between the second via and the fourth via may be greater than the shortest distance between the first via and the second via. | 2013-07-04 |
| 20130168873 | POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A power semiconductor device and a manufacturing method thereof, the power semiconductor device including a plurality of first electrodes and a plurality of second electrodes, a plurality of first via electrodes on a first insulating layer and contacting the plurality of first electrodes, a plurality of second via electrodes on the first insulating layer and contacting the plurality of second electrodes, a first electrode pad contacting the plurality of first via electrodes, a second electrode pad contacting the plurality of second via electrodes, a plurality of third via electrodes on a second insulating layer and contacting the first electrode pad, a plurality of fourth via electrodes on the second insulating layer and contacting the second electrode pad, a third electrode pad contacting the plurality of third via electrodes, and a fourth electrode pad contacting the plurality of fourth via electrodes. | 2013-07-04 |
| 20130168874 | DIE UP FULLY MOLDED FAN-OUT WAFER LEVEL PACKAGING - A method of manufacturing a semiconductor chip comprising placing a plurality of die units each having an active front surface and a back surface facing front surface up on an encapsulant layer, encapsulating the plurality of die units on the active surface of the encapsulant layer with an encapsulant covering a front surface and four side surfaces of each of the plurality of die units, and exposing, through the encapsulation on the front surface, conductive interconnects electrically connecting a die bond pad to a redistribution layer. | 2013-07-04 |
| 20130168875 | SEMICONDUCTOR DEVICE AND PACKAGE - A semiconductor device includes a semiconductor substrate having an upper surface, a lower surface, a first side and a second side, wherein the lower surface has a slope so that the first side is thicker than the second side, and a circuit pattern including a bonding pad on the upper surface of the semiconductor substrate. | 2013-07-04 |
| 20130168876 | MODULE PACKAGE AND PRODUCTION METHOD - The invention relates to a module package which comprises a module substrate | 2013-07-04 |
| 20130168877 | MASK OVERLAY METHOD, MASK, AND SEMICONDUCTOR DEVICE USING THE SAME - A mask overlay method, and a mask and a semiconductor device using the same are disclosed. According to the disclosed mask overlay technique, test marks and front layer overlay marks corresponding to a plurality of overlay mark designs are generated in a first layer of a semiconductor device. The test patterns generating the test marks each include a first sub pattern and a second sub pattern. Note that the first sub pattern has the same design as a front layer overlay pattern (which generates the front layer overlay mark corresponding thereto). Based on the test marks, performances of the plurality of overlay mark designs are graded. The front layer overlay mark corresponding to the overlay mark design having the best performance is regarded as an overlay reference for a mask of a second layer of the semiconductor device. | 2013-07-04 |
| 20130168878 | FLOTATION SYSTEM FOR WASTEWATER TREATMENT - A flotation clarification system ( | 2013-07-04 |
| 20130168879 | Venturi tube for shower head - A Venturi tube device is provided with a Venturi tube; a hollow cylindrical fitting; a shroud; and a hollow, cylindrical flow guide member disposed in the Venturi tube. In a showing operation, air can flow through one communicating hole of the shroud, a space defined by two adjacent ridges on the fitting, a conic hole between the two adjacent ridges, and a transverse hole of the Venturi tube in addition to water flowing through the flow guide member and the Venturi tube. | 2013-07-04 |
| 20130168880 | ELECTRONIC VAPORIZING DEVICE - An electronic vaporizing device that includes an atomizing device connected to an external shell. The external shell has an internal compartment that contains an airflow activated switch; a bottle of liquid; a liquid chamber; a battery; and a circuit board comprising a microchip. A user inhaling through the atomizing device triggers the airflow activated switch which in turn activates the microchip and the battery, causing the atomizing device to guide the liquid through the liquid chamber. The liquid is then vaporized by the atomizing device and can be inhaled by the user. | 2013-07-04 |
| 20130168881 | HEAT EXCHANGER PLATE AND A FILL PACK OF HEAT EXCHANGER PLATES - A heat exchanger plate includes a corrugated sheet of stiff material configured in a repetitive series of elongated corrugations. Each corrugation has a first corrugation segment, a second corrugation segment disposed offset from and extending parallel to the first corrugation segment and an intermediate corrugation segment. The first and second corrugation segments extend vertically. The intermediate corrugation segment is disposed between and interconnects the first corrugation segment and the second corrugation segment and extends obliquely relative to the first corrugation segment and the second corrugation segment to form a continuous, uninterrupted offset corrugation. A plurality of the heat exchanger plates are connected together to form a fill pack. | 2013-07-04 |
