| 27th week of 2013 patent applcation highlights part 15 |
| Patent application number | Title | Published |
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| 20130168682 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a gate, a channel layer, a gate insulation layer, a source, a drain and a silicon-aluminum-oxide layer. The gate is disposed on a substrate. The channel layer is disposed on the substrate. The channel layer overlaps the gate. The gate insulation layer is disposed between the gate and the channel layer. The source and the drain are disposed on two sides of the channel layer. The silicon-aluminum-oxide layer is disposed on the substrate and covers the source, the drain and the channel layer. | 2013-07-04 |
| 20130168683 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF - A thin film transistor is provided. A thin film transistor according to an exemplary embodiment of the present invention includes: a substrate; a gate electrode disposed on the substrate; a gate insulating layer disposed on the gate electrode; a semiconductor layer disposed on the gate insulating layer; and a source electrode and a drain electrode disposed on a portion of the semiconductor layer, wherein the semiconductor layer includes an ohmic contact layer, a channel layer, and a buffer layer, the buffer layer disposed between the channel layer and the ohmic contact layer, and the source electrode and the drain electrode contact a surface of the ohmic contact layer. | 2013-07-04 |
| 20130168684 | BACK CONTACT TO FILM SILICON ON METAL FOR PHOTOVOLTAIC CELLS - A crystal oriented metal back contact for solar cells is disclosed herein. In one embodiment, a photovoltaic device and methods for making the photovoltaic device are disclosed. The photovoltaic device includes a metal substrate with a crystalline orientation and a heteroepitaxial crystal silicon layer having the same crystal orientation of the metal substrate. A heteroepitaxial buffer layer having the crystal orientation of the metal substrate is positioned between the substrate and the crystal silicon layer to reduce diffusion of metal from the metal foil into the crystal silicon layer and provide chemical compatibility with the heteroepitaxial crystal silicon layer. Additionally, the buffer layer includes one or more electrically conductive pathways to electrically couple the crystal silicon layer and the metal substrate. | 2013-07-04 |
| 20130168685 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME - A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. The gate electrode includes a refractory metal. A depletion region is disposed in the carrier channel and under the gate electrode. | 2013-07-04 |
| 20130168686 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME - A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. Each of the source feature and the drain feature comprises a corresponding intermetallic compound at least partially embedded in the second III-V compound layer. Each intermetallic compound is free of Au and comprises Al, Ti or Cu. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A depletion region is disposed in the carrier channel and under the gate electrode. | 2013-07-04 |
| 20130168687 | ENHANCEMENT MODE GALLIUM NITRIDE BASED TRANSISTOR DEVICE - Provided is an enhancement mode GaN-based transistor device including an epitaxial stacked layer disposed on a substrate; a source layer and a drain layer disposed on a surface of the epitaxial stacked layer; a p-type metal oxide layer disposed between the source layer and the drain layer; and a gate layer disposed on the p-type metal oxide layer. Besides, the p-type metal oxide layer includes a body part disposed on the surface of the epitaxial stacked layer, and a plurality of extension parts connecting the body part and extending into the epitaxial stacked layer. With such structure, the enhancement mode GaN-based transistor device can effectively suppress generation of the gate leakage current. | 2013-07-04 |
| 20130168688 | NITRIDE BASED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A nitride based semiconductor device includes a first metallic junction layer, a Schottky junction layer on the first metallic junction layer, a first group III nitride semiconductor layer on the Schottky junction layer, a first insulating pattern layer on the first group III nitride semiconductor layer, the first insulating layer pattern including curved protrusions, a second group III nitride semiconductor layer laterally grown on the first group III nitride semiconductor layer, a first type group III nitride semiconductor layer on the second group III nitride semiconductor layer, the first type group III nitride semiconductor layer being simultaneously doped with aluminum (Al) and silicon (Si), an ohmic junction layer formed on the first type group III nitride semiconductor layer, a second metallic junction layer on the ohmic junction layer, and a metallic supporting substrate on the second metallic junction layer. | 2013-07-04 |
| 20130168689 | NITRIDE BASED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - With the formation of a Si | 2013-07-04 |
| 20130168690 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A first nitride semiconductor layer contains Ga. The first nitride semiconductor layer is, for example, a GaN layer, an AlGaN layer, or an AlInGaN layer. Then, an aluminum oxide layer has tetra-coordinated Al atoms each surrounded by four O atoms and hexa-coordinated Al atoms each surrounded by six O atoms as Al atoms in the interface region with respect to the first nitride semiconductor layer. The interface region is a region apart, for example, by 1.5 nm or less from the interface with respect to the first nitride semiconductor layer. Then, in the interface region, the tetra-coordinated Al atoms are present by 30 at % or more and less than 50 at % based on the total number of Al atoms. | 2013-07-04 |
| 20130168691 | METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT EMITTING ELEMENT, SEMICONDUCTOR LIGHT EMITTING ELEMENT, ELECTRONIC DEVICE, AND MACHINE DEVICE - Provided is a method of manufacturing a semiconductor light emitting element that is capable of making a light emitting wavelength distribution σ of a semiconductor light emitting layer that is obtained small. The method includes a process of laminating a re-growth layer of a compound semiconductor layer on the compound semiconductor substrate which is obtained by forming at least one compound semiconductor layer on a substrate and in which a warping amount H is within a range of 50 μm≦H≦250 μm. The method adopts a method of manufacturing a semiconductor light emitting element including an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer that are formed from a compound semiconductor. This method includes: a process of preparing a compound semiconductor substrate which is obtained by forming at least one compound semiconductor layer on a substrate and in which a warping amount H is within a range of 50 μm≦H≦250 μm; and a process of laminating a re-growth layer of the compound semiconductor layer on the compound semiconductor layer of the compound semiconductor substrate in a metalorganic chemical vapor deposition apparatus. | 2013-07-04 |
| 20130168692 | POLYCRYSTALLINE ALUMINUM NITRIDE BASE MATERIAL FOR CRYSTAL GROWTH OF GaN-BASE SEMICONDUCTOR AND METHOD FOR MANUFACTURING GaN-BASE SEMICONDUCTOR USING THE SAME - There is provided a polycrystalline aluminum nitride substrate that is effective in growing a GaN crystal. The polycrystalline aluminum nitride base material for use as a substrate material for grain growth of GAN-base semiconductors, contains 1 to 10% by weight of a sintering aid component and has a thermal conductivity of not less than 150 W/m·K, the substrate having a surface free from recesses having a maximum diameter of more than 200 μm. | 2013-07-04 |
| 20130168693 | PROTECTIVE-FILM-ATTACHED COMPOSITE SUBSTRATE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A protective-film-attached composite substrate includes a support substrate, an oxide film disposed on the support substrate, a semiconductor layer disposed on the oxide film, and a protective film protecting the oxide film by covering a portion that is a part of the oxide film and covered with none of the support substrate and the semiconductor layer. A method of manufacturing a semiconductor device includes the steps of: preparing the protective-film-attached composite substrate; and epitaxially growing, on the semiconductor layer of the protective-film-attached composite substrate, at least one functional semiconductor layer causing an essential function of a semiconductor device to be performed. Thus, there are provided a protective-film-attached composite substrate having a large effective region where a high-quality functional semiconductor layer can be epitaxially grown, and a method of manufacturing a semiconductor device in which the protective-film-attached composite substrate is used. | 2013-07-04 |
| 20130168694 | SUPER INTEGRATED CIRCUIT CHIP SEMICONDUCTOR DEVICE - The CP555 Super Integrated Circuit Chip has a ceramic package casing made from (B4-C) Boron Carbide: a non-conducting ceramic material. The IC is connected to connector pins by microcircuits and a custom formulated bond wire. The CP555 Integrated Circuit's ceramic Boron Carbide (B4-C) outer package casing, Heterodiamond substrates and dielectric components allows these integrated circuits to reduce electro-migration to a minimum, produce superior radiation hardness, heat resistance, electromagnetic shielding, and resistance to damage from harsh elements and environments. The CP555 Integrated Circuit can be used as a CMOS, PIC or DIE microcontroller circuit or computer processor (CPU). | 2013-07-04 |
| 20130168695 | CMOS HAVING A SIC/SIGE ALLOY STACK - A delta doping of silicon by carbon is provided on silicon surfaces by depositing a silicon carbon alloy layer on silicon surfaces, which can be horizontal surfaces of a bulk silicon substrate, horizontal surfaces of a top silicon layer of a semiconductor-on-insulator substrate, or vertical surfaces of silicon fins. A p-type field effect transistor (PFET) region and an n-type field effect transistor (NFET) region can be differentiated by selectively depositing a silicon germanium alloy layer in the PFET region, and not in the NFET region. The silicon germanium alloy layer in the PFET region can overlie or underlie a silicon carbon alloy layer. A common material stack can be employed for gate dielectrics and gate electrodes for a PFET and an NFET. Each channel of the PFET and the NFET includes a silicon carbon alloy layer, and is differentiated by the presence or absence of a silicon germanium layer. | 2013-07-04 |
| 20130168696 | Silicon Carbide Schottky Diode Device with Mesa Termination and Manufacturing Method Thereof - A silicon carbide Schottky diode device with mesa terminations and the manufacturing method thereof are provided. The silicon carbide Schottky diode device includes an n-type epitaxial silicon carbide layer with mesa terminations on an n-type silicon carbide substrate, two p-type regions in the n-type epitaxial silicon carbide layer and a Schottky metal contact on the n-type epitaxial silicon carbide layer and the p-type regions, a dielectric layer on sidewalls and planes of the mesa terminations. | 2013-07-04 |
| 20130168697 | SILICON CARBIDE STRUCTURE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a silicon carbide structure includes forming a silicon carbide layer by depositing silicon carbide on a base plate by chemical vapor deposition, removing the base plate, decreasing electrical conductivity by heat-treating the silicon carbide structure, and removing a thickness of 200 μm from an upper surface and a lower surface of the silicon carbide structure. In the present invention, silicon carbide is deposited by a CVD method, and the electrical conductivity of the silicon carbide is reduced to the electrical conductivity required for a protection ring of a plasma device through a post-treatment and a post-process. The electrical conductivity may be adjusted even without using separate additives. | 2013-07-04 |
| 20130168698 | POWER DEVICES AND METHOD FOR MANUFACTURING THE SAME - A power device includes a substrate, a silicon carbide (Si | 2013-07-04 |
| 20130168699 | SEMICONDUCTOR DEVICE - The semiconductor device of the present invention includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of the semiconductor region, and an electroconductive gate electrode formed on the insulating film. The gate electrode is made of a material whose Fermi level is closer to a Fermi level of the semiconductor region than a Fermi level of Si in at least a portion contiguous to the insulating film. | 2013-07-04 |
| 20130168700 | POWER SEMICONDUCTOR DEVICE - In a high speed switching power semiconductor device having a sense pad, a high voltage is generated during switching operations in well regions under the sense pad due to a displacement current flowing through its flow path with a resistance, whereby the power semiconductor device sometimes breaks down by dielectric breakdown of a thin insulating film such as a gate insulating film. In a power semiconductor device according to the invention, sense-pad well contact holes are provided on well regions positioned under the sense pad and penetrate a field insulating film thicker than the gate insulating film to connect to the source pad, thereby improving reliability. | 2013-07-04 |
| 20130168701 | SILICON CARBIDE SEMICONDUCTOR ELEMENT AND METHOD FOR FABRICATING THE SAME - A SiC semiconductor element includes: a SiC substrate which has a principal surface tilted with respect to a (0001) Si plane; a SiC layer arranged on the principal surface of the substrate; a trench arranged in the SiC layer and having a bottom, a sidewall, and an upper corner region located between the sidewall and the upper surface of the SiC layer; a gate insulating film arranged on at least a part of the sidewall and on at least a part of the upper corner region of the trench and on at least a part of the upper surface of the SiC layer; and a gate electrode arranged on the gate insulating film. The upper corner region has a different surface from the upper surface of the SiC layer and from a surface that defines the sidewall. The gate electrode contacts with both of a first portion of the gate insulating film located on the upper corner region and a second portion of the gate insulating film located on the sidewall. The first portion of the gate insulating film is thicker than a third portion of the gate insulating film located on the upper surface of the SiC layer. And an end portion of the gate electrode is located on the upper corner region. | 2013-07-04 |
| 20130168702 | Method For Preparing a GaAS Substrate For A Ferromagnetic Semiconductor, Method for Manufacturing One Such Semiconductor, Resulting Substrate and Semiconductor, And Uses Of Said Semiconductor - A method is provided for preparing a surface of a GaAs substrate (001) such that it can receive a ferromagnetic semiconductor deposited by epitaxy, as well as a substrate thus prepared, method for manufacturing one such semiconductor deposited on the substrate, the resulting semiconductor, and uses thereof. The preparation method renders the surface capable of receiving an epitaxially deposited ferromagnetic semiconductor which may include semiconductors from groups III-V, IV and II-VI of the periodic table, with the exception of GaAs, and which also includes at least one magnetic element of manganese, iron, cobalt, nickel and chromium. The method includes vacuum deoxidation of the surface under a reduced germanium-based flux such that, following desorption of the arsenic and gallium oxide from the said surface, the latter has a single-domain 2×1 reconstruction and is sufficiently planar and arsenic-depleted to prevent any diffusion of arsenic from the substrate to the subsequently deposited semiconductor. | 2013-07-04 |
| 20130168703 | DEPOSITION OF PHOSPHOR ON DIE TOP BY STENCIL PRINTING - A method for depositing a layer of phosphor-containing material on a plurality of LED dies includes disposing a template with a plurality of openings on an adhesive tape and disposing each of a plurality of LED dies in one of the plurality of openings of the template. The method also includes disposing a stencil over the template and the plurality of LED dies. The stencil has a plurality of openings configured to expose a top surface of each of the LED dies. Next, a phosphor-containing material is disposed on the exposed top surface of each the LED dies. The method further includes removing the stencil and the template. | 2013-07-04 |
| 20130168704 | Panel and method for fabricating the same - A panel is disclosed, in which, a patterned semiconductor layer is formed on an insulation layer. The patterned semiconductor layer includes a portion corresponding to an electrode and another portion corresponding to a wiring trace. The portion corresponding to the electrode may be formed as, for example, a channel, and the other portion corresponding to the wiring trace may protect the wiring trace during fabrication process or in the structure from scratching or corrosion. | 2013-07-04 |
| 20130168705 | SOLID-STATE LIGHT-EMITTING DEVICE AND SOLID-STATE LIGHT-EMITTING PACKAGE THEREOF - A solid-state light-emitting package includes a leadframe, a light-emitting chip, and a sealant. The leadframe includes a first electrode and a second electrode. The first electrode has at least one first contact end, and the second electrode has at least one second contact end. The light-emitting chip is electrically connected to the first electrode and the second electrode and is disposed between the first contact end and the second contact end. The sealant covers the leadframe and the light-emitting chip and has a first surface and a second surface. The first surface is the light output surface for the light-emitting chip. The first electrode and the second electrode are bent toward the first surface, where the first contact end and the second contact end are exposed by the first surface. | 2013-07-04 |
| 20130168706 | PRINTED LIGHT EMITTING DEVICES AND METHOD FOR FABRICATION THEROF - An array of light emitting devices and a method for large area fabrication of such is provided. The method includes providing a continuous flexible substrate and printing one or more layers of light emitting devices comprised of layers of transparent conductor, light emitting material, dielectric and electrode on the flexible substrate. The array of light emitting devices includes a flexible substrate and one or more layers of light emitting devices on the flexible substrate. The one or more layers of light emitting devices include layers of transparent conductor, light emitting material, dielectric and electrode. | 2013-07-04 |
| 20130168707 | ARRAY SUBSTRATE STRUCTURE OF DISPLAY PANEL AND METHOD OF MAKING THE SAME - An array substrate structure of a display panel includes a substrate, a plurality of first wirings, a first patterned insulating layer, a plurality of second wirings, a plurality of first protective patterns, and a plurality of second protective patterns. The substrate has a wiring region. The first wirings are disposed in the wiring region. The first patterned insulating layer is disposed on the first wirings. The second wirings are disposed on the first patterned insulating layer. The first protective patterns are disposed in the wiring region and disposed on the corresponding second wiring, respectively, where the first protective pattern includes a semiconductor material. The second protective patterns are disposed on the corresponding first protective pattern, respectively, where the second protective pattern includes an inorganic insulating material. | 2013-07-04 |
| 20130168708 | METHOD FOR DISPOSING FINE OBJECTS, APPARATUS FOR ARRANGING FINE OBJECTS, ILLUMINATING APPARATUS AND DISPLAY APPARATUS - This method for disposing fine objects, in a substrate preparing step, prepares a substrate having specified positions where fine objects ( | 2013-07-04 |
| 20130168709 | LIGHT EMITTING DIODE DEVICE WITH MULTIPLE LIGHT EMITTING DIODES - A light emitting diode (LED) device includes a substrate having a top surface, a first LED and a second LED arranged on the top surface of the substrate, and a lens arranged over the light emitting surface of the first and second LEDs. The first and second LEDs each have a light emitting surface away from the top surface of the substrate. A first wavelength of light emitted from the first LED is shorter than a second wavelength of light emitted from the second LED. The lens includes a convergent part located right above the second LED and a divergent part located right above the first LED. | 2013-07-04 |
| 20130168710 | SEMICONDUCTOR LIGHT SOURCE DEVICE - A semiconductor light source device is provided. The semiconductor light source device includes a light guide, at least one semiconductor light source set and at least one light transformation coupler. The light transformation coupler is disposed between the semiconductor light source set and the light guide for guiding the light emitted from the semiconductor light source set to the light guide. The light transformation coupler has an inclined surface and a curved surface. The inclined surface is a multi-level inclined surface with several slopes. | 2013-07-04 |
| 20130168711 | LIGHT EMITTING DEVICE - Disclosed are a light emitting device, a method of manufacturing the same, a light emitting device package, and a lighting system. The light emitting device includes: a substrate; a first conductive semiconductor layer on the substrate; an active layer on the first conductive semiconductor layer; a second conductive semiconductor layer; and a nitride semiconductor layer having a refractive index less than a refractive index of the second conductive semiconductor layer on the second conductive semiconductor layer. | 2013-07-04 |
| 20130168712 | Organic Light-Emitting Display Apparatus and Method of Manufacturing the Same - An organic light-emitting display apparatus includes: a substrate; a pixel electrode disposed on the substrate; a counter electrode disposed on the pixel electrode and capable of transmitting light; an organic emission layer disposed between the pixel electrode and the counter electrode so as to emit light toward at least the counter electrode; and a light-transmitting layer disposed on the counter electrode along a path of light emitted from the organic emission layer and including at least one inorganic film and organic films separated by the inorganic film. At least two of the organic films each include a first material having a first refractive index and a second material having a second refractive index. The first refractive index is greater than the second refractive index, and the first material is dispersed in the second material in the form of plurality of particles. | 2013-07-04 |
| 20130168713 | LED DEVICE HAVING UNIFORM DISTRIBUTION OF LIGHT INTENSITY OF LIGHT FILED - An LED device includes a substrate having a top surface, an LED chip arranged on the top surface of the substrate, an encapsulant arranged on the top surface of the substrate and covering the LED chip, and an optical element arranged over the encapsulant. The optical element includes a light input surface adjacent to the encapsulant and a light output surface opposite to the light input surface. The refractive index of the optical element is larger than that of the encapsulant. | 2013-07-04 |
| 20130168714 | LIGHT EMITTING DIODE PACKAGE STRUCTURE - A light emitting diode package structure is provided, including a substrate, a seal assembly, an optical element, at least one light emitting diode chip, and a packaging material layer. The seal assembly is disposed on the substrate. The optical element is disposed on the seal assembly, and an enclosed space is formed between the optical element, the seal assembly, and the substrate. The light emitting diode chip is disposed on the substrate and located in the enclosed space. The packaging material layer is located in the enclosed space and at least disposed on an upper surface of the light emitting diode chip, wherein the packaging material layer includes a liquid with high viscosity and a plurality of solid particles, and the viscosity of the liquid with high viscosity is more than 3000 mPa·s. | 2013-07-04 |
| 20130168715 | LIGHT EMITTING ELEMENT - A light emitting element includes a resonator structure which has a first reflecting member, a second reflecting member, and a light emission layer placed between the first reflecting member and the second reflecting member, and part of light resonated between the first reflecting member and the second reflecting member is transmitted through the first reflecting member or the second reflecting member in the resonator structure. A wavelength at which a resonator output spectrum from the resonator structure has a maximum value is located between a wavelength at which an inner light emission spectrum of the light emission layer has a maximum value and a wavelength at which relative luminous efficiency has a maximum value. | 2013-07-04 |
| 20130168716 | LIGHT EMITTING DIODE ASSEMBLY HAVING A DEFORMABLE LENS - A light emitting diode assembly includes a base, a light emitting chip mounted on the base, an elastic lens covering the light emitting chip, two rotation members rotatably arranged on the base, and two stopper poles fixed on the base. The two rotation members are capable of driving the elastic lens to rotate with respect to the two stopper poles. The stopper poles compress the elastic lens to cause the elastic lens to deform resiliently when the elastic lens is rotated by the rotation members to engage with the stopper poles. | 2013-07-04 |
| 20130168717 | ENCAPSULATING SHEET, PRODUCING METHOD OF OPTICAL SEMICONDUCTOR DEVICE, OPTICAL SEMICONDUCTOR DEVICE, AND LIGHTING DEVICE - An encapsulating sheet, encapsulating an optical semiconductor element, includes a first layer which contains a phosphor and a second layer which contains a phosphor, is laminated on the first layer, and encapsulates the optical semiconductor element. The ratio of the volume of the phosphor in the first layer to that of the phosphor in the second layer is 90:10 to 55:45. | 2013-07-04 |
| 20130168718 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND LED MODULE - A semiconductor light emitting device includes a semiconductor laminate including first and second conductivity-type semiconductor layers and an active layer formed therebetween, and divided into first and second regions. At least one contact hole is formed on the first region and connected to a portion of the first conductivity-type semiconductor layer through the active layer. A first electrode is formed to be connected to the first conductivity-type semiconductor layer of the first region and connected to the second conductivity-type semiconductor layer of the second region through the at least one contact hole. A second electrode is formed and connected to the second conductivity-type semiconductor layer of the first region. First and second electrode pads and a support substrate are formed. | 2013-07-04 |
| 20130168719 | METHOD FOR FORMING A LIGHT CONVERSION MATERIAL - A method and system for manufacturing a light conversion structure for a light emitting diode (LED) is disclosed. The method includes forming a transparent, thermally insulating cover over an LED chip. The method also includes dispensing a conversion material onto the cover to form a conversion coating on the cover, and encapsulating the LED, the silicone cover, and the conversion coating within an encapsulant. Additional covers and conversion coatings can be added. | 2013-07-04 |
| 20130168720 | Optoelectronic Device - An optoelectronic component includes at least one radiation-emitting semiconductor element. At least one converter element is used to convert the electromagnetic radiation emitted by the semiconductor element. At least one filter element, which includes filter particles or is formed by the same, scatters and/or absorbs at least one pre-definable wavelength range of the electromagnetic radiation emitted by the semiconductor element more strongly than a wavelength range that is different from the predefined wavelength range. The filter particles have a d50 value, measured in Q0, of at least 0.5 nm to no more than 500 nm and/or the filter particles are designed at least in some areas in a thread-like manner and in a thread-like region have a diameter that is at least 0.5 nm and no more than 500 nm. | 2013-07-04 |
| 20130168721 | LIGHT EMITTING DEVICE - A light emitting device includes a light transmissive substrate, a semiconductor layer formed on the substrate, and having an n-type layer, a light emitting layer, and a p-type layer, a reflective electrode formed on the semiconductor layer, and reflecting light from the light emitting layer toward the substrate, a barrier electrode formed on the reflective electrode, and a cover electrode formed on the barrier electrode. The reflective electrode includes a Ag layer, the cover electrode includes an layer, and the barrier electrode reduces interdiffusion between Ag and Al. | 2013-07-04 |
| 20130168722 | SURFACE-MOUNTING LIGHT EMITTING DIODE DEVICE AND METHOD FOR MANUFACTURING THE SAME - An SMT LED device includes an LED and a circuit board carrying the LED. The circuit board has two copper pads thereon, each being provided with a solder on an inner later side thereof which faces the other copper pad. The LED includes two pins and each pin includes a horizontal protrusion and a vertical portion. The LED is mounted on the circuit board between the two copper pads. The solders securely and electrically connect the two pins of the LED with the circuit board. | 2013-07-04 |
| 20130168723 | MOLDED PACKAGE FOR LIGHT EMITTING DEVICE - The present invention provides a molded package for a light emitting device including a molded resin and first and second leads, the exposed surface of the first lead having a first and second edge portions opposed to each other so as to put a mounting area therebetween in a first direction, the first and second edge portions respectively having one first cutout and second cutouts, the mounting area having a size not less than a distance between the first and the second cutouts and less than a distance between the first the second edge portions in the first direction. | 2013-07-04 |
| 20130168724 | WARM WHITE LIGHT LED CHIP WITH HIGH BRIGHTNESS AND HIGH COLOR RENDERING - A warm white light LED chip with high brightness and high color rendering includes a white light part emitting a white light, a colored light part emitting a colored light with a wavelength of 580 nm-660 nm, an N electrode ( | 2013-07-04 |
| 20130168725 | OPTOELECTRONIC DEVICE COMPRISING NANOSTRUCTURES OF HEXAGONAL TYPE CRYSTALS - An optoelectronic device comprising: a first conductive layer, a second conductive layer, an active layer between the first conductive layer and the second conductive layer, wherein the active layer comprises a submicrometer size structure of hexagonal type crystals of an element or alloy of elements selected from the carbon group. | 2013-07-04 |
| 20130168726 | MOLD FOR LIGHT-EMITTING DEVICE PACKAGE - A light-emitting device package mold and a method of manufacturing a lens of a light-emitting device package. The light-emitting device package mold includes a convex unit, an inner circumference of which has a hemispherical shape; a flat panel unit that forms a flat panel by extending from an edge of the convex unit; a cylindrical unit extending in a vertical direction with respect to an upper surface of the flat panel unit; and an injection hole and a discharge hole that penetrate through the convex unit, wherein the discharge hole is formed in a horizontal direction with respect to the flat panel unit. | 2013-07-04 |
| 20130168727 | ORGANOSILOXANE BLOCK COPOLYMER - An organosiloxane block copolymer includes 65 to 90 mol % of diorganosiloxane units having the formula R | 2013-07-04 |
| 20130168728 | LATERAL INSULATED-GATE BIPOLAR TRANSISTOR AND MANUFACTURING METHOD THEREOF - A lateral insulated-gate bipolar transistor includes a buried insulation layer which opens only part of the collector ion implantation region and isolates the other regions, thereby reducing the loss by the turn-off time. The lateral insulated-gate bipolar transistor further includes a deep ion implantation region formed to face towards the open part of the collector ion implantation region, thereby decreasing the hole current injected into a base region under an emitter ion implantation region, and thereby greatly increasing the latch-up current level by relatively increasing the hole current injected into the deep ion implantation region having no latch-up effect. | 2013-07-04 |
| 20130168729 | Voltage-Sustaining Layer Consisting of Semiconductor and Insulator Containing Conductive Particles for Semiconductor Device - A semiconductor device has at least a cell between two opposite main surfaces. Each cell has a first device feature region contacted with the first main surface and a second device feature region contacted with the second main surface. There is a voltage-sustaining region between the first device feature region and the second device feature region, which includes at least a semiconductor region and an insulator region containing conductive particles. The semiconductor region and the insulator region contact directly with each other. The structure of such voltage-sustaining region can not only be used to implement high-voltage devices, but further be used as a junction edge technique of high-voltage devices. | 2013-07-04 |
| 20130168730 | SEMICONDUCTOR DEVICE HAVING LATERAL INSULATED GATE BIPOLAR TRANSISTOR - A semiconductor device having a lateral insulated gate bipolar transistor includes a first conductivity type drift layer, a second conductivity type collector region formed in a surface portion of the drift layer, a second conductivity type channel layer formed in the surface portion of the drift layer, a first conductivity type emitter region formed in a surface portion of the channel layer, and a hole stopper region formed in the drift layer and located between the collector region and the emitter region. Holes are injected from the collector region into the drift layer and flow toward the emitter region through a hole path. The hole stopper region blocks a flow of the holes and narrows the hole path to concentrate the holes. | 2013-07-04 |
| 20130168731 | SEMICONDUCTOR POWER DEVICE HAVING WIDE TERMINATION TRENCH AND SELF-ALIGNED SOURCE REGIONS FOR MASK SAVING - A trench semiconductor power device with a termination area structure is disclosed. The termination area structure comprises a wide trench and a trenched field plate formed not only along trench sidewall but also on trench bottom of the wide trench by doing poly-silicon CMP so that the body ion implantation is blocked by the trenched field plate on the trench bottom to prevent the termination area underneath the wide trench from being implanted. Moreover, a contact mask is used to define both trenched contacts and source regions of the device for saving a source mask. | 2013-07-04 |
| 20130168732 | Vertical BJT and SCR for ESD - An electrostatic discharge (ESD) protection device includes a well region formed from semiconductor material with a first doping type and a floating base formed from semiconductor material with a second doping type. The floating base is disposed vertically above the well region. The ESD also includes a first terminal receiving region formed from semiconductor material with a third doping type. The first terminal receiving region is disposed vertically above the floating base. The ESD further includes a second terminal receiving region. The second terminal receiving region is laterally spaced apart from the first terminal receiving region by silicon trench isolation (STI) region. In some embodiments, the second terminal receiving region is formed from semiconductor material with the third doping type to form a bipolar junction transmitter (BJT) or with a fourth doping type to form a silicon controlled rectifier (SCR). | 2013-07-04 |
| 20130168733 | SEMICONDUCTOR-STACKED SUBSTRATE, SEMICONDUCTOR CHIP, AND METHOD FOR PRODUCING SEMICONDUCTOR-STACKED SUBSTRATE - Disclosed is a semiconductor-stacked substrate having a substrate, and a plurality of semiconductor layers which are different in thermal expansion coefficient from the substrate, and are formed in a plurality of regions of a surface of the substrate, respectively. Each semiconductor layer has a growth plane that is a nonpolar plane or a semi-polar plane, and has different thermal expansion coefficients between along a first axis and a second axis orthogonal to each other and parallel to the surface of the substrate. The following mathematical formula 1 is satisfied. D | 2013-07-04 |
| 20130168734 | EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a semiconductor device of normally-off operation type having a low on-resistance. An epitaxial substrate for it includes: a base substrate; a channel layer made of a first group-III nitride having a composition of In | 2013-07-04 |
| 20130168735 | SEMICONDUCTOR WAFER AND INSULATED GATE FIELD EFFECT TRANSISTOR - Provided is a technique capable of realizing an insulated gate (MIS-type) P-HEMT structure with good transistor characteristics such as an improved carrier mobility of a channel layer and a reduced influence from interface states. A semiconductor wafer includes a base wafer, a first crystalline layer, and an insulating layer. The base wafer, the first crystalline layer, and the insulating layer are stacked in the order of the base wafer, the first crystalline layer, and the insulating layer. The first crystalline layer is made of In | 2013-07-04 |
| 20130168736 | METHOD FOR GROWING CONFORMAL EPI LAYERS AND STRUCTURE THEREOF - A method for forming a conformal buffer layer of uniform thickness and a resulting semiconductor structure are disclosed. The conformal buffer layer is used to protect highly-doped extension regions during formation of an epitaxial layer that is used for inducing mechanical stress on the channel region of transistors. | 2013-07-04 |
| 20130168737 | Integrated Heterojunction Semiconductor Device and Method for Producing an Integrated Heterojunction Semiconductor Device - A method of producing a semiconductor component is provided. The method includes providing a silicon substrate having a <111>-surface defining a vertical direction, forming in the silicon substrate at least one electronic component, forming at least two epitaxial semiconductor layers on the silicon substrate to form a heterojunction above the <111>-surface, and forming a HEMT-structure above the <111>-surface. | 2013-07-04 |
| 20130168738 | SEMICONDUCTOR WAFER, INSULATED GATE FIELD EFFECT TRANSISTOR, AND METHOD FOR PRODUCING SEMICONDUCTOR WAFER - Provided is a semiconductor wafer including a base wafer, a first crystalline layer, a second crystalline layer, and an insulating layer that are positioned in the stated order, the semiconductor wafer further including: a third crystalline layer positioned either between the first crystalline layer and the second crystalline layer or between the base wafer and the first crystalline layer. The second crystalline layer and the third crystalline layer are made of a crystal that either lattice matches or pseudo lattice matches a crystal making the first crystalline layer, and has a wider band gap than the crystal making the first crystalline layer. The third crystalline layer includes a first atom that will be a donor or an acceptor. When the third crystalline layer includes a first atom that will be a donor, the second crystalline layer includes a second atom that will be an acceptor. | 2013-07-04 |
| 20130168739 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME - A vertical semiconductor device in which pinch-off characteristics and breakdown voltage characteristics can be stably improved by fixing the electric potential of a p-type GaN barrier layer with certainty is provided. The semiconductor device includes a GaN-based stacked layer having an opening, a regrown layer including a channel located so as to cover a wall surface of the opening, an n | 2013-07-04 |
| 20130168740 | INTEGRATED COMPACT MEMS DEVICE WITH DEEP TRENCH CONTACTS - A compact MEMS motion sensor device is provided, including a CMOS substrate layer, with plural anchor posts having an isolation oxide layer surrounding a conductive layer. On one side of CMOS substrate layer, the device further includes a field oxide (FOX) layer, a first set and a second set of implant doped silicon areas, a first polysilicon layer, an oxide layer embedded with plural metal layers interleaved with via hole layers, a Nitride deposition layer, an under bump metal (UBM) layer and a plurality of solder spheres. On the other side of CMOS substrate layer, the present invention further includes a backside interconnect isolation oxide layer, a first MEMS bonding layer, a first metal compound layer, a second MEMS bonding layer, a MEMS layer, a first MEMS eutectic bonding layer, a second metal compound layer, a second MEMS eutectic bonding layer, and a MEMS cap layer. | 2013-07-04 |
| 20130168741 | COMPLEMENTARY JUNCTION FIELD EFFECT TRANSISTOR DEVICE AND ITS GATE-LAST FABRICATION METHOD - The disclosure relates to a complementary junction field effect transistor (c-JFET) and its gate-last fabrication method. The method of fabricating a semiconductor device includes: forming a dummy gate on a first conductivity type wafer, forming sidewall spacers on opposite sides of the dummy gate, forming a source and a drain regions on the opposite sides of the dummy gate, removing the dummy gate, forming a first semiconductor region of a second conductivity type in an opening exposed through the removing the dummy gate, and forming a gate electrode in the opening. | 2013-07-04 |
| 20130168742 | INTEGRATED CIRCUIT CONFIGURATION AND FABRICATING METHOD THEREOF - An integrated circuit configuration includes a substrate, a diffusion region, a gate structure, an extension conductor structure, a dielectric layer, a contact structure, and a metal conductor line. The diffusion region is formed in the substrate. The gate structure is formed over the substrate and spanned across the diffusion region. The extension conductor structure is formed over the semiconductor substrate and contacted with the diffusion region. The extension conductor structure is extended externally to a first position along a surface of the substrate, wherein the first position is outside the diffusion region. The dielectric layer is formed over the substrate, the gate structure and the extension conductor structure. The contact structure is penetrated through the dielectric layer to be contacted with the first position of the extension conductor structure. The metal conductor line is formed on the dielectric layer and contacted with the contact structure. | 2013-07-04 |
| 20130168743 | STRAINED TRANSISTOR STRUCTURE - A strain enhanced transistor is provided having a strain inducing layer overlying a gate electrode. The gate electrode has sloped sidewalls over the channel region of the transistor. | 2013-07-04 |
| 20130168744 | Semiconductor Device Having a Metal Gate and Fabricating Method Thereof - The present invention provides a method of forming a semiconductor device having a metal gate. A substrate is provided and a gate dielectric and a work function metal layer are formed thereon, wherein the work function metal layer is on the gate dielectric layer. Then, a top barrier layer is formed on the work function metal layer. The step of forming the top barrier layer includes increasing a concentration of a boundary protection material in the top barrier layer. Lastly, a metal layer is formed on the top barrier layer. The present invention further provides a semiconductor device having a metal gate. | 2013-07-04 |
| 20130168745 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a gate structure in which a plurality of interlayer dielectric layers and a plurality of gate electrodes are alternately stacked; a pass gate electrode lying under the gate structure; a sub channel hole defined in the pass gate electrode; a pair of main channel holes defined through the gate structure and communicating with the sub channel hole; a channel layer formed on inner walls of the pair of main channel holes and the sub channel hole; and a metallic substance layer contacting the channel layer in the sub channel hole. | 2013-07-04 |
| 20130168746 | SEMICONDUCTOR DEVICE AND RELATED MANUFACTURING METHOD - A semiconductor device manufacturing method includes providing a mask on a semiconductor member. The method further includes providing a dummy element to cover a portion of the mask that overlaps a first portion of the semiconductor member and to cover a second portion of the semiconductor member. The method further includes removing a third portion of the semiconductor member, which has not been covered by the mask or the dummy element. The method further includes providing a silicon compound that contacts the first portion of the semiconductor member. The method further includes removing the dummy element to expose and to remove the second portion of the semiconductor member. The method further includes forming a gate structure that overlaps the first portion of the semiconductor member. The first portion of the semiconductor member is used as a channel region and is supported by the silicon compound. | 2013-07-04 |
| 20130168747 | Semiconductor Device and Method for Manufacturing A Semiconductor Device - The present invention discloses a method for manufacturing a semiconductor device. According to the method provided by the present disclosure, a dummy gate is formed on a substrate, removing the dummy gate to form an opening having side walls and a bottom gate, a dielectric material is formed on at least a portion of the sidewalls of the opening and the bottom surface of the opening, and a pre-treatment is performed to a portion of the dielectric material layer on the sidewalls of the opening, and thus the properties of the dielectric material is changed, and then the pre-treated dielectric material on the sidewalls of the opening is removed by a selective process. The semiconductor device manufactured by using the method of the present disclosure is capable of effectively reducing parasitic capacitance. | 2013-07-04 |
| 20130168748 | FIN FET STRUCTURE WITH DUAL-STRESS SPACERS AND METHOD FOR FORMING THE SAME - This application discloses a Fin FET structure and a method for forming the same. In the Fin FET structure, there are lower stress spacers disposed over the lower portion of the fin's opposite sidewalls, asserting one stress type to suppress the carrier mobility; there are also upper stress spacers disposed over the upper portion of the fin's opposite sidewalls, asserting an opposite stress type to increase the carrier mobility. Therefore, the leakage current in the fin FET is reduced and the device performance is improved. In the method, the stress spacers are formed by depositing stress layers and etching back the stress layers, where stress types and magnitudes are controllable, resulting in a simple process. | 2013-07-04 |
| 20130168749 | BORDERLESS CONTACT STRUCTURE EMPLOYING DUAL ETCH STOP LAYERS - Each gate structure formed on the substrate includes a gate dielectric, a gate conductor, a first etch stop layer, and a gate cap dielectric. A second etch stop layer is formed over the gate structures, gate spacers, and source and drain regions. A first contact-level dielectric layer and a second contact-level dielectric layer are formed over the second etch stop layer. Gate contact via holes extending at least to the top surface of the gate cap dielectrics are formed. Source/drain contact via holes extending to the interface between the first and second contact-level dielectric layers are subsequently formed. The various contact via holes are vertically extended by simultaneously etching exposed gate cap dielectrics and exposed portions of the first contact-level dielectric layer, then by simultaneously etching the first and second etch stop layers. Source/drain contact vias self-aligned to the outer surfaces gate spacers are thereby formed. | 2013-07-04 |
| 20130168750 | PHOTODIODE ARRAY AND METHODS OF FABRICATION - Photodiode arrays and methods of fabrication are provided. One photodiode array includes a silicon wafer having a first surface and an opposite second surface and a plurality of conductive vias through the silicon wafer. The photodiode array further includes a patterned doped epitaxial layer on the first surface, wherein the patterned doped epitaxial layer and the substrate form a plurality of diode junctions. A patterned etching defines an array of the diode junctions. | 2013-07-04 |
| 20130168751 | HIGH-K METAL GATE RANDOM ACCESS MEMORY - The instant disclosure relates to a high-k metal gate random access memory. The memory includes a substrate, a plurality of bit line units, source regions, gate structures, drain regions, word line units, and capacitance units. The substrate has a plurality of trenches, and the bit line units are arranged on the substrate. The source regions are disposed on the bit line units, and the gate structures are disposed on the source regions. Each gate structure has a metal gate and a channel area formed therein. The gate structures are topped with the drain regions. The word lines units are arranged between the source and drain regions The capacitance units are disposed on the drain regions. Another memory is also disclosed, where each drain region and a portion of each gate structure are disposed in the respective capacitance unit, with the drain region being a lower electrode layer. | 2013-07-04 |
| 20130168752 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a substrate including a surface, a channel layer formed on the surface of the substrate, which protrudes perpendicularly from the surface, and a plurality of interlayer dielectric layers and a plurality of gate electrode layers alternately stacked along the channel layer, wherein the plurality of gate electrode layers protrude from the plurality of interlayer dielectric layers. | 2013-07-04 |
| 20130168753 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - The technology of the present invention relates to a non-volatile memory device and a fabrication method thereof. The non-volatile memory device includes channel layers protruding vertically from a substrate, a plurality of hole-supply layers and a plurality of gate electrodes, which are alternately stacked along the channel layers, and a memory film interposed between the channel layers and the gate electrodes and between the hole-supply layers and the gate electrodes. According to this technology, the hole-supply layers are formed between the memory cells such that sufficient holes are supplied to the memory cells during the erase operation of the memory cells, whereby the erase operation of the memory cells is smoothly performed without using the GIDL current, and the properties of the device are protected from being deteriorated due to program/erase cycling. | 2013-07-04 |
| 20130168754 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE WITH INCREASED RELIABILITY - A method of forming a semiconductor device is provided. The method includes providing a semiconductor substrate, and forming a first conductive layer over the substrate. In one example, an insulating layer may be formed over the semiconductor substrate, with the first conductive layer being formed over the insulating layer. The method also includes forming an interpoly dielectric layer over the first conductive layer. In this regard, forming the interpoly dielectric layer includes forming a silicon oxide layer, and subjecting the silicon oxide layer to oxide densification to form an oxide-densified silicon oxide layer. And the method includes forming a second conductive layer over the interpoly dielectric layer. | 2013-07-04 |
| 20130168755 | SINGLE POLY EEPROM AND METHOD FOR FABRICATING THE SAME - A single poly EEPROM (Electrically Erasable Programmable Read Only Memory), which may include at least one of the following: (1) A second conductive type well formed on and/or over a semiconductor substrate. (2) A first conductive type source and drain regions formed in the second conductive type well. The single poly EEPROM may include at least one of: (a) A tunnel oxide layer formed on and/or over the second conductive type well. (b) A floating gate formed on and/or over the tunnel oxide layer and doped with second conductive type impurity ions. (c) A first conductive type impurity region formed in the second conductive type well adjacent to the floating gate. The floating gate may be configured such that a concentration of a region of the floating gate adjacent to the drain region is higher than that of the other region of the floating gate adjacent to the impurity region. | 2013-07-04 |
| 20130168756 | SOURCE/DRAIN ZONES WITH A DELECTRIC PLUG OVER AN ISOLATION REGION BETWEEN ACTIVE REGIONS AND METHODS - Devices, memory arrays, and methods are disclosed. In an embodiment, one such device has a source/drain zone that has first and second active regions, and an isolation region and a dielectric plug between the first and second active regions. The dielectric plug may extend below upper surfaces of the first and second active regions and may be formed of a dielectric material having a lower removal rate than a dielectric material of the isolation region for a particular isotropic removal chemistry. | 2013-07-04 |
| 20130168757 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a channel layer extending in a vertical direction from a substrate, a plurality of interlayer dielectric layers and word lines alternately stacked along the channel layer over the substrate; a bit line formed under plurality of interlayer dielectric layers and word lines, coupled to the channel layer, and extending in a direction crossing the word lines, and a common source layer coupled to the channel layer and formed over the plurality of interlayer dielectric layers and word lines. | 2013-07-04 |
| 20130168758 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed, in which a buried gate region is formed, a nitride film spacer is formed at sidewalls of the buried gate region, and the spacer is etched in an active region in such a manner that the spacer remains in a device isolation region. Thus, if a void occurs in the device isolation region, the spacer can prevent a short-circuit from occurring between the device isolation region and its neighboring gates. | 2013-07-04 |
| 20130168759 | FIELD EFFECT TRANSISTOR WITH A VERTICAL CHANNEL AND FABRICATION METHOD THEREOF - Disclosed herein is a field effect transistor with a vertical channel and a fabrication method thereof. A channel region of the field effect transistor is a circular ring-shaped Si platform, which is formed over a substrate and perpendicular to the substrate; a source, which is made of polysilicon, is located at an upper end of the Si platform; a drain is disposed at an outside of a lower end of the circular ring-shaped Si platform; a gate is placed on an outer side surface of the circular ring-shaped Si platform; and an inside of the circular ring-shaped Si platform is filled with a dielectric material. In comparison with the conventional vertical structure MOSFET with a Si platform, the circular ring-shaped structure field effect transistor according to the invention can effectively suppress the short channel effect and improve the device performance. | 2013-07-04 |
| 20130168760 | TRENCH MOSFET WITH RESURF STEPPED OXIDE AND DIFFUSED DRIFT REGION - A trench MOSFET with split gates and diffused drift region for on-resistance reduction is disclosed. Each of the split gates is symmetrically disposed in the middle of the source electrode and adjacent trench sidewall of a deep trench. The inventive structure can save a mask for definition of the location of the split gate electrodes. Furthermore, the fabrication method can be implemented more reliably with lower cost. | 2013-07-04 |
| 20130168761 | SEMICONDUCTOR POWER DEVICE HAVING IMPROVED TERMINATION STRUCTURE FOR MASK SAVING - A improved termination structure for semiconductor power devices is disclosed, comprising a trenched field plate formed not only along trench sidewall but also on trench bottom of the wide termination trench by doing poly-silicon CMP so that body ion implantation is blocked by the trenched field plate on the trench bottom to prevent a body region formation underneath the trench bottom of the wide termination trench, degrading avalanche voltage. | 2013-07-04 |
| 20130168762 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer of a first conductivity type having a first surface and a second surface, a source region disposed on the first surface, a gate region disposed on the first surface adjacent the source region, and a drain region disposed on the first surface. The semiconductor device also includes a pair of charge control trenches disposed between the gate region and the drain region. Each of the pair of charge control trenches is characterized by a width and includes a first dielectric material disposed therein and a second material disposed internal to the first dielectric material. Additionally, a concentration of doping impurities present in the semiconductor layer of the first conductivity type and a distance between the pair of charge control trenches define an electrical characteristic of the semiconductor device that is independent of the width of each of the pair of charge control trenches. | 2013-07-04 |
| 20130168763 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An oxide film is formed by STI in a silicon surface region in which a substrate potential heavily doped diffusion layer and a source heavily doped diffusion layer are to be provided later between trenches at predetermined intervals. The oxide film is removed after the trench is formed, to thereby form a region which is lower than a surrounding surface. Thus, in the vertical MOS transistor having a trench structure which includes a side spacer, a silicide on a gate electrode embedded in the trench and a silicide on the substrate potential heavily doped diffusion layer and the source heavily doped diffusion layer can be separated from each other. | 2013-07-04 |
| 20130168764 | TRENCH SEMICONDUCTOR POWER DEVICE HAVING ACTIVE CELLS UNDER GATE METAL PAD - A trench semiconductor power device having active cells under gate metal pad to increase total active area for lowering on-resistance is disclosed. The gate metal pad is not only for gate wire bonding but also for active cells disposition. Therefore, the device die can be shrunk so that the number of devices per wafer is increased for die cost reduction. Moreover, the device can be packaged into smaller type package for further cost reduction. | 2013-07-04 |
| 20130168765 | TRENCH DMOS DEVICE WITH IMPROVED TERMINATION STRUCTURE FOR HIGH VOLTAGE APPLICATIONS - A termination structure is provided for a semiconductor device. The termination structure includes a semiconductor substrate having an active region and a termination region. A termination trench is located in the termination region and extends from a boundary of the active region toward an edge of the semiconductor substrate. A MOS gate is formed on a sidewall of the termination trench adjacent the boundary. At least one guard ring trench is formed in the termination region on a side of the termination trench remote from the active region. A termination structure oxide layer is formed on the termination trench and the guard ring trench. A first conductive layer is formed on a backside surface of the semiconductor substrate. A second conductive layer is formed atop the active region and the termination region. | 2013-07-04 |
| 20130168766 | DRAIN EXTENDED MOS TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A drain extended MOS (DEMOS) transistor including at least one of: (1) A p-type epitaxial layer grown over an n-type semiconductor substrate. (2) An n-type well formed in a portion of the epitaxial layer. (3) A p-type drift region formed in another portion of the epitaxial layer. (4) A p-type source region formed in the well. (5) A p-type drain region formed in the drift region and spaced apart from the source region inside the epitaxial layer. (6) An n-type channel region extending between the drift region and the source region. (7) A gate structure formed over the channel region. (8) An n-type buried layer having a contact surface with the well and the drift region and formed in the epitaxial layer. A region of the buried layer has surface contact with the drift region and has a relatively low dopant concentration compared to other regions. | 2013-07-04 |
| 20130168767 | Lateral Diffused Metal-Oxide-Semiconductor Device - The present invention provides a lateral diffused metal-oxide-semiconductor device including a first doped region, a second doped region, a third doped region, a gate structure, and a contact metal. The first doped region and the third doped region have a first conductive type, and the second doped region has a second conductive type. The second doped region, which has a racetrack-shaped layout, is disposed in the first doped region, and has a long axis. The third doped region is disposed in the second doped region. The gate structure is disposed on the first doped region and the second doped region at a side of the third doped region. The contact metal is disposed on the first doped region at a side of the second doped region extending out along the long axis, and is in contact with the first doped region. | 2013-07-04 |
| 20130168768 | SEMICONDUCTOR DEVICE WITH HIGH BREAKDOWN VOLTAGE AND MANUFACTURE THEREOF - A semiconductor device includes: first and second n-type wells formed in p-type semiconductor substrate, the second n-type well being deeper than the first n-type well; first and second p-type backgate regions formed in the first and second n-type wells; first and second n-type source regions formed in the first and second p-type backgate regions; first and second n-type drain regions formed in the first and second n-type wells, at positions opposed to the first and second n-type source regions, sandwiching the first and the second p-type backgate regions; and field insulation films formed on the substrate, at positions between the first and second p-type backgate regions and the first and second n-type drain regions; whereby first transistor is formed in the first n-type well, and second transistor is formed in the second n-type well with a higher reverse voltage durability than the first transistor. | 2013-07-04 |
| 20130168769 | P-CHANNEL LDMOS TRANSISTOR AND METHOD OF PRODUCING A P-CHANNEL LDMOS TRANSISTOR - The p-channel LDMOS transistor comprises a semiconductor substrate ( | 2013-07-04 |
| 20130168770 | HIGH-VOLTAGE OXIDE TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A high-voltage oxide transistor includes a substrate; a channel layer disposed on the substrate; a gate electrode disposed on the substrate to correspond to the channel layer; a source contacting a first side of the channel layer; and a drain contacting a second side of the channel layer, wherein the channel layer includes a plurality of oxide layers, and none of the plurality of oxide layers include silicon. The gate electrode may be disposed on or under the channel layer. Otherwise, the gate electrodes may be disposed respectively on and under the channel layer. | 2013-07-04 |
| 20130168771 | Method of Forming CMOS FinFET Device - A CMOS FinFET device and method for fabricating a CMOS FinFET device is disclosed. An exemplary CMOS FinFET device includes a substrate including a first region and a second region. The CMOS FinFET further includes a fin structure disposed over the substrate including a first fin in the first region and a second fin in the second region. The CMOS FinFET further includes a first portion of the first fin comprising a material that is the same material as the substrate and a second portion of the first fin comprising a III-V semiconductor material deposited over the first portion of the first fin. The CMOS FinFET further includes a first portion of the second fin comprising a material that is the same material as the substrate and a second portion of the second fin comprising a germanium (Ge) material deposited over the first portion of the second fin. | 2013-07-04 |
| 20130168772 | SEMICONDUCTOR DEVICE FOR ELECTROSTATIC DISCHARGE PROTECTING CIRCUIT - A semiconductor device for an electrostatic discharge (ESD) protecting circuit connected to a pad is provided. The semiconductor device includes a semiconductor substrate of a first conductivity type; a plurality of metal oxide semiconductor transistors (MOSFETs) formed in the semiconductor substrate, and an isolation structure of a second conductivity type formed in the semiconductor substrate. The MOFETS are arranged in parallel. Drain electrodes of the MOSFETs are electrically connected to the pad, gate electrodes and source electrodes of the MOSFETs are connected to a constant voltage, and the gate electrodes extend in a first direction. The isolation structure includes a bottom and at least two side walls, wherein the bottom is located under the MOSFETs and the two side walls are located at two sides of the MOSFETs, and the side walls extend in the first direction. | 2013-07-04 |
| 20130168773 | High-K Metal Gate Electrode Structure Formed by Removing a Work Function on Sidewalls in Replacement Gate Technology - When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, the fill conditions upon filling in the highly conductive electrode metal, such as aluminum, may be enhanced by removing the final work function metal, for instance a titanium nitride material in P-channel transistors, only preserving a well-defined bottom layer. | 2013-07-04 |
| 20130168774 | SEMICONDUCTOR DEVICE - A semiconductor device may include a substrate including an active region defined by a device isolation layer, gate electrodes extending in a first direction on the substrate and spaced apart from each other, gate tabs extending in a second direction different from the first direction and connecting adjacent gate electrodes to each other, the gate tabs spaced apart from each other, and a first contact plug disposed on the active region under a space confined by the adjacent gate electrodes and adjacent gate tabs. The space may include a first region having a first width and a second region having a second width smaller than the first width, the first contact plug may be disposed on the active region under the second region. | 2013-07-04 |
| 20130168775 | METHODS FOR FORMING FIELD EFFECT TRANSISTOR DEVICES WITH PROTECTIVE SPACERS - A field effect transistor device prepared by a process including forming a first gate stack and a second gate stack on a substrate and depositing a first photoresist material over the second gate stack and a portion of the substrate. The process also includes implanting ions in exposed regions of the substrate to define a first source region and a first drain region adjacent to the first gate stack and depositing a first protective layer over the first source region, the first gate stack, the first drain region, and the first photoresist material. The process further includes removing portions of the first protective layer to expose the first photoresist material and to define a first spacer disposed on a portion of the first source region and a portion of the first drain region and removing the first photoresist material. | 2013-07-04 |
| 20130168776 | Complementary Metal Oxide Semiconductor (CMOS) Device Having Gate Structures Connected By A Metal Gate Conductor - A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region. | 2013-07-04 |
| 20130168777 | Integrated Circuit Including Gate Electrode Tracks Forming Gate Electrodes of Different Transistor Types and Linear Shaped Conductor Electrically Connecting Gate Electrodes - An integrated circuit includes a first gate electrode track and a second gate electrode track. The first gate electrode track includes a first gate electrode feature that forms an n-channel transistor as it crosses an n-diffusion region. The first gate electrode track does not cross a p-diffusion region. The second gate electrode track includes a second gate electrode feature that forms a p-channel transistor as it crosses a p-diffusion region. The second gate electrode track does not cross an n-diffusion region. The integrated circuit also includes a linear shaped conductor that crosses both the first and second gate electrode features in a reference direction perpendicular to the first and second gate electrode tracks. The linear shaped conductor provides electrical connection between the first and second gate electrode features. | 2013-07-04 |
| 20130168778 | Integrated Circuit Including Gate Electrode Tracks That Each Form Gate Electrodes of Different Transistor Types With Intervening Non-Gate-Forming Gate Electrode Track - A first gate electrode track includes a first gate electrode feature forming a first n-channel transistor with a first n-diffusion region and a second gate electrode feature forming a first p-channel transistor with a first p-diffusion region. A second gate electrode track includes a third gate electrode feature forming a second n-channel transistor with a second n-diffusion region and a fourth gate electrode feature forming a second p-channel transistor with a second p-diffusion region. A third gate electrode track is positioned between and parallel to the first and second gate electrode tracks, such that no other gate electrode track is positioned between the third gate electrode track and either of the first or second gate electrode tracks. The third gate electrode track is not interrupted between the first and second gate electrode tracks. The third gate electrode track does not include a gate electrode feature of any transistor. | 2013-07-04 |
| 20130168779 | MOS P-N JUNCTION DIODE WITH ENHANCED RESPONSE SPEED AND MANUFACTURING METHOD THEREOF - A MOS P-N junction diode includes a semiconductor substrate, a mask layer, a guard ring, a gate oxide layer, a polysilicon structure, a central conductive layer, a silicon nitride layer, a metal diffusion layer, a channel region, and a metal sputtering layer. For manufacturing the MOS P-N junction diode, a mask layer is formed on a semiconductor substrate. A gate oxide layer is formed on the semiconductor substrate, and a polysilicon structure is formed on the gate oxide layer. A guard ring, a central conductive layer and a channel region are formed in the semiconductor substrate. A silicon nitride layer is formed on the central conductive layer. A metal diffusion layer is formed within the guard ring and the central conductive layer. Afterwards, a metal sputtering layer is formed, and the mask layer is partially exposed. | 2013-07-04 |
| 20130168780 | METHOD AND STRUCTURE TO REDUCE FET THRESHOLD VOLTAGE SHIFT DUE TO OXYGEN DIFFUSION - Oxygen scavenging material embedded in an isolation structure provides improved protection of high dielectric constant (Hi-K) materials from oxygen contamination while avoiding alteration of work function and switching threshold shift in transistors including such Hi-K materials. | 2013-07-04 |
| 20130168781 | TWO-WAFER MEMS IONIZATION DEVICE - A microelectromechanical system (MEMS) assembly includes at least one emission source; a top wafer having a plurality of side walls and a generally horizontal portion, the horizontal portion having a thickness between a first side and a directly opposed second side, at least one window in the horizontal portion extending between the first and second sides and a transmission membrane across the at least one window; and a bottom wafer having a first portion with a first substantially planar surface, an intermediate surface directly opposed to the first substantially planar surface, a second portion with a second substantially planar surface, the at least one emission source provided on the second substantially planar surface; where the top wafer bonds to the bottom wafer at the intermediate surface and encloses a cavity within the top wafer and the bottom wafer. | 2013-07-04 |
