| 27th week of 2014 patent applcation highlights part 72 |
| Patent application number | Title | Published |
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| 20140189146 | METHOD AND APPARATUS FOR PLAYING LIVE CONTENT - A method for providing a client with a playlist of content segments accessible in a live streaming service provided in a Hypertext Transfer Protocol (HTTP) adaptive streaming format is provided. A live content processing method for a broadcast system includes transmitting and updating content-related information sent from a server to a client, checking, at the client, content segments accessible in real time and saving a previous content-related information, retrieving the content segments playable by referencing the previous content-related information, determining, at the client, whether the content requested for playback can be playable using a playlist, and notifying the user of the playback result. | 2014-07-03 |
| 20140189147 | METHOD AND APPARATUS FOR PLAYING LIVE CONTENT - A method for providing a client with a playlist of content segments accessible in a live streaming service provided in a Hypertext Transfer Protocol (HTTP) adaptive streaming format is provided. A live content processing method for a broadcast system includes transmitting and updating content-related information sent from a server to a client, checking, at the client, content segments accessible in real time and saving a previous content-related information, retrieving the content segments playable by referencing the previous content-related information, determining, at the client, whether the content requested for playback can be playable using a playlist, and notifying the user of the playback result. | 2014-07-03 |
| 20140189148 | SYSTEM AND METHOD FOR MANAGING AND ACCESSING MULTIPLE CONTENT FEEDS AND SUPPLEMENTAL CONTENT BY CONTENT PROVIDER USING AN ON-SCREEN INTERACTIVE INTERFACE - A system for a system administrator to distribute and manage multiple content feeds and supplemental content using an on-screen interactive interface includes: (a) a multimedia server configured for integrating streaming contents from various streaming content providers through a network, (b) a multimedia controller adapted for receiving broadcast contents from various broadcast systems, and the streaming contents from the multimedia server, and (c) a multimedia control platform for a user to manage, access, and select the broadcast and streaming contents from the multimedia server through an on-screen interactive interface, and to display selected contents on an end user device. The broadcast and streaming contents further include supplemental contents from various streaming content providers, and advertisements from various advertisers with the advertisement links stored in the multimedia control platform to allow the user to access the advertisement content through the links without storing the actual advertisement content in the multimedia server. | 2014-07-03 |
| 20140189149 | ROUTING OF DATA INCLUDING MULTIMEDIA BETWEEN ELECTRONIC DEVICES - Rerouting apparatus for rerouting data including multimedia data. The apparatus is for association with electronic equipment and allows for routing the data to a device regarded as the most convenient for playing the media. The apparatus comprises an announcer device for indicating to surrounding equipment that associated equipment is available for rerouting, thereby to enable receipt of rerouted communications therefrom, and a scout device for scanning surroundings of the associated equipment to find out about compatible equipment in the vicinity, thereby to reroute communications thereto. The apparatus may be attached to any device having data processing capability, to enable rerouting of data and communications therebetween. | 2014-07-03 |
| 20140189150 | METHOD FOR STREAMING VIDEO CONTENT, EDGE NODE AND CLIENT ENTITY REALIZING SUCH A METHOD - Method for streaming video content from a video server entity to a client entity via a core network and an aggregation network connected through an edge node. The server entity can be either the origin server or a serving node in a CDN that acts as a surrogate server. The video content is offered by the video server entity as a set of consecutive fragments (or chunks or segments), each fragment of this set of consecutive fragments being offered in a plurality of quality levels corresponding to respective encoded bit rates. The method comprises the steps of: transmitting via the network from said client entity to said video server entity via said edge node one or more requests for fragments with a target quality level of said video content to be displayed at said client entity; and receiving at said client entity via said network one or more replies to the requests containing fragments with said target quality levels. The method further comprises the steps of said edge node evaluating the available throughput for said client entity to transmit said fragments to said client entity over said aggregation network and said edge node informing said client entity about said available throughput. | 2014-07-03 |
| 20140189151 | METHOD AND SYSTEM FOR SPOOLING DIAMETER TRANSACTIONS - A method for spooling diameter transactions is provided. The method comprises receiving from a Diameter client a Diameter request message; determining based in part on a type of the received request message if the received request message should be spooled; determining if a current transaction rate exceeds a predefined spooling threshold, if the received request message should be spooled; and queuing the received request message if the current transaction rate exceeds the spooling threshold. | 2014-07-03 |
| 20140189152 | Methods, Systems, and Computer Program Products for Identifying a Protocol Address based on Path Information - Methods and systems are described for identifying a protocol address based on path information. In an aspect, first path information is detected that identifies a first sequence of nodes in a first network path for transmitting data between a first node and a second node in a network. Second path information is detected that identifies a second sequence of nodes in a second network path for transmitting data between the second node and a third node in the network. A first-third protocol address is determined, based on the first path information and the second path information, that identifies, according to a network protocol, the third node to the first node for communicating via the network protocol. | 2014-07-03 |
| 20140189153 | Methods, Systems, and Computer Program Products for Routing Based on a Scope-Specific Address - Methods and systems are described for routing based on a scope-specific address space. In an aspect, data is received data, from a previous node by a current node via a previous network interface operatively coupling the current node to a network, in a data unit that is specified according to a network protocol and that includes address information. A detection is made, based on the address information, a current-next protocol address that, in a current scope-specific address space specific to a current region including the current node, identifies a next node that is not included in the current region. A determination is made, based on the current-next protocol address, a next network interface operatively coupling the current node to the network. The data is sent, via the next network interface, to the next node. | 2014-07-03 |
| 20140189154 | Methods, Systems, and Computer Program Products for Determining a Shared Identifier for a Hop in a Network - Methods and systems are described for determining a shared identifier for a hop in a network. In an aspect, hop information is exchanged about a hop including a first node and a second node in a pair of consecutive nodes in a network path to transmit, via a network protocol, data sent by a source node to a destination node. A hop identifier criterion is specified based on the network protocol. A hop identifier is determined, based on the hop information, that meets the hop identifier criterion and that, in a first protocol address of the network protocol, at least one of identifies the first node to the second node and identifies the second node to the first node. | 2014-07-03 |
| 20140189155 | Methods, Systems, and Computer Program Products for Determining a Protocol Address For a Node - Methods and systems are described for determining a protocol address for a node. In an aspect, hop identifier is identified, which for a first node in a network identifies a hop that includes a pair of consecutive nodes in a network path in the network. A first protocol address is received that for a network protocol at least one of identifies the first node to a second node in the network and identifies the second node to the first node, wherein the second node is not in the hop. Based on the first protocol address and the hop identifier, a second protocol address is determined that for the network protocol at least one of identifies a node in the hop that is not the first node to the second node and identifies the second node to a node in the hop that is not the first node. | 2014-07-03 |
| 20140189156 | Methods, Systems, and Computer Program Products for Routing Based on a Path-Based Protocol Address - Methods and systems are described for routing based on a path-based protocol address. Data is detected, by a current node in a current location in a network path, in a data unit that is specified according to a network protocol and that includes a first path-based protocol address including a plurality of path segment identifiers that identify respective path segments of a network path for transmitting data from a source node to a destination node. A current-next path segment identifier is detected, based on the current location, that identifies a current-next path segment in the plurality for transmitting the data from the current node to a next node in the network path. A current-next network interface id determined, based on the current-next path segment identifier, that is included in the current-next path segment. The data is sent, via the current-next network interface, to the next node. | 2014-07-03 |
| 20140189157 | ENERGY MANAGEMENT FOR COMMUNICATION NETWORK ELEMENTS - A method of managing data flow may include determining data flows as one of data flows of known duration (KD) and data flows of arbitrary duration (AD). Profile energy consumption values for each of the KD flows is determined based on transmitting the KD flows between a first and a second node via a first network adaptor port, a second network adaptor port card, and switch port cards. Energy efficient routes for transmitting the KD flows between the nodes are also determined. Based on the profile energy consumption values, network element reference energy consumption values for each of network adaptor port cards and each of switch port cards located along the routes are determined, whereby transmission of the KD flows is based on energy consumption values at each of network adaptor port cards and each of switch port cards not exceeding respective network element reference energy consumption values. | 2014-07-03 |
| 20140189158 | TECHNIQUES FOR GUARANTEEING BANDWIDTH WITH AGGREGATE TRAFFIC - Methods, systems, and apparatus guarantee bandwidth for a network transaction. A network is logically organized as a tree having a plurality of nodes. Each node can guarantee service for a network transaction through the network. Each node monitors its traffic and reserves predefined amounts of unused bandwidth with its adjacent node. If a particular node needs additional bandwidth, that node borrows the bandwidth from its adjacent node. | 2014-07-03 |
| 20140189159 | Methods, Systems, and Computer Program Products for Identifying a Protocol Address in a Scope-Specific Address Space - Methods and systems are described for identifying a protocol address in a scope-specific address space. First address information is detected identifying a first-second protocol address identifying, according to a network protocol, a second node to a first node in the network and/or a second-first protocol address identifying, according to the protocol, the first node to the second node. Second address information is detected identifying a second-third protocol address identifying, according to the protocol, a third node in the network to the second node and a third-second protocol address identifying, according to the protocol, the second node to the third node. Based on the first and the second address information, a first-third protocol address is determined identifying, in a first scope-specific address space specific to a first region that includes the first node, the third node according to the protocol, wherein the third node is outside the first region. | 2014-07-03 |
| 20140189160 | METHODS AND SYSTEMS FOR SEAMLESS NETWORK COMMUNICATIONS BETWEEN DEVICES RUNNING INTERNET PROTOCOL VERSION 6 AND INTERNET PROTOCOL VERSION 4 - Systems are provided including at least one identifier locator network protocol (ILNP) enabled mobile node running Internet protocol version 6 (IPv6). The mobile node is attached to an IPv6 network in an IPv6 domain. The system includes a virtual root server configured to receive a binding identifiers create (BIC) message from a domain name system 64 (DNS64) server associated with the IPv6 network. The BIC message includes an ILNP address of the mobile node running IPv6, a fake ILNP address of a destination device running IPv4 assigned by the DNS64 server and an ILNP address of the DNS64 server. The fake ILNP address includes a full real address of the destination device. The virtual root server is further configures to create a binding between the ILNP address of the mobile node and the fake ILNP address of the destination device; store the binding; and send a binding identifier acknowledgement (BIA) message to the DNS64 server. | 2014-07-03 |
| 20140189161 | In-Line FIX Packet Translator - Certain embodiments provide systems and methods to perform in-line translation of message content according to FIX protocol variants in a trading system. An example method includes receiving, at a computing device, a message formatted according to a FIX protocol, the message including message content and a message wrapper, the message wrapper providing session and delivery information for the message to a target. The example method includes performing in-line translation of the message content of the received message to adjust the message content according to a predefined set of rules without affecting the message wrapper (with the possible exception of the message size) and message routing session. The example method includes facilitating routing of the message to the target based on the message wrapper. | 2014-07-03 |
| 20140189162 | REGULATING AN INPUT/OUTPUT INTERFACE - An apparatus includes an input/output (I/O) interface circuit that includes a memory and a controller. The memory stores a plurality of commands to regulate an input/output (I/O) interface. The commands indicate at least one I/O state of at least one I/O terminal of the I/O interface circuit and a time duration that is associated with the I/O state. The controller executes the commands to place the I/O interface in the the I/O state(s) in a predetermined sequence. | 2014-07-03 |
| 20140189163 | APPARATUS INCLUDING MEMORY SYSTEM CONTROLLERS AND RELATED METHODS - Memory system controllers can include a host bus adapter (HBA) and a serial advanced technology attachment (SA) programming compliant device coupled to the HBA via a function-specific interconnect configured to simultaneously transfer a command, a response, and other information between the HBA and the SA programming compliant device. | 2014-07-03 |
| 20140189164 | MEMORY BUS ATTACHED INPUT/OUTPUT ('I/O') SUBSYSTEM MANAGEMENT IN A COMPUTING SYSTEM - Memory bus attached Input/Output (‘I/O’) subsystem management in a computing system, the computing system including an I/O subsystem communicatively coupled to a memory bus, including: detecting, by an I/O subsystem device driver, a hibernation request; setting, by the I/O subsystem device driver, a predetermined memory address to a value indicating that the I/O subsystem is not to service system requests; detecting, by the I/O subsystem device driver, that the I/O subsystem device driver has been restarted; and setting, by the I/O subsystem device driver, the predetermined memory address to a value indicating that the I/O subsystem can resume servicing system requests. | 2014-07-03 |
| 20140189165 | SIZE-MINIMIZED DATA LOGGER AND SECURE DIGITAL (SD) MEMORY CARD HOUSING - Disclosed herein is a size-minimized data logger that also serves as a housing for a secure digital (SD) memory card. The SD card housing is located on one side of the data logger. The micro-SD card is used for recording raw or digital data and digitized event data. The data logger further includes, on the opposite side from the SD card housing, different functional units which are connected to one another. Exemplary functional units include an accelerometer, a magnetometer, a time unit, a temperature sensor and at least one analog/digital converter for conversion of measurement signals into digital input data, a processor unit for processing of data, a power supply source, an input interface for receiving signals or digital data and event data, and an output interface for outputting an indicator from the data logger. | 2014-07-03 |
| 20140189166 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM - The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel interface with the outside is to be used as a big endian or a little endian. A first register holds control data of the switching circuit. The switching circuit regards the parallel interface as the little endian when first predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register, and regards the parallel interface as the big endian when second predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register. Whatever the endian setting status, the control information can be correctly inputted without being influenced by the endian setting status. | 2014-07-03 |
| 20140189167 | COMPUTER APPARATUS - A computer apparatus comprising a memory, a first processor arranged to read and execute processor readable instructions stored in the memory, a peripheral device connected to and controlled by the first processor and a second processor in communication with the first processor, the second processor being operative to control an operative state of the peripheral device. | 2014-07-03 |
| 20140189168 | HARD DISK DRIVE MODULE HAVING INDICATING DEVICE - A hard disk drive module comprises a hard disk drive, a bracket to support the hard disk drive, and an indicating device. The indicating device indicates a working status of the hard disk drive. The indicating device comprises an indicating unit and a processor. The processor is electrically connected to a control system via a cable to encode a status message transmitted by the control system, and controls the indicating unit to indicate the working status of the hard disk drive. | 2014-07-03 |
| 20140189169 | REGULATING DIRECT MEMORY ACCESS DESCRIPTOR EXECUTION - An apparatus includes an integrated circuit that includes a processing core and a direct memory access (DMA) engine. The DMA engine is adapted to process descriptors to control DMA communications. The descriptors contain data indicating communication endpoints that are associated with the DMA communications. The DMA engine is adapted to use other data contained in at least one of the descriptors to control branching of descriptor execution among multiple execution paths. | 2014-07-03 |
| 20140189170 | INFORMATION PROCESSING APPARATUS, SETTING INFORMATION MANAGEMENT METHOD AND RECORDING MEDIUM - An disclosed information processing apparatus includes a memory unit for storing first setting-values for setting-items for a program in accordance with multiple priority levels, a given one of the setting-items being for one or more of the first setting-values, and each of the first setting-values having one of the priority levels assigned thereto; a setting information management unit for obtaining the first setting-values from the memory unit, and creating second setting-values by selecting, as one of the second setting-values, one of the first setting-values for any given setting-item from the first setting-values for the given setting-item such that the one of the first setting-values selected for the given setting-item has a highest priority level among the first setting-values for the given setting-item; and a program management unit for starting the program that operates based on the created second setting values. | 2014-07-03 |
| 20140189171 | OPTIMIZATION OF NATIVE BUFFER ACCESSES IN JAVA APPLICATIONS ON HYBRID SYSTEMS - Managing buffers in a hybrid system, in one aspect, may comprise selecting a first buffer management method from a plurality of buffer management methods; capturing statistics associated with access to the buffer in the hybrid system running under the initial buffer management method; analyzing the captured statistics; identifying a second buffer management method based on the analyzed captured statistics; determining whether the second buffer management method is more optimal than the first buffer management method; in response to determining that the second buffer management method is more optimal than the first buffer management method, invoking the second buffer management method; and repeating the capturing, the analyzing, the identifying and the determining. | 2014-07-03 |
| 20140189172 | DISCOVERY MECHANISMS FOR UNIVERSAL SERIAL BUS (USB) PROTOCOL ADAPTATION LAYER - A WiFi serial bus (WSB) attribute for use in Wi-Fi Alliance defined point-to-point (P2P) discovery mechanism includes a plurality of fields disposed in the frame. The WiFi serial bus attribute is arranged to provide information in the plurality of fields to support connectivity decisions for a USB device in a point-to-point network using a WSB protocol. The WSB attribute includes WSB architectural element information and information associated with a USB device behind a USB protocol adaptation layer (PAL). | 2014-07-03 |
| 20140189173 | Network Efficiency and Power Savings - A mechanism is provided for resource management. A first network interface card in a set of network interface cards receives network data from one or more servers in a set of servers. Responsive to the first network interface card determining that a first threshold has been met indicating that an overload condition is imminent in the first network interface card, the first network interface card sends a resume signal to a second network interface card in the set of network interface cards. Responsive to the first network interface card determining that a second threshold is being met indicating that the overload condition has been met in the first network interface card, the first network interface card delegates the network data that caused the overload condition to be met to the second interface card. | 2014-07-03 |
| 20140189174 | GENERAL INPUT/OUTPUT ARCHITECTURE, PROTOCOL AND RELATED METHODS TO IMPLEMENT FLOW CONTROL - An enhanced general input/output communication architecture, protocol and related methods are presented. | 2014-07-03 |
| 20140189175 | GENERIC BUS DE-MULTIPLEXER/PORT EXPANDER WITH INHERENT BUS SIGNALS AS SELECTORS - A circuit comprising: a device determiner configured to, in a first mode of operation, receive a device selection signal via at least one of: at least one control line and at least one signal line; and a device router configured to, in a second mode of operation, route signals between the at least one of: at least one control line and at least one signal line and at least one device dependent on the device selection signal. | 2014-07-03 |
| 20140189176 | PROCESSOR ARRANGEMENTS AND A METHOD FOR TRANSMITTING A DATA BIT SEQUENCE - A processor arrangement is provided. The processor arrangement includes: a first processor; a plurality of second processors, each second processor including a bit-mask generator configured to generate a processor-specific bit-mask sequence; wherein the first processor includes a bit-mask generator configured to generate the processor-specific bit-mask sequences of the second processors; wherein the first processor is configured to bit-mask a data bit sequence to be transmitted to one second processor of the plurality of second processors using a processor-specific bit-mask sequence specific to the one second processor, to thereby generate a processor-specific bit-masked data sequence to be transmitted to the one second processor. | 2014-07-03 |
| 20140189177 | HIGH SPEED OVERLAY OF IDLE I2C BUS BANDWIDTH - High-speed serial communications between programmable devices connected to an I | 2014-07-03 |
| 20140189178 | SINGLE WIRE SERIAL INTERFACE MASTER MODULE AND METHOD THEREOF FOR SAMPLING DATA INFORMATION - The present invention discloses a single wire serial interface (SSI) master module, including: a sample delay controlling unit, configured to send a delay instruction; the state machine unit, configured to wait, according to the delay instruction, for a delay period starting from a moment when an SSI master module completes sending the last bit of address information in a read operation frame, and then send a sample control signal to a selector unit; the selector unit, configured to enable a transmission channel with a sampling unit after receiving the sample control signal; and the sampling unit, configured to sample data information from an SSI slave module. In the present invention, the state machine unit delays sending the sample control signal, and the sampling unit is controlled to delay sampling the data information, which avoids a data reception error caused by slow discharging of an IO PAD. | 2014-07-03 |
| 20140189179 | SYSTEM ON CHIP AND METHOD FOR ACCESSING DEVICE ON BUS - The present invention discloses a system on a chip and a method for accessing a device on a bus, and belongs to the electronics field. The system includes: a primary device, configured to send an access request; an extension module, configured to receive the access request sent by the primary device, and extend the ID signal in the access request according to the number of primary devices; a parsing module, configured to parse the access request output by the extension module to obtain an access response instruction; and a secondary device, configured to respond to the extended access request according to the access response instruction. By using the foregoing technical solution, the present invention allows the primary device to flexibly access the secondary device, thereby reducing requirements on the primary and secondary devices. | 2014-07-03 |
| 20140189180 | METHOD AND SYSTEM FOR CHANGING BUS DIRECTION IN MEMORY SYSTEMS - A method including sorting read/write commands initiated by a memory controller based upon a destination page within a memory device. The read/write commands having a highest priority level are determined. The commands are then categorized as either page movement commands or data movement commands. The page movement commands or data movement commands are sent to the memory device based upon a signal indicating a current direction of a data bus providing communication between the memory controller and the memory device and further based upon a priority level. | 2014-07-03 |
| 20140189181 | On-Chip Bus Arbitration Method and Device Thereof - A method and device for on-chip bus arbitration are disclosed. The method includes: dividing devices into a first level, a second level and a third level from high to low; and in each arbitration period, calculating remaining processing time of each real-time transaction, and upgrading a device making a request required to be processed immediately to the first level in the current arbitration period; monitoring bandwidth usage amount of devices of the first level and the second level respectively, and downgrading a device whose bandwidth usage amount exceeds a preset bandwidth threshold value to the third level in the current arbitration period; and in devices making requests for a bus use right, if a device of the highest level is the device of the first level, authorizing the device of the first level; and if it is not the device of the first level, authorizing a device making continuous requests. | 2014-07-03 |
| 20140189182 | METHOD TO ACCELERATE MESSAGE SIGNALED INTERRUPT PROCESSING - Methods to accelerate a message signaled interrupt (MSI) are described herein. An embodiment of the invention includes an interrupt controller to receive a messaged signaled interrupt (MSI) request from a device over a bus, and an execution unit coupled to the interrupt controller to execute an interrupt service routine (ISR) associated with the device, the execution unit to retrieve interrupt data from a predetermined memory location specifically allocated to the device and to service the MSI using the interrupt data, without having to obtain the device interrupt data via an input output (IO) transaction. | 2014-07-03 |
| 20140189183 | MEMORY SYSTEM AND DRIVING METHOD THEREOF - A memory system includes first and second memory devices, a memory controller configured to control the second memory device, to store a request signal to access the first memory device, and to generate an interrupt signal, and a host configured to receive the request signal in response to the interrupt signal. | 2014-07-03 |
| 20140189184 | CREATING DYNAMIC FIXED FUNCTIONALITY FOR A HARDWARE DEVICE SYSTEM - One particular example implementation of an apparatus that includes logic, the logic at least partially comprising hardware logic to: trigger a particular interrupt based, at least in part, on input/output (I/O) activity when a predetermined state is activated on a platform; generate a system control interrupt based, at least in part, on a source associated with the particular interrupt; and route the system control interrupt to a custom system control interrupt handler. | 2014-07-03 |
| 20140189185 | INTERRUPT MONITORING SYSTEM AND COMPUTER SYSTEM - An interrupt monitoring apparatus includes a storage that stores a given threshold that corresponds to an external interrupt notification; a measuring circuit that measures time that elapses from a time when the external interrupt notification is received until a time when dispatch notification is received from a CPU; a comparing circuit that compares the given threshold and the time measured by the measuring circuit; and an output circuit that outputs to the CPU, a comparison result obtained by the comparing circuit. | 2014-07-03 |
| 20140189186 | MEMORY BUS ATTACHED INPUT/OUTPUT ('I/O') SUBSYSTEM MANAGEMENT IN A COMPUTING SYSTEM - Memory bus attached Input/Output (‘I/O’) subsystem management in a computing system, the computing system including an I/O subsystem communicatively coupled to a memory bus, including: detecting, by an I/O subsystem device driver, a hibernation request; setting, by the I/O subsystem device driver, a predetermined memory address to a value indicating that the I/O subsystem is not to service system requests; detecting, by the I/O subsystem device driver, that the I/O subsystem device driver has been restarted; and setting, by the I/O subsystem device driver, the predetermined memory address to a value indicating that the I/O subsystem can resume servicing system requests. | 2014-07-03 |
| 20140189187 | METHOD TO INTEGRATE ARM ECOSYSTEM IPS INTO PCI-BASED INTERCONNECT - Methods and apparatus for integrating ARM-based IPs in computer system employing PCI-based fabrics. An PCI-based fabric is operatively coupled to an ARM-based ecosystem employing an ARM-based fabric such as OCP, AHB, or BVCI via a corresponding fabric-to-fabric bridge. Transactions between IP operatively coupled to the PCI-based fabric and IP in the ARM-based ecosystem are facilitated by applying applicable ordering and conversions operations via the fabric-to-fabric bridge and/or fabrics. For example, posted writes originating from IP coupled to the PCI-based fabric are converted to non-posted writes and serialized via the fabric-to-fabric bridge and forwarded to the ARM-based ecosystem. | 2014-07-03 |
| 20140189188 | METHODS AND APPARATUS FOR BRIDGED DATA TRANSMISSION AND PROTOCOL TRANSLATION IN A HIGH-SPEED SERIALIZED DATA SYSTEM - An apparatus for transmitting data across a high-speed serial bus includes an IEEE 802.3-compliant PHY having a GMII interface; an IEEE 1394-compliant PHY in communication with the IEEE 802.3-compliant PHY via a switch; the switch determining whether data transmission is be routed to the IEEE 802.3-compliant PHY or the IEEE 1394-compliant PHY; a first connection, the first connection for transmitting data between a device and the IEEE 802.3-compliant PHY; and a second connection, the second connection for transmitting data between a device and the IEEE 1394-compliant PRY. | 2014-07-03 |
| 20140189189 | COMPUTER ARBITRATION SYSTEM, BANDWIDTH, ALLOCATION APPARATUS, AND METHOD THEREOF - The bandwidth allocation apparatus includes a high bandwidth arbitration module, a low bandwidth arbitration module and a multiplexer. The high bandwidth arbitration module is used to select one downstream device from the high bandwidth downstream device group for allowing uplink. The low bandwidth arbitration module is used to select one downstream device from the low bandwidth downstream device group for allowing uplink. The multiplexer selects the one of the access requests from the high bandwidth arbitration module or the low bandwidth arbitration module for allowing to uplink the access request to an upstream device. The access transmission times of the high bandwidth arbitration module and the low bandwidth arbitration module are counted respectively by a counting circuit. | 2014-07-03 |
| 20140189190 | MECHANISM FOR FACILITATING DYNAMIC CANCELLATION OF SIGNAL CROSSTALK IN DIFFERENTIAL INPUT/OUTPUT CHANNELS - A mechanism is described for facilitating dynamic cancellation of signal crosstalk in input/output differential channels according to one embodiment. A method of embodiments may include detecting crosstalk between a first differential signal channel pair (“differential pair”) and a second differential pair of a plurality of differential pairs at a computing system, and switching polarity relating to the first transmission links of the first differential pair to cancel out the crosstalk with the second differential pair. | 2014-07-03 |
| 20140189191 | APPARATUS AND METHOD FOR MEMORY-MAPPED REGISTER CACHING - A processor is described comprising: an architectural register file implemented as a combination of a register file cache and an architectural register region within a level 1 (L1) data cache, and a data location table (DLT) to store data indicating a location of each architectural register within the register file cache and/or the architectural register region within the L1 data cache. | 2014-07-03 |
| 20140189192 | APPARATUS AND METHOD FOR A MULTIPLE PAGE SIZE TRANSLATION LOOKASIDE BUFFER (TLB) - An apparatus and method for implementing a multiple page size translation lookaside buffer (TLB). For example, a method according to one embodiment comprises: reading a first group of bits and a second group of bits from a linear address; determining whether the linear address is associated with a large page size or a small page size; identifying a first cache set using the first group of bits if the linear address is associated with a first page size and identifying a second cache set using the second group of bits if the linear address is associated with a second page size; and identifying a first cache way if the linear address is associated with a first page size and identifying a second cache way if the linear address is associated with a second page size. | 2014-07-03 |
| 20140189193 | IMAGE FORMING APPARATUS AND METHOD OF TRANSLATING VIRTUAL MEMORY ADDRESS INTO PHYSICAL MEMORY ADDRESS - An image forming apparatus includes a function unit to perform functions of the image forming apparatus, and a control unit to control the function unit to perform the functions of the image forming apparatus. The control unit includes a processor core to operate in a virtual memory address, a main memory to operate in a physical memory address and store data used in the functions of the image forming apparatus, and a plurality of input/output (I/O) logics to operate in the virtual memory address and control at least one of the functions performed by the image forming apparatus. Each of the plurality of I/O logics translates the virtual memory address into the physical memory address corresponding to the virtual memory address and accesses the main memory. | 2014-07-03 |
| 20140189194 | LOW OVERHEAD PAGED MEMORY RUNTIME PROTECTION - Methods and apparatus relating to low overhead paged memory runtime protection are described. In an embodiment, permission information for guest physical mapping are received prior to utilization of paged memory by an Operating System (OS) based on the guest physical mapping. The permission information is provided through an Extended Page Table (EPT). Other embodiments are also described. | 2014-07-03 |
| 20140189195 | PROVIDING MEMORY CONDITION INFORMATION TO GUEST APPLICATIONS - Virtualization software can improve the effectiveness of a guest application running inside a virtual machine (VM) by providing information to the guest application indicative of a memory condition of the VM. The memory condition is indicative of an availability of memory resources to the guest application. When guest physical memory can be reserved by a balloon application running in the (VM), providing memory condition data indicative of the memory condition provides more accurate information regarding the availability of memory resources to the guest application than could be provided by the guest operating system of the VM. | 2014-07-03 |
| 20140189196 | DETERMINING WEIGHT VALUES FOR STORAGE DEVICES IN A STORAGE TIER TO USE TO SELECT ONE OF THE STORAGE DEVICES TO USE AS A TARGET STORAGE TO WHICH DATA FROM A SOURCE STORAGE IS MIGRATED - The present invention relates to a method, system, and computer program product for determining storage device weight values to use to select one of the storage devices to use as a target storage to which data from a source storage is migrated. A determination is made, for each of the storage devices, of static parameter values for static parameters comprising attributes of the storage device and dynamic parameter values for dynamic parameters providing device health information determined by accessing the storage device to determine operational conditions at the storage device. Storage device weight values are determined as a function of the static parameter values and the dynamic parameter values of the device. The determined storage device weight values are used to select one of the storage devices as the target storage to which data from the source storage is migrated. | 2014-07-03 |
| 20140189197 | SHARING SERIAL PERIPHERAL INTERFACE FLASH MEMORY IN A MULTI-NODE SERVER SYSTEM ON CHIP PLATFORM ENVIRONMENT - Methods and apparatus related to sharing Serial Peripheral Interface (SPI) flash memory in a multi-node server SoC (System on Chip) platform environment are described. In one embodiment, multi-port non-volatile memory is shared by a plurality of System on Chip (SoC) devices. Each of the plurality of SoC devices comprises controller logic to control access to the multi-port non-volatile memory and/or to translate a host referenced address of a memory access request to a linear address space and a physical address space of the multi-port non-volatile memory. Other embodiments are also disclosed and claimed. | 2014-07-03 |
| 20140189198 | MEMORY ALLOCATION FOR FAST PLATFORM HIBERNATION AND RESUMPTION OF COMPUTING SYSTEMS - Memory allocation for fast platform hibernation and resumption of computing systems. An embodiment of an apparatus includes logic at least partially implemented in hardware, the logic to: dynamically allocate at least a first portion of a nonvolatile memory; in response to a command to enter the apparatus into a standby state, the logic to store at least a portion of a context data from a volatile memory to the dynamically allocated first portion of the nonvolatile memory; and in response to a resumption of operation of the apparatus, the logic to copy at least the portion of the context data from the first portion of the nonvolatile memory to the volatile memory, and to reclaim the first portion of the nonvolatile memory for dynamic allocation. | 2014-07-03 |
| 20140189199 | FALSE POWER FAILURE ALERT IMPACT MITIGATION - Apparatus and computer program products implement embodiments of the present invention that include copying, by a storage system having a volatile memory configured as a write cache, write cache data from the volatile memory to a solid state device, upon receiving a signal indicating a loss of power to the storage system. Subsequent to copying the write cache data, the solid state device is configured as the write cache. | 2014-07-03 |
| 20140189200 | Flash Memory Using Virtual Physical Addresses - A system and method for using virtual physical addresses in a non-volatile memory device are disclosed. The physical layout of the non-volatile memory device may have physical die that are not a power-of-2 in number. In order to advantageously use the power-of-2 die number, which enables using a power-of-2 die interleave, a virtual physical addressing scheme is used. In particular, the virtual physical addressing scheme includes virtual die and virtual blocks, wherein the virtual die are a power-of-2 in number. Further, a conversion between the virtual physical addressing scheme and the actual physical addressing scheme is provided. In this way, for certain operations of the memory device, the virtual addressing scheme is used. For other operations, such as reading from, writing to or erasing, the actual physical addressing scheme is used. | 2014-07-03 |
| 20140189201 | Flash Memory Interface Using Split Bus Configuration - A system having a split bus flash memory and a method for operating the split bus flash memory is disclosed. The system may include a controller, a non-volatile memory (including first and second non-volatile memory chips) and the system bus. The controller is configured to communicate via an N-bit bus. The first and second non-volatile memory chips are configured to communicate via an M-bit bus, with M| 2014-07-03 | |
| 20140189202 | STORAGE APPARATUS AND STORAGE APPARATUS CONTROL METHOD - The access performance of a drive having a non-volatile memory is improved. | 2014-07-03 |
| 20140189203 | STORAGE APPARATUS AND STORAGE CONTROL METHOD - A cache memory (CM) in which data, which is accessed with respect to a storage device, is temporarily stored is coupled to a controller for accessing the storage device in accordance with an access command from a higher-level apparatus. The CM comprises a nonvolatile semi-conductor memory (NVM), and provides a logical space to the controller. The controller is configured to partition the logical space into multiple segments and to manage these segments, and to access the CM by specifying a logical address of the logical space. The CM receives the logical address-specified access, and accesses a physical area allocated to a logical area, which belongs to the specified logical address. A first management unit, which is a unit of a segment, is larger than a second management unit, which is a unit of an access performed with respect to the NVM. The capacity of the logical space is larger than the storage capacity of the NVM. | 2014-07-03 |
| 20140189204 | INFORMATION PROCESSING APPARATUS AND CACHE CONTROL METHOD - An information processing apparatus comprises a plurality types of cache memories having different characteristics, decides on a type of cache memory to be used as a data cache destination based on the access characteristics of cache-target data, and caches the data in the cache memory of the decided type. | 2014-07-03 |
| 20140189205 | METHOD AND SYSTEM FOR MANAGING PROGRAM CYCLES IN A MULTI-LAYER MEMORY - A system and method for managing program cycles in a multi-layer memory is disclosed. The method includes a controller receiving a request to program data from a host and, in advance of programming data associated with the request, determining a program cycle for programming the data associated with the request and an amount of data already programmed in the plurality of memory layers necessary to be programmed in maintenance operations to provide free memory capacity for a subsequent request to program data from the host. The controller programs the data associated with the request, and the amount of data already programmed to be programmed in maintenance operations, in predetermined programming units according to the determined program cycle. | 2014-07-03 |
| 20140189206 | METHOD AND SYSTEM FOR MANAGING BLOCK RECLAIM OPERATIONS IN A MULTI-LAYER MEMORY - A multi-later memory and method for operation is disclosed. The memory includes at least one flash memory die having multiple layers and a controller configured to execute block reclaim operations in a layer of the flash memory die until a net gain of at least one additional free block has been made in the layer. The method may include relocating data from reclaim blocks to relocation blocks within the same layer, or within a same partition in the same layer until a net gain of one free block has been achieved and an integer number of relocation blocks has been filled with relocated data. The method may also include moving data from reclaim blocks in a first layer into destination blocks in a second layer until a net gain of at least one free block has been achieved in the first layer. | 2014-07-03 |
| 20140189207 | METHOD AND SYSTEM FOR MANAGING BACKGROUND OPERATIONS IN A MULTI-LAYER MEMORY - A multi-layer memory and method for performing background maintenance operations are disclosed. The memory includes a plurality of flash memory die having multiple layers, where each layer is made up of flash memory cells having a greater bit per cell storage capacity than then prior layer and each layer may have a plurality of partitions for different data types. A controller managing the flash memory die is configured to identify an idle die and determine if a layer in the die satisfies a background maintenance criterion. Upon identifying a layer satisfying the background maintenance criterion, the valid data from reclaim blocks in the layer is relocated into a relocation block in the same layer until the relocation block is filled and the background maintenance cycle ends. | 2014-07-03 |
| 20140189208 | METHOD AND SYSTEM FOR PROGRAM SCHEDULING IN A MULTI-LAYER MEMORY - A multi-layer memory and method for operation is disclosed. The memory includes an interface, at least one flash memory die having a plurality of layers and a controller. The controller is configured to select an appropriate one of a predetermined number of program cycles for programming a fixed amount of host data, and for carrying out maintenance operations in one or more of the layers sufficient to permit a next host data write operation. The controller calculates an interleave ratio of maintenance operations to host data programming operations in each of the layers used in the determined programming cycle so that creation of free space is interspersed with host data writes in a steady manner during execution of the determined programming cycle. | 2014-07-03 |
| 20140189209 | MULTI-LAYER MEMORY SYSTEM HAVING MULTIPLE PARTITIONS IN A LAYER - A multi-layer memory and method for operation is disclosed. The memory includes multiple layers, where each layer includes flash memory cells having a greater bit per cell capacity than then prior layer and each layer may include a plurality of partitions having blocks exclusively associated with a particular data type. The method may include the steps of directing host data directly into a particular partition of a particular layer of the multi-layer memory upon receipt depending on a type of the data. The method may also include copying data within the same partition in a respective layer in a data relocation operation to generate more free blocks of memory so that data preferably stays within each layer and in the same partition, as well as transferring data from one layer to the next higher bit per cell layer within a same partition when layer transfer criteria are met. | 2014-07-03 |
| 20140189210 | MEMORY SYSTEM HAVING AN UNEQUAL NUMBER OF MEMORY DIE - A flash memory system having unequal number of memory die and method for operation is disclosed. The memory includes a plurality of flash memory die distributed unevenly among different control lines, such that there are an unequal number of die between control lines. A total physical storage capacity of the plurality of flash memory die is greater than a total logical capacity such that the memory system is over provisioned with physical storage capacity. A logical address splitter directs data received from a host system and associated with host logical block addresses such that each control line only receives data associated with predetermined host logical block address ranges and directs the data such that a ratio of physical capacity to logical capacity is equal among each of the control lines, regardless of the different number of die, and associated different physical capacity per control line. | 2014-07-03 |
| 20140189211 | Remapping Blocks in a Storage Device - In the present disclosure, a persistent storage device includes both persistent storage, which includes a set of persistent storage blocks, and a storage controller. The persistent storage device stores and retrieves data in response to commands received from an external host device. The persistent storage device stores a logical block address to physical address mapping. The persistent storage device also, in response to a remapping command, stores an updated logical block address to physical block address mapping. | 2014-07-03 |
| 20140189212 | PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL - In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme. | 2014-07-03 |
| 20140189213 | ADDRESS GENERATING CIRCUIT AND ADDRESS GENERATING METHOD - An address generating circuit according to an embodiment includes a register that maintains a partition address set by a CPU, a comparator that determines whether a designated address designated by the CPU designates the interleaved area or the non-interleaved area, a selection signal generating unit that generates the selection signal based on a least significant bit of the designated address in a case of the interleaved area and generates the selection signal based on a high-order bit other than the least significant bit of the designated address in a case of the non-interleaved area, and a physical address generating unit that generates the physical address acquired by excluding the least significant bit from the designated address in a case of the interleaved area and generates the physical address acquired by excluding the high-order bit from the designated address in a case of the non-interleaved area. | 2014-07-03 |
| 20140189214 | FALSE POWER FAILURE ALERT IMPACT MITIGATION - Methods, apparatus and computer program products implement embodiments of the present invention that include copying, by a storage system having a volatile memory configured as a write cache, write cache data from the volatile memory to a solid state device, upon receiving a signal indicating a loss of power to the storage system. Subsequent to copying the write cache data, the solid state device is configured as the write cache. | 2014-07-03 |
| 20140189215 | MEMORY MODULES AND MEMORY SYSTEMS - A memory module includes a plurality of memory devices and a buffer chip. The buffer chip manages the memory devices. The buffer chip includes a refresh control circuit that groups a plurality of memory cell rows of the memory devices into a plurality of groups according to a data retention time of tire memory cell rows. The buffer chip selectively refreshes each of the plurality of groups in each of a plurality of refresh time regions that are periodically repeated and applies respective refresh periods to the plurality of groups, respectively. | 2014-07-03 |
| 20140189216 | APPARATUS, SYSTEM, AND METHOD FOR CONDITIONAL AND ATOMIC STORAGE OPERATIONS - An apparatus, system, and method are disclosed for implementing conditional storage operations. Storage clients access and allocate portions of an address space of a non-volatile storage device. A conditional storage request is provided, which causes data to be stored to the non-volatile storage device on the condition that the address space of the device can satisfy the entire request. If only a portion of the request can be satisfied, the conditional storage request may be deferred or fail. An atomic storage request is provided, which may comprise one or more storage operations. The atomic storage request succeeds if all of the one or more storage operations are complete successfully. If one or more of the storage operations fails, the atomic storage request is invalidated, which may comprise deallocating logical identifiers of the request and/or invalidating data on the non-volatile storage device pertaining to the request. | 2014-07-03 |
| 20140189217 | SEMICONDUCTOR STORAGE DEVICE - According to an embodiment, a semiconductor storage device includes a first storage unit, a read control unit, a second storage unit, and a write control unit. The first storage unit is configured to store data supplied from a host device. The read control unit is configured to perform control of reading the data in accordance with a read request. The second storage unit is configured to store a logical address used for reading the data from the first storage unit by the read control unit. The write control unit is configured to perform control of adding the stored logical address to the data and write the resulting data into the first storage unit in a case where a size of the data requested to be written into the first storage unit by the host device is smaller than a threshold. | 2014-07-03 |
| 20140189218 | METHOD OF PROGRAMMING DATA INTO NONVOLATILE MEMORY AND METHOD OF READING DATA FROM NONVOLATILE MEMORY - Disclosed is a method of programming data into a nonvolatile memory that includes a plurality of memory cells connected with a word line, each memory cell storing first to mth bits of a plurality of bits, the plurality of bits forming first to mth pages. The method includes generating first to mth metadata based on first to mth page data received; rearranging the first to mth metadata to generate first to mth rearranged metadata; and programming the first to mth rearranged metadata and the first to mth page data into the first to mth pages, respectively. | 2014-07-03 |
| 20140189219 | SOLID STATE STORAGE ELEMENT AND METHOD - A method and system for storing and retrieving data using flash memory devices. One example system includes an apparatus within a flash memory configuration. The flash memory configuration includes a plurality of memory cells, where each memory cell has a charge storage capacity for use in implementing digital storage. The apparatus includes a processing arrangement configured to access each of the memory cells in a write operation and a read operation. The apparatus also includes an instruction set for instructing the processor to impose target charge levels for defining a plurality of data values for each of the memory cells. The target charge levels are programmably movable with respect to the charge storage capacity. | 2014-07-03 |
| 20140189220 | EXECUTE-IN-PLACE MODE CONFIGURATION FOR SERIAL NON-VOLATILE MEMORY - Example embodiments for configuring a serial non-volatile memory device for an execute-in-place mode may comprise a non-volatile configuration register to store an execute-in-place mode value that may be read at least in part in response to power being applied to the memory device. | 2014-07-03 |
| 20140189221 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor storage device includes a first nonvolatile memory to store user data of a file, a second nonvolatile memory to store management data of the file, the second nonvolatile memory being different in type from the first nonvolatile memory, and a controller to control read/write of data with respect to the first and second nonvolatile memories. | 2014-07-03 |
| 20140189222 | METHOD FOR PERFORMING DATA SHAPING, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing data shaping is applied to a controller of a Flash memory, where the Flash memory includes a plurality of blocks. The method includes: performing a program optimization operation according to original data and a plurality of shaping codes, in order to generate trace back information corresponding to a Trellis diagram and utilize the trace back information as side information; and dynamically selecting at least one shaping code from the shaping codes according to the side information to perform data shaping on the original data. | 2014-07-03 |
| 20140189223 | IC CARD, PORTABLE ELECTRONIC DEVICE, AND METHOD OF CONTROLLING IC CARD - According to one embodiment, an IC card which executes a process in accordance with a command transmitted from an external device, includes, a first storage module configured to pre-store an application including a plurality of structures, a reception module configured to receive a command transmitted from the external device, and a second storage module configured to identify, when a write command for writing the application stored by the first storage module has been received by the reception module, a structure missing in the application stored by the first storage module, and storing the identified structure. | 2014-07-03 |
| 20140189224 | TRAINING FOR MAPPING SWIZZLED DATA TO COMMAND/ADDRESS SIGNALS - Data pin mapping and delay training techniques. Valid values are detected on a command/address (CA) bus at a memory device. A first part of the pattern (high phase) is transmitted via a first subset of data pins on the memory device in response to detecting values on the CA bus; a second part of the pattern (low phase) is transmitted via a second subset of data pins on the memory device in response to detecting values on the CA bus. Signals are sampled at the memory controller from the data pins while the CA pattern is being transmitted to obtain a first memory device's sample (high phase) and the second memory device's sample (low phase) by analyzing the first and the second subset of sampled data pins. The analysis combined with the knowledge of the transmitted pattern on the CA bus leads to finding the unknown data pins mapping. Varying the transmitted CA patterns and the resulting feedbacks sampled on memory controller data signals allows CA/CTRL/CLK signals delay training with and without priory data pins mapping knowledge. | 2014-07-03 |
| 20140189225 | Independent Control Of Processor Core Retention States - In an embodiment, a processor includes a first processor core, a second processor core, a first voltage regulator to provide a first voltage to the first processor core with a first active value when the first processor core is active, and a second voltage regulator to provide a second voltage to the second processor core with a second active value when the second processor core is active. Responsive to a request to place the first processor core in a first low power state with an associated first low power voltage value, the first voltage regulator is to reduce the first voltage to a second low power voltage value that is less than the first low power voltage value, independent of the second voltage regulator. First data stored in a first register of the first processor core is retained at the second low power value. Other embodiments are described and claimed. | 2014-07-03 |
| 20140189226 | MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME - A memory device includes a memory cell array, a multi-purpose register (MPR) and a control unit. The memory cell array includes a plurality of memory blocks. The multi-purpose register (MPR) stores physical address information for each of the plurality of memory blocks. The control unit outputs the physical address information stored in the multi-purpose register in response to an MPR read command received from a memory controller. | 2014-07-03 |
| 20140189227 | MEMORY DEVICE AND A MEMORY MODULE HAVING THE SAME - A memory device is provided. The memory device includes a plurality of memory chips, and a buffer chip connected to the plurality of memory chips. The plurality of memory chips and the buffer chip are disposed in a stack. A first input/output (IO) port of the buffer chip is connected in series to an external device, and a second IO port of the buffer chip is connected in parallel to IO ports of each of the plurality of memory chips. | 2014-07-03 |
| 20140189228 | THROTTLING SUPPORT FOR ROW-HAMMER COUNTERS - Throttling of memory access commands. Accesses to rows of a memory device are monitored for a timeframe. The timeframe is divided into at least two sub-frames. If the number of accesses for any of the rows during a first sub-frame exceeds a first threshold throttling accesses to the accessed row at a first rate. Not throttling accesses to the accessed row if the number of accesses to the accessed row does not exceed the first threshold. The first threshold is associated with risk of data corruption on a row physically adjacent to the accessed row. If a number of accesses for the accessed row during a second sub-frame exceeds a second threshold, throttling accesses to the accessed row at a second rate. Not throttling accesses to the accessed row if the number of accesses to the accessed row does not exceed the second threshold. The second threshold is greater than the first threshold. The second throttling rate is greater than the first throttling rate. | 2014-07-03 |
| 20140189229 | REFRESH RATE PERFORMANCE BASED ON IN-SYSTEM WEAK BIT DETECTION - A memory subsystem can test a memory device in situ, testing the performance of the device in the system it is built into during production. Thus, the refresh rate can be adjusted specific to the memory device(s) of a specific system, rather than defaulting to a refresh frequency specified by a standard for the memory device(s). A test component embedded within the host memory subsystem can perform a test and identify specific bits or lines of memory that produce errors when a lower frequency refresh rate is used. The system maps out the identified bits or lines to prevent the bits/lines from being used in runtime of the system. The memory subsystem can then set its refresh rate to an adjusted refresh rate at which a threshold number of errors can be removed by mapping out the bits/lines. | 2014-07-03 |
| 20140189230 | MEMORY CONTROLLING DEVICE AND METHOD THEREOF - A memory controlling device and method are disclosed for controlling a memory having a partial array self refresh (PASR) function and a plurality of memory segments. The memory controlling device comprises an address mapper, an address decoder, an address selector, and a PASR configuration register storing a PASR configuration. The address mapper converts an input address set into a mapped address set according to an address offset. The mapped address set comprises a plurality of consecutive mapped addresses or at least one mapped address within a limited range. The address decoder updates the PASR configuration during writing. The address selector generates an updated address set, which is used for setting at least one mode register of the memory, according to the PASR configuration register under a sleep-or-standby mode in order that the memory can self refresh at least one of the memory segments correspondingly. | 2014-07-03 |
| 20140189231 | Audio Digital Signal Processor - A microprocessor includes a memory interface to obtain data envelopes of a first length, and control logic to implement an instruction to load an initial data envelope of a stream of data values into a buffer, each data value having a second length shorter than the first length, the stream of data values being disposed across successive data envelopes at the memory interface. Another instruction merges current contents of the buffer and the memory interface such that each invocation loads one of the data values into a first register, and moves at least a remainder of the current contents of the memory interface into the buffer for use in a successive invocation. Another instruction loads a reversed representation of a set of data values obtained via the memory interface into a second register. Another instruction implements an FIR computation including a SIMD operation involving multiple data values of the stream and the reversed representation. | 2014-07-03 |
| 20140189232 | VIRTUAL TAPE DEVICE AND VIRTUAL TAPE DEVICE CONTROL METHOD - A virtual tape device includes a determination unit and a copy creation unit. The determination unit determines, when deleting some logical volume data among a plurality of logical volume data stored on a first physical tape, whether to conduct copy processing to store a copy of the logical volume data onto a second physical tape on the basis of a storage location of the logical volume data. The copy creation unit stores, when it is determined to conduct the copy processing, a copy of the logical volume data on the second physical tape so as to cause spacing between a storage location of the logical volume data on the second physical tape and a head location on the second physical tape to become shorter than spacing between a storage location of the logical volume data on the first physical tape and a head location on the first physical tape. | 2014-07-03 |
| 20140189233 | METHOD FOR OPTIMIZING CLEANING OF MAPS IN FLASHCOPY CASCADES CONTAINING INCREMENTAL MAPS - A method for optimizing cleaning of maps in storage cascades includes determining whether a target disk of a map contains data unavailable to a downstream disk from an upstream disk in a cascade and detect whether the downstream disk has a copy of the data. Additionally, the method includes copying the data from the target disk to the downstream disk, if the target disk of the map contains data unavailable to the downstream disk from the upstream disk and the downstream disk does not have the copy of the data. Furthermore, the method includes copying the data from the target disk to the downstream disk, if the target disk of the map does not contain data unavailable to the downstream disk from the upstream disk or the downstream disk does have the copy of the data. Moreover, the method includes removing the map from the cascade. | 2014-07-03 |
| 20140189234 | PROTECTING VOLATILE DATA OF A STORAGE DEVICE IN RESPONSE TO A STATE RESET - A plurality of aligned or unaligned data packets are received in a data storage device. A data bundle is constructed by concatenating different ones of the plurality of unaligned data packets. Data loss protection identifiers are utilized to track the construction of the data bundle. The data loss protection identifiers are employed to prevent at least one of packet data loss or metadata loss in response to detecting a state reset of the data storage device. | 2014-07-03 |
| 20140189235 | STEALTH APPLIANCE BETWEEN A STORAGE CONTROLLER AND A DISK ARRAY - A stealth appliance may be coupled between a storage controller and a disk array. The stealth appliance may be configured to receive a request from the storage controller encrypted with a first community-of-interest (COI) key, to decrypt the request with the first COI key, to encrypt the request with a second COI key, and to transmit the encrypted request to the disk array. | 2014-07-03 |
| 20140189236 | DATA STORAGE METHOD AND STORAGE DEVICE - The embodiments of the present invention provide a data storage method, including: sending a performance level request to a storage device, which is used to query information about performance level of one or more logical unit number LUNs in the storage device; receiving a response sent by the storage device in response to the performance level request, wherein the response comprises the information about performance levels of the LUNs; and obtaining performance levels of the LUNs according to the information about performance levels of the LUNs so that data to be stored is written into a LUN of a corresponding performance level according to a accessing frequency level of the data to be stored comprised in a write-data instruction when the write-data instruction is received. | 2014-07-03 |
| 20140189237 | DATA PROCESSING METHOD AND APPARATUS - Embodiments of the present invention provide a data processing method and apparatus. According to the embodiments of the present invention, when it is found that a data hash value in a currently received data stream exceeds a preset first threshold, a part or all of data in the data stream is not deduplicated, and is directly stored, so as to prevent the data in the data stream from being dispersedly stored into a plurality of storage areas; instead, the part or all of the data is stored into a storage area in a centralized manner, so that a deduplication rate is effectively improved on the whole, particularly in a scenario of large data storage amount. | 2014-07-03 |
| 20140189238 | Two-Level Cache Locking Mechanism - A virtually tagged cache may be configured to index virtual address entries in the cache into lockable sets based on a page offset value. When a memory operation misses on the virtually tagged cache, only the one set of virtual address entries with the same page offset may be locked. Thereafter, this general lock may be released and only an address stored in the physical tag array matching the physical address and a virtual address in the virtual tag array corresponding to the matching address stored in the physical tag array may be locked to reduce the amount and duration of locked addresses. The machine may be stalled only if a particular memory address request hits and/or tries to access one or more entries in a locked set. Devices, systems, methods, and computer readable media are provided. | 2014-07-03 |
| 20140189239 | PROCESSORS HAVING VIRTUALLY CLUSTERED CORES AND CACHE SLICES - A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed. | 2014-07-03 |
| 20140189240 | Apparatus and Method For Reduced Core Entry Into A Power State Having A Powered Down Core Cache - A method performed by a multi-core processor is described. The method includes, while a core is executing program code, reading a dirty cache line from the core's last level cache and sending the dirty cache line from the core for storage external from the core, where, the dirty cache line has not been evicted from the cache nor requested by another core or processor. | 2014-07-03 |
| 20140189241 | Method and Apparatus to Write Modified Cache Data To A Backing Store While Retaining Write Permissions - A method is described that includes performing the following for a transactional operation in response to a request from a processing unit that is directed to a cache identifying a cache line. Reading the cache line, and, if the cache line is in a Modified cache coherency protocol state, forwarding the cache line to circuitry that will cause the cache line to be written to deeper storage, and, changing another instance of the cache line that is available to the processing unit for the transactional operation to an Exclusive cache coherency state | 2014-07-03 |
| 20140189242 | LOGGING IN SECURE ENCLAVES - Embodiments of an invention for logging in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction having an associated enclave page cache address. The execution unit is to execute the instruction without causing a virtual machine exit, wherein execution of the instruction includes logging the instruction and the associated enclave page cache address. | 2014-07-03 |
| 20140189243 | SECTORED CACHE WITH HYBRID LINE GRANULARITY - A coarse-grained cache line may be associated with a way from a set in a cache. A first sector of the coarse-grained cache line may be stored in the way. The coarse-grained cache line may include a predetermined number of sectors. A fine-grained cache line may be associated with the way. A second sector of the fine-grained cache line may be stored in the way. The fine-grained cache line may include a predetermined number of sectors. The predetermined number of sectors in the fine-grained cache line may be lower than the predetermined number of sectors in the coarse-grained cache line. | 2014-07-03 |
| 20140189244 | SUPPRESSION OF REDUNDANT CACHE STATUS UPDATES - A cache management system employs a replacement policy in a manner that manages redundant accesses to cache elements. The cache management system comprises a cache, a replacement policy state storage and an update control module. The update control module comprises a buffer for storing recent addresses, a comparison unit for comparing a new address with those stored in the recent address buffer, and an update unit which determines whether to update the replacement policy state storage. When an address matches those stored in the recent address buffer, a replacement status update is suppressed. | 2014-07-03 |
| 20140189245 | MERGING EVICTION AND FILL BUFFERS FOR CACHE LINE TRANSACTIONS - A processor includes a first cache memory and a bus unit in some embodiments. The bus unit includes a plurality of buffers and is operable to allocate a selected buffer of a plurality of buffers for a fill request associated with a first cache line to be stored in a first cache memory, load fill data from the first cache line into the selected buffer, and transfer the fill data to the first cache memory in parallel with storing eviction data for an evicted cache line from the first cache memory in the selected buffer. | 2014-07-03 |
