27th week of 2020 patent applcation highlights part 76 |
Patent application number | Title | Published |
20200212843 | MAGNETICALLY PUMPED VOLTAGE CONTROLLED OSCILLATOR - A voltage controlled oscillator includes a first inductor, a second inductor, a first metal oxide semiconductor (MOS) transistor, a second MOS transistor, and an inductor-capacitor (LC) tank circuit. A first end of the first inductor and a first end of the second inductor are coupled to a first power rail. A drain node of the first MOS transistor is coupled to a second end of the first inductor. A drain node of the second MOS transistor is coupled to a second end of the second inductor. Source nodes of the first MOS transistor and the second MOS transistor are coupled to a second power rail. The LC tank circuit is coupled to gate nodes of the first MOS transistor and the second MOS transistor, wherein energy is magnetically pumped into the LC tank circuit through the first inductor and the second inductor. | 2020-07-02 |
20200212844 | PHASE COHERENT NUMERICALLY CONTROLLED OSCILLATOR - A phase coherent NCO circuit includes a base frequency NCO, a phase seeding circuit, a scaled frequency NCO, a sine/cosine generator. The base frequency NCO is configured to generate base phase values based on a base frequency control word. The phase seeding circuit is coupled to the base frequency NCO. The phase seeding circuit is configured to generate a seed phase value based on the base phase values and a scale factor value. The scaled frequency NCO is coupled to the phase seeding circuit. The scaled frequency NCO is configured to generate oscillator phase values based on the phase seed value and an oscillator frequency control word. The sine/cosine generator is coupled to the scaled frequency NCO. The sine/cosine generator is configured to generate oscillator output samples based on the oscillator phase values. | 2020-07-02 |
20200212845 | Mixer bias circuit - The present invention discloses a mixer bias circuit including a first reference voltage generation circuit, an amplifier, a first transistor array, a first switch array, a second reference voltage generation circuit, a second transistor array, a second switch array, a first resistive component, and a second resistive component. The mixer bias circuit provides multiple bias voltages by dynamically tracking the common mode voltage of a trans-impedance amplifier (TIA) and compensates for imbalance and mismatch effects by asymmetrically trimming the bias voltages to improve the second-order intercept point of a radio frequency (RF) receiver front-end (RXFE). | 2020-07-02 |
20200212846 | POWER AMPLIFIER CIRCUIT AND POWER AMPLIFIER MODULE - A power amplifier circuit includes a first transistor; a first bias circuit that supplies a first bias current or voltage; a capacitor; a first inductor; a second inductor; a second transistor; a second bias circuit that supplies a second bias current or voltage; a third inductor; a third transistor; a third bias circuit that supplies a third bias current or voltage; and a fourth inductor. | 2020-07-02 |
20200212847 | BROADBAND, HIGH-EFFICIENCY, NON-MODULATING POWER AMPLIFIER ARCHITECTURE - Apparatus and methods for a no-load-modulation power amplifier are described. No-load-modulation power amplifiers can comprise multiple amplifiers connected in parallel to amplify a signal that has been divided into parallel circuit branches. One of the amplifiers can operate as a main amplifier in a first amplification class and the remaining amplifiers can operate as peaking amplifiers in a second amplification class. The main amplifier can see essentially no modulation of its load between the power amplifier's fully-on and fully backed-off states. The power amplifiers can operate in symmetric and asymmetric modes. Improvements in bandwidth and drain efficiency over conventional Doherty amplifiers are obtained. Further improvements can be obtained by combining signals from the amplifiers with hybrid couplers. | 2020-07-02 |
20200212848 | TRI-PHASING MODULATION FOR EFFICIENT AND WIDEBAND RADIO TRANSMITTER - According to an aspect, there is provided a method for power-amplification of a transmission signal, comprising: obtaining the transmission signal with phase and amplitude modulation; generating a power-amplified polar signal for approximating a power-amplified transmission signal by power-amplifying a first constant-envelope signal with one of two or more first amplification factors based on the transmission signal; generating an outphasing) pair of a first power-amplified outphasing signal and a second power-amplified outphasing signal based on the transmission signal; and combining the power-amplified polar signal, the first power-amplified outphasing signal and the second power-amplified outphasing signal to provide the power-amplified transmission signal. | 2020-07-02 |
20200212849 | POWER AMPLIFIER CIRCUIT - A power amplifier circuit includes a power amplifier that amplifies the power of a high frequency signal, a power amplifier temperature detector circuit that includes a temperature detection element, the temperature detection element being thermally coupled with the power amplifier, a bias control signal generator circuit that generates a bias control signal for the power amplifier based on a temperature detection signal outputted from the power amplifier temperature detector circuit, and a regulator circuit that stabilizes the temperature detection signal. The power amplifier, the power amplifier temperature detector circuit, and the regulator circuit are formed in a first integrated circuit, and the bias control signal generator circuit is formed in a second integrated circuit. The substrate material (for example, GaAs) of the first integrated circuit has a higher cutoff frequency than the substrate material (for example, SOI) of the second integrated circuit. | 2020-07-02 |
20200212850 | TEMPERATURE DETECTION CIRCUIT, POWER AMPLIFICATION CIRCUIT, AND ELECTRONIC DEVICE - Provided is a temperature detection circuit that includes: a series connection circuit that is connected between a power supply voltage input terminal and ground and includes a temperature detection transistor and a first resistance element; and a current bypass circuit that includes a first transistor that is connected in parallel with the temperature detection element and allows a bypass current to flow therethrough. The temperature detection circuit outputs a temperature detection signal from a connection point between the temperature detection transistor and the first resistance element. | 2020-07-02 |
20200212851 | EXTENDED OPERATIONAL BANDWIDTH AMPLIFIERS WITH FRACTIONAL INSTANTANEOUS BANDWIDTH FEED FORWARD CORRECTION - Apparatus and method for extended operational bandwidth amplifiers with fractional instantaneous bandwidth feed forward correction. In one embodiment, the method includes amplifying a radio frequency (RF) input signal to provide an amplified RF signal and introducing a first delay in the amplified RF signal. The method also includes receiving an error signal of the amplified RF signal and centering a correction bandwidth with respect to the amplified RF signal. The method also includes amplifying the error signal and combining the amplified RF signal and the amplified error signal to reduce an error in the amplified RF signal. The first delay is smaller than a second delay caused by the error path. | 2020-07-02 |
20200212852 | Circuit with Co-Matching Topology for Transmitting and Receiving RF Signals - A circuit with co-matching topology for transmitting and receiving RF signals for return loss improvement, wherein when transmitting RF signals, the LNA is turned off and the capacitance of an adjustable capacitive component is adjusted for transmitting RF signals, and when receiving RF signals, the power amplifier and the adjustable capacitive component are turned off, wherein a matching network is designed in favor of the LNA for receiving RF signals while the adjustable capacitive component can adjust the overall impedance of the circuit including the matching network that is also used when transmitting RF signals and the adjustable capacitive component for improving the transmitting return loss. | 2020-07-02 |
20200212853 | OPTOELECTRONIC COMPONENT HAVING AN OPTICAL DAMPING MEMBER - The invention relates to a component ( | 2020-07-02 |
20200212854 | SENSOR ARRAY WITH DISTRIBUTED LOW NOISE AMPLIFIER - A sensor circuit includes a sensor array. The sensor array includes a sensor row that includes a first sensor cell, a second sensor cell, and an output stage of a distributed amplifier circuit. The first sensor cell includes a first photodetector, and a first preamplifier stage of the distributed amplifier circuit. The first preamplifier stage is coupled to the first photodetector, and is configured to amplify a signal received from the first photodetector. The second sensor cell includes a second photodetector, and a second preamplifier stage of the distributed amplifier circuit. The second preamplifier stage is coupled to the second photodetector, and is configured to amplify a signal received from the second photodetector. The output stage of the distributed amplifier circuit is coupled to the first and second sensor cells, and is configured to amplify a signal received from the first preamplifier stage and the second preamplifier stage. | 2020-07-02 |
20200212855 | POWER SUPPLY CIRCUIT - A power supply circuit supplies a variable voltage to a power amplifier that amplifies a radio-frequency signal, and includes a transistor and a current detecting resistor. The transistor includes a collector or drain that is supplied with a fixed voltage from a fixed voltage source, a base or gate that receives an envelope signal tracking an envelope of the radio-frequency signal, and an emitter or source that outputs the variable voltage that is based on the envelope signal. The current detecting resistor is electrically connected between the fixed voltage source and the collector or drain of the transistor. | 2020-07-02 |
20200212856 | TRANSIMPEDANCE AMPLIFIER CIRCUIT - The invention relates to a circuit containing a transimpedance amplifier for converting two input currents into two output voltages, having a first amplifier part containing a first input, to which a first input voltage is applied, and into which a first input current flows, and having a second amplifier part containing a second input, to which a second input voltage is applied and into which a second input current flows, wherein the first amplifier part and the second amplifier part are connected to a common supply voltage, the first amplifier part and the second amplifier part are connected to a common current source, the input of the first amplifier part and the input of the second amplifier part have a differing direct voltage, and the first amplifier part and the second amplifier part are designed such that an output voltage of the first amplifier part is proportional to the input current of the first amplifier part and an output voltage of the second amplifier part is proportional to an input current of the second amplifier part. | 2020-07-02 |
20200212857 | METHODS AND APPARATUS FOR AN OPERATIONAL AMPLIFIER WITH A VARIABLE GAIN-BANDWIDTH PRODUCT - Various embodiments of the present technology comprise a method and apparatus for an operational amplifier with a variable gain-bandwidth product. According to various embodiments, an amplifier circuit comprising the operational amplifier operates in multiple stages and provides a low gain-bandwidth and a high gain-bandwidth. | 2020-07-02 |
20200212858 | METHODS AND APPARATUS FOR AN AMPLIFIER CIRCUIT - Various embodiments of the present technology may comprise methods and apparatus for an amplifier circuit. Methods and apparatus for an amplifier circuit according to various aspects of the present invention may comprise a first cross-connect circuit configured to receive an input signal at an input terminal and transmit the input signal to an input stage circuit. The amplifier circuit may further comprise a second cross-connect circuit connected between the input stage circuit and an output stage circuit, and a voltage adjustment circuit connected to the input stage circuit. Each cross-connect circuit may comprise a plurality of switches. | 2020-07-02 |
20200212859 | AMPLIFIER FOR CUTTING LEAKAGE CURRENT AND ELECTRONIC DEVICE INCLUDING THE AMPLIFIER - An electronic device including an amplifier which includes a first transistor configured to receive an input signal through a gate terminal thereof and having a source terminal electrically connected to ground, a second transistor configured to transmit an output signal through a drain terminal thereof and having a gate terminal electrically connected to the ground, and a switch electrically connected to the gate terminal of the second transistor and configured to switch a voltage being supplied to the gate terminal of the second transistor in accordance with turn-on or turn-off of the amplifier. | 2020-07-02 |
20200212860 | VOLTAGE DETECTION CIRCUIT - A voltage detection circuit including an input voltage stage configured to scale down an input voltage to produce a scaled down voltage, a gain loss stage configured to receive and adjust the scaled down voltage based on a determined gain or loss to be applied to the scaled down voltage, and a comparison circuit configured to determine if the input voltage is over or under a desired voltage value. | 2020-07-02 |
20200212861 | PROGRAMMABLE GAIN AMPLIFIER SYSTEMS AND METHODS - Systems and methods for amplifying an input signal include amplifier circuitry, an itail connection coupled between a positive voltage circuitry and the negative voltage circuitry and operable to generate an itail voltage corresponding to a greater of the positive voltage input signal (Vp) and the negative voltage input signal (Vn), a first resistor rgp disposed to receive the itail voltage and a first voltage corresponding to Vp, and a second resistor rgn disposed to receive the itail voltage and a second voltage corresponding to Vn. A first current output node is coupled to the output of rgp and operable to output a positive output current (Ioutp) corresponding to the current flowing through rgp, and a second current output is coupled to the output of rgn and operable to output a negative output current (Ioutn) corresponding to the current flowing through rgn. | 2020-07-02 |
20200212862 | RADIO FREQUENCY FRONT-END PROTECTION WITH TUNABLE COUPLER - A radio frequency front-end includes a power amplifier. The radio frequency front-end also includes a coupler implemented in at least a portion of a matching circuit, the matching circuit coupled to an output of the power amplifier. The radio frequency front-end further includes a control loop comprising a first feedback terminal at an output of the power amplifier. The control loop includes the coupler coupled to the first feedback terminal of the power amplifier and is configured to generate a feedback signal provided to a second feedback terminal to adjust a gain of the power amplifier. The feedback signal is based on a reflected radio frequency signal provided by the coupler. | 2020-07-02 |
20200212863 | METHOD TO CONTROL THE DYNAMIC RANGE OF A SIGNAL - Various embodiments of the present disclosure are directed to modifying an input signal. In one example of a process for modifying an input signal, the process includes splitting the input signal into at least a first input part and a second input part, the amplification of at least the first input part with a linear gain to create a first output part, the nonlinear amplification of at least the second input part of the input signal to create a second output part, and summing the first output part and the second output part in order to provide an output signal. | 2020-07-02 |
20200212864 | 2D & 3D RF Lumped Element Devices for RF System in a Package Photoactive Glass Substrates - The present invention includes a method for creating a system in a package with integrated lumped element devices is system-in-package (SiP) or in photo-definable glass, comprising: masking a design layout comprising one or more electrical components on or in a photosensitive glass substrate; activating the photosensitive glass substrate, heating and cooling to make the crystalline material to form a glass-crystalline substrate; etching the glass-crystalline substrate; and depositing, growing, or selectively etching a seed layer on a surface of the glass-crystalline substrate on the surface of the photodefinable glass, wherein the integrated lumped element devices reduces the parasitic noise and losses by at least 25% from a package lumped element device mount to a system-in-package (SiP) in or on photo-definable glass when compared to an equivalent surface mounted device. | 2020-07-02 |
20200212865 | ACOUSTIC WAVE DEVICE, FILTER, AND MULTIPLEXER - An acoustic wave device includes: a substrate; a lower electrode, an air gap being interposed between the lower electrode and the substrate; a piezoelectric film located on the lower electrode; and an upper electrode located on the piezoelectric film such that a resonance region where at least a part of the piezoelectric film is interposed between the upper electrode and the lower electrode is formed and the resonance region overlaps with the air gap in plan view, wherein a surface facing the substrate across the air gap of the lower electrode in a center region of the resonance region is positioned lower than a surface closer to the piezoelectric film of the substrate in an outside of the air gap in plan view. | 2020-07-02 |
20200212866 | FILTER CIRCUIT AND FILTER DEVICE - A filter circuit that secures the steepness from a pass range to an attenuation range while maintaining a wide-band transmission characteristic and a filter device including this filter circuit are formed. A filter circuit includes a first filter and a second filter. The first filter is a filter including an LC circuit in which a first frequency band is a pass band and a frequency band not higher than the first frequency band is an attenuation band. The second filter is a filter that attenuates a second frequency band within the first frequency band by using an attenuation pole produced by a resonance or an antiresonance of an acoustic wave resonator. Further, the first filter is placed closer to an antenna terminal than the second filter. | 2020-07-02 |
20200212867 | METHODS AND APPARATUSES FOR SELECTIVE COMMUNICATION BETWEEN TAG AND READER USING FILTER - The present disclosure relates to a method and apparatus for selective communication between a tag and a reader using a filter. According to an embodiment of the present disclosure, a communication method between a tag and a reader using a filter performed by a reader includes generating a filter based on tag information of the tag to collect data, transmitting the generated filter to the tag, and receiving data from a tag that selected through a filtering operation of the transmitted filter. | 2020-07-02 |
20200212868 | Impedance Matching Device and Impedance Matching Method - An impedance matching device | 2020-07-02 |
20200212869 | Impedance Matching Device and Impedance Matching Method - An impedance matching device comprises a variable capacitor including multiple capacitance elements and connected in parallel having capacitors and each having one end connected in series to a high-frequency power source and semiconductor switches and connected to the respective capacitors, and a control unit. The control unit derives a reflection coefficient based on the obtained information concerning an impedance viewed from the high-frequency power source toward the load side, updates the states of the respective semiconductor switches and included in the multiple capacitance elements and with a first cycle in the case where the reflection coefficient is equal to or more than a predetermined value, and updates the states of the respective semiconductor switches and included in the plurality of capacitance elements and with a second cycle longer than the first cycle in the case where the reflection coefficient is less than the predetermined value. | 2020-07-02 |
20200212870 | HIGH-FREQUENCY MODULE - A high-frequency module ( | 2020-07-02 |
20200212871 | Apparatus for Antenna Impedance-Matching and Associated Methods - An apparatus includes an impedance matching circuit for matching an impedance of a high quality factor (high-Q) antenna to an impedance of a radio-frequency (RF) circuit. The impedance matching network includes a first reactive network. The impedance matching network also includes a second reactive network coupled in series with the first reactive network. The second reactive network includes a reactive component realized by multiple reactive components so as to reduce sensitivity of the impedance matching network to component tolerances in the second reactive network. | 2020-07-02 |
20200212872 | VOLTAGE SENSOR DEVICE BASED ON A TUNABLE BULK ACOUSTIC WAVE (BAW) RESONATOR - A voltage sensor device includes an oscillator unit, the oscillator unit having a tunable bulk acoustic wave (BAW) resonator device and an oscillator core. The voltage sensor device also includes a frequency analyzer configured to obtain frequency measurements for the oscillator unit and to determine a voltage sense value based on a comparison of at least some of the obtained frequency measurements. The voltage sensor device also includes an output interface configured to store or output voltage sense values determined by the frequency analyzer. | 2020-07-02 |
20200212873 | SPURIOUS-MODE-FREE, LATERALLY-VIBRATING MICROELECTROMECHANICAL SYSTEM RESONATORS - A micro-resonator includes a first electrode positioned on a piezoelectric plate at a first end of the piezoelectric plate, the first electrode including a first set of fingers and a second electrode positioned on the piezoelectric plate at a second end of the piezoelectric plate. The second electrode including a second set of fingers interdigitated with the first set of fingers with an overlapping distance without touching the first set of fingers, the overlapping distance being less than seven-tenths the length of one of the first set of fingers or the second set of fingers. At least one of the first end or the second end of the piezoelectric plate may define a curved shape. | 2020-07-02 |
20200212874 | VIBRATION DEVICE, ELECTRONIC APPARATUS AND VEHICLE - A vibration device includes a first substrate that includes a first surface and a second surface; a second substrate that includes a third surface and a fourth surface; an intermediate substrate that is disposed between the first substrate and the second substrate and that includes a vibration element, a frame surrounding the vibration element, and a coupler linking the vibration element and the frame; a conductive first joining member that is located between the frame and the first substrate and that joins the frame and the second surface; a conductive second joining member that is located between the frame and the second substrate and that joins the frame and the third surface; an internal electrode disposed on the first substrate; and a first conductive member that is disposed between the first substrate and the intermediate substrate and that electrically couples the vibration element and the internal electrode. | 2020-07-02 |
20200212875 | MULTI-LAYER PIEZOELECTRIC SUBSTRATE WITH GROUNDING STRUCTURE - An acoustic wave device is disclosed. The acoustic wave device can include a piezoelectric layer positioned over a substrate. The acoustic wave device can also include an interdigital transducer electrode positioned over the piezoelectric layer. The acoustic wave device can also include a grounding structure positioned over the piezoelectric layer. The acoustic wave device can also include a conductive layer positioned between the piezoelectric layer and the substrate. The acoustic wave device can further include an electrical pathway that electrically connects the conductive layer to the grounding structure. | 2020-07-02 |
20200212876 | ACOUSTIC WAVE DEVICE WITH TRANSVERSE MODE SUPPRESSION - Aspects of this disclosure relate to an acoustic wave device with transverse mode suppression. The acoustic wave device can include a piezoelectric layer, an interdigital transducer electrode, a temperature compensation layer, and a multi-layer mass loading strip. The mass loading strip has a density that is higher than a density of the temperature compensation layer. The mass loading strip can overlap edge portions of fingers of the interdigital transducer electrode. The mass loading strip can include a first layer for adhesion and a second layer for mass loading. The mass loading strip can suppress a transverse mode. | 2020-07-02 |
20200212877 | RESONATOR AND RESONANCE DEVICE - A resonator includes a vibration portion with a vibration arm extending from a base and having an open end that performs bending vibration. The vibration portion includes upper and lower electrodes with a piezoelectric film disposed therebetween that causes bending vibration of the vibration arm when a voltage is applied between the upper and lower electrodes. A protective film faces the piezoelectric film with the upper electrode interposed therebetween and a conductive film faces the piezoelectric film with the protective film interposed therebetween. Moreover, the conductive film is exposed in a region at the open end and a via electrode is formed in the protective film to electrically connect the conductive film to one of the upper and lower electrodes. The via electrode is positioned closer to a first region than the open end in the second region of the vibration arm in a plan view of the piezoelectric film. | 2020-07-02 |
20200212878 | ACOUSTIC WAVE DEVICES WITH COMMON CERAMIC SUBSTRATE - An acoustic wave component is disclosed. The acoustic wave component can include a bulk acoustic wave resonator and a surface acoustic wave device. The bulk acoustic wave resonator can include a first portion of a ceramic substrate, a first piezoelectric layer positioned on the ceramic substrate, and electrodes positioned on opposing sides of the first piezoelectric layer. The surface acoustic wave device can include a second portion of the ceramic substrate, a second piezoelectric layer positioned on the ceramic substrate, and an interdigital transducer electrode on the second piezoelectric layer. | 2020-07-02 |
20200212879 | BAW RESONATOR BASED PRESSURE SENSOR - A pressure sensor apparatus is disclosed. The pressure sensor apparatus includes a bulk acoustic wave (BAW) die having a die interface side and a pressure contact side, a sensor BAW resonator and a reference BAW resonator disposed on the die interface side of the BAW die, a control circuit die coupled to the die interface side of the BAW die via an attachment layer, and an extended opening on the pressure contact side that extends into a depth of the BAW die and is generally aligned with the sensor BAW resonator, the extended opening being configured to translate an external pressure on the pressure contact side onto the sensor BAW resonator. | 2020-07-02 |
20200212880 | HIGHLY DISPERSIVE BULK ACOUSTIC WAVE RESONATORS - A resonator includes a substrate, an acoustic Bragg mirror disposed above the substrate, and a bottom metal layer disposed above the acoustic Bragg mirror. The resonator also includes a piezoelectric plate disposed above the bottom metal layer. The resonator further includes a top metal layer disposed above the piezoelectric plate. The top metal layer comprises multiple fingers within a single plane and the width of each of the fingers is between 75%-125% of a thickness of the piezoelectric plate. | 2020-07-02 |
20200212881 | INDUCTIVELY-COUPLED MEMS RESONATORS - An apparatus includes a microelectromechanical system (MEMS) die having a first surface and an opposing second surface. The MEMS die includes a surface-mounted resonator on the first surface and includes a first inductor. The apparatus also includes first and second dies. The first die has a third surface and an opposing fourth surface. The first die is coupled to the MEMS die such that the third surface of the first die faces the first surface of the MEMS die. The first and second surfaces are spaced apart. The first die includes an oscillator circuit and a second inductor. The oscillator circuit is coupled to the second inductor. The second inductor is inductively coupled to the first inductor. The second die is electrically coupled to the first die. | 2020-07-02 |
20200212882 | ACOUSTIC WAVE DEVICES WITH COMMON GLASS SUBSTRATE - An acoustic wave component is disclosed. The acoustic wave component can include a bulk acoustic wave resonator and a surface acoustic wave device. The bulk acoustic wave resonator can include a first portion of a glass substrate, a first piezoelectric layer positioned on the glass substrate, and electrodes positioned on opposing sides of the first piezoelectric layer. The surface acoustic wave device can include a second portion of the glass substrate, a second piezoelectric layer positioned on the glass substrate, and an interdigital transducer electrode on the second piezoelectric layer. | 2020-07-02 |
20200212883 | MULTI-LAYER PIEZOELECTRIC SUBSTRATE WITH CONDUCTIVE LAYER - An acoustic wave device is disclosed. The acoustic wave device can include a piezoelectric layer positioned over a substrate. The acoustic wave device can also include an interdigital transducer electrode positioned over the piezoelectric layer. The acoustic wave device can also include a grounding structure positioned over the piezoelectric layer. The acoustic wave device can also include a conductive layer positioned under the substrate such that the substrate is positioned between the conductive layer and the grounding structure. The acoustic wave device can further include an electrical pathway that electrically connects the conductive layer to the grounding structure. | 2020-07-02 |
20200212884 | BULK ACOUSTIC WAVE RESONATOR WITH CERAMIC SUBSTRATE - A bulk acoustic wave resonator is disclosed. The bulk acoustic wave resonator can include a ceramic substrate, and a piezoelectric layer on the ceramic substrate. The bulk acoustic wave resonator can also include first and second electrodes positioned on opposing sides of the piezoelectric layer. The bulk acoustic wave resonator can also include passivation layers that includes a first passivation layer and a second passivation layer. The first passivation layer can be positioned between the ceramic substrate and the first electrode. The second electrode can be positioned between the piezoelectric layer and the second passivation layer. The bulk acoustic wave resonator can further include a frame structure along an edge of an active region of the bulk acoustic wave resonator. | 2020-07-02 |
20200212885 | RESONATOR AND METHOD OF MANUFACTURING THE RESONATOR, AND STRAIN SENSOR AND SENSOR ARRAY INCLUDING THE RESONATOR - Provided are a resonator, a method of manufacturing the resonator, and a strain sensor and a sensor array including the resonator. The resonator is provided to extend in a lengthwise direction from a support. The resonator includes a single crystal material and is provided to extend in a crystal orientation that satisfies at least one from among a Young's modulus and a Poisson's ratio, from among crystal orientations of the single crystal material. | 2020-07-02 |
20200212886 | ELASTIC WAVE FILTER APPARATUS - An elastic wave filter apparatus includes at least one excitation electrode, a first electrode land, and second electrode lands provided on a first main surface of a device substrate including a piezoelectric layer. A signal terminal and metal members are provided on a second main surface of the device substrate. The first electrode land and the signal terminal are connected to a signal potential, and the second electrode lands and the metal members are connected to a ground potential. A first connection electrode connects the first electrode land and the signal terminal, and a second connection electrode connects at least one of the second electrode lands and at least one of the metal members. The at least one metal member connected to the second connection electrode overlaps at least a portion of the at least one excitation electrode across the device substrate. | 2020-07-02 |
20200212887 | ACOUSTIC WAVE DEVICE - An acoustic wave device includes a common terminal, a first terminal, a second terminal, a first filter, a second filter, and an inductor. The first filter has a pass band corresponding to a relatively low frequency range and includes a surface acoustic wave filter using an SH wave. The second filter has a pass band corresponding to a relatively high frequency range. The first filter is between a branch point and the first terminal on a path connecting the common terminal and the first terminal. The second filter is between the branch point and the second terminal on a path connecting the common terminal and the second terminal. The inductor is on a path connecting the branch point and the first filter. | 2020-07-02 |
20200212888 | FILTER DEVICE AND DUPLEXER - In a filter device, a transversal elastic wave filter, which defines a delay element, is connected in parallel with a band pass filter. The transversal elastic wave filter has the same amplitude characteristic as and the opposite phase to the band pass filter at a desired frequency inside an attenuation range of the band pass filter. When a wavelength determined by an electrode finger period of IDTs and is denoted by λ, the distance between the first IDT and the second IDT of the elastic wave filter is about 12λ or less. | 2020-07-02 |
20200212889 | ACOUSTIC WAVE FILTER DEVICE - An acoustic wave filter device includes a substrate, first and second acoustic impedance layers, a piezoelectric layer, first and second interdigital transducer electrodes, an input terminal, an output terminal, ground terminals, a series arm circuit, and a parallel arm circuits. The first interdigital transducer electrode at least partially overlaps the first acoustic impedance layer in the plan view. The second interdigital transducer electrode at least partially overlaps the second acoustic impedance layer in the plan view. The series arm circuit is provided on a first path connecting the input terminal and the output terminal and includes the first and second interdigital transducer electrodes. A conductive layer in the first acoustic impedance layer and a conductive layer in the second acoustic impedance layer are electrically insulated from each other. | 2020-07-02 |
20200212890 | ACOUSTIC WAVE FILTER AND MULTIPLEXER - An acoustic wave filter includes a piezoelectric substrate, first and second input-output terminals, and a longitudinally coupled resonator unit in a path connecting the first and second input-output terminals to each other, and the resonator unit includes five or more interdigital transducer electrodes aligned in an acoustic wave propagation direction, the IDT electrodes include a center IDT electrode at the center in the propagation direction and first and second IDT electrodes at symmetric or substantially symmetric positions in the propagation direction with respect to the center IDT electrode, each of the first and second IDT electrodes includes a main pitch portion and a pair of narrow-pitch portions provided between the main pitch portion and both ends of the IDT electrode in the propagation direction, and the first and second IDT electrodes differ from each other in the number of electrode fingers of the main pitch portion. | 2020-07-02 |
20200212891 | ACOUSTIC WAVE FILTER DEVICE AND MULTIPLEXER - An acoustic wave filter device includes a piezoelectric layer, a high-acoustic-velocity member, a low-acoustic-velocity film between the high-acoustic-velocity member and the piezoelectric layer, and first and second IDT electrodes on the piezoelectric layer to define acoustic wave resonators. An acoustic wave resonator of a series-arm resonator portion closest to an antenna end and/or an acoustic wave resonator of a parallel-arm resonator portion closest to the antenna end includes the first IDT electrode including first and second electrode fingers, and the remaining acoustic wave resonators include the second IDT electrode including third and fourth electrode fingers. In the first IDT electrode, a central area, first and second low-acoustic-velocity areas, and first and second high-acoustic-velocity areas extend along a direction perpendicular or substantially perpendicular to an acoustic wave propagating direction. First and second envelopes connecting the tips of the third and fourth electrode fingers of the second IDT electrode are inclined. | 2020-07-02 |
20200212892 | Impedance Matching Device and Impedance Matching Method - An impedance matching device includes: a variable capacitor in which a plurality of series circuits of capacitors and semiconductor switches are connected in parallel; a calculation unit that calculates an impedance or a reflection coefficient on the load side using information regarding impedance acquired from the outside; and a control unit that determines ON/OFF states to be taken by the semiconductor switches included in the variable capacitor using the impedance or the reflection coefficient calculated by the calculation unit and turns on or off the semiconductor switches based on the determined states. The control unit changes an ON/OFF control timing between one and another of the semiconductor switches. | 2020-07-02 |
20200212893 | Impedance Matching Device and Impedance Matching Method - An impedance matching device includes: a variable capacitor; a calculation unit that calculates a reflection coefficient on the load side; a storage unit that stores the reflection coefficient calculated within a predetermined period so as to be associated with ON/OFF states of the semiconductor switches; a determination unit that determines ON/OFF states to be taken by the semiconductor switches using a calculation result within the predetermined period; a control unit that turns on or off the semiconductor switches based on the determined ON/OFF states; and a counting unit that counts the number of times the determined ON/OFF states have changed. In a case where the counted number of times is larger than a predetermined number of times, the control unit turns on or off the semiconductor switches so as to match ON/OFF states associated with a reflection coefficient closer to 0, among the stored reflection coefficients, and then prohibits ON/OFF switching. | 2020-07-02 |
20200212894 | LOW-POWER-CONSUMPTION CONSTANT-ON-TIME TIMING CIRCUIT DESIGN METHOD AND TIMING CIRCUIT - Provided is a low-power-consumption Constant-On-Time (COT) timing circuit design method and a timing circuit. A Resistor-Capacitor (RC) circuit is adopted for timing, to eliminate static power consumption of a timer. A specific structure includes a fourth P-channel Metal Oxide Semiconductor (MOS) transistor M | 2020-07-02 |
20200212895 | MULTIPHASE OSCILLATOR CIRCUIT - In described examples, a ring oscillator includes a series of N stages in a first ring. Each stage includes a respective output terminal coupled to a respective input terminal of a next one of the stages in the first ring. N is a positive odd-numbered integer of at least three. A series of N level shifters in a second ring are respectively connected to the N stages. Each level shifter receives a respective clock output from a respective output terminal of a stage to which it is connected and generates a respective boosted clock output in response thereto. The boosted clock output is coupled to control an impedance state of a next one of the level shifters in the second ring. | 2020-07-02 |
20200212896 | ENHANCED IMMUNITY LATCHED LOGIC STATE RETENTION - In described examples, a latch includes circuitry for latching input information. The circuitry can be precharged in response to an indication of a first mode and can latch the input information to an indication of a second mode. The latch can optionally further latch the input information in response to a node for storing the latched input information. | 2020-07-02 |
20200212897 | TRANSMISSION HYSTERESIS DETECTING METHOD AND APPARATUS - The present disclosure provides a transmission hysteresis detecting method and apparatus. The method includes: transmitting a forward rotational instruction and a reverse rotational instruction to a motor of the servo; storing motor end positions of the motor and output shaft end positions of an output shaft corresponding to the motor in a forward rotational cycle and a reverse rotational cycle, respectively; generating first position data based on the motor end positions and the corresponding output shaft end positions in the forward rotational cycle; generating second position data based on the motor end positions and the corresponding output shaft end positions in the reverse rotational cycle; and calculating a transmission hysteresis of the servo based on the first position data and the second position data. The technical solutions of the present disclosure only needs to obtain the position data of one forward rotational cycle and one reverse rotational cycle. | 2020-07-02 |
20200212898 | CABLE AND CONNECTION DEVICE - A transmission device is enabled to satisfactorily detecting whether or not a reception device is in the operating state even in a case where an element that adjusts signal quality is interposed in a data line. A cable is connected between the transmission device and the reception device. The element that adjusts signal quality is interposed in the data line. A detection unit detects that the reception device is in the operating state. An information supply unit supplies detection information to the transmission device through a predetermined line. | 2020-07-02 |
20200212899 | METHODS AND APPARATUS FOR PHASE IMBALANCE CORRECTION - Methods, apparatus, systems and articles of manufacture are disclosed to provide phase imbalance correction. An example system includes a phase detector to obtain a first signal and generate a first output, a comparator coupled to the phase detector, the comparator to generate a second output based on the first output, and an amplifier coupled to the comparator, the amplifier to adjust a first phase response of the first signal based on the second output. | 2020-07-02 |
20200212900 | Circuit operating speed detecting circuit - Disclosed is a circuit operating speed detecting circuit configured to detect an operating speed of a target circuit during a monitor mode. The circuit operating speed detecting circuit includes a signal generator, an adjustable delay circuit, and a signal detector. During the monitor mode, the signal generator generates a predetermined signal in a current operating condition, the adjustable delay circuit generates a delay signal according to the predetermined signal in the current operating condition, and the signal detector detects the degree of delay of the delay signal in the current operating condition so as to generate a first result if the degree of delay is not greater than a predetermined threshold and generate a second result if the degree of delay is greater than the predetermined threshold, in which the first and the second results are related to the operating speed of the target circuit. | 2020-07-02 |
20200212901 | Measuring circuit for quantizing variations in circuit operating speed - Disclosed is a measuring circuit for quantizing variations in the operating speed of a target circuit. The measuring circuit includes: a signal generator configured to generate a predetermined signal; an adjustable delay circuit configured to generate a first and second delay signals according to the predetermined signal respectively; a signal detector configured to detect the first and second delay signals respectively and thereby generate a first and second detection results respectively; and a calibrating circuit configured to enable a first and second numbers of delay units of the adjustable delay circuit according to the first and second detection results respectively so as to make each of the delays respectively caused by the first and second numbers of delay units be less than a delay threshold, in which the first and second numbers relate to the operating speed of the target circuit operating in the first and second conditions respectively. | 2020-07-02 |
20200212902 | LATCH COMPARATOR CIRCUIT - A latch comparator which includes a preamplifier and a latch circuit. The preamplifier circuit operates amplification on a pair of differential input signals, and generates a pair of pre-amplified differential signals. The latch circuit receives the pre-amplified differential signals, compares the pair of pre-amplified differential signals, and generates a pair of latched comparison signals. The latch circuit includes a latch and a switch circuit. First and second input terminals of the latch receive the pre-amplified differential signals. The switch circuit includes a switch coupling between one of the first and second input terminals of the latch and the preamplifier circuit. The switch receives one of the pair of latched comparison signals as a control signal, and is switched in response to the one of the latched comparison signal. | 2020-07-02 |
20200212903 | OPERATION METHOD OF SIGNAL RECEIVER, PULSE WIDTH CONTROLLER, AND ELECTRONIC DEVICE INCLUDING THE SAME - An operation method of a signal receiver includes sequentially receiving 0-th and first bits through one signal line, and adjusting a width of any one of a first high duration and a first low duration of a first signal corresponding to the first bit, based on values of the 0-th and first bits, when the values of the 0-th and first bits are identical to each other. | 2020-07-02 |
20200212904 | BOOTSTRAPPED SWITCH CIRCUIT WITH IMPROVED SPEED - A bootstrapped switch circuit includes an auxiliary loop circuit for assisting the boosting of a bootstrap voltage in a main loop circuit having a bootstrapped switch transistor. The boosted bootstrap voltage switches on the bootstrapped switch transistor so that an input voltage signal may conduct through the bootstrapped switch transistor to charge a sampling node. | 2020-07-02 |
20200212905 | Square Wave Generating Method and Square Wave Generating Circuit - The present application provides a square wave generating method, applied in a square wave generating circuit, configured to generate a mimetic square wave signal, wherein the square wave generating circuit has a breakdown voltage. The square wave generating method comprises the square wave generating circuit generating the mimetic square wave signal as a first voltage during a first time interval; the square wave generating circuit generating the mimetic square wave signal as a second voltage during a second time interval; and the square wave generating circuit generating the mimetic square wave signal as a transient voltage during a transient interval between the first time interval and the second time interval, wherein the transient voltage is between the first voltage and the second voltage; wherein a first voltage difference between the first voltage and the second voltage is greater than the breakdown voltage. | 2020-07-02 |
20200212906 | DRIVE CIRCUIT FOR POWER SEMICONDUCTOR ELEMENT - A drive circuit for a power semiconductor element according to the present disclosure includes: a control command unit that outputs a turn-on command for a power semiconductor element; a gate voltage detection unit that detects a gate voltage applied to a gate terminal after the control command unit outputs the turn-on command; a differentiator that subjects the gate voltage detected by the gate voltage detection unit to time differentiation; and a determination unit that determines, based on the gate voltage detected by the gate voltage detection unit and a differential value by the differentiator, whether the power semiconductor element is in a short-circuit state or not. | 2020-07-02 |
20200212907 | HIGH TEMPERATURE GATE DRIVER FOR SILICON CARBIDE METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR - A high temperature (HT) gate driver for Silicon Carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET) uses commercial off-the-shelf COTS discrete components, and has an integrated short-circuit or overcurrent protection circuit and under voltage lock out (UVLO) protection circuit. | 2020-07-02 |
20200212908 | POWER SWITCHING DEVICES WITH HIGH DV/DT CAPABILITY AND METHODS OF MAKING SUCH DEVICES - Power switching devices include a semiconductor layer structure that has an active region and an inactive region. The active region includes a plurality of unit cells and the inactive region includes a field insulating layer on the semiconductor layer structure and a gate bond pad on the field insulating layer opposite the semiconductor layer structure. A gate insulating pattern is provided on the semiconductor layer structure between the active region and the field insulating layer, and at least one source/drain contact is provided on the semiconductor layer structure between the gate insulating pattern and the field insulating layer. | 2020-07-02 |
20200212909 | MILLER TRANSITION CONTROL GATE DRIVE CIRCUIT - Aspects of the present disclosure are directed toward designs and methods of improving driving of switching devices. One proposed solution to improving driving of switching devices is an auxiliary control circuit that selectively guides the switching device through at least one switching region, permitting an improved operation of the switching device. | 2020-07-02 |
20200212910 | TRANSISTOR SWITCH CIRCUIT - A transistor switch circuit includes a first transistor and a set of serially connected transistors. By the configuration of the set of serially connected transistors, the conduction paths of the body diodes of the first transistor can be cut and the body effect thereof is eliminated. Hence, the output signal is prevented from leaking via the conduction path while the first transistor is turned off. | 2020-07-02 |
20200212911 | DETECTION APPARATUS AND DETECTION METHOD THEREOF - A detection apparatus and a detecting method thereof are provided. In the method, an input impedance structure, a sensing impedance structure and an output impedance structure are provided. The sensing impedance structure is connected to the input impedance structure. At least two impedances are formed in the sensing impedance structure. The output impedance structure is connected to the sensing impedance structure. At least three discontinuous impedance surfaces are formed in the input impedance structure, the sensing impedance structure and the output impedance structure. A detection signal is inputted into the input impedance structure, and the detection signal passes through the three impedance structures. Then, a variation of at least one of the discontinuous impedance surfaces can be determined according to the outputted detection signal from the output impedance structure. | 2020-07-02 |
20200212912 | DATA RETENTION CIRCUIT - A data retention circuit includes a power switch, a first inverter and a second inverter. The power switch has a first connection terminal coupled to a power voltage, and a second connection terminal coupled to the first power terminal and a second power terminal of a second inverter. The second input terminal and the second output terminal of the second inverter are coupled to the first output terminal and the first input terminal of the first inverter, respectively. In a sleep mode, the power switch and the transistor are turned off, a first leakage current flows between the first connection terminal and the second connection terminal, a second leakage current flows between the first power terminal and the first output terminal, and the first and the second leakage currents form a steady-state voltage, higher than or equal to a data retention voltage, on a second connection terminal. | 2020-07-02 |
20200212913 | LEVEL CONVERTER AND A METHOD FOR CONVERTING LEVEL VALUES IN VEHICLE CONTROL DEVICES - A level converter for a vehicle control device, including: a first voltage terminal; a second voltage terminal; at least one output terminal; an input terminal; a first switch for switching a first current path between the first voltage terminal and the at least one output terminal or one of the output terminals; and a second switch for switching a second current path between the second voltage terminal and the at least one output terminal or another of the output terminals; the first and second switches being switchable in response to different levels at the input terminal so that when a first level is present at the input terminal, the first switch is closed and the second switch is open, and so that when a second level is present, the first switch is open and the second switch is closed. Also described is a related control device, utility vehicle and method. | 2020-07-02 |
20200212914 | LOGIC DRIVE USING STANDARD COMMODITY PROGRAMMABLE LOGIC IC CHIPS COMPRISING NON-VOLATILE RANDOM ACCESS MEMORY CELLS - A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output. | 2020-07-02 |
20200212915 | Systems and Methods for Dynamic Phase Alignment of Clocks - A phase alignment system for aligning clocks is disclosed. The system includes a calibration circuit and a phase locked loop (PLL). The calibration circuit is configured to receive a variable clock and a reference clock; determine phase alignment based on metastability; determine phase misalignment and generate a phase shift upon determining phase misalignment. The PLL is configured to generate the variable clock and incorporate the phase shift. | 2020-07-02 |
20200212916 | TIME-TO-DIGITAL CONVERTER STOP TIME CONTROL - In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages. | 2020-07-02 |
20200212917 | METHOD AND APPARATUS FOR SOURCE-SYNCHRONOUS SIGNALING - A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals. | 2020-07-02 |
20200212918 | Adaptive Non-linearity Identification and Compensation Using Orthogonal Functions in a Mixed Signal Circuit - A feedback divider in a mixed-signal circuit is modulated by a frequency control word controlling a delta-sigma modulator. An accumulated quantization error from the delta-sigma modulator is compared to a residual error in the circuit by a Least-Mean Square (LMS) correlator for gain calibration to adjust for linear errors. Upper bits of the accumulated quantization error access a lookup table to find two outputs of the compensation function that are interpolated between using lower bits of the accumulated quantization error. The interpolated result is an adjustment subtracted from the loop to compensate for non-linear errors. A set of orthogonal kernels is generated from the accumulated quantization error and calibrated using another LMS correlator and inverse transformed to generate updates to the non-linear compensation function in the lookup table. The kernels can be Walsh Hadamard (WH) and the inverse transformer an inverse WH transformer. | 2020-07-02 |
20200212919 | Atomic Oscillator And Frequency Signal Generation System - An atomic oscillator includes: a light-emitting element; an atom cell that includes a first surface on which light beams from the light-emitting element are incident and a second surface from which the light beams incident on the first surface are emitted and accommodates alkali metal atoms in a gas state; a shield that accommodates the atom cell and has a magnetic shielding property, the shield having an opening; a heat transfer member that is in contact with a portion of the atom cell via an opening of the shield and has a thermal conductivity higher than a thermal conductivity of the atom cell; a temperature control element that is in contact with the heat transfer member and controls a temperature of the atom cell; and a light-receiving element that receives the light beams emitted from the second surface. | 2020-07-02 |
20200212920 | ANALOG SYSTEM AND ASSOCIATED METHODS THEREOF - Methods and systems 10 are provided for circuits. One method is for increasing device threshold voltage distribution of a plurality of devices of a circuit. The method includes adjusting a device threshold voltage of the plurality of devices by different amounts; and selecting a subset of the plurality of devices with adjusted device threshold voltage by a device selection module for performing a function associated with the circuit. In one aspect, a system for device threshold voltage adjustment is provided. The system includes a sensor module for sensing one or more of temperature and voltage values of a die having a plurality of devices for a circuit; and a threshold temperature and voltage compensation module for receiving an input value from the sensor module to compensate variation in a device threshold voltage caused by changes of one or more of temperature and voltage of the die. | 2020-07-02 |
20200212921 | TOP PLATE SAMPLING ANALOG-TO-DIGITAL CONVERTER (ADC) WITH RESIDUE AMPLIFIER NON-LINEARITY REDUCTION - A top-plate sampling analog-to-digital converter (ADC) circuit includes a first ADC stage and a residue amplifier coupled to the first ADC stage. The residue amplifier comprises a first transistor with a control terminal, a first current terminal, and a second current terminal. The residue amplifier also comprises a second transistor with a control terminal, a first current terminal, and a second current terminal. The residue amplifier also comprises a linearity adjustment circuit coupled to a second current terminal of at least one of the first transistor and the second transistor. The linearity adjustment circuit comprises at least one switch that changes its state as a function of an input sampling phase and a gain phase of the residue amplifier. | 2020-07-02 |
20200212922 | Linear and Non-Linear Calibration for Time Interleaved Digital-to-Analog Converter - A time-interleaved digital-to-analog converter system, comprising a digital pre-distorter configured to receive an input digital signal and an error signal and output a distorted digital signal based on the input digital signal and the error signal; a time-interleaved digital-to-analog converter having a first sample rate, the time-interleaved digital-to-analog converter configured to convert the distorted digital signal to an analog signal; and a calibration system. The calibration system includes an analog-to-digital converter having a second sample rate equal to or lower than the first sample rate, the analog-to-digital converter configured to receive the analog signal and covert the analog signal to a down-sampled digital signal, a discrete-time linear model configured to receive the input digital signal and the error signal and output a model signal, and a combiner to subtract the down-sampled digital signal from the model signal to generate the error signal. | 2020-07-02 |
20200212923 | DIGITAL SIGNAL PROCESSING WAVEFORM SYNTHESIS FOR FIXED SAMPLE RATE SIGNAL SOURCES - A test and measurement instrument including a digital-to-analog converter having an output sample rate configured to receive a digital sample waveform and a reference clock and output an analog waveform at the sample rate, a waveform synthesizer configured to receive an input waveform having a baud rate and output a digital sample waveform having a baud rate less than the sample rate of the digital-to-analog converter, and a port configured to output the analog waveform. | 2020-07-02 |
20200212924 | TOP PLATE SAMPLING ANALOG-TO-DIGITAL CONVERTER (ADC) HAVING A DYNAMIC COMPARATOR WITH A PREAMPLIFIER AND A CLAMP CIRCUIT - A system includes analog-to-digital converter (ADC) logic, wherein the ADC logic includes a stage with a dynamic comparator circuit. The ADC logic also includes a residue stage. The dynamic comparator circuit includes a preamplifier and a common mode clamp circuit for the preamplifier. | 2020-07-02 |
20200212925 | ANALOG-TO-DIGITAL CONVERSION CIRCUIT AND SIGNAL CONVERSION METHOD THEREOF - A conventional analog-to-digital conversion circuit has a problem that conversion errors cannot be suppressed. According to one embodiment, the analog-to-digital conversion circuit includes a first digital-to-analog conversion circuit | 2020-07-02 |
20200212926 | DUAL OUTPUT SIGNAL PATHS FOR SIGNAL SOURCE CHANNELS TO OPTIMIZE FOR BANDWIDTH AND AMPLITUDE RANGE - A signal source device includes at least one digital-to-analog converter, at least one connector, a first output path from the at least one digital-to-analog converter to the at least one connector, and a second output path from the at least one digital-to-analog converter to the at least one connector. A method of generating a analog signal includes generating at least one analog signal from at least one digital-to-analog converter, transmitting a first analog signal of the at least one analog signal along a first output path from the at least one digital-to-analog converter to at least one connector, and transmitting a second analog signal of the at least one analog signal along a second output path from the at least one digital-to-analog converter to the at least one connector. | 2020-07-02 |
20200212927 | ELECTRONIC DEVICE FORMING A DIGITAL-TO-ANALOG CONVERTER AND A MIXER - An acquisition stage receives a digital input signal and generates therefrom a first digital signal and a second digital signal complementary thereto. First and second processing stages receive the first and second digital signals and generate therefrom first and second analog signals in time with first and second complementary clock signals. An output stage generates an internal clock signal equivalent to one of: the first clock signal phase shifted by a duration of a transient occurring during a period of the first clock signal, or the second clock signal phase shifted by a duration of a transient occurring during a period of the second clock signal. The output stage produces an analog output signal equal to the first analog signal when the internal clock signal is at a first logic level, and equal to the second analog signal when the internal clock signal is at a second logic level. | 2020-07-02 |
20200212928 | RADIO-FREQUENCY DIGITAL-TO-ANALOG CONVERTER SYSTEM - A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously. | 2020-07-02 |
20200212929 | RFDAC (RF (RADIO FREQUENCY) DAC (DIGITAL-TO-ANALOG CONVERTER)) WITH IMPROVED EFFICIENCY AND OUTPUT POWER - High efficiency amplitude DACs (Digital-to-Analog Converters) and RFDACs (Radio Frequency DACs) employing such amplitude DACs are discussed. One exemplary embodiment is a DAC comprising a plurality of DAC stages, wherein each DAC stage of the plurality of DAC stages is associated with a respective predetermined voltage of a plurality of predetermined voltages, wherein each DAC stage of the plurality of DAC stages can receive a digital signal at the respective predetermined voltage associated with that DAC stage when the respective predetermined voltage of that DAC stage is a selected predetermined voltage, wherein the selected predetermined voltage is based on an amplitude of the digital signal, and wherein each DAC stage of the plurality of DAC stages can generate a respective analog signal associated with that DAC stage based on the digital signal received at that DAC stage when the respective predetermined voltage of that DAC stage is the selected predetermined voltage. | 2020-07-02 |
20200212930 | SIGNAL PROCESSING APPARATUS, SIGNAL PROCESSING METHOD, AND PROGRAM - The present technology relates to a signal processing apparatus, a signal processing method, and a program that make it possible to cope with an output of a PCM signal using one DSD signal. A distribution apparatus includes an extraction section that, in a case where a PCM signal having a predetermined sampling frequency is generated from a DSD signal, extracts a predetermined number of samples from the DSD signal around samples at a predetermined interval determined by the predetermined sampling frequency, and a filtering section that generates the PCM signal having the predetermined sampling frequency by filtering the extracted predetermined number of samples. The present technology is applicable to, for example, a distribution apparatus, etc., that distributes the PCM signal to a client apparatus. | 2020-07-02 |
20200212931 | DATA PROCESSING APPARATUSES, METHODS, COMPUTER PROGRAMS AND COMPUTER-READABLE MEDIA - A first value of a first data element in a first set of data elements is obtained, the first set of data elements being based on a first time sample of a signal. A second value of a second data element in a second set of data elements is obtained, the second set of data elements being based on a second, later time sample of the signal. A measure of similarity is derived between the first value and the second value. Based on the derived measure, a quantisation parameter useable in performing quantisation on data based on the first time sample of the signal is determined. Output data is generated using the quantisation parameter. | 2020-07-02 |
20200212932 | REDUCING STORAGE OF BLOCKCHAIN METADATA VIA DICTIONARY-STYLE COMPRESSION - A method of reducing the storage requirements of blockchain metadata via dictionary-style compression includes receiving a request to add a transaction block to a blockchain. The method further includes determining an identifier (ID) of a dictionary block most recently stored on the blockchain. The method further includes compressing, by a processing device, one or more transactions of the transaction block based on the dictionary block to generate a compressed transaction block. The method further includes adding the ID of the dictionary block to the compressed transaction block. The method further includes providing the compressed transaction block, including the ID of the dictionary block, for storage on the blockchain. | 2020-07-02 |
20200212933 | ENCODING METHOD AND APPARATUS - This application provides an encoding method and apparatus in a wireless communications system. The method includes: performing cyclic redundancy check (CRC) encoding on A to-be-encoded information bits based on a CRC polynomial, to obtain a first bit sequence, where the first bit sequence includes L CRC bits and the A information bits; and performing polar encoding on the first bit sequence, where L has a value of one of 3, 4, 5, 8, and 16. Based on an improved CRC polynomial, coding satisfying a false alarm rate (FAR) requirement is implemented. | 2020-07-02 |
20200212934 | NON-LINEAR LLR LOOK-UP TABLES - In one implementation, the disclosure provides a system including a detector configured to generate an output of a first log-likelihood ratio for each bit in an input data stream. The system also includes at least one look-up table providing a mapping of the first log-likelihood ratio to a second log-likelihood ratio. The mapping between the first log-likelihood ratio and the second log-likelihood ratio is non-linear. The system also includes a decoder configured to generate an output data stream using the second log-likelihood ratio to generate a value for each bit in the input data stream. | 2020-07-02 |
20200212935 | VARIABLE READ ERROR CODE CORRECTION - Devices and techniques for variable read throughput control in a storage device are described herein. Bits from can be received for a read that is one of several types assigned to reads. A low-density parity-check (LDPC) iteration maximum can be set based on the type. LDPC iterations can be performed up to the LDPC iteration maximum and a read failure signaled in response to the LDPC iterations reaching the LDPC iteration maximum. | 2020-07-02 |
20200212936 | LOW LATENCY POLAR CODING AND DECODING BY MERGING OF STATES OF THE POLAR CODE GRAPH - A polar decoder kernal is described. The polar decoder kernal is configured to: receive one or more soft bits from a soft kernal encoded block having a block size of N and output one or more recovered kernal information bits from a recovered kernal information block having a block size of N. The polar decoder kernal comprises a decomposition of a polar code graph into an arbitrary number of columns depending on the kernal block size N. | 2020-07-02 |
20200212937 | METHODS AND APPARATUS FOR PROCESSING LDPC CODED DATA - Methods and Apparatus for processing data encoded by low density parity check (LDPC) in a communication system are disclosed herein. In one embodiment, a method performed by a first node is disclosed. The method comprises: encoding an information bit sequence based on an LDPC coding scheme to obtain an encoded bit sequence; generating a master bit sequence based on the encoded bit sequence; selecting a subset of the master bit sequence according to a rate matching rule to obtain a rate matched bit sequence; interleaving the rate matched bit sequence according to a predetermined index sequence to obtain a to-be-transmitted bit sequence; and transmitting the to-be-transmitted bit sequence to a second node. | 2020-07-02 |
20200212938 | MODULATOR AND MODULATION METHOD USING NON-UNIFORM 16-SYMBOL SIGNAL CONSTELLATION FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING 4/15 CODE RATE - A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 4/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis. | 2020-07-02 |
20200212939 | NON-LINEAR LLR LOOK-UP TABLES - In one implementation, the disclosure provides a system including a detector configured to generate an output of a first log-likelihood ratio for each bit in an input data stream. The system also includes at least one look-up table providing a mapping of the first log-likelihood ratio to a second log-likelihood ratio. The mapping between the first log-likelihood ratio and the second log-likelihood ratio is non-linear. The system also includes a decoder configured to generate an output data stream using the second log-likelihood ratio to generate a value for each bit in the input data stream. | 2020-07-02 |
20200212940 | CIRCULAR BUFFER RATE MATCHING FOR POLAR CODES - Methods are proposed herein to perform rate matching for polar codes via circular buffering of the polar encoded bits. Embodiments are directed to methods of operation of a transmitting node in a wireless system including performing polar encoding of a set of information bits in accordance with a polar sequence of length N | 2020-07-02 |
20200212941 | Method And Apparatus For Energy Efficient Transmission And Reception Of A Signal Using Aliasing - A method of transmitting a signal in a wireless communication network from a transmitting device to a receiving device, wherein said receiving device comprises an Analog to Digital Converter, ADC, arranged to sample a received signal at a predetermined sampling frequency. The method comprising the steps of generating | 2020-07-02 |
20200212942 | ACTIVE MULTIPLEXER REPEATER ACCESSORY - A technology is described for a bi-directional repeater having a switchable antenna port. The repeater can comprise a switchable common port, a switchable second-band port, and a switchable third-band port. The repeater can have a first-band amplification and filtering path coupled to the switchable common port via a first path of a first multiplexer. The repeater can have a second-band amplification and filtering path coupled to one of the switchable common port via a second path of the first multiplexer, a first path of a first radio frequency (RF) switch, and a first path of a second multiplexer. The repeater can have a third band amplification and filtering path coupled to the switchable common port via a first path of a second RF switch, the second path of the second multiplexer, the first path of the first RF switch, and the second path of the first diplexer. | 2020-07-02 |