27th week of 2020 patent applcation highlights part 68 |
Patent application number | Title | Published |
20200212041 | THREE-DIMENSIONAL DYNAMIC RANDOM-ACCESS MEMORY ARRAY - Disclosed are monolithically integrated three-dimensional (3D) DRAM array structures that include one-transistor, one-capacitor (1T1C) cells embedded at multiple device tiers of a layered substrate assembly. In some embodiments, vertical electrically conductive data-line and ground pillars extending through the substrate assembly provide the transistor source and ground voltages, and horizontal electrically conductive access lines at multiple device levels provide the transistor gate voltages. Process flows for fabricating the 3D DRAM arrays are also described. | 2020-07-02 |
20200212042 | CAPACITOR STRUCTURE - A capacitor structure including a semiconductor substrate; a dielectric layer on the semiconductor substrate; a storage node pad in the dielectric layer; a lower electrode including a bottle-shaped bottom portion recessed into the dielectric layer and being in direct contact with the storage node pad; and a lattice layer supporting a topmost part of the lower electrode, wherein the lattice layer is not directly contacting the dielectric layer, but is directly contacting the topmost part of the lower electrode. The bottle-shaped bottom portion extends to a sidewall of the storage node pad. The bottle-shaped bottom portion has a width that is wider than other portion of the lower electrode. | 2020-07-02 |
20200212043 | Construction Of Integrated Circuitry, DRAM Circuitry, A Method Of Forming A Conductive Line Construction, A Method Of Forming Memory Circuitry, And A Method Of Forming DRAM Circuitry - A construction of integrated circuitry comprises a horizontal longitudinally-elongated conductive line. A horizontal longitudinally-elongated void space extends longitudinally along opposing longitudinal sides of the conductive line. The void space along each of the opposing longitudinal sides has cyclically varying height longitudinally along the conductive line. Methods independent of the above structure are disclosed. | 2020-07-02 |
20200212044 | METHOD OF FABRICATING DYNAMIC RANDOM ACCESS MEMORY - A dynamic random access memory and a method of fabricating the same are provided. The dynamic random access memory includes forming a gate trench in a substrate. An isolation structure is formed in the substrate and defines a plurality of active regions arranged in a column in a first direction. A buried word line structure is formed to fill the gate trench and extend along the first direction and across the plurality of active regions and the isolation structure. A plurality of first fin structures is formed in an intersecting region of the plurality of active regions and the buried word line structure, arranged in a column along the first direction, and surrounded and covered by the buried word line structure. A dielectric layer is formed on the substrate to fill the gate trench and cover the buried word line structure. | 2020-07-02 |
20200212045 | VERTICAL 2-TRANSISTOR MEMORY CELL - Some embodiments include apparatuses and methods of forming the apparatus. One of the apparatuses and methods includes a memory cell having a first transistor and a second transistor located over a substrate. The first transistor includes a channel region. The second transistor includes a channel region located over the channel region of the first transistor and electrically separated from the first channel region. The memory cell includes a memory element located on at least one side of the channel region of the first transistor. The memory element is electrically separated from the channel region of the first transistor, and electrically coupled to the channel of the second transistor. | 2020-07-02 |
20200212046 | METHODS OF FORMING AN APPARATUS, AND RELATED APPARATUSES AND ELECTRONIC SYSTEMS - A method of forming an apparatus comprises forming a first metal nitride material over an upper surface of a conductive material within an opening extending through at least one dielectric material through a non-conformal deposition process. A second metal nitride material is formed over an upper surface of the first metal nitride material and side surfaces of the at least one dielectric material partially defining boundaries of the opening through a conformal deposition process. A conductive structure is formed over surfaces of the second metal nitride material within the opening. Apparatuses and electronic systems are also described. | 2020-07-02 |
20200212047 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes providing a substrate including a pair of first regions and a second region therebetween, forming first patterns on the respective first regions to at least partially define a stepwise portion at the second region, and forming a dummy pattern that at least partially fills the stepwise portion. The dummy pattern may be an electrically floating structure. The dummy pattern may be formed as part of forming second patterns on the respective first regions, and the dummy pattern and the second patterns may include substantially common materials. Because the dummy pattern at least partially fills the stepwise portion at the second region, the material layer covering the second patterns and the dummy pattern may omit a corresponding stepwise portion. | 2020-07-02 |
20200212048 | METHOD FOR FORMING SEMICONDUCTOR PATTERN - The present invention provides a method for forming a semiconductor pattern, comprising: firstly, a target layer is provided and a first material layer is formed on the target layer, and then a first pattern is formed on the first material layer, followed by a first self-aligned double pattering step is performed, a plurality of first grooves are formed in the first material layer. Next, a second material layer is formed on the first material layer, and a plurality of second grooves are formed in the second material layer. Next, transferring a pattern of the overlapping portion of the first grooves and the second grooves into the target layer, the target layer includes a plurality of third patterns and a plurality of fourth patterns, an area of each fourth pattern is larger than an area of each third pattern. | 2020-07-02 |
20200212049 | FUSE ARRAY STRUCTURE - A semiconductor structure includes a substrate including a substrate including a first surface, a first doped region disposed under the first surface, a second doped region disposed under the first surface, and a recess indented into the substrate and disposed between the first doped region and the second doped region; a control gate structure disposed over the first doped region and electrically connected to a control bit line; a fuse gate structure disposed over the second doped region and electrically connected to a fuse bit line; and a buried word to line disposed between the control gate structure and the fuse gate structure, wherein the buried word line is disposed within the recess of the substrate. | 2020-07-02 |
20200212050 | MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL - Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell, first, second, and third data lines, and first and second access lines. Each of the first, second, and third data lines includes a length extending in a first direction. Each of the first and second access lines includes a length extending in a second direction. The memory cell includes a first transistor including a charge storage structure, and a first channel region electrically separated from the charge storage structure, and a second transistor including a second channel region electrically coupled to the charge storage structure. The first data line is electrically coupled to the first channel region. The second data line is electrically coupled to the first channel region. The third data line is electrically coupled to the second channel region, the second channel region being between the charge storage structure and the third data line. The first access line is located on a first level of the apparatus and separated from the first channel by a first dielectric. The second access line is located on a second level of the apparatus and separated from the second channel by a second dielectric. The charge storage structure is located on a level of the apparatus between the first and second levels. | 2020-07-02 |
20200212051 | MEMORY DEVICE HAVING SHARED ACCESS LINE FOR 2-TRANSISTOR VERTICAL MEMORY CELL - Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell and first, second, and third data lines located over a substrate. The memory cell includes a first transistor and a second transistor. The first transistor includes a charge storage structure located on a first level of the apparatus, and a first channel region electrically separated from the charge storage structure. The second transistor includes a second channel region located on a second level of the apparatus and electrically coupled to the charge storage structure. The first and second data lines are located on a third level of the apparatus and electrically coupled to the first channel region. The first level is between the substrate and the third level. The third data line is electrically coupled to the second channel region and electrically separated from the first channel region. | 2020-07-02 |
20200212052 | METHOD OF DESIGNING A LAYOUT OF A STATIC RANDOM ACCESS MEMORY PATTERN - The present invention provides a method of designing a layout of a static random access memory (SRAM) pattern, the method includes the following steps: firstly, a target pattern is provided, and according to the target pattern, a plurality of first patterns and a first dummy pattern are formed in a substrate, the first pattern that disposed at the outermost boundary of the first patterns is defined as a first edge pattern, and the first dummy pattern is disposed adjacent to the first edge pattern, next, the first dummy pattern is removed, and afterwards, according to the target pattern, a plurality of second patterns are formed in the substrate, the second patterns comprises a second edge pattern that is disposed between the first edge pattern and an original position of the first dummy pattern. | 2020-07-02 |
20200212053 | SEMICONDUCTOR MEMORY - A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate. | 2020-07-02 |
20200212054 | SEMICONDUCTOR DEVICE INCLUDING AN ANTI-FUSE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a trench formed in a substrate; an active region defined in the substrate by the trench; a trench-based dielectric material formed in the trench, and including a rupture portion contacting an edge of the active region; a first conductive plug formed on the trench-based dielectric material so as to contact the rupture portion; and a gate structure including a gate dielectric layer formed on the active region and a gate electrode formed on the gate dielectric layer. | 2020-07-02 |
20200212055 | INTEGRATION SCHEME FOR FERROELECTRIC MEMORY WITH A DEEP TRENCH STRUCTURE - A memory device comprises a trench within an insulating layer. A bottom electrode material is along sidewalls and a bottom of the trench, the bottom electrode material conformal to a top surface of the insulating layer. A ferroelectric material is conformal to the bottom electrode. A top electrode material is conformal to the ferroelectric material, wherein the bottom electrode material, the ferroelectric material and the top electrode material all extend above and across the top surface of the insulating layer. | 2020-07-02 |
20200212056 | MEMORY DEVICE AND A METHOD FOR FORMING THE MEMORY DEVICE - A memory device may include a substrate, a first gate structure, a mask and a second gate structure. The substrate may include a source region and a drain region at least partially arranged within the substrate, and a channel region arranged between the source region and the drain region. The first gate structure may be at least partially arranged over the channel region, and may include a top surface that may be substantially flat. The mask may be at least partially arranged over the top surface of the first gate structure. The second gate structure may be at least partially arranged over the mask and at least partially arranged adjacent to the first gate structure. | 2020-07-02 |
20200212057 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device whose performance is improved is disclosed. In the semiconductor device, an offset spacer formed in a memory cell is formed by a laminated film of a silicon oxide film and a silicon nitride film, and the silicon oxide film is particularly formed to directly contact the sidewall of a memory gate electrode and the side end portion of a charge storage film; on the other hand, an offset spacer formed in a MISFET is formed by a silicon nitride film. Particularly in the MISFET, the silicon nitride film directly contacts both the sidewall of a gate electrode and the side end portion of a high dielectric constant film. | 2020-07-02 |
20200212058 | THREE-DIMENSIONAL MEMORY DEVICES HAVING THROUGH STAIR CONTACTS AND METHODS FOR FORMING THE SAME - Embodiments of three-dimensional (3D) memory devices having through stair contacts (TSCs) and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including a plurality of interleaved dielectric layers and sacrificial layers is formed on a substrate. A staircase structure is formed on one side of the dielectric stack. A dummy hole extending vertically through the staircase structure and reaching the substrate is formed. A spacer having a hollow core is formed in the dummy hole. A TSC in contact with the substrate is formed by depositing a conductor layer in the hollow core of the spacer. The TSC extends vertically through the staircase structure. | 2020-07-02 |
20200212059 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment includes first and second conductive layers, and a pillar. The pillar is penetrating the first conductive layers and the second semiconductor layers. The pillar includes first and second semiconductor layers, a third conductive layer, and a gate insulating film. The first semiconductor layer is facing the first conductive layers. The second semiconductor layer is facing the second conductive layers. The third conductive layer is provided between the second semiconductor layer and the second conductive layers. The gate insulating film is provided between the second semiconductor layer and the third conductive layer. The third conductive layer is electrically coupled to the second conductive layers. | 2020-07-02 |
20200212060 | NONVOLATILE MEMORY DEVICE HAVING MULTIPLE NUMBERS OF CHANNEL LAYERS - A nonvolatile memory device according to an embodiment includes a substrate, a cell electrode structure disposed on the substrate and including interlayer insulating layers and gate electrode layers that are alternately stacked, a trench penetrating the cell structure on the substrate, a charge storage structure disposed on a sidewall surface of the trench, and a channel structure disposed adjacent to the charge storage structure and extending in a direction parallel to the sidewall surface. The channel structure includes a separate hole conduction layer and an adjacent and separate electron conduction layer. A control channel layer disposed on a control dielectric layer is a portion of the electron conduction layer configured to electrically connect to the channel structure, and to the charge storage structure. A control dielectric layer and a charge barrier layer are discrete but contiguous from the control channel structure to the charge storage structure. | 2020-07-02 |
20200212061 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - A three-dimensional (3D) semiconductor memory device includes a substrate that includes a cell array region and a connection region, a dummy trench formed on the connection region, an electrode structure on the substrate and that includes vertically stacked electrodes that have a staircase structure on the connection region, a dummy insulating structure disposed in the dummy trench, the dummy insulating structure including an etch stop pattern spaced apart from the substrate and the electrode structure, a cell channel structure disposed on the cell array region and that penetrates the electrode structure and makes contact with the substrate, and a dummy channel structure disposed on the connection region and that penetrates the electrode structure and a portion of the dummy insulating structure and that makes contact with the etch stop pattern. | 2020-07-02 |
20200212062 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a stacked body by alternately stacking an insulating film and a conductive film. The method includes forming a trench in the stacked body. The trench extends in one direction and divides the conductive film. The method includes burying a diblock copolymer in the trench. The method includes phase-separating the diblock copolymer into a plurality of first blocks and an insulative second block extending in a stacking direction of the insulating film and the conductive film. The method includes forming a plurality of holes by removing the first blocks. The method includes forming charge accumulation layers on inner surfaces of the holes. And, the method includes forming a plurality of semiconductor pillars extending in the stacking direction by burying a semiconductor material in the holes. | 2020-07-02 |
20200212063 | SEMICONDUCTOR DEVICE INCLUDING A STACK HAVING A SIDEWALL WITH RECESSED AND PROTRUDING PORTIONS - A semiconductor device includes a substrate, a stack, and channel structures penetrating the stack. The stack includes gate electrodes and insulating layers alternately and repeatedly stacked on the substrate, and extending in a first direction. The channel structures in a first row are spaced apart from each other in the first direction. The stack includes a first sidewall that includes first recessed portions and first protruding portions. Each of first recessed portions is defined by an adjacent pair of the first recessed portions. Each of the first recessed portions has a shape recessed toward a first region of the stack between an adjacent pair of the channel structures of the first row. Each of the first recessed portions has a width that decreases in a direction toward the first region when measured along the first direction. | 2020-07-02 |
20200212064 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The present disclosure relates to a semiconductor device having improved structural stability and a method of manufacturing such a semiconductor device. The semiconductor device includes a first stacked structure and a second stacked structure. The semiconductor device further includes a first support including a first upper pillar passing through the second stacked structure and including at least two first lower pillars extending from the first upper pillar and passing through the first stacked structure. | 2020-07-02 |
20200212065 | Vertical String Of Memory Cells Individually Comprising A Programmable Charge Storage Transistor Comprising A Control Gate And A Charge storage Structure And Method Of Forming A Vertical String Of Memory Cells Individually Comprising A Programmable Charge Storage Transistor Comprising A Control Gate And A Charge Storage Structure - A method of forming a vertical string of memory cells comprises forming a lower stack comprising first alternating tiers comprising vertically-alternating control gate material and insulating material. An upper stack is formed over the lower stack, and comprises second alternating tiers comprising vertically-alternating control gate material and insulating material having an upper opening extending elevationally through multiple of the second alternating tiers. The lower stack comprises a lower opening extending elevationally through multiple of the first alternating tiers and that is occluded by occluding material. At least a portion of the upper opening is elevationally over the occluded lower opening. The occluding material that occludes the lower opening is removed to form an interconnected opening comprising the unoccluded lower opening and the upper opening. Charge storage material is deposited into the interconnected opening for the charge storage structures for the memory cells of the vertical string that are in each of the upper and lower stacks and thereafter tunnel insulator and channel material are formed into the interconnected opening for the memory cells of the vertical string that are in each of the upper and lower stack. Other embodiments are disclosed, including embodiments independent of method. | 2020-07-02 |
20200212066 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes first and second wiring layers above a semiconductor substrate, a memory pillar extending through the first and second wiring layers, a first plug contacting the first wiring layer, a second plug contacting the second wiring layer, a first pillar adjacent to the first plug and extending through the first wiring layer, and a second pillar adjacent to the second plug and extending through the first and second wiring layers. The memory pillar includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, and a third insulating layer, a charge storage layer, and a fourth insulating layer on a side surface of the second semiconductor layer. The distance between the center of the first plug and the center of the first pillar is greater than the distance between the center of the second plug and the center of the second pillar. | 2020-07-02 |
20200212067 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to an embodiment, a semiconductor memory device comprises: a stacked body that includes a plurality of control gate electrodes stacked above a substrate; a memory columnar body that extends in a first direction above the substrate and configures a memory string along with the stacked body; and a source contact that extends in the first direction and is electrically connected to one end of the memory string. Moreover, this source contact is adjacent to the stacked body via a spacer insulating layer. Furthermore, a spacer protective layer including a nitride or a metal oxide is provided between these source contact and spacer insulating layer. | 2020-07-02 |
20200212068 | VERTICAL MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A vertical memory device according to an aspect includes a substrate, a first gate electrode structure disposed on the substrate and a second gate electrode structure spaced apart from the first gate electrode structure in a first direction substantially perpendicular to the substrate, a channel contact electrode layer disposed between the first gate electrode structure and the second gate electrode structure, and a channel layer extending along the first direction and in contact with the channel contact electrode layers and the first and the second gate electrode structures. | 2020-07-02 |
20200212069 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region. | 2020-07-02 |
20200212070 | THIN FILM TRANSISTOR ARRAY PANEL AND DISPLAY DEVICE - A TFT array panel includes a primary display area and a slitting-edge display area. In the slitting-edge display area, a first metallic routing layer includes a first data line and a second metallic routing layer includes a first gate line. The first data line is connected to the second metallic routing layer through a hole in the interlayer dielectric layer so that the first data line overlaps the first gate line to form an overlapping capacitance to compensate for a gate line RC value. | 2020-07-02 |
20200212071 | ARRAY SUBSTRATE AND PREPARATION METHOD THEREFOR, AND DISPLAY PANEL AND DISPLAY DEVICE - The present disclosure relates to the technical field of display. Disclosed are an array substrate and a preparation method therefor, and a display panel and a display device. The array substrate includes: a substrate; multiple gate lines, wherein the gate lines are located on the substrate, and extend along a first direction; multiple data lines, wherein the data lines are located on the substrate, and extend along a second direction, and the gate lines and the data lines intersect to define multiple pixel areas; and a touch-control electrode wiring wherein the touch-control electrode wiring has the same direction as that of the gate lines, and is arranged insulated from the gate lines on a different layer, and the orthographic projection of the touch-control electrode wiring on the substrate at least has an overlapping area with the orthographic projection of part of the gate lines on the substrate. | 2020-07-02 |
20200212072 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING SAME - A display device includes a first substrate and a flexible circuit board. Data lines, scan lines, thin film transistors, gate contacts, and source contacts are disposed on the first substrate. The scan lines are intersected with the data lines. The thin film transistors are respectively connected to the data lines and the scan lines. The gate contacts are connected to the scan lines. The source contacts are connected to the data lines. The display device further includes first conductive patterns disposed on a side of the first substrate, and the first conductive patterns are connected to at least some of the gate contacts on the side of the first substrate. First pads of the flexible circuit board are connected to the first conductive patterns. | 2020-07-02 |
20200212073 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY DEVICE - A highly flexible display device and a method for manufacturing the display device are provided. A transistor including a light-transmitting semiconductor film, a capacitor including a first electrode, a second electrode, and a dielectric film between the first electrode and the second electrode, and a first insulating film covering the semiconductor film are formed over a flexible substrate. The capacitor includes a region where the first electrode and the dielectric film are in contact with each other, and the first insulating film does not cover the region. | 2020-07-02 |
20200212074 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - The purpose of the invention is to form a stable oxide semiconductor TFT in a display device. The concrete structure is: A display device having a TFT substrate that includes a TFT having an oxide semiconductor layer comprising: the oxide semiconductor layer is formed on a first insulating film that is formed by a silicon oxide layer, the oxide semiconductor layer and an aluminum oxide film are directly formed on the first insulating film. The first insulating film becomes oxygen rich when the aluminum oxide film is formed on the first insulating film by sputtering. Oxygens in the first insulating film is effectively confined in the first insulating film, eventually, the oxygens diffuse to the oxide semiconductor for a stable operation of the oxide semiconductor TFT. | 2020-07-02 |
20200212075 | THIN FILM TRANSISTORS HAVING RELATIVELY INCREASED WIDTH AND SHARED BITLINES - Thin film transistors having relatively increased width and shared bitlines are described. In an example, an integrated circuit structure includes a plurality of transistors formed in an insulator structure above a substrate. The plurality of transistors arranged in a column such that the respective lateral arrangement of the source, the gate, and the drain of each of the transistors aligns with an adjacent thin film transistor, wherein the plurality transistors extend vertically through the insulator structure at least two interconnect levels to provide increased relative width. A first conductive contact is formed between one of sources and drains of at least two of the plurality of transistors in the column, and the conductive contact extends through the insulator structure at least two interconnect levels. | 2020-07-02 |
20200212076 | THIN FILM TRANSISTOR HAVING GATE INSULATING LAYER INCLUDING DIFFERENT TYPES OF INSULATING LAYERS, METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE COMPRISING THE SAME - A thin film transistor includes an active layer on a substrate, a gate electrode configured to be spaced from the active layer and partially overlapped with the active layer, and a gate insulating layer, at least a part of the gate insulating layer being disposed between the active layer and the gate electrode, wherein the gate insulating layer includes a first gate insulating layer between the active layer and the gate electrode, and a second gate insulating layer configured to have a dielectric constant (k) which is different from a dielectric constant of the first gate insulating layer, and disposed in a same layer as the first gate insulating layer, and wherein at least a part of the second gate insulating layer is disposed between the active layer and the gate electrode. | 2020-07-02 |
20200212077 | DISPLAY APPARATUS COMPRISING DIFFERENT TYPES OF THIN FILM TRANSISTORS AND METHOD FOR MANUFACTURING THE SAME - A display apparatus includes a substrate; a pixel driving circuit on the substrate; and a display unit connected with the pixel driving circuit, wherein the pixel driving circuit includes a first thin film transistor and a second thin film transistor, wherein the first thin film transistor includes, a first gate electrode on the substrate, a first active layer spaced apart from the first gate electrode and overlapping at least a part of the first gate electrode, a first source electrode connected with the first active layer; and a first drain electrode spaced apart from the first source electrode and connected with the first active layer, and wherein the second thin film transistor includes, a second active layer on the substrate, and a second gate electrode spaced apart from the second active layer and partially overlapping at least a part of the second active layer, wherein the first gate electrode is disposed between the substrate and the first active layer, the second active layer is disposed between the substrate and the second gate electrode, and the first gate electrode and the second gate electrode are disposed at an opposite side with respect to the second active layer. | 2020-07-02 |
20200212078 | LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE - To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10 | 2020-07-02 |
20200212079 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes a thin film transistor | 2020-07-02 |
20200212080 | THREE-DIMENSIONAL PHOTODETECTOR AND METHOD OF MANUFACTURING THE SAME - The present disclosure discloses a three-dimensional photodetector and a method of manufacturing the same. The three-dimensional photodetector according to an embodiment of the present disclosure includes a base part formed in the center region of the three-dimensional photodetector; a first bending part formed around the base part; at least one branch part connected to the base part through the first bending part; second bending parts formed on the at least one branch part; bonding parts connected to the at least one branch part through the second bending parts; at least one photoresistor formed on the surface of at least one of the base part and the branch parts; and a stretchable substrate to which the bonding parts are attached, wherein the bonding parts are attached to the stretchable substrate so that the base part has a gap in the thickness direction of the stretchable substrate; and the at least one photoresistor is responsible for tracking the traveling direction of light. | 2020-07-02 |
20200212081 | DIODE AND FABRICATION METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY PANEL - A diode and its fabrication method are provided. The diode includes a substrate, a buffer layer on a side of the substrate, a first film layer, a second film layer and a third film layer. The first film layer is a polycrystalline silicon film layer; the second film layer is an amorphous silicon film layer; and the third film layer is one of the polycrystalline silicon film layer and the amorphous silicon film layer. The diode at least includes a first portion, a second portion, a third portion, a first electrode, and a second electrode. The first portion is located in the first film layer; the second portion is located in the second film layer; and the third portion is located in the third film layer. The first electrode is electrically connected to the first portion, and the second electrode is electrically connected to the third portion. | 2020-07-02 |
20200212082 | IMAGE SENSOR HAVING IMPROVED FULL WELL CAPACITY AND RELATED METHOD OF FORMATION - In some embodiments, a method is provided. The method includes forming a plurality of trenches in a semiconductor substrate, where the trenches extend into the semiconductor substrate from a back-side of the semiconductor substrate. An epitaxial layer comprising a dopant is formed on lower surfaces of the trenches, sidewalls of the trenches, and the back-side of the semiconductor substrate, where the dopant has a first doping type. The dopant is driven into the semiconductor substrate to form a first doped region having the first doping type along the epitaxial layer, where the first doped region separates a second doped region having a second doping type opposite the first doping type from the sidewalls of the trenches and from the back-side of the semiconductor substrate. A dielectric layer is formed over the back-side of the semiconductor substrate, where the dielectric layer fill the trenches to form back-side deep trench isolation structures. | 2020-07-02 |
20200212083 | IMAGE SENSOR HAVING IMPROVED FULL WELL CAPACITY AND RELATED METHOD OF FORMATION - In some embodiments, a method is provided. The method includes forming a plurality of trenches in a semiconductor substrate, where the trenches extend into the semiconductor substrate from a back-side of the semiconductor substrate. An epitaxial layer comprising a dopant is formed on lower surfaces of the trenches, sidewalls of the trenches, and the back-side of the semiconductor substrate, where the dopant has a first doping type. The dopant is driven into the semiconductor substrate to form a first doped region having the first doping type along the epitaxial layer, where the first doped region separates a second doped region having a second doping type opposite the first doping type from the sidewalls of the trenches and from the back-side of the semiconductor substrate. A dielectric layer is formed over the back-side of the semiconductor substrate, where the dielectric layer fill the trenches to form back-side deep trench isolation structures. | 2020-07-02 |
20200212084 | SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS - A solid-state imaging device includes a semiconductor layer on which a plurality of pixels are arranged along a light-receiving surface being a main surface of the semiconductor layer, photoelectric conversion units provided for the respective pixels in the semiconductor layer, and a trench element isolation area formed by providing an insulating layer in a trench pattern formed on a light-receiving surface side of the semiconductor layer, the trench element isolation area being provided at a position displaced from a pixel boundary between the pixels. | 2020-07-02 |
20200212085 | SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD OF SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS - A solid-state imaging device includes a pixel having a photoelectric conversion element which generates a charge in response to incident light, a first transfer gate which transfers the charge from the photoelectric conversion element to a charge holding section, and a second transfer gate which transfers the charge from the charge holding section to a floating diffusion. The first transfer gate includes a trench gate structure having at least two trench gate sections embedded in a depth direction of a semiconductor substrate, and the charge holding section includes a semiconductor region positioned between adjacent trench gate sections. | 2020-07-02 |
20200212086 | HYBRID BONDING METHOD FOR SEMICONDUCTOR WAFERS AND RELATED THREE-DIMENSIONAL INTEGRATED DEVICE - A method to perform hybrid bonding of two semiconductor wafers without using a dedicated tool for thermo-compression is disclosed. According to the herein disclosed technique, the semiconductor wafers to be bonded together may be placed in an oven simply staying one upon the other without applying any additional compression between them besides their own weight. This outstanding result has been attained using of a particular type of thermosetting materials, namely siloxane polymers of the type that shrink when cured. Among these siloxane polymers, the siloxane polymers of the type SC-480, siloxane polymers of the series SC-200, SC-300, SC-400, SC-500, SC-700, SC-800 and mixtures thereof are particularly suitable. | 2020-07-02 |
20200212087 | IMAGING DEVICE, MANUFACTURING METHOD, AND SUBSTRATE DIVIDING METHOD - There is provided semiconductor devices and methods of forming the same, including: a first substrate; and a second substrate adjacent to the first substrate, where a side wall of the second substrate includes one or more diced portions that can include a blade diced portion and a stealth diced portion; and also imaging devices and methods of forming the same, including: a first substrate; a transparent layer; an adhesive layer between the first substrate and the transparent layer; a second substrate, where the first substrate is disposed between the adhesive layer and the second substrate; and a groove extending from the adhesive layer to the second substrate, where the groove is filled with the adhesive layer. | 2020-07-02 |
20200212088 | VERTICAL BOARD-TYPE CAPACITOR AND IMAGE SENSING DEVICE INCLUDING THE SAME - An image sensing device is provided to include a pixel region including image pixels and a peripheral region located outside of the pixel region. The peripheral region includes logic circuits located to receive the pixel signals from the pixel region and configured to process the pixel signals, and a capacitor located adjacent to the logic circuits. The capacitor includes an active region including a first impurity region and a second impurity region formed over the first impurity region, a recessed structure including a portion formed in the active region, the portion including a conductive layer extending along a direction that the first impurity region and the second impurity region are stacked and an insulation layer formed between the conductive layer and the active region, and a first junction formed in the active region and spaced apart from the recessed structure by a predetermined distance. | 2020-07-02 |
20200212089 | IMAGE SENSOR AND METHOD OF FABRICATING THE SAME - Disclosed are image sensors and methods of fabricating the same. The image sensor includes a semiconductor substrate including a pixel zone and a pad zone and having a first surface and a second surface opposing each other, a first pad separation pattern on the pad zone and extending from the first surface of the semiconductor substrate toward the second surface of the semiconductor substrate, a second pad separation pattern extending from the second surface toward the first surface of the semiconductor substrate on the pad zone the second pad and in contact with the first pad separation pattern, and a pixel separation pattern on the pixel zone and extending from the second surface of the semiconductor substrate toward the first surface of the semiconductor substrate. | 2020-07-02 |
20200212090 | INTEGRATED CIRCUIT DEVICE AND METHOD OF FABRICATING INTEGRATED CIRCUIT - An integrated circuit device includes a complementary metal oxide semiconductor (CMOS) image sensor. The complementary metal oxide semiconductor (CMOS) image sensor includes a P-N junction photodiode, a transistor gate, a polysilicon plug and a stacked metal layer. The P-N junction photodiode is disposed in a substrate. The transistor gate and the polysilicon plug are disposed on the substrate, wherein the polysilicon plug is directly connected to the P-N junction photodiode. The stacked metal layer connects the polysilicon plug to the transistor gate, wherein the stacked metal layer includes a lower metal layer and an upper metal layer, and the lower metal layer includes a first metal silicide part contacting to the polysilicon plug. The present invention also provides a method of fabricating said integrated circuit device. | 2020-07-02 |
20200212091 | PIXEL CROSSTALK CORRECTION - A time-of-flight camera calibration system includes a time-of-flight camera and a calibration processor. The calibration processor is coupled to the time-of-flight camera. The calibration processor is configured to receive an input phase image captured by the time-of-flight camera, and generate a blurred phase image by applying a low pass filter to the input phase image. The calibration processor is also configured to generate a crosstalk correction matrix based on the blurred phase image, and provide the crosstalk correction matrix to the time-of-flight camera. | 2020-07-02 |
20200212092 | VERTICAL PIN-TYPE CAPACITOR AND IMAGE SENSING DEVICE INCLUDING THE SAME - An image sensing device is provided to include a pixel region and a peripheral region located outside of the pixel region. The peripheral region includes logic circuits located to receive a pixel signals from the pixel region and configured to process the pixel signals and a capacitor located adjacent to the logic circuits. The capacitor includes an active region, a recessed structure, and a first junction. The active region includes a first impurity region and a second impurity region formed over the first impurity region. The recessed structure is at least partly disposed in the active region and including a first portion disposed in the active region and including a conductive material and a second portion surrounding the first portion and including an insulation material. The first junction is formed in the active region and spaced apart from the recessed structure by a predetermined distance. | 2020-07-02 |
20200212093 | IMAGE SENSOR WITH SHALLOW TRENCH EDGE DOPING - The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip has a photodetector region arranged within a semiconductor substrate. One or more dielectric materials are disposed within a trench defined by one or more interior surfaces of the semiconductor substrate. A doped epitaxial material is arranged within the trench and is laterally between the one or more dielectric materials and the photodetector region. A dielectric protection layer is arranged over the one or more dielectric materials within the trench. The dielectric protection layer laterally contacts a sidewall of the doped epitaxial material. | 2020-07-02 |
20200212094 | IMAGING DEVICE, MODULE, ELECTRONIC DEVICE, AND METHOD OF OPERATING THE IMAGING DEVICE - An imaging device that has a structure where a transistor is used in common by a plurality of pixels and is capable of imaging with a global shutter system is provided. A transistor that resets the potential of a charge detection portion, a transistor that outputs a signal corresponding to the potential of the charge detection portion, and a transistor that selects a pixel are used in common by the plurality of pixels. A node AN (a first charge retention portion), a node FD (a second charge retention portion), and a node FDX (the charge detection portion) are provided. Imaging data obtained in the node AN is transferred to the node FD, and the imaging data is sequentially transferred from the node FD to the node FDX to be read. | 2020-07-02 |
20200212095 | IMAGE SENSING DEVICE AND METHOD FOR FORMING THE SAME - An image sensing device and a method for forming the same are disclosed. The image sensing device includes a substrate including one or more photoelectric conversion elements, and a grid structure disposed over the substrate. The grid structure includes an air layer, a support film formed over the air layer, and a capping film formed at side surfaces of the air layer and the support film and at a top surface of the support film. | 2020-07-02 |
20200212096 | IMAGING APPARATUS AND MANUFACTURING METHOD FOR IMAGING APPARATUS - In an imaging apparatus provided with a substrate having transparency, warping of the substrate is prevented while stray light is shielded. The imaging apparatus includes a sensor chip, a transparent substrate, a light shielding wall, and an optical filter. In this imaging apparatus, a solid-state imaging element is provided in a light receiving region of the sensor chip. Furthermore, in the imaging apparatus, the transparent substrate is equipped on an outer edge portion of the sensor chip. In addition, in the imaging apparatus, the light shielding wall shields light that passes through the transparent substrate and enters the front light receiving region. The light shielding wall is formed on the optical filter. | 2020-07-02 |
20200212097 | SOLID STATE IMAGING DEVICE - A first region includes first transfer column regions distributed in a first direction. A second region includes second transfer column regions distributed in the first direction. The second region is positioned downstream of the first region in a charge transfer direction. Lengths in a second direction of the first transfer column regions are equal. Lengths in the second direction of the second transfer column regions are longer than the length of the first transfer column region, and increase as the second transfer column region is positioned downstream in the charge transfer direction. A third region is disposed to correspond to the first region and extends along the first direction. A fourth region is disposed to correspond to the second region and extends such that an interval between the fourth region and a pixel region increases in response to a change in the lengths of the second transfer column regions. | 2020-07-02 |
20200212098 | SOLID STATE IMAGING DEVICE - The photosensitive region includes a first impurity region and a second impurity region having a higher impurity concentration than that of the first impurity region. The photosensitive region includes one end positioned away from the transfer section in the second direction and another end positioned closer to the transfer section in the second direction. A shape of the second impurity region in plan view is line-symmetric with respect to a center line of the photosensitive region along the second direction. A width of the second impurity region in the first direction increases in a transfer direction from the one end to the other end. An increase rate of the width of the second impurity region in each of sections, obtained by dividing the photosensitive region into n sections in the second direction, becomes gradually higher in the transfer direction. Here, n is an integer of two or more. | 2020-07-02 |
20200212099 | MULTIPLE WAVELENGTH LIGHT-EMITTING DIODE EPITAXIAL STRUCTURE - A multi-wavelength light-emitting diode epitaxial structure comprises of a substrate and at least three light-emitting elements, wherein the light-emitting elements are sequentially stacked on the substrate. For each two adjacent light-emitting elements, the light-emitting element disposed closer to the light-exiting surface has a higher bandgap than that of the light-emitting element disposed farther from the light-exiting surface. Each of the light-emitting elements comprises of an active layer and two cladding layers disposed on two opposite sides of the active layer, and each active layer includes a multiple quantum well structure. Cladding layers of different refractive indexes are arranged incrementally from the substrate to the light-exiting surface. Any given two adjacent cladding layers from two light-emitting elements have a combined thickness of 1 μm or less. The emission wavelengths of the light-emitting elements are ultraviolet or infrared bands. | 2020-07-02 |
20200212100 | PIXELATED LED ARRAY WITH OPTICAL ELEMENTS - The pcLED pixels in a phosphor-converted LED array each comprise an optical element on the light-emitting surface above the phosphor layer. In methods for making such pixelated LED arrays, a thin layer of a sacrificial phosphor carrier substrate is retained as the optical element on the output surface of the phosphor pixels upon completion of the fabrication process. | 2020-07-02 |
20200212101 | ULTRA-SMOOTH SIDEWALL PIXELATED ARRAY LEDS - Pixelated array light emitters are formed with closely-spaced pixels having ultra-smooth sidewalls. In methods for making such pixelated array light emitters, a converter layer of phosphor particles dispersed in a binder is disposed on a carrier, and then singulated by saw cuts or similar methods to form an array of phosphor pixels. The binder is fully cured prior to singulation of the converter layer. Further, the carrier is rigid rather than flexible. As a consequence of fully curing the binder and of using a rigid carrier to support the converter layer, singulation results in phosphor pixels having smooth side walls. The array of phosphor pixels is subsequently attached to a corresponding array of LEDs with an adhesive layer, separate from the binder used to form the converter layer. The pixel sidewalls may be formed with controlled morphology, for example at acute or obtuse angles with respect to the carrier. | 2020-07-02 |
20200212102 | LIGHT EMITTING DIODE DISPLAY APPARATUS - A light emitting diode display apparatus includes a display substrate having a plurality of subpixel areas; and a light emitting diode disposed on the display substrate to correspond to a corresponding subpixel area of the plurality of subpixel areas, wherein the light emitting diode includes an emission area and a non-emission area adjacent to the emission area, wherein the light emitting diode includes a trench part provided to overlap a boundary between the emission area and the non-emission area, and wherein the trench part is configured such that a side light emitted from the emission area is reflected in a display direction of the light emitting diode display apparatus. | 2020-07-02 |
20200212103 | SPIN-ORBIT TORQUE MAGNETORESISTIVE RANDOM ACCESS MEMORY AND METHOD FOR MANUFACTURING THE SAME - A spin-orbit torque magnetoresistive random access memory, and a method for manufacturing a spin-orbit torque magnetoresistive random access memory are provided. The spin-orbit torque magnetoresistive random access memory includes a spin-orbit coupling layer and a magnetoresistive tunnel junction located on the spin-orbit coupling layer. The magnetoresistive tunnel junction includes a first magnetic layer, a tunneling layer, and a second magnetic layer that are sequentially stacked from bottom to top, and each of the first magnetic layer and the second magnetic layer has perpendicular anisotropy. In a direction of a current in the spin-orbit coupling layer, defects are generated in a part of the magnetoresistive tunnel junction by an ion implantation process. | 2020-07-02 |
20200212104 | MAGNETIC TUNNEL JUNCTION ELEMENTS AND MAGNETIC RESISTANCE MEMORY DEVICES INCLUDING THE SAME - A magnetic tunnel junction (MTJ) element includes a free layer, a pinned layer on the free layer, and a dielectric layer extending between the free layer and the pinned layer. A spin orbit torque (SOT) generator is provided, which contacts at least a portion of the free layer. A plane extending between the SOT generator and the free layer intersects a plane extending between the free layer and the dielectric layer. The SOT generator is configured to modulate current that passes between the free layer, the dielectric layer, and the pinned layer. This SOT generator can include a pair of electrodes that are spaced apart from each other in a direction orthogonal to a stacking direction of the free layer, the dielectric layer and the pinned layer. This SOT generator may include a metal selected from a group consisting of Pt, W, and Ta, or may include a topological insulator. | 2020-07-02 |
20200212105 | ASYMMETRIC SELECTOR ELEMENT FOR LOW VOLTAGE BIPOLAR MEMORY DEVICES - Embedded non-volatile memory structures having asymmetric selector elements are described. In an example, a memory device includes a word line. An asymmetric selector element is above the word line. The asymmetric selector element includes a first electrode material layer, a selector material layer on the first electrode material layer, and a second electrode material layer on the selector material layer, the second electrode material layer different in composition than the first electrode material layer. A bipolar memory element is above the word line, the bipolar memory element on the asymmetric selector element. A bit line is above the word line. | 2020-07-02 |
20200212106 | MULTILAYER BACK END OF LINE (BEOL)-STACKABLE CROSS-POINT MEMORY ARRAY WITH COMPLEMENTARY PASS TRANSISTOR SELECTORS - A multi-layer cross point memory array includes a plurality of layers, each in turn with a plurality of word lines; a plurality of intersecting lines intersecting the word lines at a plurality of points; and a plurality of memory element-transistor stacks. Each of the latter is formed on the intersecting lines; each stack in turn includes a memory element; and a complementary pair of parallel-connected field effect selection transistors including a p-FET and an n-FET, each of which has a gate, a first drain-source terminal connected to a corresponding one of the intersecting lines, and a second drain-source terminal connected to a corresponding one of the memory elements. The gate of the p-FET and the gate of an n-FET in an adjacent stack are connected to the same word line; and the mirror image is true for the n-FET and a p-FET in the adjacent stack on the opposite side. | 2020-07-02 |
20200212107 | PHOTOELECTRIC CONVERSION ELEMENT, OPTICAL SENSOR, AND IMAGING ELEMENT - An object of the invention is to provide a photoelectric conversion element exhibiting an excellent production suitability. | 2020-07-02 |
20200212108 | IMAGING ELEMENT, LAMINATED IMAGING ELEMENT, AND SOLID-STATE IMAGING DEVICE - An imaging element includes a photoelectric conversion unit formed by laminating a first electrode | 2020-07-02 |
20200212109 | DISPLAY DEVICE - Provided is a display apparatus including a display module having a folding region and a plurality of non-folding regions adjacent to the folding region and including a display surface configured to display an image, and a support member below the display module and supporting the display module, wherein the display module is operated in a plurality of modes, and the plurality of modes includes a first mode in which the folding region has a first curvature radius and is folded in a first bending direction which surrounds a virtual first bending axis defined below the display module and a second mode in which the folding region has a second curvature radius and is folded in a second bending direction which surrounds a virtual second bending axis defined above the display module, wherein the first curvature radius is greater than the second curvature radius. | 2020-07-02 |
20200212110 | Transparent Display Device - A transparent display device for providing only a viewer located at the front with an image is disclosed. The transparent display device comprises a substrate provided with a first subpixel, a second subpixel and a third subpixel, a first electrode provided in each of the first subpixel, the second subpixel and the third subpixel on the substrate, a light emitting layer provided on the first electrode, a second electrode provided on the light emitting layer, an upper color filter provided over the second electrode, a lower color conversion layer provided between the substrate and the first electrode, and a lower color filter provided between the substrate and the lower color conversion layer. | 2020-07-02 |
20200212111 | DISPLAY APPARATUS - A display apparatus includes a substrate including a first subpixel and a second subpixel, a first electrode including a first sub-electrode provided in the first subpixel and a second sub-electrode provided in the second subpixel, the first electrode being provided on the substrate, an organic light emitting layer on the first electrode, a second electrode on the organic light emitting layer, a first bank between the first sub-electrode and the second sub-electrode, the first bank dividing the first subpixel and the second subpixel, a color filter layer on the second electrode, a reflective metal at a portion of the color filter layer, and a light absorbing part on an upper surface of the reflective metal, the light absorbing part absorbing light, wherein the first electrode is provided as a reflective electrode, and the organic light emitting layer is disposed between the reflective electrode and the reflective metal. | 2020-07-02 |
20200212112 | LIGHTING APPARATUS - A lighting apparatus comprising a lighting part that includes a light emitting area having a plurality of first light emitting areas that are separated apart from each other and a plurality of second light emitting areas separated apart from each other and a non-light emitting area including a first non-light emitting area surrounding the plurality of first light emitting areas and the plurality of second light emitting areas and a plurality of second non-light emitting areas extending from the first non-light emitting area, the lighting apparatus comprises a substrate; a plurality of first electrodes disposed on the substrate in the light emitting area; an organic layer disposed on the plurality of first electrodes; a second electrode disposed on the organic layer; and an encapsulation part disposed on the second electrode; wherein the plurality of first light emitting areas are arranged in a first direction, and the plurality of second light emitting areas are arranged in a second direction intersecting with the first direction, and wherein the second non-light emitting areas correspond to an area in which a plurality of patterns are included. | 2020-07-02 |
20200212113 | DISPLAY DEVICE - A display device is provided. The display device includes: a display substrate on which a plurality of light-emitting areas are defined; and a color conversion substrate on which a plurality of light-transmitting areas respectively associated with the plurality of light-emitting areas and light-blocking areas between the plurality of light-transmitting areas are defined, the color conversion substrate comprising color patterns in the light-blocking areas, and light-blocking members on the color patterns, wherein at least one of the light-emitting areas has an area smaller than the area of the light-transmitting area that overlaps it in a thickness direction, and the color patterns include a blue colorant. | 2020-07-02 |
20200212114 | DISPLAY PANEL INCLUDING TOUCH SENSOR, DISPLAY PANEL COMPRISING THE SAME AND METHOD FOR DETECTING DEFECT THEREOF - A display panel, a display device comprising the display panel, and a method for detecting a defect thereof are provided. The display panel includes a touch sensor having at least one defect detection pattern to detect a defect by changing the configuration of an array. Thereby, a defect detection at the outside of the array can be easily accomplished. | 2020-07-02 |
20200212115 | DISPLAY DEVICE - Provided is a display device in which a defect by external light reflection is minimized in a non-display area. The display device includes a display panel and a touch unit arranged on the display panel. The display panel may include: a substrate including a display area and a non-display area arranged around the display area; an insulator including a valley portion, the valley portion being defined as an opening arranged along an outer side of the display area in the non-display area; and a display unit arranged in the display area and including a light-emitting element electrically connected to a thin film transistor. The touch unit may include a reflection prevention unit that overlaps the valley portion and is configured to reduce reflectivity of external light. | 2020-07-02 |
20200212116 | TOUCH DISPLAY DEVICE - A touch display device comprises a substrate; planarization film disposed over the substrate; an anode electrode and a touch metal disposed on the planarization film; a bank disposed over the planarization film on which the anode electrode and the touch metal are disposed, and the bank including a first cavity exposing the anode electrode and a second cavity exposing the touch metal; an organic light emitting layer disposed in the first cavity and disposed over the anode electrode; and a cathode electrode disposed over the organic light emitting layer and the bank, wherein the cathode electrode includes a first cathode electrode and a second cathode electrode, which are separated from each other, and a part of the first cathode electrode is disposed in the second cavity and connected to the touch metal in the second cavity. | 2020-07-02 |
20200212117 | DISPLAY DEVICE - The present disclosure relates to a stretchable display device. According to an embodiment of the present disclosure, a stretchable display device includes a lower substrate having a plurality of first areas in which a plurality of sub-pixels is included, a plurality of second areas in which a plurality of connection lines is included, the connection lines electrically connecting adjacent ones of the first areas, and a plurality of third areas other than the first areas and the second areas. The stretchable display device further includes a plurality of additional sub-pixels in the respective third areas, and a plurality of piezoelectric patterns electrically connected to the respective additional sub-pixels. Adjacent ones of the first areas are spaced apart from one another. The stretchable display device may suppress deterioration of image quality when it is stretched. | 2020-07-02 |
20200212118 | HIGH RESOLUTION LOW POWER CONSUMPTION OLED DISPLAY WITH EXTENDED LIFETIME - Full-color pixel arrangements for use in devices such as OLED displays are provided, in which multiple sub-pixels are configured to emit different colors of light, with each sub-pixel having a different optical path length than some or all of the other sub-pixels within the pixel. | 2020-07-02 |
20200212119 | DISPLAY DEVICE - A display device is disclosed. The display device includes: a substrate including a first sub-pixel and a second sub-pixel; a first electrode in each of the first sub-pixel and the second sub-pixel; a third electrode in each of the first sub-pixel and the second sub-pixel; a second electrode between the first electrode and the third electrode; a first light-emitting layer between the first electrode and the second electrode, wherein the first light-emitting layer emits light of a first color; a second light-emitting layer between the second electrode and the third electrode, wherein the second light-emitting layer is configured to emit mixed light of second and third colors; and a color filter including a first color filter corresponding to the first sub-pixel and a second color filter corresponding to the second sub-pixel, wherein the first sub-pixel and the second sub-pixel each are configured to emit light of three colors. | 2020-07-02 |
20200212120 | DISPLAY DEVICE - A display device comprises a substrate provided with a first subpixel, a second subpixel, a third subpixel, and a fourth subpixel, a first electrode provided on the substrate, an organic light emitting layer arranged on the first electrode, and a second electrode arranged on the organic light emitting layer, wherein the organic light emitting layer includes a first organic light emitting layer and a second organic light emitting layer, the first organic light emitting layer and the second organic light emitting layer are arranged on the first subpixel, the second subpixel, and the fourth subpixel, only the second organic light emitting layer is arranged on the third subpixel, only the first organic light emitting layer emits light on the first subpixel and the second subpixel, only the second organic light emitting layer emits light on the third subpixel, and both of the first organic light emitting layer and the second light emitting layer emit light on the fourth subpixel. Since the organic light emitting layer may emit light in accordance with one-stack voltage even in case of a two-stack structure of the first subpixel and the second subpixel, overall power consumption may be reduced. | 2020-07-02 |
20200212121 | DISPLAY DEVICE - A display device can include a first subpixel and a second subpixel disposed on a substrate; a first electrode disposed in each of the first subpixel and the second subpixel; a first light emitting layer disposed on the first electrode, the first light emitting layer being configured to emit light of a first color; a second electrode disposed on the first light emitting layer; a second light emitting layer disposed on the second electrode, the second light emitting layer being configured to emit light of a second color; and a third electrode disposed on the second light emitting layer, in which the first light emitting layer and the second electrode are both included in the first subpixel, and the first light emitting layer and the second electrode are both absent from the second subpixel. | 2020-07-02 |
20200212122 | DISPLAY DEVICE - A light absorbing member includes a first dichroic dye and a second dichroic dye. The first dichroic dye has an absorption peak wavelength between a first emission peak wavelength of the first light-emitting layer and a second emission peak wavelength of a second light-emitting layer. The second dichroic dye has an absorption peak wavelength between the second emission peak wavelength of the second light-emitting layer and a third emission peak wavelength of the third light-emitting layer. An angle of a molecule of the first dichroic dye in an absorption axis and an angle of a molecule of the second dichroic dye in an absorption axis with respect to a normal direction of the reflective layer are from 70 degrees to 90 degrees. | 2020-07-02 |
20200212123 | LIGHT EMITTING DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed are a light emitting display device and a method for manufacturing the same. The light emitting display device changes a configuration of common layers disposed in edge areas and can thus satisfy structural characteristics of a narrow bezel and prevent light leakage generated around the edge areas. | 2020-07-02 |
20200212124 | ORGANIC LIGHT-EMITTING DISPLAY PANEL AND DISPLAY DEVICE - An organic light-emitting display panel includes a plurality of pixel defining aperture regions each having a same shape and size. Each pixel defining aperture region is partitioned into six sub-pixel regions, the six sub-pixels has a same area defined by six boundary lines, each boundary line is a connection line running from a center point to an edge of the pixel defining aperture region. The plurality of the pixel defining aperture regions is characterized with three different colors. The six sub-pixels of any one of the pixel defining aperture regions is characterized with a same color. Two adjacent pixel defining aperture regions are characterized with different colors. Three connection lines between the center points of three adjacent pixel defining aperture regions have different colors constitute an isosceles right triangle, and three sub-pixel regions defined by the isosceles right triangle constitute one pixel unit. | 2020-07-02 |
20200212125 | DISPLAY SUBSTRATE AND DISPLAY DEVICE - A display substrate and a display device. The display substrate includes a first sub-pixel, a second sub-pixel, and a first spacer. A line connecting the center of the first sub-pixel and the center of the second sub-pixel is a center line; the center line is not perpendicular to a first direction; the first direction is at least one of the row direction or the column direction. The first spacer is disposed between the first sub-pixel and the second sub-pixel, and the extension direction of first spacer between the first sub-pixel and the second sub-pixel is not perpendicular to the first direction. | 2020-07-02 |
20200212126 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE - An organic light emitting diode display device includes a substrate, a buffer layer, a first circuit structure, a sub-pixel structure, and a first signal wire. The substrate includes a display region including a plurality of sub-pixel regions and a peripheral region surrounding the display region. The buffer layer is disposed in the display region and peripheral region on the substrate. The first circuit structure is disposed in the peripheral region on the buffer layer. The sub-pixel structure is disposed in each of the sub-pixel regions on the first circuit structure. The first signal wire is disposed in the peripheral region between the substrate and the buffer layer, and overlaps the first circuit structure when viewed from a plan view in a thickness direction of the substrate. | 2020-07-02 |
20200212127 | Foldable Display Apparatus - A foldable display apparatus includes: a non-folding area, and a folding area, in which an aperture ratio of a plurality of red sub pixels in the folding area is lower than an aperture ratio of a plurality in red sub pixels of the non-folding area, an aperture ratio of the plurality of green sub pixels in the folding area is lower than an aperture ratio of the plurality of green sub pixels of the non-folding area, and an aperture ratio of the plurality in blue sub pixels of the folding area is lower than an aperture ratio of the plurality of blue sub pixels of the non-folding area. | 2020-07-02 |
20200212128 | ELECTROLUMINESCENT DISPLAY DEVICE - An electroluminescent display device comprises a substrate; a plurality of sub-pixels arranged on the substrate, including sub-pixels with different colors arranged along a first direction and sub-pixels with a same color arranged along a second direction; a light-emitting diode disposed at each sub-pixel and including a first electrode, a light-emitting layer and a second electrode; a bank having an opening corresponding to a sub-pixel row along the second direction and disposed between two adjacent sub-pixels along the first direction; and a control pattern between two adjacent sub-pixels along the second direction, wherein the control pattern includes a first control pattern corresponding to a center portion of the sub-pixel row and a second control pattern spaced apart from the first control pattern along the second direction, and where a first end of each of the first and second control patterns is spaced apart from the bank and has an first surface parallel to or inclined with respect to the second direction, and a slope of the first surface of the second control pattern is larger than a slope of the first surface of the first control pattern. | 2020-07-02 |
20200212129 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A display device achieves a high resolution and a low power consumption through provision of subpixels each including a single light emitting layer and subpixels each including a plurality of overlapping light emitting layers. In the display device, it is also unnecessary to increase the number of expensive fine metal masks even for rendering of various grayscales. In addition, in the display device, different light emitting layers overlap with each other, and a charge generation layer is disposed between the overlapping light emitting layers, and, as such, emission of a secondary color can be achieved without necessity of a material for an additional light emitting layer of the secondary color. | 2020-07-02 |
20200212130 | Transparent Display Device - Disclosed is a transparent display device which has improved transmittance and luminous uniformity according to wavelength. The transparent display device includes a capping structure. The capping structure is formed by stacking a high refractive index first capping layer having destructive interference properties and a low refractive index second capping layer. | 2020-07-02 |
20200212131 | Organic Light Emitting Display Apparatus - An organic light emitting display apparatus is disclosed, wherein the organic light emitting display apparatus comprises a driving thin film transistor provided on a substrate and disposed in a pixel area including a plurality of sub pixels; an organic light emitting diode electrically connected with the driving thin film transistor; and a repair portion provided at one side of the organic light emitting diode, wherein the organic light emitting diode is electrically connected with the driving thin film transistor through the repair portion. | 2020-07-02 |
20200212132 | Display Device - A display device is disclosed that includes one or more crack detection units. The crack detection units can detect a crack position in the display device without requiring the disassembly of the display device. The crack detection units may be disposed across one or more non-active areas of the display device. | 2020-07-02 |
20200212133 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF FABRICATING THEREOF - An organic light emitting display device and a method of fabricating thereof are discussed. The organic light emitting display device according to an example includes a plurality of first bank layers arranged along a first direction and a second direction on a substrate to define a plurality of pixels; a plurality of second bank layers disposed along the first direction on the first bank layers to divide the columns of pixels having different colors; an organic light emitting layer in each pixel; at least one first pocket pixel unit at both sides of the pixel having the smallest area; and a first dummy organic light emitting layer in the first pocket pixel unit. | 2020-07-02 |
20200212134 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - An organic light-emitting display device and a method of fabricating the same are provided. The organic light emitting display device according to an example comprises a substrate including a pixel region including a plurality of red-subpixels, a plurality of green-subpixels, and a plurality of blue-subpixels, and a dummy pixel region including a plurality of dummy subpixels; a plurality of first bank layers disposed in the pixel region in a first direction and a second direction to define a plurality of subpixels; a plurality of second bank layers disposed on the first bank layers in the first direction in the pixel region to partition boundaries between a red-subpixel column, a green-subpixel column, and a blue-subpixel column; and an organic light-emitting element formed on each of the subpixels; and wherein at least one dummy subpixel forms a first dispensing region onto which an organic light-emitting material is dispensed. | 2020-07-02 |
20200212135 | DISPLAY PANEL AND DISPLAY APPARATUS - A display panel and a display apparatus including the display panel are provided. The display panel includes: a first substrate; a light emitting device on the first substrate, the light emitting device being configured to emit light; a light shielding layer on the first substrate, the light shielding layer being configured to shield light, which is emitted from the light emitting device and reflected by a touch body, from being transmitted through the light shielding layer; and at least one light transmitting portion in the light shielding layer, the light transmitting portion being configured to allow the light, which is emitted from the light emitting device and reflected by the touch body, to pass through the light transmitting portion and irradiate onto an optical sensor,
| 2020-07-02 |
20200212136 | DISPLAY MICROPHONE DEVICE - A display microphone device includes a display panel having a front surface from which light is emitted and a rear surface opposite the front surface. A front electrode is coupled to the rear surface of the display panel, a rear electrode faces and is spaced apart from the front electrode. A power supply is connected to the front electrode and the rear electrode. The display microphone device outputs an audio signal based on a change in a voltage between the front electrode and the rear electrode. | 2020-07-02 |
20200212137 | ARRAY SUBSTRATE, DISPLAY APPARATUS AND LUMINANCE CALIBRATION METHOD THEREFOR - An array substrate includes a plurality of sub-pixels and at least one light photosensitive detection assembly, and each photosensitive detection assembly corresponds to at least one sub-pixel. The at least one photosensitive detection assembly includes: a photosensitive element and a signal reading element coupled to the photosensitive element and a first reading signal line, the photosensitive element is configured to detect a luminance of a corresponding sub-pixel, and output a light detection signal according to the luminance of the corresponding sub-pixel. The signal reading element is configured to read the light detection signal output by the photosensitive element, and output a first detection signal to the first reading signal line according to the light detection signal. | 2020-07-02 |
20200212138 | DISPLAY DEVICE - Provided is a display device including a light emitting device and a light receiving device. The light receiving device includes a first light receiving electrode and a light receiving layer. The light receiving device receives a second light reflected from an external object and generates current. | 2020-07-02 |
20200212139 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device includes a substrate, an insulation layer structure, a light emitting layer, and an optical module. The substrate has an opening region, a peripheral region surrounding the opening region, and a display region surrounding the peripheral region. An opening is defined through the substrate in the opening region. The insulation layer structure is disposed in the display region and the peripheral region on the substrate. The light emitting layer is disposed on the insulation layer structure, and extends in a first direction from the display region into the opening region. A first opening is defined through the light emitting layer in the peripheral region. The optical module is disposed in the opening of the substrate. | 2020-07-02 |
20200212140 | ELECTROLUMINESCENCE DISPLAY DEVICE HAVING A THROUGH-HOLE IN DISPLAY AREA - An electroluminescence display device comprising a through-hole in a display area is discussed. The electroluminescence display device according to one embodiment of the present disclosure comprises a substrate having a display area and a non-display area arranged near the display area; a light emitting diode in the display area; an encapsulation layer on the light emitting diode; a through-hole arranged inside the display area to penetrate the substrate; an inner dam surrounding the through-hole; a trench arranged between the inner dam and the through-hole; and an etch-stopper arranged between the trench and the through-hole on the an insulating layer. | 2020-07-02 |