27th week of 2020 patent applcation highlights part 66 |
Patent application number | Title | Published |
20200211841 | EPITAXIAL GROWTH SUBSTRATE, METHOD OF MANUFACTURING EPITAXIAL GROWTH SUBSTRATE, EPITAXIAL SUBSTRATE, AND SEMICONDUCTOR DEVICE - An epitaxial growth substrate on an embodiment includes a non-oriented base material and a buffer layer including a metal chalcogenide on the base material. The metal chalcogenide has uniform crystal orientation on a surface of the buffer layer opposite to the base material side. The buffer layer has a thickness of at least 1.0 μm. | 2020-07-02 |
20200211842 | HIGH BREAKDOWN VOLTAGE STRUCTURE FOR HIGH PERFORMANCE GAN-BASED HEMT AND MOS DEVICES TO ENABLE GAN C-MOS - An integrated circuit structure comprises a relaxed buffer stack that includes a channel region, wherein the relaxed buffer stack and the channel region include a group III-N semiconductor material, wherein the relaxed buffer stack comprises a plurality of AlGaN material layers and a buffer stack over the plurality of AlGaN material layers, wherein the buffer stack comprises the group III-N semiconductor material and has a thickness of less than approximately 25 nm. A back barrier is in the relaxed buffer stack between the plurality of AlGaN material layers and the buffer stack, wherein the back barrier comprises an AlGaN material of approximately 2-10% Al. A polarization stack over the relaxed buffer stack. | 2020-07-02 |
20200211843 | METHODS OF FORMING TUNGSTEN STRUCTURES - Described are methods for forming a multilayer conductive structure for semiconductor devices. A seed layer is formed comprising a metal and an additional constituent that in combination with the metal inhibits nucleation of a fill layer of the metal formed over the seed layer. Tungsten may be doped or alloyed with silicon to form the seed layer, with a tungsten fill being formed over the seed layer. | 2020-07-02 |
20200211844 | METHOD OF PROCESSING A TARGET MATERIAL - Methods of processing a target material are disclosed. In one arrangement, a multilayer structure is irradiated with a radiation beam. The multilayer structure comprises at least a target layer comprising the target material and an additional layer not comprising the target material. The additional layer is metallic. The target layer is irradiated through the additional layer during the irradiation of the multilayer structure. A transfer of energy from the radiation beam to the target layer and to the additional layer is such as to cause a thermally-induced change in the target layer. The thermally-induced change comprising one or more of: crystal growth in the target material, increased carrier mobility in the target material, increased chemical stability in the target material, and increased uniformity of electrical properties in the target material. | 2020-07-02 |
20200211845 | IN-DIE METROLOGY METHODS AND SYSTEMS FOR PROCESS CONTROL - Systems and methods for in-die metrology using target design patterns are provided. These systems and methods include selecting a target design pattern based on design data representing the design of an integrated circuit, providing design data indicative of the target design pattern to enable design data derived from the target design pattern to be added to second design data, wherein the second design data is based on the first design data. Systems and methods can further include causing structures derived from the second design data to be printed on a wafer, inspecting the structures on the wafer using a charged-particle beam tool, and identifying metrology data or process defects based on the inspection. In some embodiments the systems and methods further include causing the charged-particle beam tool, the second design data, a scanner, or photolithography equipment to be adjusted based on the identified metrology data or process defects. | 2020-07-02 |
20200211846 | METHOD OF FILLING GROOVES AND HOLES IN A SUBSTRATE - A method of forming a pattern of metallic material on a substrate includes providing a plurality of void regions on a surface of the substrate. At a first temperature, a first layer of a first metallic material of a eutectic-forming pair of metallic materials is deposited on the substrate to form a conformal metallic film over the substrate and over the surfaces of the plurality of void regions. The substrate and conformal metallic film are warmed to a second temperature greater than a eutectic-liquid-formation temperature of the eutectic pair of metallic materials. At the second temperature, the second metallic material of the eutectic-forming pair of metallic materials is deposited on the conformal metallic film to initiate a eutectic-liquid-forming reaction, such that the plurality of void regions are filled with a mixture of the first and second metallic materials of the eutectic-forming pair of metallic materials. | 2020-07-02 |
20200211847 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device and a semiconductor processing apparatus are provided. The method of fabricating a semiconductor device comprises preparing a semiconductor substrate having a front side and a back side, opposing each other, and forming a material layer on the semiconductor substrate. The material layer is formed on at least a portion of the back side of the semiconductor substrate while being formed on the front side of the semiconductor substrate. The material layer formed on the at least a portion of the back side of the semiconductor substrate is removed, while the material layer formed on the front side of the semiconductor substrate remains. A semiconductor process is performed to fabricate the semiconductor device using the material layer remaining on the front side of the semiconductor substrate. | 2020-07-02 |
20200211848 | SEMICONDUCTOR STRUCTURE PROVIDING FOR AN INCREASED PATTERN DENSITY ON A SUBSTRATE AND METHOD FOR FORMING SAME - Disclosed are a semiconductor structure and a method for forming the same. The method includes: providing a base, including a first region and a second region, where a pitch between target patterns formed on the first region is greater than a pitch between target patterns formed on the second region; forming a bottom core material layer on the base; forming first core layers on the bottom core material layer; forming a first mask sidewall on a sidewall of the first core layer of the first region, and forming a second mask sidewall on a sidewall of the first core layer of the second region, where the thickness of the second mask sidewall is greater than the thickness of the first mask sidewall; removing the first core layers; patterning the bottom core material layer by using the first mask sidewall and the second mask sidewall as masks, to form a second core layer; removing the first mask sidewall and the second mask sidewall; forming a third mask sidewall on a sidewall of the second core layer; removing the second core layer; and patterning the base by using the third mask sidewall as a mask, to form target patterns protruding out of a residual base. The present disclosure meets the requirement of different pitches of the target patterns. | 2020-07-02 |
20200211849 | LOW CONTACT RESISTANCE GRAPHENE DEVICE INTEGRATION - A method, e.g. of forming an electronic device, includes forming a carbon-doped metal layer over a substrate. The carbon-doped metal layer is heated and cooled such that a first graphene layer is formed on a top surface of the carbon-doped metal layer, and a second graphene layer is formed between the carbon-doped metal layer and the substrate. A portion of the first graphene layer is removed and a portion of the carbon-doped metal layer is removed, thereby forming first and second spaced-apart contact layers on the second graphene layer. | 2020-07-02 |
20200211850 | CARRIER-ASSISTED METHOD FOR PARTING CRYSTALLINE MATERIAL ALONG LASER DAMAGE REGION - A method for removing a portion of a crystalline material (e.g., SiC) substrate includes joining a surface of the substrate to a rigid carrier (e.g., >800 μm thick), with a subsurface laser damage region provided within the substrate at a depth relative to the surface. Adhesive material having a glass transition temperature above 25° C. may bond the substrate to the carrier. The crystalline material is fractured along the subsurface laser damage region to produce a bonded assembly including the carrier and a portion of the crystalline material. Fracturing of the crystalline material may be promoted by (i) application of a mechanical force proximate to at least one carrier edge to impart a bending moment in the carrier; (ii) cooling the carrier when the carrier has a greater coefficient of thermal expansion than the crystalline material; and/or (iii) applying ultrasonic energy to the crystalline material. | 2020-07-02 |
20200211851 | LIGHT IRRADIATION TYPE HEAT TREATMENT METHOD AND HEAT TREATMENT APPARATUS - Multiple theoretical reflectances determined by simulation for a silicon substrate with thin films of multiple types and thicknesses formed thereon are registered in association with the types and the thicknesses in a database. A carrier storing semiconductor wafers in a lot is transported into a heat treatment apparatus. A reflectance of a semiconductor wafer is measured by applying light to a surface of the semiconductor wafer. The theoretical reflectance of the semiconductor wafer is calculated from the measured reflectance thereof. A theoretical reflectance closely resembling the theoretical reflectance of the semiconductor wafer is extracted from among the multiple theoretical reflectances registered in the database, whereby the type and thickness of the thin film formed on the surface of the semiconductor wafer are specified. Treatment conditions for the semiconductor wafer are determined based on the specified type and thickness of the thin film. | 2020-07-02 |
20200211852 | METHODS AND APPARATUS FOR ENHANCING SELECTIVITY OF TITANIUM AND TITANIUM SILICIDES DURING CHEMICAL VAPOR DEPOSITION - Methods and apparatus for selectively depositing a titanium material layer atop a substrate having a silicon surface and a dielectric surface are disclosed. In embodiments an apparatus is configured for forming a remote plasma reaction between titanium tetrachloride (TiCl | 2020-07-02 |
20200211853 | METAL FILL PROCESS FOR THREE-DIMENSIONAL VERTICAL NAND WORDLINE - Disclosed are methods of depositing a transition metal such as tungsten on a semiconductor substrate. The method includes providing a gas mixture of diborane with a balance of hydrogen, where the hydrogen serves to stabilize the diborane in the gas mixture. The method further includes delivering the gas mixture to the semiconductor substrate to form a boron layer, where the boron layer serves as a reducing agent layer to convert a metal-containing precursor to metal, such as a tungsten-containing precursor to tungsten. In some implementations, the semiconductor substrate includes a vertical structure, such as a three-dimensional vertical NAND structure, with horizontal features or wordlines having openings in sidewalls of the vertical structure, where the boron layer may be conformally deposited in the horizontal features of the vertical structure. | 2020-07-02 |
20200211854 | ETCHING METHOD - An etching method of etching a silicon nitride region with high selectivity is provided. In the etching method, a processing target object, having a silicon nitride region and a silicon-containing region having a composition different from the silicon nitride region, is accommodated in a processing vessel, and the silicon nitride region is selectively etched. In a first process, a deposit containing hydrofluorocarbon is formed on the silicon nitride region and the silicon-containing region by generating plasma of a processing gas containing a hydrofluorocarbon gas within the processing vessel. In a second process, the silicon nitride region is etched by radicals of the hydrofluorocarbon contained in the deposit. The first process and the second process are repeated alternately. | 2020-07-02 |
20200211855 | Improved Mask For Protecting A Semiconductor Material For Localized Etching Applications - The invention relates to the chemical etching of a semiconductor material, including:
| 2020-07-02 |
20200211856 | ETCHING SOLUTION, AND METHOD OF PRODUCING SEMICONDUCTOR ELEMENT - A SiGe compound etching solution for selectively etching a compound represented by general formula Si | 2020-07-02 |
20200211857 | SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING SYSTEM - A substrate processing method is provided. In the method, a substrate is provided. A monomer that is chemically bonded to the substrate is supplied onto the substrate. An initiator for polymerizing the monomer is supplied to the substrate having the supplied monomer thereon, thereby forming a polymer film. | 2020-07-02 |
20200211858 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - There is provided a technique that includes: loading a substrate having a metal film composed of a single metal element formed on a surface of the substrate into a process chamber; generating reactive species by plasma-exciting a processing gas containing hydrogen and oxygen; and modifying the metal film by supplying the reactive species to the substrate, wherein in the act of modifying the metal film, the metal film is modified such that a crystal grain size of the metal element constituting the metal film is larger than that before performing the act of modifying the metal film. | 2020-07-02 |
20200211859 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME - A semiconductor structure and a method for forming same, the forming method including: providing a base, where a dummy gate structure is formed on the base, an interlayer dielectric layer is formed on the base the dummy gate structure exposes, and the interlayer dielectric layer exposes the top of the dummy gate structure; forming an isolation structure in the interlayer dielectric layer between adjacent dummy gate structures, where the isolation structure further extends into the base; after forming the isolation structure, removing the dummy gate structure and forming a gate opening in the interlayer dielectric layer; filling a gate electrode material into the gate opening, where the gate electrode material further covers the top of the interlayer dielectric layer; and performing at least one polishing treatment to remove the gate electrode material above the top of the interlayer dielectric layer and retaining the gate electrode material in the gate opening as a gate electrode layer, where the step of the polishing treatment includes: performing first polishing treatment using a metal polishing liquid; and performing second polishing treatment using deionized water. With the second polishing performance, the probability of forming a residue of the gate electrode material on the top surface of the interlayer dielectric layer is reduced, thereby improving device performance. | 2020-07-02 |
20200211860 | METHOD OF DRY ETCHING COPPER THIN FILM - A method of etching a copper (Cu) thin film and a Cu thin film prepared therefrom, the method including patterning a hard mask layer on the Cu thin film to form a hard mask on the Cu thin film; forming a plasma of a mixed gas, the mixed gas including an inert gas and an organic chelator material including an amine group, the mixed gas not including a halogen gas or a halide gas; and etching the Cu thin film through the hard mask using the plasma generated in the forming of the plasma of the mixed gas. | 2020-07-02 |
20200211861 | DIE BONDING PROCESS FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURED THEREBY - A die bonding process for manufacturing a semiconductor device includes the steps of: a) preparing a semiconductor structure and a substrate, b) mounting an electrode structure on the semiconductor structure to form a semiconductor component, c) forming a protective component at a die bonding region, and d) mounting the semiconductor component on the substrate via a die bonding technique. The protective component is made of an adsorbent material which has a greater adsorption capability for a suspended pollutant around the semiconductor device than an adsorption capability for the suspended pollutant of a material for the electrode structure. | 2020-07-02 |
20200211862 | 3D PRINTED SEMICONDUCTOR PACKAGE - In described examples, a method for encapsulating a semiconductor device includes the steps of immersing a layer of the semiconductor device in a liquid encapsulation material, irradiating portions of the liquid encapsulation material to polymerize the liquid encapsulation material, and moving the semiconductor device further from a surface of the liquid encapsulation material proximate to the layer. Immersing the semiconductor device is performed to cover a layer of the device in the liquid encapsulation material. Targeted locations of the liquid encapsulation material covering the layer are irradiated to form solid encapsulation material. The semiconductor device is moved from a surface of the liquid encapsulation material so that a new layer of the semiconductor device and/or of the solid encapsulation material can be covered by the liquid encapsulation material. The irradiating and moving steps are then repeated until a three dimensional structure on the semiconductor device is formed using the solid encapsulation material. | 2020-07-02 |
20200211863 | SEMICONDUCTOR DEVICE PACKAGE - The present disclosure relates to a semiconductor device package including a substrate, a semiconductor device and an underfill. The substrate has a first surface and a second surface angled with respect to the first surface. The semiconductor device is mounted on the first surface of the substrate and has a first surface facing the first surface of the substrate and a second surface angled with respect to the first surface of the substrate. The underfill is disposed between the first surface of the semiconductor device and the first surface of the substrate. The second surface of the substrate is located in the substrate and external to a vertical projection of the semiconductor device on the first surface of the substrate. A distance between the second surface of the substrate and an extension of the second surface of the semiconductor device on the first surface of the substrate is less than or equal to twice a distance between the first surface of the semiconductor device and the first surface of the substrate. The second surface of the substrate extends along at least three sides of the semiconductor device. | 2020-07-02 |
20200211864 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - According to one embodiment, a substrate processing apparatus includes a table configured to place a substrate thereon and to connect the substrate to a positive electrode, an counter electrode located opposite to the table, having a plurality of holes, and connected to a negative electrode, and a holding unit located opposite to the table across the counter electrode and configured to supply a chemical liquid to the counter electrode while holding the counter electrode. | 2020-07-02 |
20200211865 | SUBSTRATE LIQUID PROCESSING APPARATUS - A substrate processing apparatus includes: a processing tank that stores a processing liquid for performing a liquid processing on a plurality of substrates; a substrate support that supports the plurality of substrates such that main surfaces of each of the plurality of substrates follow a vertical direction in the processing tank; a processing liquid ejection unit provided below the plurality of substrates supported by the substrate support, and generates an ascending flow of the processing liquid in the processing tank; and a rectifying section that adjusts flow of the processing liquid in a side space formed between a first side wall of the processing tank and a first substrate having a main surface facing the first side wall of the processing tank among the plurality of substrates. | 2020-07-02 |
20200211866 | GAS INTRODUCTION STRUCTURE, TREATMENT APPARATUS, AND TREATMENT METHOD - A gas introduction structure includes: a gas introduction pipe inserted in a process chamber; and a discharge part covering an end portion of the gas introduction pipe at a side of the process chamber, and configured to discharge a gas supplied to the gas introduction pipe into the process chamber, wherein the discharge part includes a porous portion formed of a porous body, and a dense portion disposed at a location closer to a leading end of the discharge part than the porous portion and having a porosity lower than that of the porous portion. | 2020-07-02 |
20200211867 | SUBSTRATE PROCESSING APPARATUS AND OPERATION METHOD OF SUBSTRATE PROCESSING APPARATUS - A plasma processing apparatus includes a storage; processors; a liquid supply which supplies, into the storage, at least a first liquid composed of a processing liquid or source liquids for composing the processing liquid; a detector which detects a value of a parameter indicating a state of the first liquid supplied into the storage or a state of the processing liquid in the storage; and a controller which controls the processors to perform a liquid processing in sequence. The controller determines, based on a detection result of the value of the parameter, whether it is possible to supply the processing liquid continuously into a preset number of processors concurrently under a condition requested by the processors, and, if not, the controller performs a simultaneous processing restricting control of reducing a number of processors which are supposed to perform the liquid processing concurrently to be lower than the preset number. | 2020-07-02 |
20200211868 | SUBSTRATE TREATING APPARATUS AND SUBSTRATE TRANSPORTING METHOD - Disclosed is a substrate treating apparatus and a substrate transporting method. An ID block | 2020-07-02 |
20200211869 | SAMPLE HOLDER - A sample holder includes: a ceramic body including a one main surface, and a sample holding surface on the one main surface; a heat-generating resistor disposed on an other main surface of the ceramic body; and a plurality of grooves arranged in a lattice on a surface of the heat-generating resistor, the plurality of grooves having extending directions that are different on different portions of the surface of the heat-generating resistor. | 2020-07-02 |
20200211870 | SUBSTRATE PROCESSING APPARATUS, TRANSFER MODULE, AND COUPLING MODULE - A first processing module includes a first specified processing unit and a first delivery part. A substrate supply part is on a first direction side of the first processing module. A transfer module is on a second direction side on the opposite of the first processing module from the first direction. The transfer module includes a frame, a first floor, a second floor, and a gateway. The frame defines a placement space in which a first transfer apparatus of the transfer module is placed. A first transfer apparatus is installed on the first floor. The second floor is on a third direction side, which is a horizontal direction orthogonal to the first direction, with respect to the first floor inside the placement space. The gateway is provided on the third direction side with respect to the second floor and communicates the placement space to the outside of the frame. | 2020-07-02 |
20200211871 | SUBSTRATE PROCESSING APPARATUS AND METHOD - Disclosed is a substrate processing apparatus that includes an interference member for minimizing a collision between a descending flow of gas supplied by a fan unit and a gas flow directed toward a transfer space from the inside of a container. | 2020-07-02 |
20200211872 | TEMPERATURE CONTROLLING APPARATUS AND METHOD OF CONTROLLING THE TEMPERATURE CONTROLLING APPARATUS - A temperature controlling apparatus includes a member having a member flow path within the member, and includes a first temperature controller configured to control a temperature of a first temperature-controlled medium to a first temperature. The temperature controlling apparatus includes a second temperature controller configured to control a temperature of a second temperature-controlled medium to a second temperature, the second temperature differing from the first temperature. The temperature controlling apparatus includes a first flow path of the first temperature-controlled medium, between the member flow path and the first temperature controller. The temperature controlling apparatus includes a second flow path of the second temperature-controlled medium, between the member flow path and the second temperature controller, and includes a third flow path of the first temperature-controlled medium that flows to the first temperature controller, without using the member flow path. | 2020-07-02 |
20200211873 | Temperature Control Apparatus for Semiconductor Processing Equipment, And Temperature Control Method for The Same - Disclosed are a temperature control apparatus for semiconductor processing equipment and a corresponding temperature control method, wherein each heating element in each row or each column in a heating element matrix forms a power return circuit with a same power source, respectively, and a same switch module is provided for the power return circuits of all heating elements in each column or each row of the heating element matrix; the input powers to the heating elements in an entire row or column controlled by each power output port of the power source are adjusted by adjusting the output power magnitude of the corresponding power source, and conduction/disconnection of the power return circuits of an entire column or row controlled by each switch module is controlled by controlling ON/OFF of each switch module. The present disclosure reduces circuit complexity and saves costs; the present disclosure reduces temperature control complexity while guaranteeing temperature control accuracy, thereby achieving a uniform and flexible temperature control result. | 2020-07-02 |
20200211874 | APPARATUS AND METHOD FOR TREATING SUBSTRATE - Disclosed is a substrate treating apparatus that includes a housing having a process space therein, a plate that supports a substrate in the housing, a heating member that is provided in the plate and that heats the substrate, a plurality of controllers that control the heating member and that have different gains, a temperature measurement member that measures temperature in the housing, and a control member that switches the plurality of controllers to cause one of the plurality of controllers to control the heating member depending on a temperature drop section, a temperature rise section, and an anneal section in the housing. | 2020-07-02 |
20200211875 | LASER MARKING DEVICE AND LASER MARKING METHOD - A laser marking device includes a laser emission unit configured to emit a laser beam to a first surface of an object to be processed, and a pressing unit configured to press a second surface that is opposite to the first surface of the object to be processed to make the first surface of the object to be flat. The pressing unit includes a first pressing portion configured to press an edge area of the second surface in a contact manner, and at least one second pressing portion configured to press a middle area of the second surface in a non-contact manner to maintain a separation distance from the second surface within a certain distance. | 2020-07-02 |
20200211876 | RETICLE POD HAVING SIDE CONTAINMENT OF RETICLE - A reticle pod includes an outer pod, an inner pod cover and an inner base plate. A reticle is supported on the base and is contained within the environment created by the inner pod cover and the inner pod base. The inner pod cover can include a plurality of reticle retainers configured to contact a side wall of the reticle and limit movement of the reticle in a horizontal direction. | 2020-07-02 |
20200211877 | LATCHING MECHANISM FOR A SUBSTRATE CONTAINER - A substrate container that utilizes a rocker linkage or a linear cam arrangement in latch mechanism that is actuated by a rotary cam. The rocker linkage or linear cam is mounted to an interior panel of a door of the substrate container and may be disposed proximate an edge portion of the interior panel. The rocker linkage or linear cam may be configured to exert an axial force component on a housing of the substrate container to seat the door against a seal member. The rocker linkage or linear cam also transfers the axial latching forces to the door to reduce transfer of forces to the cam. The rocker linkage or linear cam may be arranged to transfer axial forces in a radially outward direction when the latch mechanism is engaged, to prevent push back on the rotary cam. | 2020-07-02 |
20200211878 | Method and Apparatus for Poling Polymer Thin Films - A poling apparatus for poling a polymer thin film formed on a workpiece carried by a workpiece carrier. The workpiece has grounding electrodes and grounding pads located at edges, and a thin film covering the grounding electrodes but exposing the grounding pads. The workpiece carrier has carrier electrodes located around the workpiece and inside grounding ports at the bottom. The poling apparatus includes, in a poling chamber, a poling source generating a plasma, a Z-elevator to raise the workpiece carrier toward the poling source using the grounding ports, and grounding mechanisms including downwardly biased electrical contacts which, when the workpiece carrier is raised by the Z-elevator, connect the grounding pads of the workpiece with the carrier electrodes, to ground the workpiece. The poling apparatus additionally includes preparation platform and transfer platform with conveyer systems with rollers and Z-elevators to move the workpiece carrier in and out of the poling chamber. | 2020-07-02 |
20200211879 | LAYOUT STRUCTURE BETWEEN SUBSTRATE, MICRO-LED ARRAY AND MICRO-VACUUM MODULE FOR MICRO-LED ARRAY TRANSFER USING MICRO-VACUUM MODULE, AND METHOD FOR MANUFACTURING MICRO-LED DISPLAY USING THE SAME - The present disclosure provides a method for transfer and assembly of RGB micro-light-emitting diodes using vacuum suction force whereby the vacuum state of micrometer-sized adsorption holes to which micro-light-emitting diodes formed on a mother substrate or a temporary substrate are bonded is controlled selectively, so that only the micro-light-emitting diode devices desired to be detached from the mother substrate or the temporary substrate are detached from the mother substrate or the temporary substrate using vacuum suction force and then transferred to a target substrate | 2020-07-02 |
20200211880 | SUBSTRATE TREATING APPARATUS AND SUBSTRATE TRANSPORTING METHOD - Disclosed are a substrate treating apparatus and a substrate transporting method. A platform is placed on a first ID block, and a platform is placed on a second ID block. A currently-used carrier platform is provided only on the first ID block. Accordingly, a substrate is transported in both a forward path and a return path between the first ID block and an IF block. According to the disclosure, the substrate is sent in the return path from the IF block to the second ID block disposed between a coating block and a developing block without being transported from the IF block to the first ID block. Consequently, transportation process in the return path by the coating block disposed between the first ID block and the second ID block is reduced. As a result, an entire throughput of a substrate treating apparatus can be enhanced. | 2020-07-02 |
20200211881 | SUBSTRATE TREATING APPARATUS, CARRIER TRANSPORTING METHOD, AND CARRIER BUFFER DEVICE - Disclosed is a substrate treating apparatus, a carrier transporting method, and a carrier buffer device. A carrier transport mechanism transports a carrier between platforms of two openers and carrier storage shelves. The carrier storage shelves and the carrier transport mechanism are each mounted on a first treating block. Accordingly, there is no need as before to provide the carrier storage shelves and the carrier transport mechanism horizontally in an extended manner from the indexer block, achieving reduction in installation area extending horizontally. In other words, reduction in footprint of a substrate treating apparatus is obtainable. | 2020-07-02 |
20200211882 | SUBSTRATE TREATING APPARATUS AND SUBSTRATE TRANSPORTING METHOD - Disclosed are a substrate treating apparatus and a substrate transporting method. A first ID block takes a substrate from a carrier placed on a carrier platform and sends the taken substrate to one of six treatment layers. Moreover, a second ID block returns the substrate, sent from the treatment layer, for example, to a carrier placed on a platform. This allows the first ID block to transport many substrates to the six treatment layers arranged in an upward/downward direction more rapidly. Moreover, this simultaneously allows the second ID block to transport many substrates, having been sent from the six treatment layers arranged in the upward/downward direction, to the carrier more rapidly. As a result, a throughput of a substrate treating apparatus can be enhanced. | 2020-07-02 |
20200211883 | ADHESIVE-LESS SUBSTRATE BONDING TO CARRIER PLATE - Methods for bonding and de-bonding a thin substrate film to a carrier plate are provided herein. In some embodiments, a method of processing a semiconductor substrate includes applying a polymer layer that is non-adhesive to a carrier plate formed of a dielectric material. A second layer is then applied to the polymer layer. One or more redistribution layers are then formed on the second layer. The second layer is then separated from the carrier plate via at least one of magnetic induction heating, infrared exposure, or electrostatic repulsion. | 2020-07-02 |
20200211884 | COMPOSITE SINTERED BODY, ELECTROSTATIC CHUCK MEMBER, AND ELECTROSTATIC CHUCK DEVICE - A composite sintered body, wherein the composite sintered body consists of ceramic composite sintered body, the ceramic composite sintered body comprises aluminum oxide as a main phase, and silicon carbide as a sub-phase, in which the composite sintered body has mullite in crystal grains of the aluminum oxide. | 2020-07-02 |
20200211885 | SUBSTRATE PLACING TABLE AND SUBSTRATE PROCESSING APPARATUS - A substrate placing table according to an exemplary embodiment includes a base and an electrostatic chuck provided on the base. The electrostatic chuck includes a lamination layer portion, an intermediate layer, and a covering layer. The lamination layer portion is provided on the base. The intermediate layer is provided on the lamination layer portion. The covering layer is provided on the intermediate layer. The lamination layer portion includes a first layer, an electrode layer, and a second layer. The first layer is provided on the base. The electrode layer is provided on the first layer. The second layer is provided on the electrode layer. The intermediate layer is provided between the second layer and the covering layer and is in close contact with the second layer and the covering layer. The second layer is a resin layer. The covering layer is ceramics. | 2020-07-02 |
20200211886 | MEASUREMENT METHOD AND MEASURING JIG - In a measurement method, a terminal is brought into contact with an electrode in an electrostatic chuck in contact with a substrate that is grounded. Further, the terminal, the electrostatic chuck and the substrate are fixed, and a current value and a voltage value are measured using an ammeter and a voltmeter, respectively, that are connected to the terminal. In addition, whether or not the terminal and the electrode are electrically connected is determined from a slope of the current value and/or a peak current value based on the measured current value and the voltage value. | 2020-07-02 |
20200211887 | FAN-OUT INTERCONNECT STRUCTURE AND METHODS FORMING THE SAME - A method includes forming an adhesive layer over a carrier, forming a sacrificial layer over the adhesive layer, forming through-vias over the sacrificial layer, and placing a device die over the sacrificial layer. The Method further includes molding and planarizing the device die and the through-vias, de-bonding the carrier by removing the adhesive layer, and removing the sacrificial layer. | 2020-07-02 |
20200211888 | PATTERNED CARRIER WAFERS AND METHODS OF MAKING AND USING THE SAME - An apparatus is provided, comprising: a wafer having a first planar surface and a second surface opposite the first surface. The second surface includes a plurality of recesses. Each recess includes a plurality of sidewalls and a lower surface and is configured to receive a semiconductor device. The plurality of sidewalls of each recess is configured to align the semiconductor device and constrain the semiconductor device from moving in a direction parallel to the second surface. | 2020-07-02 |
20200211889 | DICING DIE-BONDING FILM - The present invention relates to a dicing die-bonding film including: a substrate; an antistatic layer formed on the substrate and including an aliphatic or alicyclic polyurethane resin and a conductive filler; a cohesive layer formed on the antistatic layer; and an adhesive layer formed on the cohesive layer, and a dicing method of a semiconductor wafer using the dicing die-bonding film. | 2020-07-02 |
20200211890 | METHOD AND APPARATUS FOR FABRICATING DISPLAY PANEL - A method and an apparatus for fabricating a display panel are provided. The method comprises steps of: providing a substrate; transferring the substrate to a coating chamber; clamping end edge positions of the substrate with clamps; performing a coating operation; and releasing the clamps and transferring the substrate out of the coating chamber. The apparatus comprises a guide rail device for transporting a substrate, and a clamp device for clamping and fixing the substrate, and the guide rail device is movably connected to the clamp device, and the clamp device is provided with clamps for clamping the substrate, and the clamps are placed at positions corresponding to end edges of the substrate. Since the clamps clamp the end edge positions of the substrate, force bearing points can be effectively dispersed, and the substrate can be effectively fixed and its movement limited, effectively preventing the substrate from falling. | 2020-07-02 |
20200211891 | SUBSTRATE HOLDING DEVICE - A substrate holding device is provided. The substrate holding device includes a substrate holder, a shaft attached to the substrate holder, a motor attached to the shaft, lifting pins, and a transmission assembly. The lifting pins are movable between a retracted position below a surface of the substrate holder, and a protruded position protruding from the surface. The transmission assembly is provided between the shaft and lifting pins and switches the substrate holding device between a transmittable state in which a driving force from the motor is transmitted to the lifting pins to move the lifting pins between the retracted position and the protruded position, and a non-transmittable state in which the driving force from the motor is not transmitted to the lifting pins but rotates the substrate holder. | 2020-07-02 |
20200211892 | MOUNTING TABLE, SUBSTRATE PROCESSING APPARATUS, AND CONTROL METHOD - A mounting table is provided. The mounting table includes a base having a first flow path, a recess, and a second flow path connected to the recess, and a variable control mechanism configured to variably control a contact area between a target object disposed on the base and a mounting surface for mounting thereon the target object by filling and discharging fluid into and from the recess through the second flow path. | 2020-07-02 |
20200211893 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - The present disclosure provides a semiconductor structure and a method of manufacturing the same. The semiconductor structure includes a semiconductor substrate, an air gap region, a capping layer, and an isolating layer. The air gap region is disposed in the semiconductor substrate. The capping layer is disposed on the air gap region. The isolating layer is disposed on the semiconductor substrate and partially encircles the capping layer. | 2020-07-02 |
20200211894 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME - Disclosed are a semiconductor structure and a method for forming same. One form of the forming method includes: providing a base, including a substrate and a fin protruding out of the substrate, where a fin mask layer is formed on the top of the fin, and the base includes a graphics-intensive region and a graphics-sparse region; forming an isolation material layer on the substrate exposed by the fin, to expose a top of the fin mask layer; performing first etching processing on the isolation material layer, where a residual isolation material layer covers a partial sidewall of the fin mask layer, and a top of the residual isolation material layer located on the graphics-sparse region is lower than a top of the residual isolation material layer located on the graphics-intensive region; removing the fin mask layer after the first etching processing is performed; and performing second etching processing on the residual isolation material layer using an isotropic dry etching process after the fin mask layer is removed, where the etched isolation material layer is used as an isolation layer, and the isolation layer covers a partial sidewall of the fin. Embodiments of the present disclosure help to improve the height consistency of the tops of isolation layers located on different graphics density regions, thereby improving the performance of the semiconductor structure. | 2020-07-02 |
20200211895 | METHOD FOR FORMING DUAL DAMASCENE INTERCONNECT STRUCTURE - A method for forming a dual damascene interconnect structure. A substrate having a conductor layer, an etch stop layer on the conductor layer, a dielectric stack on the etch stop layer, and a hard mask layer on the dielectric stack is provided. A photoresist layer having a resist opening is formed on the hard mask layer. The hard mask layer is etched through the resist opening to form a hard mask opening. The dielectric stack is etched through the hard mask opening to form a partial via hole. The photoresist layer is trimmed to form a widened resist opening above the partial via hole. The hard mask layer is etched through the widened resist opening to form a widened hard mask opening above the partial via hole. The dielectric stack is etched through the widened hard mask opening and the partial via hole to form a dual damascene via. | 2020-07-02 |
20200211896 | SEMICONDUCTOR SUBSTRATE AND METHOD OF PROCESSING THE SAME - The present disclosure provides a semiconductor substrate. The semiconductor substrate includes a base, a plurality of mesas extending from an upper surface of the base, a plurality of protrusions connected to the mesas, an insulating layer disposed on the protrusions, a capping layer disposed on the insulating layer, and a passivation layer disposed on sidewalls of the protrusions, the insulating layer, and the capping layer. The passivation layer includes at least one first film and at least one second film arranged in a staggered configuration. | 2020-07-02 |
20200211897 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed. | 2020-07-02 |
20200211898 | MULTI-PASS PLATING PROCESS WITH INTERMEDIATE RINSE AND DRY - A method includes electroplate depositing a first metal layer to a first thickness on a metal seed layer, rinsing the first metal layer with deionized water, and after the first rinse process, drying the wafer. The method also includes performing one or more additional electroplating processes that respectively deposit an additional metal layer to a second thickness over the first metal layer, performing an additional rinse process that rinses the additional metal layer with deionized water, and performing an additional drying processes that dries the wafer. | 2020-07-02 |
20200211899 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure including a substrate, a complementary metal oxide semiconductor (CMOS) device, a bipolar junction transistor (BJT), and a first interconnect structure is provided. The substrate has a first side and a second side opposite to each other. The CMOS device includes an NMOS transistor and a PMOS transistor disposed on the substrate. The BJT includes a collector, a base and an emitter. The collector is disposed in the substrate. The base is disposed on the first side of the substrate. The emitter is disposed on the base. A top surface of a channel of the NMOS transistor, a top surface of a channel of the PMOS transistor and a top surface of the collector of the BJT have the same height. The first interconnect structure is electrically connected to the base at the first side of the substrate and extends to the second side of the substrate. | 2020-07-02 |
20200211900 | FINFET STRUCTURE AND METHOD OF MANUFACTURING THE SAME - The present disclosure relates to a FinFET structure and a method of manufacturing the same. The FinFET structure includes a first fin and a second fin. The first fin is over a first base and has a first channel region. The first channel region has a first channel length. The second fin is over a second base and has a second channel region. The second channel region has a second channel length. The second channel length is different from the first channel length. | 2020-07-02 |
20200211901 | METHODS FOR DOPING A SUB-FIN REGION OF A SEMICONDUCTOR FIN STRUCTURE AND DEVICES CONTAINING THE SAME - Methods for doping a subfin region of a semiconductor fin structure include forming a fin on a substrate; forming an oxide material on the substrate and a portion of the fin that corresponds to a sub-fin region of the fin; forming a hard mask on a top-fin region of the fin that is disposed above the sub-fin region; exposing a surface of the sub-fin region by removing the oxide material from a surface of the sub-fin region and leaving a layer of the oxide material on the substrate; depositing a dopant material on the hard mask, the surface of the subfin region, and the layer of the oxide material on the substrate; and removing the hard mask from the top-fin region to expose a surface of the top-fin region. Devices constructed using the disclosed methods are also provided, and other embodiments are discussed | 2020-07-02 |
20200211902 | GATE STACK OPTIMIZATION FOR WIDE AND NARROW NANOSHEET TRANSISTOR DEVICES - A method of forming a nanosheet device is provided. The method includes forming a plurality of narrow nanosheets on a first region of a substrate, and forming a plurality of wide nanosheets on a second region of the substrate. The method further includes forming an interfacial layer on the plurality of narrow nanosheets and the plurality of wide nanosheets. The method further includes depositing a gate dielectric layer on the plurality of narrow nanosheets and the plurality of wide nanosheets. The method further includes depositing a dummy gate layer on the gate dielectric layer on the plurality of narrow nanosheets and the plurality of wide nanosheets. The method further includes forming a dummy cover layer on the dummy gate layer on the plurality of narrow nanosheets and the plurality of wide nanosheets. | 2020-07-02 |
20200211903 | SEMICONDUCTOR STRUCTURE WITH SHAPED TRENCH AND METHODS OF FORMING THE SAME - The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to methods of forming a two-part trench in a semiconductor device that includes one or more field-effect transistors (FETs). The present method includes forming a semiconductor layer above a substrate, forming a mask layer above the semiconductor layer, forming a mask opening with sidewalls in the mask layer and exposing the semiconductor layer, depositing a profile control layer on the sidewalls of the mask opening, and forming a trench in the semiconductor layer by simultaneously etching the profile control layer and the exposed semiconductor layer, where the etching of the profile control layer forms the trench with top and bottom sections having different widths. | 2020-07-02 |
20200211904 | SEMICONDUCTOR STRUCTURES - A semiconductor structure is provided. The semiconductor structure comprises a substrate, including isolation regions and a device region between adjacent isolation regions; a plurality of fin structures, formed on the device region of the substrate; and an isolation layer, formed on the substrate. A top surface of the isolation layer is lower than top surfaces of the fin structures. A height of each fin structure exposed by the isolation layer is identical. | 2020-07-02 |
20200211905 | THREE DIMENSIONAL INTEGRATED CIRCUITS WITH STACKED TRANSISTORS - Embodiments herein describe techniques for a semiconductor device including a first transistor stacked above and self-aligned with a second transistor, where a shadow of the first transistor substantially overlaps with the second transistor. The first transistor includes a first gate electrode, a first channel layer including a first channel material and separated from the first gate electrode by a first gate dielectric layer, and a first source electrode coupled to the first channel layer. The second transistor includes a second gate electrode, a second channel layer including a second channel material and separated from the second gate electrode by a second gate dielectric layer, and a second source electrode coupled to the second channel layer. The second source electrode is self-aligned with the first source electrode, and separated from the first source electrode by an isolation layer. Other embodiments may be described and/or claimed. | 2020-07-02 |
20200211906 | METHOD OF PRODUCING MICROELECTRONIC COMPONENTS - A method is provided for producing a microelectronic component on a substrate including in an exposed manner on a first face thereof, an active zone and an electrical isolation zone adjacent thereto, the method including forming a gate on the active zone, forming spacers each configured to cover a surface of a different edge of the gate, and forming source and drain zones by doping portions of the active zone adjacent to the gate, the method successively including forming a first layer of spacer material above the active zone and the electrical isolation zone; an ion implantation to produce doping of the portions through the first layer; removing a modified portion of the first layer disposed overlooking the portions, the modified portion coming from the ion implantation, the removing being configured to preserve at least part of the first layer at a level of edges of the gate. | 2020-07-02 |
20200211907 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES BY ETCHING ACTIVE FINS USING ETCHING MASKS - In a method of manufacturing a semiconductor device, first to third active fins are formed on a substrate. Each of the first to third active fins extends in a first direction, and the second active fin, the first active fin, and the third active fin are disposed in this order in a second direction crossing the first direction. The second active fin is removed using a first etching mask covering the first and third active fins. The third active fin is removed using a second etching mask covering the first active fin and a portion of the substrate from which the second active fin is removed. A first gate structure is formed on the first active fin. A first source/drain layer is formed on a portion of the first active fin adjacent the first gate structure. | 2020-07-02 |
20200211908 | REPLACEMENT METAL GATE PROCESS FOR VERTICAL TRANSPORT FIELD-EFFECT TRANSISTORS WITH MULTIPLE THRESHOLD VOLTAGES - A method of forming a semiconductor structure includes forming a plurality of fins over a top surface of a bottom source/drain region disposed over a top surface of a substrate, the fins providing vertical transport channels for a plurality of vertical transport field-effect transistors. The method also includes forming a first gate conductor surrounding a first one of an adjacent pair of the plurality of fins providing a first vertical transport channel for a first vertical transport field-effect transistor, forming a second gate conductor surrounding a second one of the adjacent pair of the plurality of fins providing a second vertical transport channel for a second vertical transport field-effect transistor, and forming at least one shared gate contact to the first gate conductor and the second gate conductor, the at least one shared gate contact being formed at first ends of the adjacent pair of the plurality of fins. | 2020-07-02 |
20200211909 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The reliability of the semiconductor device is suppressed from deteriorating. A first gate electrode is formed on the semiconductor layer SM located in the SOI region | 2020-07-02 |
20200211910 | MULTILAYER MOS DEVICE AND METHOD FOR MANUFACTURING THE SAME - A multilayer MOS device and a method for manufacturing the same. The manufacturing method includes: providing a MOS device including n layers, where n is a natural number greater than zero; forming a semiconductor layer on the MOS device including n layers; forming a gate oxide layer and a dummy gate on the semiconductor layer sequentially, where at least a part of the gate oxide layer is located between the dummy gate and the semiconductor layer; forming a metal silicide layer in the semiconductor layer at two sides of the dummy gate, to obtain a MOS device of an (n+1)-th layer, where the metal silicide layer serves as a metallized source-drain region or the metal silicide layer is doped to form a metalized source-drain region; and connecting a MOS device of an n-th layer of the n layers with the MOS device of the (n+1)-th layer via metallic interconnection. | 2020-07-02 |
20200211911 | SPACER-PATTERNED INVERTERS BASED ON THIN-FILM TRANSISTORS - A semiconductor device may include a first gate electrode and a second gate electrode. A first channel area and a second channel area may be above the first gate electrode, where the first channel area may include a first type channel material, and the second channel area may include a second type channel material. A third channel area and a fourth channel area may be above the second gate electrode, where the third channel area may include the first type channel material, and the fourth channel area may include the second type channel material. The third channel area may be separated from the first channel area by a spacer. An inverter may include the first gate electrode, the first channel area, and the second channel area, while another inverter may include the second gate electrode, the third channel area, and the fourth channel area. Other embodiments may be described/claimed. | 2020-07-02 |
20200211912 | METHODS AND SYSTEMS FOR MEASURING SEMICONDUCTOR DEVICES - Semiconductor devices having measurement features and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a plurality of stacked semiconductor dies each having measurement features formed along an outer periphery of a surface thereof. One or more image capture devices can image the semiconductor device and a controller can detect the measurement features in imaging data received from the image capture devices. The controller can further determine the distance between two or more of the measurement features to estimate a bond line thickness between semiconductor dies in the stack. | 2020-07-02 |
20200211913 | ELECTRICAL DEVICE WITH TEST PADS ENCASED WITHIN THE PACKAGING MATERIAL - An electrical device includes a substrate orientated parallel to a first plane and a first integrated circuit die disposed above the substrate. The first integrated circuit die includes pads that are electrically coupled to at least some of the pads at the top surface of the substrate. The electrical device has a packaging material disposed above the first integrated circuit die. The electrical device includes one or more test pads that are orientated parallel to the first plane and disposed above the first integrated circuit die in the vertical direction. The one or more test pads are electrically coupled to the first integrated circuit die and encased within the packaging material such that the one or more test pads are not exposed external to the electrical device. | 2020-07-02 |
20200211914 | METHOD AND APPARATUS FOR ON-CHIP STRESS DETECTION - A microelectronic chip device includes a semiconductor substrate and multiple on-chip strain sensors (OCSS s) constructed on the substrate at various locations of the substrate. The OCSSs may each include multiple piezoresistive devices configured to sense a strain at a location of the various locations and produce a strain signal representing the strain at that location. A strain measurement circuit may also be constructed on the semiconductor substrate and configured to measure strain parameters from the strain signals produced by the OCSSs. The strain parameters represent the strains at the various location. Values of the strain parameters can be used for analysis of mechanical stress on the chip device. | 2020-07-02 |
20200211915 | WIRING SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A wiring substrate includes a substrate body composed of a plurality of ceramic layers (insulating materials) and having a front surface and a back surface located on opposite sides thereof and having a side surface located between the front surface and the back surface. The outline of the substrate body in a plan view which is a view from the front surface side is composed of a plurality of curved portions separated from one another and a plurality of straight portions each located between adjacent ones of the curved portions. The total length of the curved portions in the plan view is at least 40% of the sum of the total length of the curved portions and the total length of the straight portions. | 2020-07-02 |
20200211916 | PACKAGE COOLING BY COIL CAVITY - A semiconductor device assembly can include a first die package comprising a bottom side; a top side; and lateral sides extending between the top and bottom sides. The assembly can include an encapsulant material encapsulating the first die package. In some embodiments, the assembly includes a cooling cavity in the encapsulant material. The cooling cavity can have a first opening; a second opening; and an elongate channel extending from the first opening to the second opening. In some embodiments, the elongate channel surrounds at least two of the lateral sides of the first die package. In some embodiments, the elongate channel is configured to accommodate a cooling fluid. | 2020-07-02 |
20200211917 | DISPLAY PANEL AND DISPLAY DEVICE - Disclosed are a display panel and a display device, and the display panel includes a substrate, a thin ink film, and a protecting film stacked over each other, where an orthographical projection of the thin ink film onto the substrate covers an orthographical projection of the protecting film onto the substrate, an edge of the thin ink film is coated sealing glue. | 2020-07-02 |
20200211918 | ELECTRONIC DEVICE INCLUDING COOLING STRUCTURE - An electronic device according to various embodiments of the present disclosure includes a housing, a printed circuit board located inside the housing, an electrical element mounted on the printed circuit board, and a shield can that covers the electrical element. A recess area is formed on at least a portion of the shield can, and a metal structure is mounted in the recess area to cool heat generated by the electrical element. | 2020-07-02 |
20200211919 | CRYSTALLINE OXIDE FILM - A crystalline oxide film with excellent crystalline qualities that is useful for semiconductors requiring heat dissipation is provided. A crystalline oxide film including a first crystal axis, a second crystal axis; a metal oxide as a major component that includes gallium, a first side; and a second side that is shorter than the first side, a linear thermal expansion coefficient of the first crystal axis is smaller than a linear thermal expansion coefficient of the second crystal axis, a direction of the first side is parallel and/or substantially parallel to a direction of the first crystal axis, and a direction of the second side is parallel and/or substantially parallel to a direction of the second crystal axis. | 2020-07-02 |
20200211920 | ADHESIVE FILM, SEMICONDUCTOR APPARATUS USING THE SAME, AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - An adhesive film includes a porous metal layer having a plurality of pores therein, a first adhesive layer on one side of the porous metal layer, an adhesive substance at least partially filling the pores of the porous metal layer, and a plurality of first thermal conductive members distributed in the first adhesive layer. | 2020-07-02 |
20200211921 | SEMICONDUCTOR MODULE, METHOD FOR MANUFACTURING THE SAME, AND POWER CONVERSION DEVICE - A semiconductor module includes: a base plate; a semiconductor chip on the base plate; a case surrounding the semiconductor chip on the base plate, and sealing resin sealing the semiconductor chip inside the case, wherein a linear expansion coefficient of the sealing resin increases continuously from the semiconductor chip toward an upper surface of the sealing resin. | 2020-07-02 |
20200211922 | Integrated Circuit Package and Method - In an embodiment, a device includes: a package component including integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure over the encapsulant and the integrated circuit dies, and sockets over the redistribution structure; a mechanical brace physically coupled to the sockets, the mechanical brace having openings, each one of the openings exposing a respective one of the sockets; a thermal module physically and thermally coupled to the encapsulant and the integrated circuit dies; and bolts extending through the thermal module, the mechanical brace, and the package component. | 2020-07-02 |
20200211923 | EFFICIENT HEAT-SINKING IN PIN DIODE - The thermal impedance of p-i-n diodes integrated on semiconductor-on-insulator substrates can be reduced with thermally conducting vias that shunt heat across thermal barriers such as, e.g., the thick top oxide cladding often encapsulating the p-i-n diode. In various embodiments, one or more thermally conducting vias extend from a top surface of the intrinsic diode layer to a metal structure connected to the doped top layer of the diode, and/or from that metal structure down to at least the semiconductor device layer of the substrate. | 2020-07-02 |
20200211924 | THERMAL INTERFACE FORMED BY CONDENSATE - Methods and apparatus of forming a thermal interface with condensate are described. In an example, a device may be disposed in a test environment or a test apparatus. An amount of condensate may be accumulated on a heat sink to coat the heat sink with a layer of condensate. The coated heat sink may be disposed on the device, where the layer of condensate is directed towards the device, and the disposal of the coated heat sink causes the layer of condensate to spread among voids between the heat sink and the device to form a thermal interface that includes the condensate. A test may be executed on the device with the thermal interface comprising the condensate between the coated heat sink and the device. | 2020-07-02 |
20200211925 | COOLING SYSTEM - A cooling system includes: an evaporator configured to evaporate coolant by receiving heat of a heating device; a heat radiator configured to radiate heat of the coolant; a circulation passage through which the coolant circulates between the evaporator and the heat radiator; a pump that is provided in the circulation passage and is configured to circulate the coolant through the circulation passage; and an expandable device that is provided in the circulation passage and has expandable inner space into which the coolant flows, wherein the evaporator, the heat radiator, the circulation passage and the inner space are fully filled with the coolant. | 2020-07-02 |
20200211926 | CIRCUIT DEVICE - A circuit device includes a circuit component electrically connected to a conductor and a first heat dissipation member includes an insulation member interposed between the conductor and the attachment surface. A control element outputs a control signal, a circuit board is spaced apart from the first heat dissipation member and the conductor. A housing member includes a housing chamber housing the circuit component and the circuit board, a heat dissipation chamber through which air flows while being in contact with a heat dissipation surface of a second heat dissipation member, and a partition plate has a plurality of communication holes placing the heat dissipation chamber and the housing chamber in communication with each other. A portion of the first heat dissipation member excluding the attachment surface and a portion of the second heat dissipation member excluding the heat dissipation surface are in contact with air outside the circuit device. | 2020-07-02 |
20200211927 | MICROELECTRONIC ASSEMBLIES HAVING A COOLING CHANNEL - Microelectronic assemblies that include a cooling channel, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a surface, a die having a surface, and a fluidic channel between the surface of the die and the surface of the package substrate, wherein a top surface of the fluidic channel is defined by the surface of the die and a bottom surface of the fluidic channel is defined by the surface of the package substrate. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a surface; and an interposer having a fluidic channel between the surface of the die and the surface of the package substrate. | 2020-07-02 |
20200211928 | SEMICONDUCTOR PACKAGE WITH LIQUID METAL CONDUCTORS - A semiconductor package includes a lead frame, a semiconductor device, a liquid metal conductor, and an encapsulation material. The semiconductor device is affixed to the lead frame. The liquid metal conductor couples the semiconductor device to the lead frame. The encapsulation material encases the semiconductor device, the liquid metal conductor, and at least a portion of the lead frame. | 2020-07-02 |
20200211929 | DISPLAY PANEL AND TILED DISPLAY APPARATUS HAVING THE SAME - A display panel includes a display area, in which a plurality of pixels is arranged and a plurality of peripheral areas surrounding the display area. The display panel includes a first substrate, a second substrate disposed opposite to the first substrate, a first external signal line disposed on the first substrate in a first peripheral area of plurality of peripheral areas and connected to an external device, and a first through-hole terminal including a conductive material filled in a hole defined through the first substrate in an area in which the first external signal line is disposed. | 2020-07-02 |
20200211930 | Semiconductor Chip Set with Double-Sided Off-chip Bonding Structure - A semiconductor chip set with double-sided off-chip bonding structure in the disclosure comprises at least one first off-chip bonding structure formed above a first surface of the semiconductor chip set, and at least one second off-chip bonding structure formed above a second surface of the semiconductor chip set, wherein the first surface is opposite to the second surface and each of the first off-chip bonding structure and the second off-chip bonding structure is used for connecting to an electrical connecting point external to the semiconductor chip set through bonding wire, through-silicon via (TSV) or micro bump. | 2020-07-02 |
20200211931 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING INTERLAYER INSULATING FILMS HAVING DIFFERENT YOUNG'S MODULUS - A preferred aim of the invention is to provide technique for improving reliability of semiconductor devices when using a low-dielectric-constant film having a lower dielectric constant than a silicon oxide film to apart of an interlayer insulating film. More specifically, to achieve the preferred aim, an interlayer insulating film IL | 2020-07-02 |
20200211932 | INTERNALLY-SHIELDED MICROELECTRONIC PACKAGES AND METHODS FOR THE FABRICATION THEREOF - Internally-shielded microelectronic packages having increased resistances to electromagnetic cross-coupling are disclosed, as are methods for fabricating such microelectronic packages. In embodiments, the internally-shielded microelectronic package includes a substrate having a frontside and a longitudinal axis. A first microelectronic device is mounted to the frontside of the substrate, while a second microelectronic device is further mounted to the frontside of the substrate and spaced from the first microelectronic device along the longitudinal axis. An internal shield structure includes or consists of a shield wall, which is positioned between the first and second microelectronic devices as taken along the longitudinal axis. The internal shield structure is at least partially composed of a magnetically-permeable material, which decreases electromagnetic cross-coupling between the first and second microelectronic devices during operation of the internally-shielded microelectronic package. | 2020-07-02 |
20200211933 | LEADFRAME DIE PAD WITH PARTIALLY-ETCHED GROOVE BETWEEN THROUGH-HOLE SLOTS - A leadframe includes a die pad for mounting a semiconductor die with its top side facing up using a die attach resin material including a resin, the leadframe having leads or lead terminals beyond the die pad. The die pad includes slots including a first slot and at least a second slot on at least a first side of the die pad that penetrate a full thickness of the die pad. At least one non-penetrating groove is in the die pad for providing a fluid connection including between the first and second slots for providing a flow channel for guiding the resin when received by the grooves after bleeding out from under the semiconductor die to flow to at least one of the first slot and the second slot. | 2020-07-02 |
20200211934 | LEADFRAME FOR MULTICHIP DEVICES WITH THINNED DIE PAD PORTIONS - A leadframe for a multichip semiconductor package includes a first die pad and at least a second die pad both vertically offset at least 0.2 mm relative to leads or lead terminals that are positioned on at least 2 sides beyond the first die pad and the second die pad. At least one of the first and second die pads has a reduced thickness portion and a full thickness portion, and wherein the full thickness portion has a same thickness as a thickness of at least an outside portion the leads or the lead terminals. | 2020-07-02 |
20200211935 | SURFACE-MOUNT INTEGRATED CIRCUIT PACKAGE WITH COATED SURFACES FOR IMPROVED SOLDER CONNECTION - Methods are disclosed for forming flat no-leads packages (e.g., QFN packages) with soldering surfaces that are fully coated, e.g., by a tin immersion process, for improved solder connections of the packages to a PCB or other structure. The method includes forming a flat no-leads package structure including a leadframe terminal structure having an exposed top or bottom surface; forming a first coating of a first coating material (e.g., tin) on the exposed top or bottom surface; cutting through a full thickness of the leadframe terminal structure to define an exposed terminal sidewall surface; and forming a second coating of a second coating material (e.g., tin) over the full height of the exposed terminal sidewall surface. The coating (e.g., tin immersion coating) covering the full height of the leadframe terminal sidewall may enhance the flow of solder material, e.g., when soldering to a PCB, to provide an improved solder connection. | 2020-07-02 |
20200211936 | SURFACE-MOUNT INTEGRATED CIRCUIT PACKAGE WITH COATED SURFACES FOR IMPROVED SOLDER CONNECTION - Methods are disclosed for forming flat leads packages (e.g., QFP or SOT packages) having leads coated with a solder-enhancing material for improved solder mounting to a PCB or other structure. The method may include forming a flat leads package structure including an array of encapsulated IC structures formed on a common leadframe. An isolation cutting process may be performed to electrically isolate the IC structures from each other and define a plurality of leadframe leads extending from each IC structure. After the isolation cutting process, an immersion coating process is performed to coat exposed surfaces of the leadframe leads, including the full surface area of a distal end of each leadframe lead. The coating (e.g., tin coating) covering the distal ends of the leadframe leads may enhance the flow of solder material, e.g., when soldering to a PCB, to provide an improved solder connection. | 2020-07-02 |
20200211937 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element, leads, and an encapsulation resin covering a portion of each of the leads and the semiconductor element. Each of the leads includes an external connection portion projecting from a side surface of the encapsulation resin. The external connection portion of at least one of the leads has opposite ends in a width-wise direction that extends along the side surface of the encapsulation resin. The external connection portion includes two recesses arranged toward a center in the width-wise direction from the opposite ends. The two recesses extend from a distal surface toward the encapsulation resin. The opposite ends in the width-wise direction define an end connection part. The external connection portion includes a part between the two recesses defining a center connection part. | 2020-07-02 |
20200211938 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposite to the active surface, a heat-dissipating member, including graphite, which is disposed on the inactive surface of the semiconductor chip; an encapsulant sealing at least a portion of each of the semiconductor chip and the heat-dissipating member, and a connection structure, which includes a redistribution layer electrically connected to the connection pad, disposed on the active surface of the semiconductor chip, and at least a side surface of the heat-dissipating member is coplanar with a side surface of the semiconductor chip. | 2020-07-02 |
20200211939 | PACKAGED ELECTRONIC DEVICE WITH SUSPENDED MAGNETIC SUBASSEMBLY - A packaged electronic device includes a die pad directly connected to a first set of conductive leads of a leadframe structure, a semiconductor die attached to the conductive die pad, a conductive support structure directly connected to a second set of conductive leads, and spaced apart from all other conductive structures of the leadframe structure. A magnetic assembly is attached to the conductive support structure, and a molded package structure that encloses the conductive die pad, the conductive support structure, the semiconductor die, the magnetic assembly and portions of the conductive leads, the molded package structure including a top side, and an opposite bottom side, wherein the lamination structure is centered between the top and bottom sides. | 2020-07-02 |
20200211940 | HIGH VOLTAGE SEMICONDUCTOR DEVICE LEAD FRAME AND METHOD OF FABRICATION - An apparatus includes a first die attach pad and a second die attach pad. A first die is attached to the first die attach pad and a second die is attached to the second die attach pad. The first die attach pad and the second die attach pad are separated by a gap. A first edge of the first die attach pad adjacent to the gap is thinner than a second edge of the first die attach pad. The first edge of the first die attach pad is opposite the second edge of the first die attach pad. A first edge of the second die attach pad adjacent to the gap is thinner than a second edge of the second die attach pad. The first edge of the second die attach pad is opposite the second edge of the second die attach pad. | 2020-07-02 |