27th week of 2015 patent applcation highlights part 61 |
Patent application number | Title | Published |
20150187810 | DISPLAY DEVICE - A display device including a first substrate. The first substrate including an active region and a dummy region formed in an outer edge of the active region, the active region including a plurality of pixel regions and being configured to implement an actual image, the dummy region including a gate in panel (GIP) circuit, control signal lines, a ground, and common lines. The GIP circuit is overlapped by at least a part of the control signal lines, the ground, and the common lines with an insulating layer interposed therebetween. The display device further includes a thin film transistor (TFT) for a shift register is provided in each of a plurality of stages of the GIP circuit; and a source contact hole and a gate contact hole of each TFT for the shift registers, the source contact hole and the gate contact hole being formed along a corresponding control signal line. | 2015-07-02 |
20150187811 | THIN FILM TRANSISTOR ARRAY PANEL - A thin film transistor array panel includes an insulation substrate; a gate line and a first electrode on the insulation substrate; a gate insulating layer on the gate line and the first electrode; a data line on the gate insulating layer; a passivation layer on the gate insulating layer and the data line; and a second electrode on the passivation layer. Relative permittivity (ε) of the gate insulating layer is more than about 15, and a thickness of the gate insulating layer is about 2000 angstroms. | 2015-07-02 |
20150187812 | SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND ELECTRONIC APPLIANCE - In case the size of the transistor is enlarged, power consumption of the transistor is increased. Thus, the present invention provides a display device capable of preventing a current from flowing to a display element in signal writing operation without varying potentials of power source lines for supplying a current to the display element per row. In setting a gate-source voltage of a transistor by applying a predetermined current to the transistor, a potential of a gate terminal of the transistor is adjusted so as to prevent a current from flowing to a load connected to a source terminal of the transistor. Therefore, a potential of a wire connected to the gate terminal of the transistor is differentiated from a potential of a wire connected to a drain terminal of the transistor. | 2015-07-02 |
20150187813 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor array panel is disclosed. The thin film transistor array panel may include a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, a data wiring layer disposed on the substrate and including a data line crossing the gate line, a source electrode connected to the data line and a drain electrode facing the source electrode, a polymer layer covering the source electrode and the drain electrode, and a passivation layer disposed on the polymer layer. The data wiring layer may include copper or a copper alloy and the polymer layer may include fluorocarbon. | 2015-07-02 |
20150187814 | SEMICONDUCTOR DEVICE - A semiconductor device that is suitable for miniaturization is provided. A semiconductor device including a first element, a first insulator over the first element, a first barrier film over the first insulator, a first conductor over the first barrier film, a second barrier film over the first conductor, a second insulator over the second barrier film, and a semiconductor over the second insulator is provided. The first conductor is surrounded by the first barrier film and the second barrier film. | 2015-07-02 |
20150187815 | MULTI-FIN FINFETS WITH MERGED-FIN SOURCE/DRAINS AND REPLACEMENT GATES - A semiconductor structure including semiconductor fins, a gate over a middle portion of the semiconductor fins, and faceted semiconductor regions outside of the gate separated from gaps may be formed. The semiconductor structure may be formed by forming fins on a semiconductor substrate where each fin has a pair of sidewalls aligned parallel to the length of the fin, growing dummy semiconductor regions on the sidewalls of the fins, forming a sacrificial gate that covers a center portion of the fins and the dummy semiconductor regions, removing portions of the dummy semiconductor regions not covered by the sacrificial gate, and growing faceted semiconductor regions on the sidewalls of the portions of the fins not covered by the sacrificial gate. The faceted semiconductor regions may intersect to form gaps between the faceted semiconductor regions and the gate. | 2015-07-02 |
20150187816 | FINFET WITH REDUCED CAPACITANCE - An finFET structure including a plurality of fins etched from a semiconductor substrate, a plurality of gates above and perpendicular to the plurality of fins, each comprising a pair of spacers on opposing sides of the gates, and a gap fill material above the semiconductor substrate, below the gate, and between the plurality of fins, wherein the gate separates the gap fill material from each of the plurality of fins. | 2015-07-02 |
20150187817 | LIQUID CRYSTAL DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A liquid crystal display device includes a gate electrode; a gate insulating layer on the gate electrode; an active layer on the gate insulating layer corresponding to the gate electrode; source and drain electrodes on the active layer; a first passivation layer on the source and drain electrodes; a common electrode on the first passivation layer; a second passivation layer on the common electrode, covering the common electrode, and having a separate region from the first passivation layer at a thickness of the common electrode; a pixel electrode on the second passivation layer and connected to the drain electrode through a drain contact hole; and a common line at a same layer as the pixel electrode and connected to the common electrode. | 2015-07-02 |
20150187818 | LIGHT-EMITTING DEVICE - A light-emitting device capable of suppressing variation in luminance among pixels is provided. A light-emitting device includes a pixel and first and second circuits. The first circuit has a function of generating a signal including a value of current extracted from the pixel. The second circuit has a function of correcting an image signal by the signal. The pixel includes at least a light-emitting element and first and second transistors. The first transistor has a function of controlling supply of the current to the light-emitting element by the image signal. The second transistor has a function of controlling extraction of the current from the pixel. A semiconductor film of each of the first and second transistors includes a first semiconductor region overlapping with a gate, a second semiconductor region in contact with a source or a drain, and a third semiconductor region between the first and second semiconductor regions. | 2015-07-02 |
20150187819 | SEMICONDUCTOR DEVICE - A semiconductor device having a high aperture ratio and including a capacitor capable of increasing the charge capacity is provided. A semiconductor device includes a transistor over a substrate, a first light-transmitting conductive film over the substrate, an oxide insulating film covering the transistor and having an opening over the first light-transmitting conductive film, a nitride insulating film over the oxide insulating film and in contact with the first light-transmitting conductive film in the opening, a second light-transmitting conductive film connected to the transistor and having a depressed portion in the opening, and an organic resin film with which the depressed portion of the second light-transmitting conductive film is filled. | 2015-07-02 |
20150187820 | ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE - An array substrate is disclosed. The array substrate includes a non-display region surrounding a display region. The array substrate also includes gate lines in the display region, and a gate drive circuit and a bus electrically insulated from the gate lines and a gate drive circuit in the non-display region. The gate lines extend into the non-display region and are electrically connected to the gate drive circuit, and each of the gate lines crosses the bus in a first overlap region. The array substrate also includes auxiliary electrode line segments between the bus and the display region. The auxiliary electrode line segments are electrically insulated from one another and from the gate lines, and the auxiliary electrode line segments are disposed in either of a same conductive layer as the bus, or a layer between the conductive layer of the bus and a conductive layer of the gate lines are disposed. | 2015-07-02 |
20150187821 | THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - To prevent light leakage and compensate for a step between a display region and a non-display region, a thin film transistor array substrate can include a base substrate having a display region and a non-display region, a plurality of pixel regions defined by gate lines and data lines crossing each other in the display region of the base substrate, a common line corresponding to between adjacent pixel regions, a thin film transistor and a color filter in each pixel region, a first dummy color filter between the adjacent pixel regions, a second dummy color filter in the non-display region on the base substrate, the second dummy color filter being provided at an upper surface thereof with at least one recess, and a protective film over the entire surface of the base substrate to cover the first and second dummy color filters and fill the recess. | 2015-07-02 |
20150187822 | ELECTRONIC DEVICE AND ELECTRONIC APPARATUS - An EL display having high operating performance and reliability is provided. LDD regions | 2015-07-02 |
20150187823 | SEMICONDUCTOR DEVICE - A semiconductor device that is suitable for miniaturization is provided. Alternatively, a highly reliable semiconductor device is provided. A semiconductor device including a capacitor and a transistor is provided. In the semiconductor device, the transistor includes a semiconductor layer, the semiconductor layer is positioned over the capacitor, and the capacitor includes a first electrode that is electrically connected to the transistor. | 2015-07-02 |
20150187824 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device having a first transistor and a second transistor over the first transistor. The first transistor includes a first semiconductor, and the second transistor includes an oxide semiconductor that is different from the first semiconductor. A gate of the first transistor is electrically connected to a source or drain electrode of the second transistor. The second transistor has a semiconductor layer including the oxide semiconductor over the source and drain electrodes and a gate electrode over the semiconductor layer with an insulating layer therebetween. | 2015-07-02 |
20150187825 | Method of Manufacturing Array Substrate of LCD - A method for manufacturing an array substrate includes: forming a gate metal film on an bottom substrate, coating the gate metal film with photoresist, exposure imaging and etching the photoresist by a first monotone mask to form patterns with gate scan lines and a gate, and eliminating corresponding photoresist by ashing; continuously depositing a gate insulating layer film, an active layer film and a source-drain metal film on the bottom substrate with the patterns, coating the source-drain metal film with photoresist, exposure imaging the photoresist by a gray-scale mask, and photoresist ashing and etching to form a source, a drain, a channel, and through holes connecting a common electrode lead wire connection area to a gate lead wire connection area; forming a passivation layer on the bottom substrate with the patterns by photoetching process; forming a pixel electrode on the bottom substrate with the patterns by photoetching process. By using the present invention method, it reduces cost of manufacturing the array substrate and improves performance of the array substrate. | 2015-07-02 |
20150187826 | SOLID STATE IMAGING DEVICE, METHOD OF MANUFACTURING SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS - The present technique aims to provide a solid-state imaging device that reduces shading and color mixing between pixels. The present invention also provides a method of manufacturing the solid-state imaging device. The present technique further relates to a solid-state imaging device that enables provision of an electronic apparatus that uses the solid-state imaging device, a method of manufacturing the solid-state imaging device, and an electronic apparatus. | 2015-07-02 |
20150187827 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes an epitaxial layer including a first surface and a silicon layer disposed on the first surface and including a second surface opposite to the first surface, wherein the silicon layer includes a plurality of pillars on the second surface, a portion of the plurality of pillars on a predetermined portion of the second surface are in substantially same dimension, each of the plurality of pillars on the predetermined portion of the second surface stands substantially orthogonal to the second surface, the plurality of pillars are configured for absorbing an electromagnetic radiation of a predetermined wavelength projected from the epitaxial layer and generating an electrical energy in response to the absorption of the electromagnetic radiation. | 2015-07-02 |
20150187828 | OPTICAL AND INFRARED IMAGING SYSTEM - Imaging systems may include an image sensor and a microelectromechanical systems array. The microelectromechanical systems array may be mounted over the image sensor. The system may include an infrared lens that focuses infrared light onto a first surface of the microelectromechanical systems array and a visible light source that illuminates an opposing second surface of the microelectromechanical systems array. The image sensor may capture images of the opposing second surface of the microelectromechanical systems array. The system may include processing circuitry that generates infrared images of a scene using the captured images of the microelectromechanical systems array. Microelectromechanical systems elements in the microelectromechanical systems array may change position or shape in response to infrared light that is absorbed by the microelectromechanical systems elements. Each microelectromechanical systems element may include infrared absorbing material on a metal layer. The system may include optical elements that focus visible light onto the image sensor. | 2015-07-02 |
20150187829 | OPTOELECTRONIC PHOTODETECTOR (VARIANTS) - A optoelectronic photo sensor to obtain single mosaic digital photographic images. Photo sensor is designed as a plurality of identical lenses having rows of staggered identical matrices arranged on a common focal surface with the gaps between adjacent matrices not exceeding the length of the effective number of pixels oriented along the row. Said arrangement provides a single large survey field from a plurality of individual matrices. Said design contemplates the use of several small individual lenses instead of one large and expensive lens, as well as many small matrices instead of one large and expensive matrix. The lenses are arranged at an angle to each other with a strictly defined dependence on the focal distance and the length of the gap between matrices in the row, which ensures continuous imaging by individual matrices over the surface surveyed with preset overlapping for subsequent cross-linking of images into one single film. | 2015-07-02 |
20150187830 | PHOTOSENSITIVE UNIT, ARRAY SUBSTRATE OF DISPLAY PANEL AND MANUFACTURING METHOD THEREOF - The present disclosure relates to a photosensitive unit, an array substrate of a display panel and a manufacturing method thereof. In the photosensitive unit, a PIN structure is adopted for photoelectric conversion, and the generated photocurrent has low probability of dramatic change due to the fluctuation of a working voltage, and thus the accuracy is relatively high. In addition, because the photosensitive unit preferably has the PIN structure arranged longitudinally, when the photosensitive unit is configured on the array substrate of the display panel, the sizes of the length, width and height of the intrinsic region can be designed in a more flexible manner. Therefore, the photosensitive region of the photosensitive unit can be enlarged to a maximum extent, and the photoelectric conversion efficiency can be improved. Consequently, the array substrate of the display panel including the photosensitive unit and the display panel have better ambient light sensing capability, high sensitivity and high reliability. The present disclosure is applicable to various display panels. | 2015-07-02 |
20150187831 | SOLID STATE IMAGING DEVICE - According to one embodiment, a solid state imaging device includes a semiconductor substrate, a photodiode formed in the semiconductor substrate, a first insulating film having a first refractive index, and disposed on a surface of the semiconductor substrate, a second insulating film having a second refractive index higher than the first refractive index, and formed on the first insulating film above the photodiode, a third insulating film having a third refractive index higher than the second refractive index, and formed on the second insulating film above the photodiode, and a micro lens provided above the photodiode. | 2015-07-02 |
20150187832 | IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating image sensor is disclosed. The method includes the steps of: providing a substrate having a dielectric layer thereon; forming a plurality of filtering layers on the dielectric layer; patterning the filtering layers for forming a first pass filter; coating a material layer on the dielectric layer such that a top surface of the material layer is even with a top surface of the first pass filter; and forming a plurality of color filters on the first pass filter. | 2015-07-02 |
20150187833 | IMAGE SENSOR INCLUDING MULTIPLE LENSES AND METHOD OF MANUFACTURE THEREOF - A method includes fabricating an image sensing element in a substrate. A plurality of inter-metal dielectric (IMD) layers are formed over the substrate. Each IMD layer includes a metal layer and a dielectric layer. A planar top surface of a top IMD layer of the plurality of IMD layers is planarized. A portion of the top IMD layer is then removed to transform a region of the planar top surface to a curved recess. A lens is formed on the top IMD layer and in the curved recess. A color filter layer is disposed over the lens and the image sensing element. | 2015-07-02 |
20150187834 | Ridge Structure for Back Side Illuminated Image Sensor - Provided is an image sensor device. The image sensor device includes a substrate having a front side and a back side. The image sensor includes first and second radiation-detection devices that are disposed in the substrate. The first and second radiation-detection devices are operable to detect radiation waves that enter the substrate through the back side. The image sensor also includes an anti-reflective coating (ARC) layer. The ARC layer is disposed over the back side of the substrate. The ARC layer has first and second ridges that are disposed over the first and second radiation-detection devices, respectively. The first and second ridges each have a first refractive index value. The first and second ridges are separated by a substance having a second refractive index value that is less than the first refractive index value. | 2015-07-02 |
20150187835 | TRANSISTOR, IMAGE SENSOR INCLUDING THE SAME AND METHOD FOR FABRICATING THE SAME - A transistor includes a substrate and a gate insulation layer formed on the substrate having a negative charge storage layer with a fixed negative charge to induce a buried channel in the substrate. A gate electrode is formed on the gate insulation layer. | 2015-07-02 |
20150187836 | IMAGE SENSOR DEVICE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a transfer gate transistor of an image sensor device is disclosed. The transistor includes a substrate, a gate oxide layer on the substrate and a gate electrode portion on the gate oxide layer. The gate electrode portion has a trench or an insulating layer used for accurately defining a first region and a second region in the gate electrode portion, wherein the first region has a first conductivity type, and the second region has a second conductivity type or is an undoped region. | 2015-07-02 |
20150187837 | METHOD OF MANUFACTURING PHOTODIODE DETECTORS - A radiation detector assembly including an organic photodetector that generate charge in response to an incident radiation, a thin film transistor array including a plurality of pixels. The plurality of pixels may produce electric signals corresponding to the charge generated by the organic photodetector. The radiation detector assembly also includes a spacer disposed on the thin film transistor array. The spacer surrounds one or more pixels and may confine the organic photodetector within the surrounded one or more pixels such that the surrounded one or more pixels are electrically isolated from a neighboring pixel. | 2015-07-02 |
20150187838 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A light emitting device includes: a base member; and a plurality of light emitting elements mounted on the base member. The plurality of light emitting elements includes: at least one first light emitting element having a side surface uncovered by a light reflective member; and at least one second light emitting element having a side surface covered by the light reflective member. | 2015-07-02 |
20150187839 | LIGHT-EMITTING PART AND LIGHT-EMITTING APPARATUS, AND PRODUCTION METHODS THEREFOR - The present invention provides a light-emitting part and a light-emitting apparatus exhibiting high brightness per unit area, and simplified production methods therefor. The light-emitting unit comprises a single base substrate, and a plurality of light-emitting devices thereon. The light-emitting unit includes a serial connection body which connects at least a part of the light-emitting devices in series. The serial connection body comprises light-emitting devices which make a current path, a light-emitting device which does not make a current path, and a connection member which electrically connects an n-electrode and a p-electrode of the light-emitting devices. | 2015-07-02 |
20150187840 | SYSTEMS AND METHODS FOR FABRICATION OF SUPERCONDUCTING INTEGRATED CIRCUITS - Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector. | 2015-07-02 |
20150187841 | Method of forming current-programmable inline resistor - Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A ReRAM cell includes an embedded resistor and a variable resistance layer that are interconnected in series by, for example, stacking the two. The embedded resistor prevents excessive electrical currents through the variable resistance layer thereby preventing its over-programming. The embedded resistor is configured to maintain a constant resistance during the operation of the ReRAM cell, such as applying switching currents and changing the resistance of the variable resistance layer. Specifically, the embedded resistor may be electrically broken down during fabrication of the ReRAM cell to improve the subsequent stability of the embedded resistance to electrical fields during operation of the ReRAM cell. The embedded resistor may be made from materials that allow this initial breakdown and to avoid future breakdowns, such metal silicon nitrides, metal aluminum nitrides, and metal boron nitrides. | 2015-07-02 |
20150187842 | NONVOLATILE MEMORY DEVICES - A nonvolatile memory device includes a plurality of first electrode lines including upper portions that have convex top surfaces. A plurality of second electrode lines are disposed over the plurality of first electrode lines to cross the plurality of first electrode lines, and a plurality of memory patterns are disposed between the plurality of first electrode lines and the plurality of second electrode lines. | 2015-07-02 |
20150187843 | SOLID-STATE IMAGE PICKUP DEVICE AND ELECTRONIC APPARATUS - A solid-state image pickup device includes at least two stacked first and second photoelectric conversion sections in each of a plurality of pixels. Sensitivity of the first photoelectric conversion section to a light incident angle is equivalent to sensitivity of the second photoelectric conversion section to a light incident angle, for each of the pixels. | 2015-07-02 |
20150187844 | UNIT PIXEL OF STACKED IMAGE SENSOR AND STACKED IMAGE SENSOR INCLUDING THE SAME - A unit pixel of a stacked image sensor includes a stacked photoelectric conversion unit, a first and second signal generating units. The stacked photoelectric conversion unit includes first, second and third photoelectric conversion elements that are stacked on each other. The first, second and third photoelectric conversion elements collect first, second and third photocharges based on first, second and third components of incident light. The first signal generating unit generates a first pixel signal based on the first photocharges and a first signal node and generates a second pixel signal based on the second photocharges and the first signal node. The second signal generating unit generates a third pixel signal based on the third photocharges and a second signal node. At least a portion of the second signal generating unit is shared by the first signal generating unit. | 2015-07-02 |
20150187845 | ORGANIC LIGHT-EMITTING DIODE (OLED) DISPLAY - An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a display substrate including first and second surfaces opposing each other. The OLED display further includes a touch sensing layer formed over the encapsulation substrate and configured to sense a touch input, a display flexible printed circuit board electrically attached to the second surface of the display substrate, and a touch flexible printed circuit board electrically connected to the touch sensing layer and attached to the second surface of the display substrate. An impact absorbing layer is formed over the second surface of the display substrate and attaches the display flexible printed circuit board and the touch flexible printed circuit board to the second surface of the display substrate. The impact absorbing layer includes a metal layer electrically connected to the display flexible printed circuit board and the touch flexible printed circuit board. | 2015-07-02 |
20150187846 | LIGHT EMITTING ELEMENT - A light emitting element is provided, including a first electrode layer, a second electrode layer, and an organic light emitting layer sandwiched between the first electrode layer and the second electrode layer. The organic light emitting layer is patterned to include a plurality of light emitting blocks with different densities. In an embodiment, the light emitting blocks are divided into a plurality of light emitting block groups that are arranged in an alternate manner. In another embodiment, a light emitting element includes a first electrode layer, a first organic light emitting layer, a charge generating layer, a second organic light emitting layer, and a second electrode layer sequentially stacked on one another. The first and second organic light emitting layer are patterned to form a plurality of first and second light emitting blocks with different densities, respectively. Thus, the light emitting element generates full-color, gray-scale, three-dimensional, or dynamic images. | 2015-07-02 |
20150187847 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An OLED device according to one example includes a substrate defined into a plurality of sub-pixel regions which includes red, green and blue sub-pixel regions; a first electrode formed on the substrate; an organic emission layer formed on the first electrode; a second electrode formed on the organic emission layer; and a capping layer formed on the second electrode. The capping layer is formed to contain an optical adjustment material which rises in proportion to a wavelength of incident light. | 2015-07-02 |
20150187848 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device including a first electrode defined into red, green and blue sub-pixel regions; a hole injection layer disposed on the first electrode; a first hole transport layer disposed on the hole injection layer; first, second and third organic emission layers arranged on the first hole transport layer opposite to the respective red, green and blue sub-pixel regions; an electron transport layer disposed on the first, second and third organic emission layers; and a second electrode disposed on the electron transport layer. The second organic emission layer opposite to the green sub-pixel region is formed in a stacked structure including first and second hole host layers and a dopant host layer. | 2015-07-02 |
20150187849 | METHODS OF MANUFACTURING FLEXIBLE SUBSTRATES, FLEXIBLE DISPLAY DEVICES AND METHODS OF MANUFACTURING FLEXIBLE DISPLAY DEVICES - In a method of manufacturing a flexible substrate, a preliminary sacrificial layer that includes polyimide is formed on a carrier substrate. The preliminary sacrificial layer is transformed into a sacrificial layer that includes a modified polyimide. A base substrate layer that includes polyimide is formed on the sacrificial layer. A device structure is formed on the base substrate layer. A combination of the base substrate layer and the device structure is separated from the carrier substrate. | 2015-07-02 |
20150187850 | ORGANIC LIGHT EMITTING DIODE AND ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE INCLUDING THE SAME - Discussed is an organic emitting diode including an anode; a cathode facing the anode; a first emitting material layer between the anode and the cathode and including a first host material, the first host material having a first triplet energy; and a hole transporting layer between the first emitting material layer and the anode, a material of the hole transporting layer having a second triplet energy being larger than the first triplet energy. | 2015-07-02 |
20150187851 | ORGANIC LIGHT-EMITTING DIODE DISPLAY AND METHOD OF FABRICATING THE SAME - An organic light-emitting diode display can include an improved aperture ratio by configuring a circuit pattern between neighboring subpixels in a symmetrical fashion such that the subpixels share signal lines. Each pixel of the organic light-emitting diode display is formed in a symmetrical fashion with respect to one contact area, the number of reference connecting patterns can be reduced and therefore the area occupied by an opening area for each pixel can be made wider, thus leading to an improved aperture ratio. | 2015-07-02 |
20150187852 | Display Device - To improve image quality of a full-color organic EL display panel. A partition has a stacked structure formed using different materials. A lower partition has a curved shape, and an upper partition has a flat top surface. An angle formed between a plane surface connecting a lower end of a side surface with an upper end of the side surface of the upper partition and the top surface of the upper partition is less than or equal to 90°. The height of the partition is controlled to be greater than or equal to 0.5 μm and less than or equal to 1.3 μm. With such a structure, a large color organic EL display panel achieves high-definition display. | 2015-07-02 |
20150187853 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A display device includes an organic light emitting element and a capacitor connected to the a thin film transistor. The transistor includes a semiconductor layer uniformly disposed on an entire area of a substrate. The transistor also includes a first insulating layer on the semiconductor layer, a gate electrode pattern on the first insulating layer, a gate guard on a same layer as and surrounding the gate electrode pattern, a second insulating layer on the gate electrode pattern and the gate guard, and source and drain electrodes passing through the first insulating layer and the second insulating layer and connected to the semiconductor layer. The gate electrode pattern includes a plurality of gate center portions and a gate peripheral portion having a closed-loop shape extending from the gate center portions. | 2015-07-02 |
20150187854 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND FABRICATING METHOD THEREOF - Disclosed is an organic light emitting display device. The organic light emitting display device includes: at least one transistor arranged in a transistor region of the substrate and configured to include a channel layer, an insulation film, a gate electrode, a source electrode and a drain electrode; a storage capacitor arranged in the storage capacitor region, the pixel region and the pad region of the substrate and configured to include a first storage electrode, an insulation film pattern and a second storage electrode; a color filter arranged over the storage capacitor opposite to the pixel region; and an organic light emitting diode arranged on the color filter and configured to include a first electrode, an organic emission layer and a second electrode. | 2015-07-02 |
20150187855 | SEMICONDUCTOR DEVICE - A display device that includes a first flexible substrate, a first bonding layer over the first flexible substrate, a first insulating film over the first bonding layer, a first element layer over the first insulating film, a second element layer over the first element layer, a second insulating film over the second element layer, a second bonding layer over the second insulating film, and a second flexible substrate over the second bonding layer is provided. The first element layer includes a pixel portion and a circuit portion. The pixel portion includes a display element and a first transistor, and the circuit portion includes a second transistor. The second element layer includes a coloring layer and a light-blocking layer. | 2015-07-02 |
20150187856 | Organic Light Emitting Display Device and Method for Manufacturing the Same - Provided are an organic light emitting display (OLED) device and method for manufacturing the same. The OLED device includes: a plurality of gate lines in one direction on a substrate, a plurality of light-shielding patterns corresponding to at least parts of peripheries of the respective pixel regions on the substrate, the light-shielding patterns spaced apart from the gate lines, at least one insulating film covering the substrate, the gate lines, and the light-shielding patterns, a plurality of data lines in another direction crossing the gate lines on the insulating film to define the pixel areas, a passivation film covering the insulating film and the data lines, a plurality of color filters in the pixel areas on the passivation film, an over-coating film evenly covering the passivation film and covering the color filters, and a plurality of organic light emitting elements in the pixel areas on the over-coating film. | 2015-07-02 |
20150187857 | DISPLAY UNIT AND ELECTRONIC APPARATUS - There are provided a display unit and an electronic apparatus that are capable of preventing color mixture in adjacent color pixels, and improving color reproducibility and chromaticity viewing angle. The display unit includes: a drive substrate having a plurality of pixels with a partition therebetween; and a first light shielding film provided on the partition. | 2015-07-02 |
20150187858 | OLED DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME AND DISPLAY APPARATUS - An Organic Light Emitting Diode (OLED) display panel is disclosed. The display panel includes a substrate, a plurality of power lines disposed on the substrate, and a reflection layer disposed on the power lines, where the reflection layer is electrically connected with the power lines. The display panel also includes an anode disposed on the reflection layer, an optical modulation layer disposed between the reflection layer and the anode, a cathode disposed on the anode, and an organic emitting device layer disposed between the anode and the cathode, where the reflection layer is insulated from the anode, and the OLED display panel is configured to transmit light from a side of the reflection layer away from the substrate. | 2015-07-02 |
20150187859 | DISPLAY DEVICE - A display device comprises a substrate, a first pixel on the substrate, the first pixel comprising a first subpixel, a second subpixel, and a third subpixel, a second pixel on the substrate, the second pixel comprising a fourth subpixel, a fifth subpixel, and a sixth subpixel, first, second, third and fourth power supply lines extending in one direction and respectively coupled to the first, third, fifth, and sixth subpixels, and fifth and sixth power supply lines crossing the first, second, third, and fourth power supply lines and respectively coupled to the fourth and second subpixels. | 2015-07-02 |
20150187860 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed is an organic light emitting display device. The organic light emitting display device includes a switching thin film transistor (TFT) that includes a lower gate, a source, and a drain formed on a substrate and on the same layer, a first gate insulating layer formed to cover the lower gate, the source, and the drain, an active layer formed on the first gate insulating layer, a conductive line formed to contact the source and the drain, a second gate insulating layer formed on the active layer, and an upper gate formed on the second gate insulating layer. The lower gate of the switching TFT is a light shield that blocks light from being irradiated onto the active layer. | 2015-07-02 |
20150187861 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE - An organic light emitting diode display device in accordance with various embodiments may include: a pixel region defined by a gate line and a data line and having an emitting area and a transparent area; at least one driving element disposed in the emitting area; a power line overlapping the emitting area and connected to the at least one driving element; a first capacitor electrode disposed in the emitting area and overlapping the power line, wherein the power line and the first capacitor electrode form a first storage capacitor; and a second capacitor electrode disposed in the emitting area and overlapping the first capacitor electrode, wherein the first capacitor electrode and the second capacitor electrode form a second storage capacitor. | 2015-07-02 |
20150187862 | Top Emission Type Organic Light Emitting Display Device and Method of Manufacturing the Same - A top-emission type light emitting display device and a corresponding manufacturing method are described. A device substrate has display area and non-display areas. In the display area are formed: a thin film transistor including an active layer, a gate electrode, a source electrode, and a drain electrode; and an organic light emitting element including an anode, an organic light emitting layer, and a cathode. In the non-display area a second voltage supply wire is formed on, and overlaps with, a first voltage supply wire. An anti-burning layer is disposed between the first voltage and the second voltage supply wires. The anti-burning layer is an insulation layer with the same thickness as a space sufficient to suppress burning of the wires in the overlapping region between the first voltage supply wire and the second voltage supply wire, thus improving reliability and manufacturing yield of the device. | 2015-07-02 |
20150187863 | INTEGRATED CIRCUITS INCLUDING A RESISTANCE ELEMENT AND GATE-LAST TECHNIQUES FOR FORMING THE INTEGRATED CIRCUITS - Integrated circuits with a resistance element and gate-last techniques for forming the integrated circuits are provided. An exemplary technique includes providing a semiconductor substrate that includes a shallow trench isolation (STI) structure disposed therein. A dummy gate electrode structure is patterned overlying semiconductor material of the semiconductor substrate, and a resistor structure is patterned overlying the STI structure. The dummy gate electrode structure and the resistor structure include a dummy layer overlying a metal capping layer. A gate dielectric layer underlies the metal capping layer. An interlayer dielectric layer is formed overlying the semiconductor substrate and the STI structure. End terminal recesses for the resistance element are concurrently patterned through the dummy layer of the resistor structure along with removing the dummy layer of the dummy gate electrode structure to form a gate electrode recess. Metal gate material is deposited in the end terminal recesses and a gate electrode recess. | 2015-07-02 |
20150187864 | METAL-INSULATOR-METAL (MIM) CAPACITOR TECHNIQUES - Some embodiments relate to a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes a capacitor bottom metal (CBM) electrode, a high-k dielectric layer arranged over the CBM electrode, and a capacitor top metal (CTM) electrode arranged over the high-k dielectric layer. A capping layer is arranged over the CTM electrode. A lower surface of the capping layer and an upper surface of the CTM electrode meet at an interface. Protective sidewalls are adjacent to outer sidewalls of the CTM electrode. The protective sidewalls have upper surfaces at least substantially aligned to the interface at which the upper surface of the CTM electrode meets the lower surface of the capping layer. | 2015-07-02 |
20150187865 | Capacitors Including Inner and Outer Electrodes - Provided are capacitor stacks for use in integrated circuits and methods of fabricating these stacks. A capacitor stack includes a dielectric layer and one or two inner electrode layers, such as a positive inner electrode layer and a negative inner electrode layer. The inner electrode layers directly interface the dielectric layer. The stack may also include outer electrode layers. The inner electrode layers are either chemically stable or weakly chemically unstable, while in contact with the dielectric layer based on the respective phase diagrams. Furthermore, the electron affinity of the positive inner electrode layer may be less than the electron affinity of the dielectric layer. The sum of the electron affinity and bandgap of the negative inner electrode layer may be less than that of the dielectric layer. In some embodiments, inner electrode layers are formed from heavily doped semiconducting materials, such as gallium arsenide or gallium aluminum arsenide. | 2015-07-02 |
20150187866 | Metal-Insulator-Metal (MIM) Capacitor Within Topmost Thick Inter-Metal Dielectric Layers - Embodiments of MIM capacitors may be embedded into a thick IMD layer with enough thickness (e.g., 10 KŘ30 KÅ) to get high capacitance, which may be on top of a thinner IMD layer. MIM capacitors may be formed among three adjacent metal layers which have two thick IMD layers separating the three adjacent metal layers. Materials such as TaN or TiN are used as bottom/top electrodes & Cu barrier. The metal layer above the thick IMD layer may act as the top electrode connection. The metal layer under the thick IMD layer may act as the bottom electrode connection. The capacitor may be of different shapes such as cylindrical shape, or a concave shape. Many kinds of materials (Si | 2015-07-02 |
20150187867 | INDEPENDENT GATE VERTICAL FINFET STRUCTURE - A semiconductor device includes a substrate extending in a first direction to define a substrate length and a second direction perpendicular to the first direction to define a substrate width. A first semiconductor fin is formed on an upper surface of the substrate. The first semiconductor fin extends along the second direction at a first distance to define a first fin width. A first gate channel is formed between a first source/drain junction formed in the substrate and a second source/drain junction formed in the first semiconductor fin. A first gate stack is formed on sidewalls of the first gate channel. A first spacer is interposed between the first gate stack and the first source/drain junction. | 2015-07-02 |
20150187868 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device may include: an active region in which a current flows through a channel formed when the device being turned on; a termination region disposed around the active region; a first semiconductor region of a first conductive type disposed in the termination region in a direction from the active region to the termination region; and a second semiconductor region of a second conductive type disposed in the termination region in the direction from the active region to the termination region, the first semiconductor region and the second semiconductor region being disposed alternately. | 2015-07-02 |
20150187869 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device may include: a first conductivity-type first semiconductor region; a resurf region disposed in the first semiconductor region and including first conductivity-type second semiconductor regions and second conductivity-type third semiconductor regions alternately disposed in a width direction; a first conductivity-type first cover region disposed in the first semiconductor region, disposed to be contiguous with an upper surface of the resurf region, and having an impurity concentration higher than that of the first semiconductor region; a second conductivity-type fourth semiconductor region disposed above the first semiconductor region; a first conductivity-type fifth semiconductor region disposed on an inner side of an upper portion of the fourth semiconductor region; and a trench gate disposed to penetrate from the fifth semiconductor region to a portion of an upper portion of the first semiconductor region and including a gate insulating layer and a conductive material. | 2015-07-02 |
20150187870 | SEMICONDUCTOR DEVICE - In a semiconductor device, an edge termination region which surrounds an active region includes an electric field reduction mechanism including guard rings, first field plates which come into contact with the guard rings, and second field plates which are provided on the first field plates, with an interlayer insulating film interposed therebetween. The second field plate is thicker than the first field plate. A gap between the second field plates is greater than a gap between the first field plates. A barrier metal film is provided between the second field plate and the interlayer insulating film so as come into conductive contact with the second field plate. A gap between the barrier metal films is equal to the gap between the first field plates. | 2015-07-02 |
20150187871 | Silicon Carbide Device and a Method for Manufacturing a Silicon Carbide Device - A silicon carbide device includes an epitaxial silicon carbide layer including a first conductivity type and a buried lateral silicon carbide edge termination region located within the epitaxial silicon carbide layer including a second conductivity type. The buried lateral silicon carbide edge termination region is covered by a silicon carbide surface layer including the first conductivity type. | 2015-07-02 |
20150187872 | SUPER JUNCTION WITH AN ANGLED TRENCH, TRANSISTOR HAVING THE SUPER JUNCTION AND METHOD OF MAKING THE SAME - A super junction includes a substrate and an epitaxial layer over the substrate, the epitaxial layer having a first dopant type. The super junction further includes an angled trench in the epitaxial layer, the angled trench having sidewalls disposed at an angle ranging from about 85-degrees to about 89-degrees with respect to a top surface of the epitaxial layer. The super junction further includes a doped body in the epitaxial layer surrounding the angled trench, the doped body having a second dopant type, the second dopant type opposite that of the first dopant type. | 2015-07-02 |
20150187873 | SUPERJUNCTION STRUCTURES FOR POWER DEVICES AND METHODS OF MANUFACTURE - A power device includes an active region and a termination region surrounding the active region. A plurality of pillars of first and second conductivity type are alternately arranged in each of the active and termination regions. The pillars of first conductivity type in the active and termination regions have substantially the same width, and the pillars of second conductivity type in the active region have a smaller width than the pillars of second conductivity type in the termination region so that a charge balance condition in each of the active and termination regions results in a higher breakdown voltage in the termination region than in the active region. | 2015-07-02 |
20150187874 | Field-Effect Semiconductor Device and Manufacturing Therefor - A power semiconductor device includes a semiconductor body having a first surface and including an active area including n-type semiconductor regions and p-type semiconductor regions, the n-type semiconductor regions alternating, in a direction substantially parallel to the first surface, with the p-type semiconductor regions. The semiconductor body further includes a peripheral area surrounding the active area and including a low-doped semiconductor region having a first concentration of n-dopants lower than a doping concentration of n-dopants of the n-type semiconductor regions, and at least one auxiliary semiconductor region having a concentration of n-dopants higher than the first concentration and a concentration of p-dopants higher than the first concentration. | 2015-07-02 |
20150187875 | SEMICONDUCTOR BODY WITH A BURIED MATERIAL LAYER AND METHOD - One aspect includes a method for forming a buried material layer in a semiconductor body, including providing a semiconductor body having a first side and having a plurality of first trenches extending from the first surface into the semiconductor body. Each of the plurality of first trenches has a bottom and has at least one sidewall and the plurality of first trenches is separated from one another by semiconductor mesa regions. A first material layer is formed on the bottom of each of the plurality of first trenches such that the first material layer leaves at least one segment of at least one sidewall of each of the plurality of trenches uncovered. Each of the plurality of first trenches is filled by epitaxially growing a semiconductor material from the at least one uncovered sidewall segment. After filling the first trenches, second trenches are formed in the mesa regions. | 2015-07-02 |
20150187876 | NITRIDE SEMICONDUCTOR STRUCTURE - A nitride semiconductor structure including a silicon substrate, a nucleation layer, a buffer layer and a nitride semiconductor layer is provided. The nucleation layer is disposed on the silicon substrate. The buffer layer is disposed on the nucleation layer, in which the buffer layer includes n sub-buffer layers where n≧2, and each of the sub-buffer layers has island structures. The nitride semiconductor layer is disposed on the buffer layer. | 2015-07-02 |
20150187877 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device may include: an active region having a channel formed therein when the power semiconductor device is turned on, the channel allowing a current to flow therethrough; a termination region formed around the active region; first trenches formed in the active region, each first trench having an insulating layer formed on a surface thereof and filled with a conductive material; and second trenches formed in the termination region, each second trench having an insulating layer formed on a surface thereof and filled with a conductive material. | 2015-07-02 |
20150187878 | SEMICONDUCTOR DEVICE - To provide a semiconductor device including a transistor in which an oxide semiconductor is used and on-state current is high. In a semiconductor device including a first transistor provided in a driver circuit portion and a second transistor provided in a pixel portion, the first transistor and the second transistor have different structures. Furthermore, the first transistor and the second transistor are transistors having a top-gate structure in which conductive films serving as a gate electrode, a source electrode, and a drain electrode do not overlap. Furthermore, in an oxide semiconductor film, an impurity element is contained in a region which does not overlap with the gate electrode, the source electrode, and the drain electrode. | 2015-07-02 |
20150187879 | LATERAL MOS POWER TRANSISTOR HAVING BACKSIDE TERMINAL - A semiconductor component may include a semiconductor layer which has a front side and a back side, a first terminal electrode on the front side, a second terminal electrode on the back side, a first dopant region of a first conduction type on the front side, which is electrically connected to one of the terminal electrodes, a second dopant region of a second conduction type in the semiconductor layer, which is electrically connected to the other terminal electrode, a pn junction being formed between the first and second dopant regions, a dielectric layer on the back side between the semiconductor layer and the second terminal electrode, and the dielectric layer having an opening through which an electrical connection between the second terminal electrode and the first or second dopant region is passed. | 2015-07-02 |
20150187880 | Semiconductor Structure with Compositionally-Graded Transition Layer - The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications. | 2015-07-02 |
20150187881 | CONTACT RESISTANCE REDUCTION IN FINFETS - A semiconductor device having fin transistors includes a plurality of substantially parallel semiconductor fins formed over a substrate and a gate structure formed over the fins transversely to a longitudinal axis of the fins. Source and drain regions are formed on opposite sides of the gate structure and are merged with the fins by an epitaxially grown crystalline material between the fins in merged regions. Interface layers are formed on the fins in regions disposed apart from both sides of the gate structure. The interface layers are formed over a top and at least a portion of opposing sides of the fins. Contact lines are formed over the interface layers such that contact is made at the top surface of the interface layer on the fins and at least a portion of the sides of the interface layer on the fins. | 2015-07-02 |
20150187882 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME AND POWER SEMICONDUCTOR DEVICE INCLUDING THE SAME - A method of manufacturing a semiconductor device may include: preparing a substrate formed of SiC; depositing crystalline or amorphous silicon (Si) on one surface of the substrate to form a first semiconductor layer; and performing a heat treatment under a nitrogen atmosphere to form a second semiconductor layer formed of SiCN between the substrate and the first semiconductor layer. | 2015-07-02 |
20150187883 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a first n− type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate; a p type epitaxial layer disposed on the first n− type epitaxial layer; a second n− type epitaxial layer disposed on the p type epitaxial layer; an n+ region disposed on the second n− type epitaxial layer; a trench passing through the second n− type epitaxial layer, the p type epitaxial layer, and the n+ region, and disposed on the first n− type epitaxial layer; a p+ region disposed on the p type epitaxial layer and separated from the trench; and a gate insulating layer positioned in the trench, in which channels are disposed in the second n− type epitaxial layer of both sides of the trench and the p type epitaxial layer of both sides of the trench. | 2015-07-02 |
20150187884 | METHOD AND SYSTEM FOR TRANSIENT VOLTAGE SUPPRESSION - A transient voltage suppression (TVS) device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (μm) and 22.0 μm thick, the second layer operating using punch-through physics, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer. | 2015-07-02 |
20150187885 | SEMICONDUCTOR EPITAXIAL STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor epitaxial structure is provided, which includes: a nitride nucleation layer, formed on a substrate including silicon, sapphire, patterned sapphire substrate (PSS) or silicon carbide, a nitride layer on the nitride nucleation layer and an multi-layer structure in the nitride layer. The multi-layer structure includes a first intermediate layer and a second intermediate layer formed on the first intermediate layer. The first intermediate layer includes AlGaN, the second intermediate layer includes AlGaN or aluminium nitride, and the average composition of Al in the first intermediate layer is less than that in the second intermediate layer. A method for forming a semiconductor epitaxial structure is provided. The semiconductor epitaxial structure according to the present disclosure can not decrease the crystalline quality when a compressive stress is introduced, which may avoid a crack phenomenon or quality degradation caused by the change of temperature. | 2015-07-02 |
20150187886 | NITRIDE SEMICONDUCTOR DEVICE - Provided is a nitride semiconductor device including: a substrate having through via holes; first and second nitride semiconductor layers sequentially stacked on the substrate; drain electrodes and source electrodes provided on the second nitride semiconductor layer; and an insulating pattern provided on the second nitride semiconductor layer, the insulating pattern having upper via holes provided on the drain electrodes, wherein the through via holes are extended into the first and second nitride semiconductor layers and expose a bottom of each of the source electrodes. | 2015-07-02 |
20150187887 | III NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a III nitride semiconductor device higher heat dissipation performance, and a method of manufacturing a III nitride semiconductor device which makes it possible to fabricate such a III nitride semiconductor device at higher yield. In a method of a III nitride semiconductor device, a semiconductor structure obtained by sequentially stacking an n-layer, an active layer, and a p-layer is formed on a growth substrate; a support body including a first support electrically connected to an n-layer to serve as an n-side electrode, a second support electrically connected to a p-layer to serve as a p-side electrode, and structures made of an insulator for insulation between first and second supports is formed on the p-layer side of the semiconductor structure; and the growth substrate is separated using a lift-off process. The first support and the second support are grown by plating. | 2015-07-02 |
20150187888 | ENGINEERED SUBSTRATES FOR USE IN CRYSTALLINE-NITRIDE BASED DEVICES - A spalling process can be employed to generate a fracture at a predetermined depth within a high quality crystalline nitride substrate, such as a bulk GaN substrate. A first crystalline conductive film layer can be separated, along the line of fracture, from the crystalline nitride substrate and subsequently bonded to a layered stack including a traditional lower-cost substrate. If the spalled surface of the first crystalline conductive film layer is exposed in the resulting structure, the structure can act as a substrate on which high quality GaN-based devices can be grown. | 2015-07-02 |
20150187889 | SURFACE-CONTROLLED SEMICONDUCTOR NANO-DEVICES, METHODS AND APPLICATIONS - Semiconductor structures and semiconductor devices may include: (1) an n-type compound semiconductor material having a surface Fermi level pinned to a conduction band of the n-type compound semiconductor material; (2) a p-type compound semiconductor material having a surface Fermi level pinned to a valence band of the p-type compound semiconductor material; and/or (3) an i-type compound semiconductor materials having a surface Fermi level pinned within a band gap of the i-type compound semiconductor material. Semiconductor structures and semiconductor devices in accordance with the foregoing n-type, p-type and i-type compound semiconductor materials provide the semiconductor structures and semiconductor devices with enhanced performance. | 2015-07-02 |
20150187890 | METHOD OF FORMING TRENCH ON FINFET AND FINFET THEREOF - A method is provided for forming a trench on a FinFET. In an exemplary embodiment, a first inter-layer dielectric layer is formed between a first gate and a second gate of the FinFET in an interposed manner. A second inter-layer dielectric layer is formed above the first inter-layer dielectric layer, the first gate of the FinFET, and the second gate of the FinFET. A photoresist layer is formed above the second inter-layer dielectric layer. And part of the second inter-layer dielectric layer that is not below the photoresist layer is etched. | 2015-07-02 |
20150187891 | Formation of Gate Sidewall Structure - A semiconductor device having a gate stack on a substrate is disclosed. The gate stack may include a mask layer disposed over a first gate conductor layer. The first gate conductor layer may be laterally etched beneath the mask layer to create an overhanging portion of the mask layer. A sidewall dielectric can be formed on the sidewall of the first gate conductor layer beneath the overhanging portion of the mask layer. A sidewall structure layer can be formed adjacent to the sidewall dielectric and beneath the overhanging portion of the mask layer. The mask layer can be removed. The first gate conductor layer can be used to form a memory gate and the sidewall structure layer can be used to form a select gate. | 2015-07-02 |
20150187892 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is disclosed, comprising: forming a contact sacrificial layer on the substrate, etching the contact sacrificial layer to form a contact sacrificial pattern, wherein the contact sacrificial pattern covers the source region and the drain region and has a gate trench that exposes the substrate; forming a gate spacer and a gate stack structure in the gate trench; partially or completely etching off the contact sacrificial pattern that covers the source region and the drain region so as to form a source/drain contact trench; and forming a source/drain contact in the source/drain contact trench. By means of the double-layer contact sacrificial layer, the method for manufacturing a semiconductor device in accordance with the present invention effectively reduces the spacing between the gate spacer and the contact region and increases the area of contact region, thus effectively reducing the parasitic resistance of the device. | 2015-07-02 |
20150187893 | SEMICONDUCTOR DEVICES WITH FIELD PLATES - A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer. | 2015-07-02 |
20150187894 | DISPLAY DEVICE SUBSTRATE AND DISPLAY DEVICE EQUIPPED WITH SAME - This thin film transistor substrate is provided with: a drain electrode that is formed on an insulating film, and comprises copper; an interlayer insulating film formed on the drain electrode; and a pixel electrode that is formed in the contact hole, which is formed in the insulating film and the interlayer insulating film, and on the interlayer insulating film, and is electrically connected to the drain electrode via the contact hole. In a plan view of the contact hole, the drain electrode is formed inside part of the contact hole in such a manner that part of the drain electrode and part of the outer periphery of the contact hole are overlapping, and part of the pixel electrode and the drain electrode are electrically connected. | 2015-07-02 |
20150187895 | THIN FILM TRANSISTOR STRUCTURE - A thin film transistor structure includes a substrate, a gate structure, a semiconductor active layer, a drain structure and a source structure. The gate structure and the semiconductor active layer are disposed above the substrate. The drain structure and the source structure are disposed on a first surface of the semiconductor active layer. At least a gap is formed between the source structure and the drain structure. The gap is extended along the first surface of the semiconductor active layer and is located in a projection area of the gate structure. A first portion of the gap includes a first straight segment, a first curved segment and a second curved segment. The first curved segment and the second curved segment are connected to a first end and a second end of the first straight segment, respectively. The first curved segment and the second curved segment have opposite bending directions. | 2015-07-02 |
20150187896 | SILICIDE PROTECTION DURING CONTACT METALLIZATION AND RESULTING SEMICONDUCTOR STRUCTURES - A semiconductor transistor has a structure including a semiconductor substrate, a source region, a drain region and a channel region in between the source region and the drain region. A metal gate, having a top conductive portion of tungsten is provided above the channel region. A first silicon nitride protective layer over the source region and the drain region and a second silicon nitride protective layer over the gate region are provided. The first silicon nitride protective layer and the second silicon nitride protective layer are configured to allow punch-through of the first silicon nitride protective layer while preventing etching through the second silicon nitride protective layer. Source and drain silicide is protected by avoiding fully etching a gate opening unless either the etching used would not harm the silicide, or the silicide and source and drain contacts are created prior to fully etching an opening to the gate for a gate contact. | 2015-07-02 |
20150187897 | PARTIAL SACRIFICIAL DUMMY GATE WITH CMOS DEVICE WITH HIGH-K METAL GATE - A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections, a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers, source and drain regions, a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer, an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation, and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack. | 2015-07-02 |
20150187898 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A novel semiconductor device with a transistor using an oxide semiconductor film, in which a conductive film including Cu is used as a wiring or the like, is provided. The semiconductor device includes a first insulating film, an oxide semiconductor over the first insulating film, a gate electrode overlapping the oxide semiconductor with a gate insulating film positioned therebetween, a second insulating film in contact with a side surface of the gate electrode, and a third insulating film in contact with a top surface of the gate electrode. The gate electrode includes a Cu—X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, Ti, Zr, Mg, Ca, or a mixture of two or more of these elements). | 2015-07-02 |
20150187899 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device includes a junction region on both sides of a trench in a semiconductor substrate, a first gate electrode with a first workfunction buried in the trench, and a second gate electrode formed of a polycide layer having a second workfunction overlapping with the junction region at an upper part of the first gate electrode. | 2015-07-02 |
20150187900 | COMPOSITE MATERIALS FOR USE IN SEMICONDUCTOR COMPONENTS - An integrated circuit including a transistor, wherein the transistor includes a substrate including a surface, a gate oxide deposited on the substrate surface and a gate deposited on the gate oxide. The gate oxide includes one or more dielectric domains and a band gap matrix. The dielectric domains includes a first material and the band gap matrix includes a second material, wherein a dielectric constant of the first material is greater than a dielectric constant of the second material and a band gap of the first material is less than a band gap of the second material. | 2015-07-02 |
20150187901 | MULTI-PLASMA NITRIDATION PROCESS FOR A GATE DIELECTRIC - A gate dielectric can be formed by depositing a first silicon oxide material by a first atomic layer deposition process. The thickness of the first silicon oxide material is selected to correspond to at least 10 deposition cycles of the first atomic layer deposition process. The first silicon oxide material is converted into a first silicon oxynitride material by a first plasma nitridation process. A second silicon oxide material is subsequently deposited by a second atomic layer deposition process. The second silicon oxide material is converted into a second silicon oxynitride material by a second plasma nitridation process. Multiple repetitions of the atomic layer deposition process and the plasma nitridation process provides a silicon oxynitride material having a ratio of nitrogen atoms to oxygen atoms greater than 1/3, which can be advantageously employed to reduce the leakage current through a gate dielectric. | 2015-07-02 |
20150187902 | SEMICONDUCTOR STRUCTURE HAVING INTERFACIAL LAYER AND HIGH-K DIELECTRIC LAYER - A semiconductor structure includes a semiconductor substrate. The semiconductor structure further includes an interfacial layer over the semiconductor substrate, the interfacial layer having a capacitive effective thickness of less than 1.37 nanometers (nm). The semiconductor structure further includes a high-k dielectric layer over the interfacial layer. | 2015-07-02 |
20150187903 | FRINGE CAPACITANCE REDUCTION FOR REPLACEMENT GATE CMOS - A replacement metal gate transistor structure and method with thin silicon nitride sidewalls and with little or no high-k dielectric on the vertical sidewalls of the replacement gate transistor trench | 2015-07-02 |
20150187904 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - Embodiments of a method for forming a semiconductor device structure are provided. The method includes forming a gate stack over a semiconductor substrate and forming a sealing structure over a sidewall of the gate stack. The method also includes forming a dummy shielding layer over the semiconductor substrate, the sealing structure, and the gate stack. The method further includes performing an ion implantation process on the dummy shielding layer to form source and drain regions in the semiconductor substrate. In addition, the method includes removing the dummy shielding layer after the source and drain regions are formed. | 2015-07-02 |
20150187905 | METHODS OF FORMING GATE STRUCTURES FOR SEMICONDUCTOR DEVICES USING A REPLACEMENT GATE TECHNIQUE AND THE RESULTING DEVICES - One method disclosed herein includes, among other things, forming sidewall spacers adjacent opposite sides of a sacrificial gate electrode of a sacrificial gate structure, forming a tensile-stressed layer of insulating material adjacent the sidewall spacers, removing the sacrificial gate structure to define a replacement gate cavity positioned between the sidewall spacers, forming a replacement gate structure in the replacement gate cavity, forming a tensile-stressed gate cap layer above the replacement gate structure and within the replacement gate cavity and, after forming the tensile-stressed gate cap layer, removing the tensile-stressed layer of insulating material. | 2015-07-02 |
20150187906 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench. | 2015-07-02 |
20150187907 | SEMICONDUCTOR DEVICE INCLUDING GATE ELECTRODE PROVIDED OVER ACTIVE REGION IN P-TYPE NITRIDE SEMICONDUCTOR LAYER AND METHOD OF MANUFACTURING THE SAME, AND POWER SUPPLY APPARATUS - A semiconductor device includes a nitride semiconductor stacked structure including a carrier transit layer and a carrier supply layer; a p-type nitride semiconductor layer provided over the nitride semiconductor stacked structure and including an active region and an inactive region; an n-type nitride semiconductor layer provided on the inactive region in the p-type nitride semiconductor layer; and a gate electrode provided over the active region in the p-type nitride semiconductor layer. | 2015-07-02 |
20150187908 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - Methods for fabricating semiconductor devices are provided. Gate structures are formed on a top surface of a substrate to form semiconductor devices. Trenches are formed in the substrate on both sides of each gate structure of each semiconductor device. The trenches on the both sides of each gate structure are filled with stress layers, the stress layers in the substrate protruding over the top surface of the substrate The stress layers are ion-doped and annealed on the both sides of each gate structure, and are pulse-etched to form a source region and a drain region of each gate structure. The pulse-etching is controlled such that the source regions and the drain regions of the plurality of semiconductor devices have a top surface coplanar with the top surface of the substrate. | 2015-07-02 |
20150187909 | METHODS FOR FABRICATING MULTIPLE-GATE INTEGRATED CIRCUITS - A method for fabricating an integrated circuit includes providing a silicon semiconductor substrate including a single-crystal crystallography, removing a portion of the semiconductor substrate to form a fin structure, the fin structure being defined by adjacent trenches formed within the semiconductor substrate, and forming an insulating material in the trenches, the insulating material covering a first portion of the fin and leaving a second portion of the fin exposed. The method further includes applying a wet etchant to the second portion of the fin, the wet etchant including an etching chemistry that selectively etches the fin against a <111> crystallographic orientation of the single-crystal silicon. | 2015-07-02 |