27th week of 2015 patent applcation highlights part 59 |
Patent application number | Title | Published |
20150187610 | SUBSTRATE PROCESSING APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM - A substrate processing apparatus includes a common pipe connected to a process container wherethrough a first and second process gases flow; a buffer unit connected to an upstream side of the common pipe and having a width greater than a diameter of the common pipe; a first supply pipe wherethrough the first process gas flows, connected to a first surface of the buffer unit where the common pipe is connected or a second surface of the buffer unit opposite to the first surface; and a second supply pipe wherethrough the second process gas flows, connected to the first or second surface. Each of the first and second supply pipes is installed outer than the common pipe, and a distance between the first and second surfaces is shorter than a distance between a center axis of the common pipe and that of the first or second supply pipe. | 2015-07-02 |
20150187611 | SUBSTRATE PROCESSING SYSTEM, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM - A substrate processing system includes a plurality of processing chambers accommodating substrates, a processing gas supply system configured to supply a processing gas sequentially into the plurality of processing chambers, a reactive gas supply system configured to supply an activated reactive gas sequentially into the plurality of processing chambers, a buffer tank installed at the processing gas supply system, and a control unit configured to control the processing gas supply system and the reactive gas supply system such that a time period of supplying the reactive gas into one of the plurality of processing chambers is equal to a sum of a time period of supplying the processing gas into the one of the plurality of processing chambers and a time period of supplying the processing gas into the buffer tank, and the processing gas and the reactive gas are alternately supplied into the plurality of processing chambers. | 2015-07-02 |
20150187612 | APPARATUS FOR TREATING SURFACES OF WAFER-SHAPED ARTICLES - An apparatus for processing wafer-shaped articles, comprises a closed process chamber providing a gas-tight enclosure. A rotary chuck is located within the closed process chamber, and is adapted to hold a wafer shaped article thereon. A lid is secured to an upper part of the closed process chamber, and comprises a lower surface facing inwardly of the chamber. At least one heating element heats the lower surface of the lid to a desired temperature, so as to prevent condensation of process vapour on the inwardly facing surface of the lid. | 2015-07-02 |
20150187613 | SUBSTRATE LIQUID PROCESSING APPARATUS - A substrate liquid processing apparatus of the present disclosure supplies a plurality of processing liquids from a processing liquid supplying unit in a switching manner to a substrate held on a substrate holding unit. An elevatable inner cup surrounds the substrate holding unit laterally and forms a first drain path that drains the first processing liquid. An outer cup surrounds the inner cup and forms a second drain path that drains the second processing liquid. A cover covers the outside of the outer cup, includes an eaves portion that extends inwardly from an upper side, and forms an exhaust path between the cover and the outer cup. The exhaust path is connected to the first drain path and the second drain path above inlets of the first drain path and the second drain path. | 2015-07-02 |
20150187614 | EDGE SEAL FOR LOWER ELECTRODE ASSEMBLY - A lower electrode assembly useful for supporting a semiconductor substrate in a plasma processing chamber includes a temperature controlled lower base plate, an upper plate, a mounting groove surrounding a bond layer and an edge seal comprising a ring compressed in the groove. A gas source supplies inert gas to the groove and maintains the inert gas at a pressure of 100 mTorr to 100 Torr in the groove. | 2015-07-02 |
20150187615 | COMPONENT OF A PLASMA PROCESSING APPARATUS INCLUDING AN ELECTRICALLY CONDUCTIVE AND NONMAGNETIC COLD SPRAYED COATING - A semiconductor plasma processing apparatus used to process semiconductor components comprises a plasma processing chamber, a process gas source in fluid communication with the plasma processing chamber for supplying a process gas into the plasma processing chamber, a RF energy source adapted to energize the process gas into the plasma state in the plasma processing chamber, and a vacuum port for exhausting process gas from the plasma processing chamber. The semiconductor plasma processing apparatus further comprises at least one component wherein the component has a body which has a relative magnetic permeability of about 70,000 or greater and a cold sprayed electrically conductive and nonmagnetic coating on a surface of the body wherein the coating has a thickness greater than the skin depth of a RF current configured to flow therethrough during plasma processing. | 2015-07-02 |
20150187616 | MECHANISMS OF ADJUSTABLE LASER BEAM FOR LASER SPIKE ANNEALING - Mechanisms of adjustable laser beams for LSA (Laser Spike Annealing) are provided. A computing device receives input mask information relative to a silicon wafer, and analyzes the input mask information so as to generate a control signal. A laser generator generates a laser beam, and adjusts a beam length of the laser beam according to the control signal. Such mechanisms of the disclosure effectively eliminate the stitch effect on the silicon wafer and further increase the wafer yield. | 2015-07-02 |
20150187617 | DIE BONDER AND A METHOD OF CLEANING A BOND COLLET - A die bonder comprises a movable bond collet for holding an electronic device, and a platform which comprises a cleaning surface for cleaning the bond collet when the bond collet contacts the cleaning surface. The die bonder also comprises a cleaning agent supply, wherein the cleaning agent supply is operative to provide a cleaning agent to the cleaning surface to facilitate the cleaning of the bond collet. | 2015-07-02 |
20150187618 | SYSTEM AND METHOD FOR FORMING GAN-BASED DEVICE - A system and a method for forming a GaN based device are provided. The system may include: at least one MOCVD reaction chamber; at least one ALD or CVD reaction chamber; and a loadlock transfer connecting with the MOCVD reaction chamber and the ALD or CVD reaction chamber. The MOCVD reaction chamber may be a standard chamber for nitride growth. The ALD or CVD reaction chamber may be used for growing nitride and oxide dielectric layers, which may have a highest growth temperature no less than about 500° C., such that nitride and oxide may have better qualities. The system may include a cleaning chamber for cleaning the substrate and the nitride films. Using the integrated system, cleaning processes and growing processes for epitaxial layers and dielectric layers can be implemented in a same system, which may avoid contaminations in the air. Device performance may be improved. | 2015-07-02 |
20150187619 | METHOD AND APPARATUS FOR CONTROLLING SPATIAL TEMPERATURE DISTRIBUTION - A chuck for a plasma processor comprises a temperature-controlled base, a thermal insulator, a flat support, and a heater. The temperature-controlled base is controlled in operation a temperature below the desired temperature of a workpiece. The thermal insulator is disposed over at least a portion of the temperature-controlled base. The flat support holds a workpiece and is disposed over the thermal insulator. A heater is embedded within the flat support and/or mounted to an underside of the flat support. The heater includes a plurality of heating elements that heat a plurality of corresponding heating zones. The power supplied and/or temperature of each heating element is controlled independently. The heater and flat support have a combined temperature rate change of at least 1° C. per second. | 2015-07-02 |
20150187620 | Water Carrier Having Thermal Cover for Chemical Vapor Deposition Systems - The invention relates generally to semiconductor fabrication technology and, more particularly, to chemical vapor deposition (CVD) processing and associated apparatus for addressing temperature non-uniformities on semiconductor wafer surfaces. Embodiments include a wafer carrier for use in a system for growing epitaxial layers on one or more wafers by CVD, the wafer carrier comprising a top plate and base plate which function coordinately to reduce temperature variability caused during CVD processing. | 2015-07-02 |
20150187621 | SUBSTRATE PROCESSING APPARATUS - A throughput can be improved. A substrate processing apparatus includes processing units arranged in a vertical direction and configured to process substrates; and a substrate transfer device configured to be moved in the vertical direction and perform loading/unloading of the substrates into/from the processing units. Further, the substrate transfer device comprises a first transfer arm and a second transfer arm which are arranged in the vertical direction and configured to be moved in the vertical direction independently, and movement ranges of the first transfer arm and the second transfer arm in the vertical direction are overlapped with each other. | 2015-07-02 |
20150187622 | METHODS AND DEVICES FOR SECURING AND TRANSPORTING SINGULATED DIE IN HIGH VOLUME MANUFACTURING - A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed. | 2015-07-02 |
20150187623 | POSITIONING FRAME STRUCTURE - A positioning frame structure for the centering and positioning of an IC is disclosed, in which the positioning frame structure comprises an IC carrier having a first chamber defined therein and an IC positioning magnet disposed in the first chamber of the IC carrier. The positioning frame structure further comprises an IC holder disposed over the IC positioning magnet, and the IC is held on the IC holder, so as to provide centering and positioning of the IC relative to the IC positioning magnet. The present invention can be used to control the centering and positioning of the IC and the positioning magnet on the carrier. The positioning magnet can be made to be larger than the IC. In addition, a large air gap can be obtained so as to facilitate the subsequent operation of the IC. Furthermore, without the operation using adhesive, the technical solution of the present invention saves the cost of operation. | 2015-07-02 |
20150187624 | APPARATUS FOR TREATING SURFACES OF WAFER-SHAPED ARTICLES - An apparatus for processing wafer-shaped articles comprises a closed process chamber providing a gas-tight enclosure. A rotary chuck is located within the closed process chamber, the rotary chuck being adapted to hold a wafer shaped article thereon. A lid is secured to an upper part of the closed process chamber, the lid comprising an upper plate formed from a composite fiber-reinforced material and a lower plate that faces into the process chamber and is formed from a chemically-resistant plastic. | 2015-07-02 |
20150187625 | ELECTROSTATIC CHUCK WITH EXTERNAL FLOW ADJUSTMENTS FOR IMPROVED TEMPERATURE DISTRIBUTION - An electrostatic chuck is described with external flow adjustments for improved temperature distribution. In one example, an apparatus has a dielectric puck to electrostatically grip a silicon wafer. A cooling plate is fastened to and thermally coupled to the ceramic puck. A supply plenum receives coolant from an external source and a plurality of coolant chambers are thermally coupled to the cooling plate and receive coolant from the supply plenum. A return plenum is coupled to the cooling zones to exhaust coolant from the cooling zones and a plurality of flow control valves are positioned between the supply plenum and a respective one of the cooling zones to control the flow rate of coolant from the supply plenum to the cooling zones. | 2015-07-02 |
20150187626 | ELECTROSTATIC CHUCK WITH INTERNAL FLOW ADJUSTMENTS FOR IMPROVED TEMPERATURE DISTRIBUTION - An electrostatic chuck is described with external flow adjustments for improved temperature distribution. In one example, an apparatus has a dielectric puck to electrostatically grip a silicon wafer. A cooling plate is fastened to and thermally coupled to the ceramic puck. A supply plenum receives coolant from an external source and a plurality of coolant chambers are thermally coupled to the cooling plate and receive coolant from the supply plenum. A return plenum is coupled to the cooling zones to exhaust coolant from the cooling zones. A plurality of adjustable orifices are positioned between the supply plenum and a respective one of the cooling zones to control the flow rate of coolant from the supply plenum to the cooling zones. | 2015-07-02 |
20150187627 | DEVICE FOR MACHINING A SUBSTRATE AND A METHOD FOR THIS PURPOSE - In a device for machining, in particular etching and/or developing, substrates, in particular wafers, in particular etching and/or developing, having a turntable, the turntable has a Venturi gap. | 2015-07-02 |
20150187628 | Vacuum Device by Using Centrifugal Resources - A wafer holding vacuum for a wafer polishing system and the wafer suction device for CMP (Chemical Mechanical Polishing) by utilizing existing resources provided by the rotating polishing post is provided. The device introduces a channel configured in the wafer suction device. One end of the channel is exposed at downside of the holding block, and another end of the tube is exposed at lateral side of the holding block. By aforementioned configuration, the channel can suck gas and/or liquid between the wafer and the device, and can discharge them to the outer environment at the lateral side using centrifugal force naturally provided by the polishing post. | 2015-07-02 |
20150187629 | APPARATUS FOR TREATING SURFACES OF WAFER-SHAPED ARTICLES - An apparatus for processing wafer-shaped articles comprises a closed process chamber providing a gas-tight enclosure. A rotary chuck is located within the closed process chamber, and is adapted to hold a wafer shaped article thereon. A lid is secured to an upper part of the closed process chamber. The lid comprises an annular chamber, gas inlets communicating with the annular chamber and opening on a surface of the lid facing outwardly of the closed process chamber, and gas outlets communicating with the annular chamber and opening on a surface of the lid facing inwardly of the closed process chamber. | 2015-07-02 |
20150187630 | SUPPORT RING WITH MASKED EDGE - A support ring for semiconductor processing is provided. The support ring includes a ring shaped body defined by an inner edge and an outer edge. The inner edge and outer edge are concentric about a central axis. The ring shaped body further includes a first side, a second side, and a raised annular shoulder extending from the first side of the ring shaped body at the inner edge. The support ring also includes a coating on the first side. The coating has an inner region of reduced thickness region abutting the raised annular shoulder. | 2015-07-02 |
20150187631 | SUBSTRATE SUPPORTING EDGE RING WITH COATING FOR IMPROVED SOAK PERFORMANCE - Embodiments of the present invention provide a substrate supporting edge ring for supporting a substrate. In one embodiment, a substrate support ring is provided. The substrate support ring comprises an annular body. The annular body comprises an outer band extending radially inward from an outer annular sidewall; and a substrate supporting region extending inward from an inner portion of the outer band, wherein the annular body comprises a first material that is exposed and at least a portion of the substrate supporting region is covered with a coating comprising a second material that is different than the first material. | 2015-07-02 |
20150187632 | METAL THIN FILM RESISTOR AND PROCESS - An integrated circuit with a metal thin film resistor with an overlying etch stop layer. A process for forming a metal thin film resistor in an integrated circuit with the addition of one lithography step. | 2015-07-02 |
20150187633 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD - Semiconductor devices and fabrication methods are provided. First metal layers are provided in a substrate including a first region and a second region. An interlayer dielectric (ILD) layer formed over the substrate includes a top surface in the second region coplanar with a bottom of a trench in the ILD layer in the first region. Through-holes are formed in the ILD layer. A polymer layer fills the through-holes and the trench in ILD layer and covers top surface of ILD layer in both regions. The polymer layer is exposed and developed to form vias, each including an upper via in the polymer layer and a lower via in ILD layer. A second metal layer is formed to fill each via on a corresponding first metal layer in both regions. The polymer layer between adjacent second metal layers is removed to form air gaps in the second region. | 2015-07-02 |
20150187634 | MECHANISMS FOR FORMING FINFETS WITH DIFFERENT FIN HEIGHTS - Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a first fin partially surrounded by a first isolation structure and protruding through a top surface thereof. The semiconductor device also includes a second fin partially surrounded by a second isolation structure and protruding through a top surface thereof. The top surface of the first isolation structure is higher than the top surface of the second isolation structure such that the second fin has a height higher than that of the first fin. The second isolation structure has a dopant concentration higher than that of the first isolation structure. | 2015-07-02 |
20150187635 | METHOD TO REDUCE PARTICLES DURING STI FILL AND REDUCE CMP SCRATCHES - A method of filling STI trenches with dielectric with reduced particle formation. A method of depositing unbiased STI oxide on an integrated circuit during STI trench fill that reduces STI defects during STI CMP. | 2015-07-02 |
20150187636 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first semiconductor chip comprising a first metallic structure, a top surface, and a bottom surface, a second semiconductor chip comprising a second metallic structure, wherein the second semiconductor chip is bonded with the first semiconductor chip on the bottom surface, a conductive material connecting the first metallic structure and the second metallic structure, wherein a portion of the conductive material is inside the first semiconductor chip and the second semiconductor chip, and a dielectric layer disposed surrounding the portion of the conductive material. | 2015-07-02 |
20150187637 | MANUFACTURING METHOD FOR DISPLAY DEVICE - A method of manufacturing a display device that includes: performing a surface treatment on at least one of two opposing surfaces of a carrier substrate and a mother substrate; bonding the carrier substrate and the mother substrate; performing a thin film formation process on the mother substrate; and separating the carrier substrate and the mother substrate. The thin film formation process includes a heat treatment operation, the surface treatment includes using an inorganic acid or an organic acid, and the surface treatment controls a content of —OH, —OH | 2015-07-02 |
20150187638 | PROCESS FOR TRANSFERRING A LAYER - This transfer process comprises the following steps: (a) providing a donor substrate and a support substrate; (b) forming an embrittlement region in the donor substrate; (c) forming what is called a bonding layer between the first part of the donor substrate and the support substrate; and assembling the donor substrate to the support substrate, and is noteworthy in that it comprises the following step: (e) exposing, in succession, portions of the embrittlement region to electromagnetic irradiations for an exposure time at a given power density, the exposure time being chosen depending on the thickness of the bonding layer so that the support substrate is thermally decoupled from the first part of the donor substrate, the exposure time being chosen depending on the power density in order to activate kinetics that weaken the embrittlement region. | 2015-07-02 |
20150187639 | SILICON-ON-INSULATOR SUBSTRATE AND METHOD OF MANUFACTURING THEREOF - A method of manufacturing a silicon-on-insulator (SOI) substrate is provided. The method includes forming an island-shaped insulating layer on a first surface of a first semiconductor substrate in a first region, forming a silicon epitaxial layer on the first surface of the first semiconductor substrate so as to cover the island-shaped insulating layer, forming a trench by etching the silicon epitaxial layer so as to expose the island-shaped insulating layer, and forming a first insulating adhesive layer on the silicon epitaxial layer and the island-shaped insulating layer so as to fill the trench. | 2015-07-02 |
20150187640 | TFT ARRAY SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE - A TFT substrate and a method of manufacturing the TFT array substrate are disclosed. The method includes providing a substrate, forming an organic layer on the substrate, forming a first transparent conductive layer on the organic layer, and forming a photolithography layer on the first transparent conductive layer, where the photolithography layer has an opening. The method also includes patterning the first transparent conductive layer to form a first via hole in the first transparent layer using the photolithography layer as a mask, where the first via hole is all med with the opening in the photolithography layer and patterning the organic layer to form a second via hole in the organic using the photolithography layer as a mask, where the second via hole is aligned with the opening in the photolithography layer. | 2015-07-02 |
20150187641 | INTEGRATED CIRCUITS WITH IMPROVED GAP FILL DIELECTRIC AND METHODS FOR FABRICATING SAME - Integrated circuits with reduced shorting and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes depositing a gap fill dielectric overlying a semiconductor substrate. The gap fill dielectric is formed with an upper surface having a height differential. The method includes reducing the height differential of the upper surface of the gap fill dielectric. Further, the method includes depositing an interlayer dielectric overlying the gap fill dielectric. Also, the method forms an electrical contact to a selected location overlying the semiconductor substrate. | 2015-07-02 |
20150187642 | DOUBLE-SIDED SEGMENTED LINE ARCHITECTURE IN 3D INTEGRATION - Embodiments of the present invention relate generally to electronic components such as semiconductor wafers and more particularly, to a double-sided three-dimensional (3D) hierarchal architecture scheme for multiple semiconductor wafers using an arrangement of through silicon vias (TSVs) and backside wiring. In an embodiment a first word line architecture may be formed on a front side of an IC chip and connected to a second word line architecture formed on a back side of the IC chip through intra-wafer, TSVs, thereby relocating required wiring to the back side of the IC chip. | 2015-07-02 |
20150187643 | Depression Filling Method and Processing Apparatus - A depression filling method for filling a depression of a workpiece including a semiconductor substrate and an insulating film formed on the semiconductor substrate includes: forming an impurity-doped first semiconductor layer along a wall surface which defines the depression; forming, on the first semiconductor layer, a second semiconductor layer which is lower in impurity concentration than the first semiconductor layer and which is smaller in thickness than the first semiconductor layer; annealing the workpiece to form an epitaxial region at the bottom of the depression corresponding to crystals of the semiconductor substrate from the first semiconductor layer and the second semiconductor layer; and etching the first amorphous semiconductor region and the second amorphous semiconductor region. | 2015-07-02 |
20150187644 | SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device and a semiconductor device formed by the method. The method includes form a stack conductive structure by stacking a first conductive pattern and an insulation pattern over a substrate; forming a sacrificial pattern over sidewalls of the stack conductive structure; forming a second conductive pattern having a recessed surface lower than a top surface of the stack conductive structure; forming a sacrificial spacer to expose sidewalls of the insulation pattern by removing an upper portion of the sacrificial pattern; reducing a width of the exposed portion of the insulation patters; forming a capping spacer to cap the sidewalls of the insulation pattern having the reduced width over the sacrificial spacer; and forming an air gap between the first conductive pattern and the second conductive pattern by converting the sacrificial spacer to volatile byproducts | 2015-07-02 |
20150187645 | Semiconductor Device Having Non-Planar Interface Between a Plug Layer and a Contact Layer - A semiconductor device is provided, in which it becomes easy to reliably couple a plug conductive layer and a wiring layer located over the plug conductive layer to each other and falling of the wiring can be suppressed. The plug conductive layer contacts a source/drain region formed over a major surface of the semiconductor substrate. A contact conductive layer is formed so as to contact both the upper surface and the side surface of the plug conductive layer. Wiring layers are formed over the contact conductive layer so as to be electrically coupled to the contact conductive layer. | 2015-07-02 |
20150187646 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - According to one embodiment, a first core pattern is formed in a wiring portion on a process target film and a second core pattern, which is led out from the first core pattern and includes an opening, is formed in a leading portion on the process target film, a sidewall pattern is formed along an outer periphery of the first core pattern and the second core pattern and a sidewall dummy pattern is formed along an inner periphery of the opening of the second core pattern, the first core pattern and the second core pattern are removed, and the process target film is processed to transfer the sidewall pattern and the sidewall dummy pattern. | 2015-07-02 |
20150187647 | THROUGH VIA CONTACTS WITH INSULATED SUBSTRATE - Device and a method of forming a device are disclosed. The method includes providing a crystalline-on-insulator (COI) substrate. The COI substrate includes at least a base substrate over a buried insulator layer. Through via (TV) contacts are formed within the substrate. The TV contact extends from a top surface of the base substrate to within the buried insulator layer. Upper interconnect levels are formed over the top surface of the base substrate. A lower redistribution (RDL) is formed over a bottom surface of the base substrate. The buried insulator layer corresponds to a first RDL dielectric layer of the lower RDL and protects the sidewalls of the TV contacts. | 2015-07-02 |
20150187648 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method for fabricating the same are disclosed, which can prevent migration of copper (Cu) ion when forming a Through Silicon Via (TSV). The semiconductor device includes a through silicon via (TSV) formed to pass through a semiconductor substrate; an oxide film located at a lower sidewall of the TSV; and a first prevention film formed to cover an upper portion of the TSV, an upper sidewall of the TSV, and an upper surface of the oxide film. | 2015-07-02 |
20150187649 | MANUFACTURING METHOD FOR SOLID-STATE IMAGING DEVICE AND SOLID-STATE IMAGING DEVICE - A method for manufacturing a solid-state imaging device comprises a first step of preparing an imaging element having a second principal surface having an electrode arranged thereon, and a photoelectric converter part configured to photoelectrically convert the incident energy line so as to generate a signal charge; a second step of preparing a support substrate, provided with a through hole extending in a thickness direction thereof, having a third principal surface; a third step of aligning the imaging element and the support substrate with each other so that the electrode is exposed out of the through hole while the second and third principal surfaces oppose each other and joining the imaging element and the support substrate to each other; and a fourth step of arranging a conductive ball-shaped member in the through hole and electrically connecting the ball-shaped member to the electrode after the third step. | 2015-07-02 |
20150187650 | WAFER PROCESSING METHOD - A wafer processing method includes a functional layer cutting step of applying a laser beam along each division line formed on a functional layer to thereby ablate the functional layer and form a laser processed groove along each division line. A protective member is attached to the front side of the functional layer. A groove is cut by positioning a cutting blade on the back side of the substrate in the area corresponding to each division line. The cut groove has a depth not reaching the functional layer. A dicing tape is attached to the back side of the substrate to support the outer circumferential portion of the dicing tape to an annular frame. The protective member is peeled off and the dicing tape attached to the back side of the substrate is expanded to increase the spacing between the devices. | 2015-07-02 |
20150187651 | Semiconductor Device and Method of Manufacturing the Same - A method of manufacturing a semiconductor device includes: a step of forming an inorganic insulating film and an organic insulating film on one surface of a first substrate; a step of forming an opening portion by dry-etching a laminated film of them; a step of forming a bump electrode inside the opening portion; and a step (bonding step) of bonding the one surface of the first substrate having a bump electrode formed thereon and one surface of a second substrate having a bump electrode formed thereon to each other. A surface treatment on the inorganic insulating film is performed subsequent to the step of forming the opening portion but prior to the bonding step. By performing the surface treatment on the organic insulating film, connecting property between the substrates can be improved. | 2015-07-02 |
20150187652 | METHOD FOR PRODUCING A COMPOSITE WAFER AND A METHOD FOR PRODUCING A SEMICONDUCTOR CRYSTAL LAYER FORMING WAFER - A method for producing a composite wafer by using a forming wafer having a monocrystal layer, the method comprising:
| 2015-07-02 |
20150187653 | HIGH-K / METAL GATE CMOS TRANSISTORS WITH TiN GATES - An integrated circuit with a thick TiN metal gate with a work function greater than 4.85 eV and with a thin TiN metal gate with a work function less than 4.25 eV. An integrated circuit with a replacement gate PMOS TiN metal gate transistor with a workfunction greater than 4.85 eV and with a replacement gate NMOS TiN metal gate transistor with a workfunction less than 4.25 eV. An integrated circuit with a gate first PMOS TiN metal gate transistor with a workfunction greater than 4.85 eV and with a gate first NMOS TiN metal gate transistor with a workfunction less than 4.25 eV. | 2015-07-02 |
20150187654 | Method of Manufacturing a Semiconductor Device with Buried Channel/Body Zone and Semiconductor Device - A semiconductor device includes a source zone of a first conductivity type formed in a first electrode fin that extends from a first surface into a semiconductor portion. A drain region of the first conductivity type is formed in a second electrode fin that extends from the first surface into the semiconductor portion. A channel/body zone is formed in a transistor fin that extends between the first and second electrode fins at a distance to the first surface. The first and second electrode fins extend along a first lateral direction. A width of first gate sections, which are arranged on opposing sides of the transistor fin, along a second lateral direction perpendicular to the first lateral direction is greater than a distance between the first and second electrode fins. | 2015-07-02 |
20150187655 | METHOD TO IMPROVE TRANSISTOR MATCHING - A method to adjust transistor gate geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to form a reticle. A method to adjust transistor geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to compensate for transistor turn on voltage drop off where the transistor gate crosses the isolation/active interface. | 2015-07-02 |
20150187656 | LASER ANNEALS FOR REDUCED DIODE LEAKAGE - An integrated circuit with reduced gate induced drain leakage and with reduced reverse biased diode leakage is formed using a process that employs a first laser anneal, a rapid thermal anneal, and a second laser anneal after implanting the source and drain dopant to improve transistor performance. | 2015-07-02 |
20150187657 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - In an n-channel HK/MG transistor including: a gate insulating film made of a first high dielectric film containing La and Hf; and a gate electrode which is formed of a stacked film of a metal film and a polycrystalline Si film and which is formed in an active region in a main surface of a semiconductor substrate and surrounded by an element separation portion formed of an insulating film containing oxygen atoms, a second high dielectric film which contains Hf but whose La content is smaller than a La content of the first high dielectric film is formed below the gate electrode which rides on the element separation portion, instead of the first high dielectric film. | 2015-07-02 |
20150187658 | IMPLANT PROFILING WITH RESIST - A process for forming at least two different doping levels at the surface of a wafer using one photo resist pattern and implantation process step. A resist layer is developed (but not baked) to form a first resist geometry and a plurality of sublithographic resist geometries. The resist layer is baked causing the sublithographic resist geometries to reflow into a continuous second resist geometry having a thickness less that the first resist geometry. A high energy implant implants dopants through the second resist geometry but not through the first resist geometry. A low energy implant is blocked by both the first and second resist geometries. | 2015-07-02 |
20150187659 | HIGH QUALITY DIELECTRIC FOR HI-K LAST REPLACEMENT GATE TRANSISTORS - A replacement metal gate transistor is formed with high quality gate dielectric under the high-k dielectric. The high quality gate dielectric is formed on the substrate at a temperature of at least 850° C. A sacrificial gate dielectric is formed on the high quality gate dielectric and a polysilicon replacement gate is formed on the sacrificial gate dielectric. The polysilicon replacement gate is removed leaving a gate trench. The sacrificial gate dielectric is removed from a bottom of the gate. A high-k dielectric is deposited into the gate trench. Metal gate material is deposited on the high-k dielectric. | 2015-07-02 |
20150187660 | BALANCING ASYMMETRIC SPACERS - An issue arises when manufacturing semiconductor circuits including PFETs with an SiGe alloy embedded in their source/drain regions and NFETs without any embedded SiGe alloy. In this case, the thickness of the NFET spacers is considerably greater than that of the PFET spacers. In order to alleviate this asymmetry in spacer thickness, a manufacturing flow is proposed wherein a spacer-reducing etching process is introduced before the salicidation. The etching process is performed directly after the ion implantation performed in order to form deep regions of source/drain regions of the NFETs. Thus, the spacer-reducing etching process may be performed in the presence of the same mask used during the NFET deep implantations. The spacer-reducing etching process results in thinning of the NFET spacer structures, thus alleviating the spacer thickness imbalance between NFETs and PFETs. | 2015-07-02 |
20150187661 | DUAL LAYER HARDMASK FOR EMBEDDED EPI GROWTH - A process for forming an integrated circuit with an embedded epitaxially grown semiconductor using an epi blocking bilayer. The epi blocking bilayer comprised of a two different materials that may be etched selectively with respect to each other such as silicon nitride and silicon dioxide. | 2015-07-02 |
20150187662 | METHOD AND/OR SYSTEM FOR CHEMICAL MECHANICAL PLANARIZATION (CMP) - One or more methods or systems for performing chemical mechanical planarization (CMP) are provided. The system includes at least one of an emitter, a detector, a spectroscopic signal generator, a comparator, a spectral library, a controller or a CMP device. A spectroscopic signal is generated and is used to determine the thickness of a first material formed on or from a wafer by comparing the spectroscopic signal to a spectral library. Responsive to the thickness not being equal to the desired thickness, the controller instructs the CMP device to perform a rotation to reduce the thickness of the first material. The system and method herein increase the sensitivity of the CMP, such that the thickness of the first material is reduced with greater accuracy and precision, as compared to where the thickness is not measured between consecutive rotations of a wafer. | 2015-07-02 |
20150187663 | SYSTEMS AND METHODS OF LOCAL FOCUS ERROR COMPENSATION FOR SEMICONDUCTOR PROCESSES - A system and method of compensating for local focus errors in a semiconductor process. The method includes providing a reticle and applying, at a first portion of the reticle, a step height based on an estimated local focus error for a first portion of a wafer corresponding to the first portion of the reticle. A multilayer coating is formed over the reticle and an absorber layer is formed over the multilayer coating. A photoresist is formed over the absorber layer. The photoresist is patterned, an etch is performed of the absorber layer and residual photoresist is removed. | 2015-07-02 |
20150187664 | High Productivity Combinatorial Testing of Multiple Work Function Materials on the Same Semiconductor Substrate - Provided are methods of high productivity combinatorial (HPC) screening of work function materials. Multiple test materials may be deposited as separate blanket layers on the same substrate while still forming individual interfaces with a common base layer. The thickness of each test material layer ensures that its work function properties are not impacted when other layers are deposited over that layer. A method may involve depositing a blocking layer over the base layer and selectively removing the blocking layer from a first site isolated region. A first test material is then deposited as a blanket layer and forms an interface with the base layer in that first region only. The first test material layer and the blocking layer are selectively removed from a second site isolated region followed by depositing a second test material layer as another blanket layer, which forms an interface with the base layer in the second region only. | 2015-07-02 |
20150187665 | METHODS OF PREDICTING UNITY GAIN FREQUENCY WITH DIRECT CURRENT AND/OR LOW FREQUENCY PARAMETERS - Various embodiments include approaches for predicting unity gain frequency in a MOSFET. In some cases, a method includes predicting a unity gain frequency (f | 2015-07-02 |
20150187666 | INTEGRATED CIRCUIT COMPRISING BUFFER CHAIN - Among other things, an integrated circuit and method for routing electrical pathways of an integrated circuit is provided. The integrated circuit comprises a buffer chain coupling a first cell of the integrated circuit to a second cell of the integrated circuit. An electrical pathway coupling a first inverter of the buffer chain with a second inverter of the buffer chain extends through a first set of metal layers and is routed to form a pulse-like shape having an apex at a top layer of the first set. | 2015-07-02 |
20150187667 | INLINE MEASUREMENT OF THROUGH-SILICON VIA DEPTH - A through-silicon via (TSV) capacitive test structure and method of determining TSV depth based on capacitance is disclosed. The TSV capacitive test structure is formed from a plurality of TSV bars that are evenly spaced. A first group of bars are electrically connected to form a first capacitor node, and a second group of bars is electrically connected to form a second capacitor node. The capacitance is measured, and a TSV depth is computed, prior to backside thinning. The computed TSV depth may then be fed to downstream grinding and/or polishing tools to control the backside thinning process such that the semiconductor wafer is thinned such that the backside is flush with the TSV. | 2015-07-02 |
20150187668 | SEMICONDUCTOR DEVICE - A semiconductor device includes an insulating substrate on which semiconductor elements are mounted and a surrounding case in which the insulating substrate is housed. Two terminal conductors, both ends of each of which are fixed in sidewalls of the surrounding case, are provided between the sidewalls, and connection terminals protruding toward the insulating substrate side are provided on the respective terminal conductors. The connection terminals and a conductive foil on the insulating substrate are soldered together. Insulating blocks for keeping the distance between the adjacent terminal conductors at a fixed distance or greater are provided in the vicinity of the central portion of the terminal conductor. The insulating blocks suppress the terminal conductor being deformed by being thermally expanded when soldering. Because of this, it is possible to stabilize solderability, and it is possible to prevent an occurrence of defective connection. | 2015-07-02 |
20150187669 | SEMICONDUCTOR DEVICE - A miniaturized semiconductor device includes a frame body having an opening region formed in a central portion, an insulating substrate which is provided in the opening region of the frame body and on which semiconductor chips are mounted, lead portions, each including an inclined portion that is at least partially exposed to the opening region formed in the frame body and extends so as to be inclined with respect to an end surface forming the opening region, and a bonding wire that is bonded between the lead portion and the semiconductor chip by ultrasonic bonding. | 2015-07-02 |
20150187670 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, AND RINSING LIQUID - A method for manufacturing a semiconductor device including: a process of applying a sealing composition for a semiconductor to a semiconductor substrate, to form a sealing layer for a semiconductor on at least the bottom face and the side face of a recess portion of an interlayer insulating layer, the sealing composition including a polymer having a cationic functional group and a weight average molecular weight of from 2,000 to 1,000,000, each of the content of sodium and the content of potassium in the sealing composition being 10 ppb by mass or less on an elemental basis; and a process of subjecting a surface of the semiconductor substrate at a side at which the sealing layer has been formed to heat treatment of from 200° C. to 425° C., to remove at least a part of the sealing layer. | 2015-07-02 |
20150187671 | SEMICONDUCTOR DEVICE - A semiconductor device according to the invention includes an insulating substrate including an insulating plate, a circuit pattern that is formed on a front surface of the insulating plate, and a radiator plate that is fixed to a rear surface of the insulating plate, a semiconductor chip that is fixed to the circuit pattern, an external lead terminal that is connected to a surface electrode of the semiconductor chip through a wiring line, a molding resin that covers the insulating substrate, the semiconductor chip, the wiring line, and the external lead terminal such that a rear surface of the radiator plate and a portion of the external lead terminal are exposed, and an anchor layer including a stripe-shaped concave portion which is formed in the circuit pattern by laser beam irradiation. | 2015-07-02 |
20150187672 | METAL OXIDE SEMICONDUCTOR STRUCTURE - A metal oxide semiconductor structure, the structure including: a substrate; a gate electrode, deposited on the substrate; a gate insulation layer, deposited over the gate electrode and the substrate; an IGZO layer, deposited on the gate insulation layer and functioning as a channel; a source electrode, deposited on the gate insulation layer and being at one side of the IGZO layer; a drain electrode, deposited on the gate insulation layer and being at another side of the IGZO layer; a first passivation layer, deposited over the source electrode, the IGZO layer, and the drain electrode; a second passivation layer, deposited over the first passivation layer; and an opaque resin layer, deposited over the source electrode, the second passivation layer, and the drain electrode. | 2015-07-02 |
20150187673 | REDUCED STRESS TSV AND INTERPOSER STRUCTURES - A microelectronic component with circuitry includes a substrate (possibly semiconductor) having an opening in a top surface. The circuitry includes a conductive via (possibly metal) in the opening. The opening has a first sidewall of a first material, and the conductive via has a second sidewall of a second material (possibly metal). At least at one side of the opening, the first and second sidewalls are spaced from each other at the top surface of the substrate but the first and second sidewalls meet below the top surface of the substrate at a meeting location. Between the meeting location and the top surface of the substrate, the first and second sidewalls are separated by a third material (possibly foam) which is a dielectric different from the first material. The third material lowers thermal stress in case of thermal expansion compared to a structure in which the third material were replaced with the second material. | 2015-07-02 |
20150187674 | SEMICONDUCTOR DEVICE - A surface of a power semiconductor chip, mounted within a power semiconductor module and not being opposed to a wiring thin film, and a surface of a bonding wire are sealed with a resin that does not contain a thermally-conductive filler, and the resin that does not contain a thermally-conductive filler is sealed with a resin that contains a thermally-conductive filler. | 2015-07-02 |
20150187675 | METHODS AND APPARATUS FOR DISSIPATING HEAT FROM A DIE ASSEMBLY - An embodiment of a method facilitates heat dissipation from a die assembly. The method includes removing material from a first side of a die of the die assembly to create a set of recesses in the first side of the die, and depositing a metal-containing layer over the first side of the die to form a heat spreader that contains a set of contours that fill the set of recesses. An embodiment of a die assembly fabricated using the method includes an assembly substrate and a die with a set of recesses formed in a first side of the die. The die assembly also includes an encapsulant formed on the assembly substrate that is absent at least over the set of recesses, and a heat spreader affixed to the first side of the die that includes a set of contours that fill the set of recesses in the die. | 2015-07-02 |
20150187676 | ELECTRONIC COMPONENT MODULE - An electronic component module may include a substrate configured to have a cavity formed therein, and an electronic component embedded in the cavity while being attached to one surface of the heat radiating plate. The electronic component module may significantly decrease effects of element interference and electromagnetic wave interference between electronic components by forming a wiring pattern above a cavity. | 2015-07-02 |
20150187677 | Lid for Integrated Circuit Package - A lid has a heat conductive substrate, a crystallized amorphous silicon layer and a native silicon oxide layer formed on the crystallized amorphous silicon layer. Another embodiment has a lid with a copper substrate and a native silicon oxide layer connected to the substrate by at least one intermediate layer. A method of providing a heat path through an integrated circuit package includes providing a substrate with an exterior layer of native silicon oxide and interfacing the layer of native silicon oxide with a layer of thermal interface material. | 2015-07-02 |
20150187678 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device may include: a first conductivity-type first semiconductor layer; a second conductivity-type second semiconductor layer disposed above the first semiconductor layer; and a heat dissipation trench disposed to penetrate from an upper surface of the second semiconductor layer into a portion of the second semiconductor layer and having an insulating layer disposed on a surface thereof. | 2015-07-02 |
20150187679 | Lid Design for Heat Dissipation Enhancement of Die Package - Embodiments of a lid covering a device die improving heat dissipation for a die package are described. Trenches are formed on the bottom side of a lid to increase surface area for heat dissipation. Various embodiments of the trenches on the lid are described. The layout and design of the trenches could be optimized to meet the heat dissipation need of the device die(s). By using the lid with trenches, heat dissipation efficiency is improved and the amount of thermal interface material (TIM) could be reduced. In addition, the selection of thermal interface materials for the lid is widened. | 2015-07-02 |
20150187680 | SEMICONDUCTOR APPARATUS, MANUFACTURING METHOD THEREOF AND TESTING METHOD THEREOF - A semiconductor apparatus includes one or more semiconductor chips. Each semiconductor chip includes a semiconductor substrate formed with a through-silicon via, and a bottom wiring layer with a first dielectric layer formed on a bottom of the semiconductor substrate. A first opening is defined in the first dielectric layer. | 2015-07-02 |
20150187681 | FLEXIBLE MICROELECTRONIC ASSEMBLY AND METHOD - This disclosure relates generally to a system and method including a substrate and an electronic component. The substrate includes a circuit board including a hole, a routing layer, and a first interconnect portion positioned, at least in part, within the hole. The electronic component includes a second interconnect portion, coupled to the first interconnect portion, forming an interconnect between the electronic component and the routing layer. | 2015-07-02 |
20150187682 | SEMICONDUCTOR DEVICE - A semiconductor device is reduced in size. The semiconductor device includes a die pad, a plurality of leads arranged around the die pad, a memory chip and a power source IC chip mounted over the die pad, a logic chip mounted over the memory chip, a plurality of down bonding wires for connecting the semiconductor chip to the die pad, a plurality of lead wires for connecting the semiconductor chip to leads, and a plurality of inter-chip wires. Further, the logic chip is arranged at the central part of the die pad in a plan view, and the power source IC chip is arranged in a corner part region of the die pad in the plan view. This reduces the size of the QFN. | 2015-07-02 |
20150187683 | QFN PACKAGE AND METHOD FOR FORMING QFN PACKAGE - The present invention relates to a semiconductor package and a method for forming a semiconductor package. A lead frame adapted to a semiconductor package includes a first carrier, an adjacent second carrier, a first array of leads, and a second array of leads. The first array and the second array of leads are configured to be connected to circuits located at the first and second carriers at respective near sides of the arrays. The first array of leads and the second array of leads are connected through connecting ribs, and a groove is provided on exposed surfaces. After the connecting rib is removed, a part of the groove still remains. The to remaining part of the groove is exposed in a separate die package, and in a surface-mount procedure, molten solder achieves wetting more easily along the groove to make surface mounting more secure. | 2015-07-02 |
20150187684 | SEMICONDUCTOR PACKAGE - There is provided a semiconductor package capable of preventing a lead frame from being separated from a molded portion during a manufacturing process. The semiconductor package according to an exemplary embodiment in the present disclosure includes: at least one electronic device; a lead frame including a plurality of leads electrically connected to the electronic device; a lead connecting member coupled to at least one of the leads; and a molded portion sealing the electronic device and the lead connecting member. | 2015-07-02 |
20150187685 | LEADFRAME ASSEMBLY, HOUSING ASSEMBLY, MODULE ASSEMBLY AND METHOD OF DETERMINING AT LEAST ONE VALUE OF A MEASUREMENT VARIABLE OF AN ELECTRONIC MODULE - A leadframe assembly is formed from an electrically conductive material. The leadframe assembly includes a first longitudinal element, at least one second longitudinal element, a plurality of first leadframe sections and a plurality of second leadframe sections. | 2015-07-02 |
20150187686 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device that includes a circuit board, a semiconductor element mounted to the circuit board, a control signal terminal disposed on the opposite side of the semiconductor element from the circuit board, and a bonding wire connecting the semiconductor element and the control signal terminal. | 2015-07-02 |
20150187687 | Semiconductor Device - A trench portion (trench or groove) is formed at each of four corner portions of a chip bonding region having a quadrangular planar shape smaller than an outer-shape size of a die pad included in a semiconductor device. Each trench is formed along a direction of intersecting with a diagonal line which connects between the corner portions where the trench portions are arranged, and both ends of each trench portion are extended to an outside of the chip bonding region. The semiconductor chip is mounted on the chip bonding region so as to interpose a die-bond material. In this manner, peel-off of the die-bond material in a reflow step upon mounting of the semiconductor device on a mounting substrate can be suppressed. Also, even if the peel-off occurs, expansion of the peel-off can be suppressed. | 2015-07-02 |
20150187688 | Method For Treating A Leadframe Surface And Device Having A Treated Leadframe Surface - A method for manufacturing an integrated circuit device is disclosed. A leadframe is provided having a die support area configured to receive an integrated circuit die and a plurality of leadframe fingers adjacent the die support area, each leadframe finger including a finger tip area at one end of the leadframe finger. The leadframe is masked such that one or more areas of the leadframe are covered and one or more areas of the leadframe are exposed, wherein for each leadframe finger, a first region of the respective finger tip area is covered by the masking and a second region of the respective finger tip area is exposed. The one or more exposed areas of the leadframe are silver plated such for each leadframe finger, the second region of the respective finger tip area is sliver plated and the first region of the respective finger tip area is not sliver plated. | 2015-07-02 |
20150187689 | SEMICONDUCTOR DEVICE - The semiconductor device includes an insulating substrate on which is mounted a main circuit part including a semiconductor chip, a printed substrate wherein a conductive connection member connected to the semiconductor chip is disposed on the surface opposing the insulating substrate, a first sealing member that seals so as to enclose the semiconductor chip between the opposing surfaces of the insulating substrate and printed substrate, and a second sealing member that covers the whole excepting a bottom portion of the insulating substrate, the semiconductor device having sealing region regulation rod portions disposed in an outer peripheral portion of a sealing region of the first sealing member and connected between the insulating substrate and printed substrate, wherein the heat resistance temperature of the first sealing member is set to be higher than the heat resistance temperature of the second sealing member. | 2015-07-02 |
20150187690 | IC PACKAGE WITH METAL INTERCONNECT STRUCTURE IMPLEMENTED BETWEEN METAL LAYERS OF DIE AND INTERPOSER - An integrated circuit package includes a die having a first substrate implementing an integrated circuit comprising circuit elements. The die includes a first plurality of metal layers implementing a first portion of a metal interconnect structure for the integrated circuit. The die also includes a first plurality of pads at or overlying a top metal layer of the first plurality of metal layers. The integrated circuit package includes an interposer having a second plurality of metal layers implementing a second portion of the metal interconnect structure. The interposer includes a second plurality of pads at or overlying a top metal layer of the second plurality of metal layers. A plurality of solder structures couple the first and second pluralities of pads. The first and second portions of the metal interconnect structure together complete a signal path between two or more circuit blocks of the integrated circuit. | 2015-07-02 |
20150187691 | THREE-DIMENSIONAL ELECTRONIC PACKAGES UTILIZING UNPATTERNED ADHESIVE LAYER - An electronic package may be fabricated by forming a first layer of insulating material on a first substrate such that the first layer covers a contact pad; forming an opening through the first layer to expose the contact pad; forming an un-patterned second layer on the first layer, the second layer including an adhesive having a viscosity less than that of the first layer, wherein a region of the second layer obstructs the contact pad; removing the region to re-expose the contact pad; aligning a second substrate with the first substrate such that a via of the second substrate is aligned with the opening; bonding the first substrate and the second substrate together at the second layer; and forming an interconnect in contact with the contact pad by depositing a conductive material through the via and the opening. | 2015-07-02 |
20150187692 | PACKAGING SUBSTRATE HAVING A THROUGH-HOLED INTERPOSER - A through-holed interposer is provided, including a board body, a conductive gel formed in the board body, and a circuit redistribution structure disposed on the board body. The conductive gel has one end protruding from a surface of the board body, and an area of the protruded end of the conductive gel that is in contact with other structures (e.g., packaging substrates or circuit structures) is increased, thereby strengthening the bonding of the conductive gel and reliability of the interposer. | 2015-07-02 |
20150187693 | SEMICONDUCTOR DEVICE - An embodiment of the invention relates to a semiconductor device comprising: first and second electrodes comprising first and second busbars respectively that decrease in cross section in opposite directions; and a plurality of interleaving first and second conducting fingers that extend from the first and second busbars respectively. | 2015-07-02 |
20150187694 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a stacked structure, a dielectric layer, a conductive structure, a dielectric structure and a conductive plug. The stacked structure includes dielectric films and conductive films arranged alternately. The dielectric layer is between the conductive structure and a sidewall of the stacked structure. The dielectric structure is on the stacked structure and defining a through via. The conductive plug fills the through via and physically contacts one of the conductive films exposed by the through via and adjoined with the dielectric layer. | 2015-07-02 |
20150187695 | Staggered Via Redistribution Layer (RDL) for a Package - An embodiment staggered via redistribution layer (RDL) for a package includes a first polymer layer supported by a metal via. The first polymer layer has a first polymer via. A first redistribution layer is disposed on the first polymer layer and within the first polymer via. The first redistribution layer is electrically coupled to the metal via. A second polymer layer is disposed on the first redistribution layer. The second polymer layer has a second polymer via laterally offset from the first polymer via. A second redistribution layer is disposed on the second polymer layer and within the second polymer via. The second redistribution layer is electrically coupled to the first redistribution layer. | 2015-07-02 |
20150187696 | Interconnect Structure and Method of Forming the Same - An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a low-k (LK) dielectric layer over a substrate; a first conductive feature and a second conductive feature in the LK dielectric layer; a first spacer along a first sidewall of the first conductive feature; a second spacer along a second sidewall of the second conductive feature, wherein the second sidewall of the second conductive feature faces the first sidewall of the first conductive feature; an air gap between the first spacer and the second spacer; and a third conductive feature over the first conductive feature, wherein the third conductive feature is connected to the first conductive feature. | 2015-07-02 |
20150187697 | Interconnect Structure for Semiconductor Devices - An interconnect and a method of forming an interconnect for a semiconductor device is provided. The interconnect is formed by treating an upper surface of a dielectric layer to create a high density layer. The treatment may include, for example, creating a high density monolayer using hexamethyldisilazane (HMDS), trimethylsilydiethylamine (TMSDEA) or trimethylsilylacetate (OTMSA). After treating, the dielectric layer may be patterned to create openings, which are subsequently filled with a conductive material. Excess conductive material may be removed using, for example, a chemical mechanical polishing. | 2015-07-02 |
20150187698 | SEMICONDUCTOR APPARATUS AND AN IMPROVED STRUCTURE FOR POWER LINES - A semiconductor apparatus includes a first power supply pad configured to supply a first power; a second power supply pad configured to supply a second power; a first power line configured to be directly electrically coupled to the first power supply pad; and a second power line configured to be directly electrically coupled to the second power supply pad. | 2015-07-02 |
20150187699 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - Semiconductor devices are provided. A semiconductor device includes gaps between conductive patterns. Moreover, the semiconductor device includes a permeable layer on the conductive patterns. Methods of fabricating semiconductor devices are also provided. | 2015-07-02 |
20150187700 | RELIABLE INTERCONNECTS - Semiconductor device and method for forming a semiconductor device are presented. The method includes providing a substrate prepared with intermediate dielectric layer having interconnect levels. The interconnect levels include M | 2015-07-02 |
20150187701 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first semiconductor chip including a first substrate and a first conductive feature formed over the first substrate, and a second semiconductor chip bonded to the first semiconductor chip. The second semiconductor chip includes a second substrate and a second conductive feature formed over the second substrate. A conductive plug is disposed through the first conductive feature and is coupled to the second conductive feature. The conductive plug includes a first portion disposed over the first conductive feature, the first portion having a first width, and a second portion disposed beneath or within the first conductive feature. The second portion has a second width. The first width is greater than the second width. | 2015-07-02 |
20150187702 | MIDDLE-OF-THE-LINE CONSTRUCTS USING DIFFUSION CONTACT STRUCTURES - An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions. | 2015-07-02 |
20150187703 | BOX-IN-BOX OVERLAY MARK - A box-in-box overlay mark is described, including an inner box region and an outer box region surrounding the same, dense narrow trenches in the previous layer in the inner box region and the outer box region, x- and y-directional linear photoresist patterns defining a rectangle over the narrow trenches in the inner box region, and x- and y-directional linear patterns defining another rectangle in the outer box region. At least the narrow trenches in the inner box region are orientated in a direction different from the x-direction and the y-direction. The linear photoresist patterns are defined in or from a photoresist layer for defining a current layer, each of which is wider than each of the narrow trenches. The linear patterns are defined in or from the previously layer, each of which is wider than each of the narrow trenches. | 2015-07-02 |
20150187704 | METHOD OF JOINING SEMICONDUCTOR SUBSTRATE - A method of joining semiconductor substrates, which may include: forming an alignment key on a first semiconductor substrate; forming an insulating layer on the first semiconductor substrate and the alignment key; forming a first metal layer pattern and a second metal layer pattern on the insulating layer; forming a first protrusion and a second protrusion, and an alignment recess positioned between the first protrusion and the second protrusion on a second semiconductor substrate; forming a third metal layer pattern and a fourth metal layer pattern on the first protrusion and the second protrusion, respectively; and joining the first semiconductor substrate and the second semiconductor substrate, in which the alignment key is positioned at the alignment recess when the first semiconductor substrate and the second semiconductor substrate are joined, is provided. | 2015-07-02 |
20150187705 | SEMICONDUCTOR PACKAGE HAVING EMI SHIELDING AND METHOD OF FABRICATING THE SAME - A semiconductor package includes a dielectric layer in which a chip is embedded, interconnection parts disposed on a first surface of the dielectric layer, through connectors each of which penetrates a portion of the dielectric layer over the chip to electrically couple the chip to a corresponding one of the interconnection parts, a shielding plate covering a second surface of the dielectric layer that is opposite to the first surface, and a shielding encapsulation part connected to one of the interconnection parts and covering sidewalls of the dielectric layer. The shielding encapsulation part includes a portion contacting the shielding plate. | 2015-07-02 |
20150187706 | Semiconductor Device Having Metal Lines with Slits - A semiconductor device including a semiconductor substrate, an integrated circuit on the semiconductor substrate, an insulation layer covering the integrated circuit, and a plurality of metal line patterns on the insulation layer. First and second adjacent metal line patterns of the plurality of metal line patterns are spaced apart from each other by a space, and each of the first and second adjacent metal line patterns has at least one slit. | 2015-07-02 |
20150187707 | Biometric Image Sensor Packaging and Mounting - A method for providing a biometric sensor arrangement includes: forming the biometric sensor comprising sensor elements and a controller IC disposed on a substrate; at least partially enclosing the biometric sensor within a molded body; depositing capping material on the biometric sensor to form a capping layer on the biometric sensor; embossing the capping material of the capping layer; and curing the capping layer. | 2015-07-02 |
20150187708 | Thermal Flow Meter - Provided is a thermal flow meter that can be prevented from being eroded due to adhesion of water or like to a cut end portion of the lead exposed from the mold resin of the circuit package. A thermal flow meter | 2015-07-02 |
20150187709 | METAL FUSE BY TOPOLOGY - Embodiments of the present disclosure describe techniques and configurations for overcurrent fuses in integrated circuit (IC) devices. In one embodiment, a device layer of a die may include a first line structure with a recessed portion between opposite end portions and two second line structures positioned on opposite sides of the first line structure. An isolation material may be disposed in the gaps between the line structures and in a first recess defined by the recessed portion. The isolation material may have a recessed portion that defines a second recess in the first recess, and a fuse structure may be disposed in the second recess. Other embodiments may be described and/or claimed. | 2015-07-02 |