27th week of 2009 patent applcation highlights part 73 |
Patent application number | Title | Published |
20090172398 | Method and Arrangement for Providing a Wireless Mesh Network - Provided are a method and an arrangement for creating a wireless mesh network in which a new node is provided that is connected between mesh nodes and an AAA server located in an infrastructure network. Based on basic encoding data that is available to the new node following successful initial authentication of a first mesh node, the new node performs the authentication similar to a proxy server instead of an AAA server, particularly for a limited time, during subsequent authentication attempts. | 2009-07-02 |
20090172399 | Communication System For Providing The Delivery of E-Mail Message - A communication system comprising a sender unit, a recipient unit and a control unit, wherein the sender unit is adapted to generate an electronic message, to send the electronic message directly to the recipient unit, and to send a sending information message to the control unit indicating that the sender unit has sent the electronic message to the recipient unit, wherein the recipient unit is adapted to receive the electronic message directly from the sender unit and to send a receipt information message to the control unit, the receipt information message indicating that a user of the recipient unit has received the electronic message. | 2009-07-02 |
20090172400 | DIGITAL CONTENT DISTRIBUTION AND CONSUMPTION - Digital content distribution and consumption that provides the advantages of digital content being locally stored under user control while concurrently having the widest acceptance by legacy players/platforms (i.e., no need to perform complex software integration) while still remaining compatible with state of the art security in order to satisfy content provider requirements. | 2009-07-02 |
20090172401 | METHOD AND SYSTEM FOR CONTROLLING A DEVICE - A system and method for controlling a device. Data that was encrypted using a first encryption scheme is decrypted, then re-encrypted using a second encryption scheme. The re-encrypted data is then decrypted. | 2009-07-02 |
20090172402 | Multi-factor authentication and certification system for electronic transactions - The present invention provides computer-enable certification and authentication in, for example, e-commerce with wireless and mobile devices. The present authentication method offers ease of operation by automatically embedding a one-time passcode to the message without the sender input. A one-time key can also be used to encrypt the message, further providing transmission security. In addition, sensitive information and one-time passcode generator are pre-arranged and stored at both sender and receiver devices, avoiding information comprising in wireless environment transmission. | 2009-07-02 |
20090172403 | METHOD AND SYSTEM FOR GENERATING AND DISTRIBUTING MOBILE IP SECURITY KEY AFTER REAUTHENTICATION - A method for generating and distributing MIP security key after Re-Authentication, including: an AAA Server generates an EMSK during a Re-Authentication process; the MS generate a new first MIP security key for the MS according to the EMSK, and replaces the corresponding old first MIP security key with the new first MIP security key; and a HA receives new second MIP security key information for the HA which is sent by the AAA Server actively, or requests from the AAA Server the new second MIP security key information for the HA, and replaces the corresponding old second MIP security key that is locally stored with the new second MIP security key that is sent by the AAA Server actively or requested from the AAA Server. The present invention ensures execution of MIP Registration process after Re-Authentication. | 2009-07-02 |
20090172404 | Method and Apparatus for Hybrid Watermarking - A hybrid watermark insertion method includes the steps of dividing the digital image into a low frequency region and a high frequency region using an edge map of the digital image; inserting a watermark into the low frequency region of the image by employing a watermarking method using a human visual system (HVS); and inserting the watermark into the high frequency region of the image by employing a quantization index modulation (QIM) method. A hybrid watermark extraction method includes the steps of estimating a reference value used when inserting a watermark, and searching a maximum value of correlation coefficients in an image of the watermark image while changing the estimated reference value within a designated range, to thereby find out the watermark insertion method. Accordingly, the watermark insertion method can be easily identified, thereby enabling the watermark extraction in a more readily manner. | 2009-07-02 |
20090172405 | AUDIO DATA PROCESSING APPARATUS AND AUDIO DATA PROCESSING METHOD - According to one embodiment, an audio data processing apparatus of this invention comprises a decryption unit which selects audio data to be reproduced under copyright protection, an HDMI unit which outputs the audio data selected by the decryption unit in the form of a bitstream to an AV amplifier connected via a dedicated cable, and a system control unit which acquires specification identification data from the AV amplifier before the bitstream output of the audio data and recognizes a watermark detection function of the AV amplifier on the basis of the specification identification data. | 2009-07-02 |
20090172406 | METHOD AND SYSTEM FOR PROTECTING PATIENT DATA - A method for a medical system to transmitting patient information to an external USB storage device includes checking the validity of the USB storage device according to the registered information therein, generating a new identification file according to a new times of using value that is incremented each time the validity checks are passed, and a unique ID number of the USB device, and writing the new identification file into the USB storage device to replace the old identification file. | 2009-07-02 |
20090172407 | VIRTUAL SMART CARD SYSTEM AND METHOD - A public key authentication system and method for use in a computer system having a plurality of users. The system includes a virtual smart card server, storage connected to the virtual smart card server, and a virtual smart card agent connected to the virtual smart card server. The storage includes a plurality of virtual smart cards, wherein each virtual smart card is associated with a user and wherein each smart card includes a private key. The virtual smart card agent authenticates the user and accesses the authenticated user's virtual smart card to obtain the user's private key. | 2009-07-02 |
20090172408 | METHOD AND SYSTEM FOR MANAGING THE DISPLAY OF SENSITIVE CONTENT IN NON-TRUSTED ENVIRONMENTS | 2009-07-02 |
20090172409 | CORE DUMP PRIVACY DURING APPLICATION FAILURE - Embodiments of the present invention address deficiencies of the art in respect to core dump generation during application fault handling and provide a method, system and computer program product for privacy preservation of core dump data during application fault handling. In an embodiment of the invention, a method for privacy preservation of core dump data during application fault handling can be provided. The method can include receiving a crash signal for an application and generating a core dump with object data for the application. The method further can include obfuscating the object data in the core dump and writing the core dump with obfuscated object data to a file. In this way, the privacy of the object data in the core dump can be preserved. | 2009-07-02 |
20090172410 | PERSONAL VAULT - In some embodiments data input to an input device is encrypted before it is received by any software, and information is stored securely so that the information is not accessible to any software. Other embodiments are described and claimed. | 2009-07-02 |
20090172411 | Protecting the security of secure data sent from a central processor for processing by a further processing device - A data processing apparatus comprising: a data processor for processing data in a secure and a non-secure mode, said data processor processing data in said secure mode having access to secure data that is not accessible to said data processor in said non-secure mode, and processing data in said secure mode being performed under control of a secure operating system and processing data in said non-secure mode being performed under control of a non-secure operating system; and a further processing device for performing a task in response to a request from said data processor, said task comprising processing data at least some of which is secure data; wherein said further processing device is responsive to receipt of a signal to suspend said task to initiate: processing of said secure data using a secure key; and storage of said processed secure data to a non-secure data store; and is responsive to receipt of a signal to resume said task to initiate: retrieval of said processed secure data from said non-secure data store; and restoring of said processed secure data using said secure key; wherein said secure key is securely stored such that it is not accessible to other processes operating in said non-secure mode. | 2009-07-02 |
20090172412 | SYSTEM FOR AND METHOD OF AUTO-REGISTRATION WITH CRYPTOGRAPHIC MODULES - A system for and method of registering devices an applications with cryptographic modules is presented. The system and method prevent devices and applications from operating in conjunction with cryptographic modules unless such devices and applications have previously been registered with the module. | 2009-07-02 |
20090172413 | High Speed Cryptographic System with Modular Architecture - The present invention concerns a cryptographic system ( | 2009-07-02 |
20090172414 | DEVICE AND METHOD FOR SECURING SOFTWARE - A device that includes a first memory unit adapted to store encrypted instructions, a processor adapted to execute decrypted instructions, a second memory unit accessible by the processor, and a decryption unit. The device is characterized by including a key database and a key selection circuit, wherein the key selection circuit is adapted to select a selected decryption key from the key database for decrypting encrypted instructions. The selection is responsive to a fixed selection information stored within the integrated circuit and to received key selection information. | 2009-07-02 |
20090172415 | PROCESSOR APPARATUS - The control unit includes a CPU which generates an access signal for performing writing or reading on the external memory, encryption/decryption means which, when the access signal is used for writing, encrypts an address designated by the CPU to generate a write address and encrypts write data contained in the access signal to generate write encrypted data, and which, when the access signal is used for reading, encrypts an address designated by the CPU to generate a read address and decrypts the encrypted data read from the external memory to generate plaintext data, and external control means which writes the write encrypted data in a position designated by the write address generated by the encryption/decryption means and which reads the encrypted data from a position designated by the read address generated by the encryption/decryption means and supplies the same to the encryption/decryption means for its decryption. | 2009-07-02 |
20090172416 | Storage and Retrieval of Encrypted Data Blocks with In-Line Message Authentication Codes - Techniques are disclosed for in-line storage of message authentication codes with respective encrypted data blocks. In one aspect, a given data block is encrypted and a message authentication code is generated for the encrypted data block. A target address is determined for storage of the encrypted data block in a memory. The target address is then modified to permit in-line storage of the message authentication code with the encrypted data block in the memory, and the encrypted data block and the message authentication code are transferred to the memory for storage at the modified address. Illustrative embodiments of the techniques advantageously facilitate secure off-chip storage of data in a processing system. | 2009-07-02 |
20090172417 | KEY MANAGEMENT METHOD FOR REMOTE COPYING - A computer system comprising a host computer and a first storage system coupled to the host computer. The first storage system includes a first controller for controlling the first storage system, a first volume for storing data written by the host computer and a second volume for storing updated data when the data stored in the first volume is updated The first controller generates update information based on write data contained in the write request upon reception of a write request from the host computer, encrypts the write data based on an encrypted status of the data stored in the second volume and an encryption key for encrypting the data stored in the second volume and stores the generated update information and the encrypted write data in the second volume. | 2009-07-02 |
20090172418 | Methods and Apparatus for Efficient Computation of One-Way Chains in Cryptographic Applications - Techniques are disclosed for efficient computation of consecutive values of one-way chains and other one-way graphs in cryptographic applications. The one-way chain or graph may be a chain of length s having positions i=1, 2, . . . s each having a corresponding value ν | 2009-07-02 |
20090172419 | DATA STORAGE DEVICE, MANAGEMENT SERVER, INTEGRATED CIRCUIT, DATA UPDATE SYSTEM, HOME ELECTRIC APPARATUSES, DATA UPDATE METHOD, ENCRYPTION METHOD, AND ENCRYPTION/DECRYPTION KEY GENERATION METHOD - Provided is a data storage device capable of safely and effectively updating software of a home electric apparatus. In the home electric apparatus ( | 2009-07-02 |
20090172420 | TAMPER RESISTANT METHOD AND APPARATUS FOR A STORAGE DEVICE - A method for authenticating software for use in a device includes encrypting software to be input to a device with a private key, and decrypting the software presented to the device with a public key retrieved from a memory accessible by the device. | 2009-07-02 |
20090172421 | FACILITATING COMMUNICATION AND POWER TRANSFER BETWEEN ELECTRICALLY-ISOLATED POWERED DEVICE SUBSYSTEMS - A system employing power over Ethernet (PoE) technology may include at least one powered device and power sourcing equipment (PSE). The powered device may include a first powered device (PD) subsystem and a second powered device (PD) subsystem that is electrically isolated from the first PD subsystem. The powered device may also include an interface connecting the first PD subsystem and the second PD subsystem. The PSE may be operable to provide power to one or more of the PD subsystems through a link connecting the PSE to the powered device. Also, the first PD subsystem may be operable to receive a communication from and transfer power to the second PD subsystem through the interface while maintaining the electrical isolation. | 2009-07-02 |
20090172422 | KEYBOARD WITH DETACHABLE RECHARGEABLE MOUSE - In one embodiment an electronic device comprising a keyboard coupled to a power supply and a mouse coupled to the keyboard. In one embodiment the keyboard further has a docking station into which the rechargeable mouse or other input device can be mounted. Furthermore, in one embodiment, the mouse can be used while in the keyboard or when separated from the keyboard through a wired or wireless connection. | 2009-07-02 |
20090172423 | METHOD, SYSTEM, AND APPARATUS FOR REROUTING INTERRUPTS IN A MULTI-CORE PROCESSOR - A method, system, and apparatus may route an interrupt to a first core of a plurality of cores of a multi-core system. If the first core is in an idle or low power state, or operating in a power state at or below a threshold power state, a core in a least idle state may be found. The interrupt may be rerouted to and processed by the core in the least idle state. Cores in a multi-core system may be rated based on for example, power states or other characteristics, and interrupts may be assigned based on these ratings. Other embodiments are described and claimed. | 2009-07-02 |
20090172424 | THREAD MIGRATION TO IMPROVE POWER EFFICIENCY IN A PARALLEL PROCESSING ENVIRONMENT - A method and system to selectively move one or more of a plurality threads which are executing in parallel by a plurality of processing cores. In one embodiment, a thread may be moved from executing in one of the plurality of processing cores to executing in another of the plurality of processing cores, the moving based on a performance characteristic associated with the plurality of threads. In another embodiment of the invention, a power state of the plurality of processing cores may be changed to improve a power efficiency associated with the executing of the multiple threads. | 2009-07-02 |
20090172425 | Digitally controlled dynamic power management unit for uninterruptible power supply - A memory system power management process includes providing a first level of power to operate a memory system while a primary power source is enabled, detecting an interruption of the primary power source, increasing a frequency of an oscillator driving a charge pump of a power converter providing the first level of power, and beginning a memory operation that increases a load on the power converter. | 2009-07-02 |
20090172426 | PORTABLE ELECTRONIC DEVICE HAVING SYNCHRONOUS PROCESSING MODULE - A portable electronic device includes a system chip, an enabling switch, a signal conversion circuit, a power switching circuit, a storage medium and a synchronous processing module. The enabling switch is triggered to issue an analog signal. The signal conversion circuit converts the analog signal into a digital control signal. The power switching circuit selects one of multiple power sources to be outputted as a voltage signal. The storage medium receives the voltage signal. The synchronous processing module is electrically connected to the system chip, the storage medium, the signal conversion circuit, the power switching circuit and the transmission line. In response to the digital control signal, the storage medium is communicated with an external electronic device through a transmission line, so that the storage medium of the portable electronic device is used as an external storage medium of the external electronic device. | 2009-07-02 |
20090172427 | Method and system for power management of a motherboard - A method for power management of a motherboard is provided to manage a power supply on the motherboard and specially to manage an output power of a power management module on the mother board. The motherboard at least comprises a microprocessor, and the power management module provides a power with a number of output phases to the microprocessor. First, a first load of the microprocessor is detected in a first time. Then a second load of the microprocessor in a second time is detected. When the second load is less than the first load and is lower than a first predetermined value, the number of output phases of the power outputted from the power management module is reduced. | 2009-07-02 |
20090172428 | APPARATUS AND METHOD FOR CONTROLLING POWER MANAGEMENT - The present invention relates to an apparatus and a method for controlling power management based on information on ticks for performing program tasks and information on each of power management states, which is applicable to every apparatus and component able to enter a power saving state. | 2009-07-02 |
20090172429 | POWER MODE CONTROL METHOD AND CIRCUITRY - In some embodiments, a power up (or power mode) interface is provided whereby a chip's power up signals are encoded into multiple states to provide more functions than the number of signals used to define the states. | 2009-07-02 |
20090172430 | ELECTRONIC DEVICE AND POWER-SAVING SETTING METHOD - According to one embodiment, an electronic device includes a connection unit which is connected to a network, a reception unit which receives setting information for making a power-saving setting for a device connected to the network, a sending unit which sends the setting information received by the reception unit to the network via the connection unit, and a setting unit which, upon receiving via the network the setting information from The electronic device connected to the network, makes a power-saving setting based on the received setting information. | 2009-07-02 |
20090172431 | METHOD AND APPARATUS FOR REDUCING POWER CONSUMPTION FOR ISOCHRONOUS DATA TRANSFERS - A method and article for reducing power consumption for isochronous data transfers are described. The method may include receiving packets of data having multimedia information with empty spaces. The packets of data may be stored in a first buffer having a first buffer size allocated for a universal serial bus processing stack. The empty spaces may be removed from the packets of data and the packets of data having the empty spaces removed may be copied to a second buffer having a second buffer size allocated for a media information processing stack. Other embodiments are described and claimed. | 2009-07-02 |
20090172432 | Power management in electronic systems - In one embodiment, an electronic apparatus comprises at least one processor and a computer readable medium coupled to the processor and comprising logic instructions encoded in the computer readable medium, wherein the instructions, when executed in a processing system, cause the processing system to perform operations comprising initializing a direct memory access profiler in an electronic system, wherein the direct memory access is coupled to a policy manager in the electronic system, measuring at least one memory consumption characteristic of the electronic system, communicating the at least one memory consumption characteristic to a policy manager of the electronic system, and using the at least one memory consumption characteristic to adjust a power state of the electronic system. | 2009-07-02 |
20090172433 | Powering on devices via intermediate computing device - Methods and apparatus relating to powering on devices via an intermediate computing device are described. In an embodiment, a request for data by a first device may be detected at a second device. The second device may determine a third device that stores the requested data and cause it to be turned on if the third device is in a reduced power consumption state. Other embodiments are also disclosed. | 2009-07-02 |
20090172434 | Latency based platform coordination - In some embodiments, an electronic apparatus comprises at least one processor, a plurality of components, and a policy engine comprising logic to receive latency data from one or more components in the electronic device, compute a minimum latency tolerance value from the latency data, and determine a power management policy from the minimum latency tolerance value. | 2009-07-02 |
20090172435 | METHOD OF MINIMIZING ELECTRIC POWER CONSUMPTION IN NON-BEACON NETWORK - Disclosed herein is a method of minimizing electric power consumption in a non-beacon network including a parent node which maintains an active state only for a specific period in each predetermined cycle, and a child node which attempts to communicate for periods only when data is generated. When data that must be transmitted to the child node exists, the child node notifies the parent node that there is data to be transmitted. The child node periodically transmits the same message to the parent node until the parent node maintains an initial active state. If the parent node is switched into an active state and receives the data transmission notification message, the parent node commands the child node to transmit data. The child node transmits the data to the parent node. Thereafter, the parent node notifies the child node that the reception of data is normally performed. | 2009-07-02 |
20090172436 | ENERGY SAVING METHOD AND ELECTRONIC DEVICE USING THE SAME - An electronic device for selectively reproducing information. The electronic device includes a display, a power supply for supplying power, a switch, and a processor. The switch is connected to the display and the power supply. The processor is connected to the switch. When the processor identifies that the selected information is audio type, the processor turns off the switch to disconnect an electrical connection between the power supply and the display. A power saving method for reducing the energy consumption of the electronic device is also provided. | 2009-07-02 |
20090172437 | Power Switch and Power Supply Using the Same - A power switch includes a power status providing module, a trigger, and a logic circuit. The power status providing module is configured for providing a first signal when being turned on, and for providing a second signal when being turned off. The trigger is configured for providing a first logic voltage when being pushed down, and for providing a second logic voltage when being released. The logic circuit has a data input terminal, a clock input terminal and an output terminal. The data input terminal is configured for receiving the first signal and the second signal to form a data signal. The clock input terminal is configured for receiving the first logic voltage and the second logic voltage to form an operation clock. The output terminal is configured for outputting a power control signal inverse to the data signal according to the operation clock. | 2009-07-02 |
20090172438 | METHOD AND APPARATUS FOR COST AND POWER EFFICIENT, SCALABLE OPERATING SYSTEM INDEPENDENT SERVICES - A low cost, low power consumption scalable architecture is provided to allow a computer system to be managed remotely during all system power states. In a lowest power state, power is only applied to minimum logic necessary to examine a network packet. Power is applied for a short period of time to an execution subsystem and one of a plurality of cores selected to handle processing of received service requests. After processing the received service requests, the computer system returns to the lowest power state. | 2009-07-02 |
20090172439 | SYSTEM AND METHOD FOR FAST PLATFORM HIBERNATE AND RESUME - In some embodiments, an apparatus includes processor cores, a smaller non-volatile memory, a larger non-volatile memory to hold an operating system, programs, and data for use by the processor cores. The apparatus also includes volatile memory to act as system memory for the processor cores, and power management logic to control at least some aspects of power management. In response to a power state change command, a system context is stored in the smaller non-volatile memory followed by the volatile memory losing power, and in response to a resume command, the volatile memory receives power and receives at least a portion of the system context from the smaller non-volatile memory. Other embodiments are described. | 2009-07-02 |
20090172440 | COUPLED LOW POWER STATE ENTRY AND EXIT FOR LINKS AND MEMORY - In some embodiments if a new request appears in a receive queue relating to a resource, and a controlled direction of the resource is in a low power state, a method starts an exit of the controlled direction after a delay. If receive direction of power control of the resource is in a low power state and preparation is being made to enter a low power state at the controlled direction, then the method decreases a watch and wait period that occurs prior to moving into the low power state at the controlled direction. Other embodiments are described and claimed. | 2009-07-02 |
20090172441 | HARDWARE PROACTIVE IMPLEMENTATION FOR ACTIVE MODE POWER CONTROL OF PLATFORM RESOURCES - In some embodiments, estimating a duration of an idle period gap of a lower power state of a resource by exponentially smoothing successive idle period gaps. Other embodiments are described and claimed. | 2009-07-02 |
20090172442 | SYSTEM AND METHOD FOR MEMORY PHASE SHEDDING - Embodiments of the invention supply power to DRAM or other memory devices with a multi-phase voltage regulator. A power controller coupled to the multi-phase voltage regulator causes one or more phases of the multi-phase voltage regulator to be activated or deactivated (shed) according to predetermined criteria. Embodiments of the invention thus improve power management by providing one or more reduced power states for the memory devices. Other embodiments are described. | 2009-07-02 |
20090172443 | Methods and apparatuses for processing wake events of communication networks - Methods, apparatuses, and computer program products that respond to wake events of communication networks are disclosed. One or more embodiments comprise setting a wake password of a computing device, such as a notebook computer or a server. Some of the embodiments comprise receiving a wake request from a communications network, establishing a secure communication session, and setting the wake password with the secure communication session. Some embodiments comprise an apparatus having a network controller to allow a platform to communicate via a communications network, non-volatile memory that stores a wake password, and a management controller which may communicate with a management console via a secure communication session to update the wake password. One or more embodiments the network controller may wake management hardware and/or wake the management controller while keeping one or more of the devices in the power conservation mode. | 2009-07-02 |
20090172444 | Computer System and Power-Saving Method Thereof - The present invention relates to a computer system and a power-saving method thereof. The computer system comprises a slot, a switch set, and a controlling module. An expansion card is capable of inserting into the slot. The switch set controls transmission of a power, a clock, and a bus signal to the slot. When activating a power-saving operation, the controlling module is capable of sending a controlling signal to command the switch set to cut off transmission of power, the clock, and the bus signal to the slot. | 2009-07-02 |
20090172445 | ELECTRONIC DEVICE WITH SERIAL ATA INTERFACE AND POWER SAVING METHOD FOR SERIAL ATA BUSES - In an electronic device with a serial ATA interface, upon detection of the issue or reception of a preset command, a confirmation device, such as a CPU, confirms the completion of execution of the command. Upon confirming the completion of execution of the command, a controller, which may also be the CPU, controls shifting of the serial ATA interface to a power saving mode. | 2009-07-02 |
20090172446 | ELECTRONIC DEVICE WITH SERIAL ATA INTERFACE AND POWER SAVING METHOD FOR SERIAL ATA BUSES - In an electronic device with a serial ATA interface, upon detection of the issue or reception of a preset command, a confirmation device, such as a CPU, confirms the completion of execution of the command. Upon confirming the completion of execution of the command, a controller, which may also be the CPU, controls shifting of the serial ATA interface to a power saving mode. | 2009-07-02 |
20090172447 | ELECTRONIC DEVICE WITH SERIAL ATA INTERFACE AND POWER SAVING METHOD FOR SERIAL ATA BUSES - In an electronic device with a serial ATA interface, upon detection of the issue or reception of a preset command, a confirmation device, such as a CPU, confirms the completion of execution of the command. Upon confirming the completion of execution of the command, a controller, which may also be the CPU, controls shifting of the serial ATA interface to a power saving mode. | 2009-07-02 |
20090172448 | ELECTRONIC DEVICE WITH SERIAL ATA INTERFACE AND POWER SAVING METHOD FOR SERIAL ATA BUSES - In an electronic device with a serial ATA interface, upon detection of the issue or reception of a preset command, a confirmation device, such as a CPU, confirms the completion of execution of the command. Upon confirming the completion of execution of the command, a controller, which may also be the CPU, controls shifting of the serial ATA interface to a power saving mode. | 2009-07-02 |
20090172449 | SYSTEM-DRIVEN TECHNIQUES TO REDUCE MEMORY OPERATING VOLTAGE - Disclosed herein are approaches to reducing a guardband (margin) used for minimum voltage supply (Vcc) requirements for memory such as cache. | 2009-07-02 |
20090172450 | Mobile systems with seamless transition by activating second subsystem to continue operation of application executed by first subsystem as it enters sleep mode - A computer system includes two or more subsystems. In one example, a first subsystem is executing a multimedia application using data stored in a first storage device. A copy of the data is also stored in a second storage device associated with a second subsystem. The second subsystem may be a dedicated multimedia player controller. When the first subsystem is to enter a sleep state, the second subsystem may continue to process the multimedia data stored in the second storage device. The second subsystem may also use the same audio port that the first subsystem was using before it enters the sleep state. Appropriate transition point may be determined by the second subsystem to ease audio disruption. | 2009-07-02 |
20090172451 | METHOD AND COMPUTER PROGRAM FOR CONTROLLING A STORAGE DEVICE HAVING PER-ELEMENT SELECTABLE POWER SUPPLY VOLTAGES - A method and computer program product for controlling a storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device. | 2009-07-02 |
20090172452 | System and Method of Leakage Control in an Asynchronous System - Systems and methods of leakage control in an asynchronous pipeline are disclosed. In an embodiment, a signal is received from a preceding stage at an operative stage of an asynchronous circuit device, and a switch associated with the operative stage is activated in response to the control signal being sent to the operative stage to enable power to the operative stage. | 2009-07-02 |
20090172453 | APPARATUS, SYSTEM, AND METHOD FOR AN INTEGRATED POWER SUPPLY EFFICIENT IN HIGH AND LOW POWER CONDITIONS - An apparatus, system, and method are disclosed for a power supply that is efficient in both high and low power conditions. An integrated power supply regulates current on a regulated bus to maintain a regulated bus voltage under varying load conditions. The integrated power supply includes a first power supply rated to provide full load power to the load and second power supply rated to provide power at levels below a minimum power threshold. The second power supply includes switching elements that have lower switching losses than switching elements of the first power supply. A sensing module measures power. A switching module starts up the second power supply and shuts down the first power supply if the measured power falls below the minimum power threshold, and starts up the first power supply and shuts down the second power supply if the measured power rises above the minimum power threshold. | 2009-07-02 |
20090172454 | INFORMATION RECORDING DEVICE AND INFORMATION RECORDING METHOD - An information recording device is a device for writing data to a disk-shaped recording medium and a cache memory and has a memory storing connection information showing a presence or an absence of a connection of an external power source; a determiner determining whether to write data recorded only in the cache memory to the disk-shaped recording medium based on the connection information; and a writer writing data recorded only in the cache memory to the disk-shaped recording medium according to the determination result. | 2009-07-02 |
20090172455 | Using Travel-Time as Means for Improving the Accuracy of Simple Network Time Protocol - A method for improving accuracy of simple network time protocol. A time inquiry is sent from at least one device in a substation to a time provider. A message including a reference time is received from the time provider. An accuracy of the reference time is evaluated. If the accuracy of the reference time is less than a threshold value the accuracy of the reference time is improved. The reference time is utilized for synchronization. | 2009-07-02 |
20090172456 | METHOD AND APPARATUS FOR CONTROLLING DATA PROCESSING MODULE - Provided are a method and apparatus for controlling a plurality of data processing modules that process data independently and output the processed data. A method of controlling a first data processing module and a second data processing module that process data independently and synchronize and output the processed data, the method including acquiring first data output rate information representing a current data output rate of the first data processing module, acquiring second data output rate information representing a current data output rate of the second data processing module, and adjusting a data output rate of at least one of the first data processing module and the second data processing module, on the basis of the first data output rate information and the second data output rate information. | 2009-07-02 |
20090172457 | Monitoring Presentation Timestamps - Techniques to monitor presentation timestamps for content are described, which may be used to render content at a client. In an implementation, content is received having timestamps that define expected timing for output of the content at a client. The timestamps may then be monitored and compared to a client clock to determine if the content rendered matches the content expected to be rendered. When a discrepancy is detected, one or more corrective actions may be undertaken to restore output of the content to the timing defined by the timestamps. | 2009-07-02 |
20090172458 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND CLOCK CONTROL METHOD - A plurality of operation units connected in a pipeline structure performs an operation processing on data. A process control unit operates in synchronization with a system clock signal and generates a process control signal for controlling the operation units upon receiving a data notification signal that notifies the process control unit of an arrival of data from outside. A clock-control signal generating unit operates in synchronization with the system clock signal and generates a clock control signal for controlling a clock supply to each of the operation units upon receiving the process control signal. | 2009-07-02 |
20090172459 | MEMORY INTERFACE - A double data rate memory interface circuit for transferring data between an interfacing device and double data rate memory device. The interface circuit comprises a data input for receiving a data signal from a first of those devices, and a strobe input for receiving a strobe signal from that first device. The interface circuit also comprises delay circuitry for supplying the data and strobe signals to the other device with a timing offset introduced therebetween. The delay circuitry comprises a software programmable storage medium and a digitally controllable delay element coupled to the storage medium, the delay element being arranged to control the timing offset in dependence on a delay setting programmed into that storage medium. | 2009-07-02 |
20090172460 | DEFINING A COMPUTER RECOVERY PROCESS THAT MATCHES THE SCOPE OF OUTAGE - Recovery processing is defined that matches the scope of an outage. A programmatic analysis of the resources that have been impacted, of implications of the failure and what degradations have occurred is performed to construct an appropriate level of recovery. This includes selecting the appropriate set of resources to be recovered. Recovery operations are selected based on the current state of the environment. | 2009-07-02 |
20090172461 | CONDITIONAL ACTIONS BASED ON RUNTIME CONDITIONS OF A COMPUTER SYSTEM ENVIRONMENT - Conditionally performing delegated actions based on runtime conditions of the environment. A component of an Information Technology environment conditionally performs an action, such as its own recovery, based on whether the component can have such action delegated to it and/or whether that component is currently being shared by multiple business applications of the environment. | 2009-07-02 |
20090172462 | METHOD AND SYSTEM FOR RECOVERY OF A COMPUTING ENVIRONMENT - A method and system for recovery of a computing environment includes monitoring during a pre-boot phase and a runtime phase of a computing device for selection of a hot key sequence by a user and performing a recovery action in response to the selection of the hot key sequence by the user. The recovery action may be any one of a number of predetermined and/or selectable actions such as restoring system defaults, migrating memory, displaying a menu of options, setting various software flags, restarting or rebooting the computing device, and/or the like. | 2009-07-02 |
20090172463 | METHOD, SYSTEM AND MACHINE ACCESSIBLE MEDIUM OF A RECONNECT MECHANISM IN A DISTRIBUTED SYSTEM (CLUSTER-WIDE RECONNECT MECHANISM) - A method, system and machine accessible medium for validating a plurality of connections to a backend in a distributed system. A connection request requiring access to a backend is processed at a first node of a distributed system. The access to the backend enabled through a connection from a plurality of connections on the first node. The plurality of connections on the first node is validated in response to a connection request failure. A plurality of connections on a second node is validated in response to the connection request failure. | 2009-07-02 |
20090172464 | METHOD AND APPARATUS FOR REPAIRING UNCORRECTABLE DRIVE ERRORS IN AN INTEGRATED NETWORK ATTACHED STORAGE DEVICE - In one embodiment, the invention provides a method for repairing a defective storage device in a physical storage-device array having a plurality of storage devices. The method comprises the steps of identifying a disk error associated with the defective storage device; effecting an error recovery pause based on the disk error; processing one or more outstanding data storage or retrieval requests; and generating a new data storage request instructing the physical disk device array having the defective storage device to store valid data associated with the data storage or retrieval request corresponding to the disk device error, whereby the defective storage device is repaired. | 2009-07-02 |
20090172465 | Semiconductor device having coupling elimination circuit - A semiconductor device including a plurality of repairable signal lines, the device including a first driver adapted to maintain a first portion of each defective one of the repairable signal lines at a first voltage level, and a second driver adapted to drive a second portion of each of the defective ones of the repairable signal lines being repaired to the first voltage level. | 2009-07-02 |
20090172466 | NAND power fail recovery - Techniques to recover data from an indirected non-volatile memory system after unexpected power failure, as, e.g., NAND memory in electronic devices are disclosed. | 2009-07-02 |
20090172467 | INFORMATION PROCESSING APPARATUS - An information processing apparatus includes: a nonvolatile memory that has a start block for storing a boot program and a spare block for storing a spare of the boot program; and a system controller that reads out the boot program from the start block and executes start-up process in accordance with the boot program, the system controller exclusively performs error correction and detection on the nonvolatile memory, wherein when the boot program is read out from the start block and a read error that cannot be corrected based on an error correction code occurs, the system controller performs recovery process for recovering the start block using the spare of the boot program stored in the spare block. | 2009-07-02 |
20090172468 | METHOD FOR PROVIDING DEFERRED MAINTENANCE ON STORAGE SUBSYSTEMS - A set of disks in a plurality of disk arrays are configured to have one or more spare partitions. Upon detecting a faulty disk in a faulty array, the method involves the steps of: (a) migrating data in the faulty array containing the faulty disk to one or more spare partitions; (b) reconfiguring the faulty array to form a new array without the faulty disk; (c) migrating data from one or more spare partitions in the set of disks to the reconfigured new array; (d) monitoring to identify when overall spare capacity falls below a predetermined threshold; and when the predetermined threshold is exceeded, scheduling a service visit for replacement of the failed disks. | 2009-07-02 |
20090172469 | METHOD, APPARATUS, LOGIC DEVICE AND STORAGE SYSTEM FOR POWER-FAIL PROTECTION - A method, apparatus, logic device, and storage system for power-fail protection are disclosed. The method includes: when a system power supply fails, supplying, by a battery, power to a south bridge chip (SBC), a non-volatile flash storage medium, an interface conversion circuit (ICC) between the SBC and the non-volatile flash storage medium and a memory; and transmitting unsaved data in the memory to the corresponding non-volatile flash storage medium via the ICC, by using an unused bus interface of the SBC. The ICC converts a bus interface of the SBC into a corresponding bus interface of the non-volatile flash storage medium. The embodiments of the invention can effectively solve problems of data loss in case of system power failure and short retention time, and realize protection operation in case of system power failure, convenient upgrading memory capacity, and saving system space, without adding cost and total capacity of battery. | 2009-07-02 |
20090172470 | MANAGING PROCESSING OF A COMPUTING ENVIRONMENT DURING FAILURES OF THE ENVIRONMENT - Recovery processing is provided for management components of an Information Technology (IT) environment. The recovery processing recovers the components, as well as performs one or more tasks that were being performed by the components prior to recovery. | 2009-07-02 |
20090172471 | METHOD AND SYSTEM FOR RECOVERY FROM AN ERROR IN A COMPUTING DEVICE - A method and system for supporting recovery of a computing device includes determining and storing a sub-set of firmware instructions used to establish a pre-boot environment and executing the sub-set of firmware instructions in response to an error. | 2009-07-02 |
20090172472 | COMPUTER, AND METHOD FOR ERROR-DETECTING AND BOOTING OF BIOS THEREOF - A computer has a first BIOS unit, a second BIOS unit, a bus, a detecting unit, and a first delay unit. The detecting unit is connected to the bus, the first BIOS unit, and the second BIOS unit operationally. In addition, the first delay unit is electrically connected to the detecting unit for controlling the detecting unit to check a status of a bus signal on the bus after a predetermined delay time. Accordingly, the detecting unit may enable the first BIOS unit or the second BIOS unit to boot the computer system according to the state of the bus signal. | 2009-07-02 |
20090172473 | SYSTEM AND METHOD FOR SYNCHRONIZING TEST RUNS ON SEPARATE SYSTEMS - A system and method provide for test automation of a process running on separated systems. The systems may be separated physically and/or logically separated. The system and method provide that all information required for a test run are made available on one system. In an embodiment, a central component is used to provide all required status and result information regarding the test status of every system in the test landscape. In further embodiment, an extension of the capabilities of existing test tools is made so that the test tool communicates with the central component via an appropriate protocol. | 2009-07-02 |
20090172474 | Network Diagnostic Systems and Methods for Light Levels of Optical Signals - A network diagnostic system may include a network diagnostic device. The network diagnostic device may be configured to receive data indicating a light level of an optical signal and to perform at least one network diagnostic function at least partially in response to the receipt of the data. A network diagnostic method may include detecting a light level of an optical signal; and performing at least one network diagnostic function at least partially in response to the detection of the light level of the optical signal. Exemplary network diagnostic functions may include triggering an alarm; triggering a capture of at least a portion of one or more network messages; storing data indicating the light level of the optical signal on a computer readable medium (e.g., for use in subsequent reports); and/or any other suitable network diagnostic function. | 2009-07-02 |
20090172475 | REMOTE RESOLUTION OF SOFTWARE PROGRAM PROBLEMS - Method, system, and computer program product for remotely resolving problems in software programs are provided. A problem is detected in a software program. An instant message is sent to an operator to notify the operator of the problem detected in the software program. An instant message is received from the operator. The instant message from the operator includes selection of a resolution option for the problem detected in the software program. The selected resolution option is then carried out. | 2009-07-02 |
20090172476 | Test Executive System with Memory Leak Detection for User Code Modules - A system and method for automatically detecting heap corruption errors and memory leak errors caused by user-supplied code modules that are called by steps of a test executive sequence. The test executive sequence may first be created by including a plurality of test executive steps in the test executive sequence and configuring at least a subset of the steps to call user-supplied code modules. The test executive sequence may then be executed on a host computer under control of a test executive engine. For each step that calls a user-supplied code module, the test executive engine may perform certain actions to automatically detect whether the user-supplied code module causes a heap corruption error and/or automatically detect whether the user-supplied code module causes a memory leak error. | 2009-07-02 |
20090172477 | REMOTE MONITORING SYSTEM, TERMINAL MANAGEMENT SERVER AND TERMINAL MANAGEMENT SERVER CONTROL PROGRAM - An insulation monitoring system, functioning as a remote monitoring system, comprises a plurality of insulation monitoring terminals, functioning as remote monitoring terminals, for monitoring facilities and a terminal management server controlling the insulation monitoring terminals. The insulation monitoring terminals and terminal management server are connected each other to bidirectionally transmit and receive information therebetween. The terminal management server includes collective input unit for accepting collectively input configuration information pieces to be set in the insulation monitoring terminals, storage unit for storing the plurality of configuration information pieces input by the collective input unit, and distribution unit for distributing the plurality of configuration information pieces stored in the storage unit to the insulation monitoring terminals respectively associated with the configuration information pieces. | 2009-07-02 |
20090172478 | Information Processing Apparatus, Backup Device and Information Processing Method - According to an aspect of the present invention, there is provided an information processing apparatus including: a connector to which a backup device is connected; a data storing unit that stores an objective data; and a processor that is configured: to write the objective data to the backup device as a backup data; to record a change log that specifies an updated part of the objective data; to detect a difference part between the objective data and the backup data when the backup device is connected to the connector; to determine whether the difference part matches the updated part specified by the change log; and if the difference part does not match the updated part, to identify a mismatching part between the difference part and the updated part as an abnormal data. | 2009-07-02 |
20090172479 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR TESTING THE SAME - A semiconductor memory device includes an alignment unit configured to align data received from the outside, a plurality of data input/output lines corresponding to the aligned data, respectively and a realignment unit configured to change correspondence between the data and the data input/output lines in response to one or more change signals in a test mode. A method for testing the semiconductor memory device includes inputting data in series using a testing apparatus, aligning the serial data in parallel, and realigning the parallel data in response to one or more change signals. | 2009-07-02 |
20090172480 | System and method for testing a packetized memory device - Integrated circuits, load boards and methods are disclosed, such as those associated with a memory testing system that includes an algorithmic pattern generator generating a pattern of command, address or write data digits according to an algorithm. In one such embodiment, the pattern of digits are applied to a frame generator that arranges the pattern of digits into a packet. The packet is then applied to a plurality of parallel-to-serial converters that convert the packet into a plurality of serial digits of a command/address packet or a write data packet, which are output through a plurality of bit lanes. The system might also include a plurality of serial-to-parallel converters receiving respective sets of digits of a read data packet through respective bit lanes. The read data packet is applied to a frame decomposer that extracts a pattern of read data digits from the packet. An error detecting circuit then determines if any of the received read data digits are erroneous. | 2009-07-02 |
20090172481 | Partial Voltage Read of Memory - A partial voltage level read is made on memory cells of a solid state memory device during a voltage settling time after the memory cells are charged (e.g., by a pulse from a charge pump). Digital values representing partial voltage levels are checked for errors (e.g., by an error correction code (ECC) engine). If the values can be corrected, then the values are released for host access. If the values cannot be corrected, then a full voltage read is performed on the memory cells after the voltage levels have substantially settled. Digital values corresponding to the full voltage reads can be released for host access. The use of partial voltage reads results in faster read of solid state memory devices. | 2009-07-02 |
20090172482 | METHODS FOR PERFORMING FAIL TEST, BLOCK MANAGEMENT, ERASING AND PROGRAMMING IN A NONVOLATILE MEMORY DEVICE - Methods for performing a fail test, block management, erase operations and program operations are used in a nonvolatile memory device having a block switch devoid of a fuse and a PMOS transistor. A method for performing a fail test in a nonvolatile memory device includes performing a fail test for a memory cell block; storing good block information in a block information store associated with the corresponding block when the memory cell block is a good block; and repeating the performing and storing steps for all memory cell blocks. | 2009-07-02 |
20090172483 | ON-CHIP FAILURE ANALYSIS CIRCUIT AND ON-CHIP FAILURE ANALYSIS METHOD - An on-chip failure analysis circuit for analyzing a memory comprises a memory in which data is stored, a built-in self test unit which tests the memory, an failure detection unit which detects an failure of output of the memory, an fail data storage unit in which fail data is stored, the fail data including a location of the failure, an failure analysis unit which performs failure analysis using the number of failures detected by the failure detection unit and the location of the failure, the failure analysis unit writing fail data including the analysis result in the fail data storage unit, and an analysis result output unit which outputs the analysis result of the failure analysis unit. | 2009-07-02 |
20090172484 | Method for Implementing a Serialization Construct Within an Environment of Parallel Data Flow Graphs - A serialization construct is implemented within an environment of a number of parallel data flow graphs. A quiesce node is appended to every active data flow graph. The quiesce node prevents a token from passing to a next data flow graph within a chain before an execution of the active data flow graph has been finished. A serial data flow graph is implemented to provided for a serial execution while no other data flow graph is active. A serialize node is appended to a starting point of a serial data flow graph. A serialize end node is appended to an endpoint of the serial data flow graph. The serialize node is activated to start a serial operation. The serialize end node is activated after the serial operation has been terminated. | 2009-07-02 |
20090172485 | INTERCONNECTIONS FOR PLURAL AND HIERARCHICAL P1500 TEST WRAPPERS - A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores. The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals. | 2009-07-02 |
20090172486 | TESTING EMBEDDED MEMORIES IN AN INTEGRATED CIRCUIT - Various new and non-obvious apparatus and methods for testing embedded memories in an integrated circuit are disclosed. One of the disclosed embodiments is an apparatus for testing an embedded memory in an integrated circuit. This exemplary embodiment comprises input logic that includes one or more memory-input paths coupled to respective memory inputs of the embedded memory, a memory built-in self-test (MBIST) controller, and at least one scan cell coupled between the input logic and the MBIST controller. The scan cell of this embodiment is selectively operable in a memory-test mode and a system mode. In memory-test mode, the scan cell can apply memory-test data to the memory inputs along the memory-input paths of the integrated circuit. Any of the disclosed apparatus can be designed, simulated, and/or verified (and any of the disclosed methods can be performed) in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool. | 2009-07-02 |
20090172487 | Multiple pBIST Controllers - A system on a single integrated circuit chip (SoC) includes a plurality of operational circuits to be tested. A plurality of programmable built-in self-test (pBIST) controllers is connected to respective ones of the plurality of operational circuits in a manner that allows the pBIST controllers to test the respective operation circuits in parallel. An interface is connected to each of the plurality of pBIST controllers for connection to an external tester to facilitate programming of each of the plurality of pBIST controllers by the external tester, such that the plurality of pBIST controllers are operable to test the plurality of operational circuits in parallel and report the results of the parallel tests to the external tester, thereby reducing test time. | 2009-07-02 |
20090172488 | SEMICONDUCTOR DEVICE - A semiconductor device includes a test target circuit; scan chains that enable scanning of the test target circuit; a first random number generation circuit that forms test patterns supplied to the scan chains; a second random number generation circuit that is provided separately from the first random number generation circuit; and a random number control circuit that uses the random numbers generated by the second random number generation circuit to change the random numbers generated by the first random number generation circuit. In a test of the semiconductor device, since a period of a clock of a scan chain does not need to be longer than that of a clock of a pattern generator, the number of clocks of the pattern generator needed for a test can be prevented from increasing. Accordingly, a test time can be prevented from increasing. | 2009-07-02 |
20090172489 | CIRCUIT ARRANGEMENT AND METHOD FOR CHECKING THE FUNCTION OF A LOGIC CIRCUIT IN A CIRCUIT ARRANGEMENT - A circuit arrangement comprising a logic circuit to be tested and a test circuit is provided. The logic circuit is designed to provide output data from input data, said output data being generated from the input data by logic-circuit-internal combinations, such that the output data are in a predetermined relationship with the input data. The logic circuit is designed to detect whether the relationship is fulfilled and to provide an error signal if the relationship is not fulfilled. The test circuit is designed to alter logic-circuit-internal combinations. The test circuit is designed to detect the error signal, and is furthermore designed to output an alarm signal if the error signal is not detected upon alteration of the logic-circuit-internal combinations. | 2009-07-02 |
20090172490 | DATA RETRANSMISSION METHOD AND WIRELESS COMMUNICATION APPARATUS - A data retransmission method for retransmitting a data using a wireless communication, including: receiving data transmitted from a transmitting apparatus; determining whether the received data is correct or not; transmitting data including information indicating that the received data is received correctly to the transmitting apparatus upon being determined the received data is correct, and transmitting data including information indicating that the received data is not received correctly to the transmitting apparatus upon being determined the received data is not correct; measuring an elapsed time from transmission of the data including information indicating that the received data is not received correctly; and monitoring whether to receive data corresponding to the received data from the transmitting apparatus before the elapsed time reaches a predetermined time. | 2009-07-02 |
20090172491 | METHODS AND SYSTEMS FOR ERROR DETECTION OF DATA TRANSMISSION - The invention provides an error detection method for data transmission in a transmission system with a first device, a second device and a data line. The method comprises the following steps. Firstly, a clock signal is sent to synchronize the first and second devices. Secondly, at least one serial data is sent from the first device to the second device in response to the clock signal. After sending the serial data, the first device sends an acknowledgement signal to the second device. After sending the acknowledgement signal, the first device reads the data line to obtain a reading value and determines whether the serial data is correct according to the reading value and a default value of the data line. | 2009-07-02 |
20090172492 | Method and apparatus for interleaving low density parity check (LDPC) codes over mobile satellite channels - Systems, methods and apparatus are described to interleave LDPC coded data for reception over a mobile communications channel, such as, for example, a satellite channel. In exemplary embodiments of the present invention, a method for channel interleaving includes segmenting a large LDPC code block into smaller codewords, randomly shuffling the code segments of each codeword and then convolutionally interleaving the randomly shuffled code words. In exemplary embodiments of the present invention, such random shuffling can guarantee that no two consecutive input code segments will be closer than a defined minimum number of code segments at the output of the shuffler. In exemplary embodiments of the present invention, by keeping data in, for example, manageable sub-sections, accurate SNR estimations, which are needed for the best possible LDPC decoding performance, can be facilitated based on, for example, iterative bit decisions. | 2009-07-02 |
20090172493 | METHOD AND DEVICE FOR DECODING LOW DENSITY PARITY CHECK CODE - An apparatus for decoding a Low Density Parity Check (LDPC) is provided. The apparatus includes a variable node message memory for storing a variable node message vector, a controller for controlling a node computing unit to read from and write to the variable node message memory and controlling an iteration process for the apparatus, and a node computing unit for updating a check node message and a variable node message, and determining a hard decision message, the node computing unit includes a variable node message generation unit for determining the variable node message for use in a check node message calculation unit according to the variable node message vector, a check node message calculation unit for updating the check node message, a variable node message updating unit for updating a corresponding variable node message, a hard decision calculation unit for determining the hard decision message for a corresponding variable node, and a parity check unit for determining a parity bit and outputting the parity bit to a decoding termination controller. | 2009-07-02 |
20090172494 | DATA PROCESSING APPARATUS AND METHOD, AND PROGRAM - In order to correctly perform error analysis, test, or the like, a 64B/66B converter of a PCS processing unit of a transmitter conforming to 10 GBASE-R PHY performs 64B/66B conversion on data on a block basis that is transmitted over four lanes, the block being formed of two columns. In the conversion, when a control signal inputted via a control signal input terminal indicates a normal operation mode, if an error code in a block to be converted is detected by an error detector, error expansion that replaces all 8 bytes of data in the block with an error code /E/ is performed. In contrast, when the control signal indicates an analysis mode, the error expansion is not performed even if an error code is detected by the error detector. | 2009-07-02 |
20090172495 | Methods and Apparatuses for Parallel Decoding and Data Processing of Turbo Codes - Methods and apparatuses for parallel decoding and data processing of Turbo codes are provided. The method includes: a codeword dividing step for dividing a whole codeword into Q sub-blocks to form a plurality of boundaries between adjacent sub-blocks of the Q sub-blocks so as to decode the Q sub-blocks, wherein the decoding process comprises P times of decoding iterations, and wherein Q is a positive integer and Q>1 and P is a positive integer and P>1; and a boundary moving step for moving at least one position of the boundaries formed in a pth decoding iteration by an offset Δ before performing a (p+n)th decoding iteration, wherein p is a positive integer and 1≦p | 2009-07-02 |
20090172496 | TECHNIQUE FOR MEMORY IMPRINT RELIABILITY IMPROVEMENT - One embodiment of the present invention relates to a method of reducing imprint of a memory cell. The method comprises adding an inversion condition bit operably associated with one or more memory cells storing a memory word. The inversion condition bit indicates whether the memory word represents an actual payload or an inversion of the actual payload. The inversion condition bit and memory word are selectively toggled by a control circuitry. Inversion is performed by reading the inversion condition bit and memory word and rewriting the memory word back to the one or more memory cells in an inverted or non-inverted state, depending on an inversion condition bit. The inversion condition bit is then written to the inversion status bit value. The memory address is incremented, and the inversion status data state is toggled once the address counter addresses the entire memory array. Other methods and circuits are also disclosed. | 2009-07-02 |
20090172497 | DATA PROCESSING SYSTEM AND METHOD FOR PROCESSING OPTICAL INFORMATION - Provided is a data processing system for recording holographic optical information. The data processing system includes: a data interface constructing a data page by using data transmitted from a host information device; a memory storing data transmitted from the data interface; an encoder ECC-encoding data that is stored in the memory; and a modulator modulating the encoded data so as to record optical information. Accordingly, it is possible to efficiently transmit data when recording and reproducing holographic optical information. | 2009-07-02 |