| 27th week of 2009 patent applcation highlights part 71 |
| Patent application number | Title | Published |
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| 20090172198 | SYSTEM AND METHOD FOR SYNCHRONISING A DATA PROCESSING NETWORK - A data processing system according to the invention comprising a group of at least a first and a second module, wherein each module has a data processing facility, a clock for timing data transmissions from the module to another module, a time-slot counter for counting a number of time slots which are available for transmission of data. The modules have a first operational state wherein the counted number of time slots is less than or equal to a predetermined number, in which operational state data transmission is enabled, and a second operational state wherein the number is in excess of the predetermined number, in which second operational state data transmission is disabled, Each module has a notifying facility for notifying when it is in the second operational state. The data processing system has at least one detecting facility that detects whether the other modules have notified that they are in the second operational state and the modules each have an initialization facility for resetting the time-slot counter when the module is in the second operational state and each of the other modules has notified that it is in the second operational state. | 2009-07-02 |
| 20090172199 | METHOD AND SYSTEM FOR CALIBRATING RESPONSE OF POINTER WITH RESPECT TO MOUSE - Disclosed is a method for calibrating response of a pointer of a remote computer with respect to a mouse of a client computer. The method of the present invention includes steps: (a) showing the pointer of the remote computer in a screen of a display of the client computer; (b) directing the pointer to move in a predetermined distance by shifting the mouse; (c) calculating a relation between a shift of the mouse and the predetermined distance; and (d) synchronizing the mouse with the pointer according to the relation. The system thereof according to the present invention includes a KVM switch and a calibration mechanism. The KVM switch shows the pointer in the screen of the display. The calibration mechanism calculates a relation between a shift of the mouse and a predetermined distance and then, synchronizes the mouse with the pointer according to the relation. | 2009-07-02 |
| 20090172200 | Synchronization of audio and video signals from remote sources over the internet - The present invention is an architecture and technology for a method for synchronizing multiple streams of time-based digital audio and video content from separate and distinct remote sources, so that when the streams are joined, they are perceived to be in unison. | 2009-07-02 |
| 20090172201 | PEER TO PEER SYNCRONIZATION SYSTEM AND METHOD - A method and system for enabling peer to peer synchronization between members of a synchronized network. A predefined synchronization reference area on each member of the network is provided. A common identifier associated with the synchronization network is provided to each member. Changes are detected on a member regarding a data item. A network identifier associated is obtained. A unique identifier of a synchronization module is obtained. A relative path to the data item within the predefined synchronization reference area is obtained. A unique value is calculated based upon a content of a version of the data item that is associated with the change. A log number counter is incremented. A log representing the data item and the chance is created. The log includes data regarding the type of change, the network identifier, the unique identifier of the synchronization module, the relative path, the unique value, and the log number. | 2009-07-02 |
| 20090172202 | Method for Receiving Data over an SDIO Interface and Device Using the Same - A method for receiving data with a secure digital input/output (SDIO) interface, which is utilized for providing a data transmission connection between a master device and a slave device, starts with receiving a first packet of the data from the slave device. The first packet is transferred with a plurality of data blocks. A first data block of the plurality of data blocks has reception information of a second packet. The method then generates a control signal to receive the second packet from the slave device according to the reception information of the second packet, which is a next packet of the first packet in the data. | 2009-07-02 |
| 20090172203 | SYSTEM AND PROGRAM PRODUCTS FOR FACILITATING INPUT/OUTPUT PROCESSING BY USING TRANSPORT CONTROL WORDS TO REDUCE INPUT/OUTPUT COMMUNICATIONS - Input/output processing is facilitated by reducing communications between input/output communications adapters and control units during input/output processing. The number of exchanges and sequences between an input/output communications adapter and control unit is reduced by sending a plurality of commands from the adapter to the control unit as a single entity for execution by the control unit. The control unit executes the commands and provides the data, if any, in one sequence. The control unit relieves the adapter of the responsibility of tracking state of the individual commands and is able to calculate precise measurement data relating to execution of the commands. | 2009-07-02 |
| 20090172204 | ELECTRONIC DEVICE WITH SERIAL ATA INTERFACE AND POWER SAVING METHOD FOR SERIAL ATA BUSES - In an electronic device with a serial ATA interface, upon detection of the issue or reception of a preset command, a confirmation device, such as a CPU, confirms the completion of execution of the command. Upon confirming the completion of execution of the command, a controller, which may also be the CPU, controls shifting of the serial ATA interface to a power saving mode. | 2009-07-02 |
| 20090172205 | METHOD AND SYSTEM FOR ENABLING A SIDESHOW DEVICE TO RETRIEVE SYSTEM INFORMATION FROM A COMPUTING DEVICE - A method and system for enabling an auxiliary system to retrieve the system information from a computing device are disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of requesting for the system information from an embedded controller of the computing device through a first bi-directional data bus if the computing device is shut down, requesting for the system information from the computing device through the first bidirectional bus during the boot-up sequence of the computing device, and requesting for the system information from the computing device through a general purpose input/output (GPIO) after the computing device completes the boot-up sequence. | 2009-07-02 |
| 20090172206 | DETECTION AND CONFIGURATION OF SAS/SATA CONNECTION - Given the different configurations for SAS and SATA Host and Target Ports, embodiments of the present invention automatically detect the configuration of SATA and SAS Phys when any device is inserted into a port enclosure and properly configure the connection regardless of the Phy configuration of the connected device. When a device is connected to the system, the port listens for either a SATA or SAS OOB signal to determine if the receive pin of the port is properly connected to the transmit signal of the attached device. By switching the configuration periodically and listening for the OOB signal, the port can determine which configuration is proper. Once a signal is detected, the port can properly configure the connection and continue with the SATA or SAS insertion algorithm. A user may alternatively choose which configuration to use and bypass the automatic detection and configuration. | 2009-07-02 |
| 20090172207 | COMMUNICATING THROUGH A PHYSICAL PORT OF AN ELECTRONIC DEVICE - An electronic device has a physical port, and a control circuit coupled to the physical port. The control circuit is arranged to electrically sense the physical port, and operate the physical port as one of an Ethernet port and an RS-232 port based on electrically sensing the physical port. In some arrangements, the physical port operates as an Ethernet port at one time and an RS-232 port at another time. In some arrangements, the electronic device senses for Ethernet signals and RS-232 signals concurrently. In other arrangements, the electronic device senses for Ethernet signals and RS-232 signals at different times in an alternating manner. | 2009-07-02 |
| 20090172208 | Wibro USB modem device having storage device - Disclosed herein is a Wireless Broadband (WiBro) Universal Serial Bus (USB) modem device having a storage device and a WiBro communication device. A USB hub is connected to the USB interface of the WiBro communication device and the USB interface of the storage device, and configured to relay data to a user terminal through a USB connector. A switching mode power supply unit is configured to have a DC-DC switching mode, receive power from the user terminal, and apply the power by performing high-speed switching so that the WiBro communication device and the storage device are simultaneously driven. The switching mode power supply unit includes a dual output switching mode power supply unit and a single output switching mode power supply unit. | 2009-07-02 |
| 20090172209 | ELECTRONIC DEVICE WITH SERIAL ATA INTERFACE AND POWER SAVING METHOD FOR SERIAL ATA BUSES - In an electronic device with a serial ATA interface, upon detection of the issue or reception of a preset command, a confirmation device, such as a CPU, confirms the completion of execution of the command. Upon confirming the completion of execution of the command, a controller, which may also be the CPU, controls shifting of the serial ATA interface to a power saving mode. | 2009-07-02 |
| 20090172210 | Methods and apparatuses for wireless network communications - In some embodiments a method is disclosed that includes creating a network connection status between a host device and a peripheral network device, determining characteristics of the peripheral device such as receive capacity or a quality of service classification for the transmission and flow control for performing control and data transfers. A transfer is initiated when a uniform serial bus request block (URB) is generated by a host application. The URB can have parameters that can be utilized to generate a transaction over a wireless network providing Quality of Service (QoS) guarantees. Other embodiments are also disclosed. | 2009-07-02 |
| 20090172211 | STORAGE DEVICE WITH TRANSACTION LOGGING CAPABILITY - In one aspect, a system for indexing transactions over a shared bus is described. In various embodiments, the system includes a host controller and a plurality of storage devices in communication with the bus. Each of the storage devices is configured to store data. The bus facilitates communications between the host controller and the plurality of storage devices. A selected one of the storage devices is configured to function as a transaction indexer to monitor the bus and index and store selected transaction information associated with operations that occur over the bus. While the host controller may be arranged to configure the transaction indexer, the transaction monitoring, indexing and storing are performed substantially automatically by the transaction indexer without requiring further instructions from the host controller. | 2009-07-02 |
| 20090172212 | System and method for managing input/output requests in data processing systems - An apparatus and method for managing input/output transactions in data processing systems. I/O processors (IOPs) of the computing system are logically separated into multiple groups. Multiple global completion indicator groups are provided, one for each of the groups of IOPs. A state of the global completion indicator group is modified by its respective group of IOPs when any of the IOPs of the respective group completes an I/O request. Each of the global completion indicator groups is independently monitored for I/O requests completed by any of the IOPs in the respective IOP group. | 2009-07-02 |
| 20090172213 | COMMAND COMPLETION DETECTION IN A MASS STORAGE DEVICE - In some embodiments, after a hold off time following issuance of a memory command has elapsed, a status read operation is performed to determine a status of the memory command. In some embodiments, if the memory command has not yet completed, a polling interval is used to perform a status read operation to determine the status of the memory command after the polling interval has expired, and repeating the process until the memory command has been completed. Other embodiments are described and claimed. | 2009-07-02 |
| 20090172214 | USB HOST CONTROLLER - In some embodiments, a USB host controller interface interfaces with a USB device at a device level by presenting a pipe of the USB device as a work queue to system software. Other embodiments are described and claimed. | 2009-07-02 |
| 20090172215 | Even and odd frame combination data path architecture - Methods and apparatus to odd and even frame combination data path architectures are described. In one embodiment, a logic may include a buffer and a parallel input, serial output (PISO) logic that may be utilized for transferring data between a source and a destination. The logic may be utilized for transferring the data whether or not the data is transmitted in accordance with single ended or differential signals. Other embodiments are also described. | 2009-07-02 |
| 20090172216 | METHOD AND APPARATUS FOR TRANSMITTING DATA IN A FLEXRAY NODE - A method of transmitting data to a recipient comprising the steps of dividing the data into a plurality of groups, providing a synchronising means for each of the groups, using the synchronising means to synchronise the data in each group, and transmitting the data to a recipient characterised in that the data is divided in accordance with its synchronisation requirements with the recipient. | 2009-07-02 |
| 20090172217 | DISTRIBUTED STORAGE SERVICE SYSTEMS AND ARCHITECTURE - Various methods, devices and systems are described for providing distributed storage services. A data storage device is capable of initiating a communication session with an external entity such as a local host computer (and vice versa) coupled directly to the data storage device, a remote server computer, or directly with remote data storage devices with or without intervention by a local host computer. | 2009-07-02 |
| 20090172218 | High Definition Media Interface Controller Having A Modular Design Internal Bus Structure, And Applications Thereof - The present invention provides a high definition media interface (HDMI) controller having a modular design internal bus structure, and applications thereof. The controller includes a circuit interface, an address decoder coupled to the circuit interface, a plurality of sub-circuits, wherein each sub-circuit includes registers used to configure and control the sub-circuit, and a bus that couples the registers of each sub-circuit to the address decoder. After startup of the controller, the sub-circuits are configured by using the circuit interface, address decoder, and bus to write values to the registers of the sub-circuits. The sub-circuits of the controller include a video pixel sampler, an audio sampler, a frame composer, and a power controller. The video sampler can be configured to convert one of a plurality of RGB and YCbCr signals to a common format signal used by other sub-circuits of the controller. | 2009-07-02 |
| 20090172219 | DEVICE AND METHOD FOR AUTOMATICALLY LAUNCHING APPLICATIONS RESIDING ON USB FLASH DRIVES - A USB peripheral device may automatically launch an application residing in its memory after it is connected to a host or after restarting the host if the USB flash drive has already been connected. Alternatively, the USB peripheral \device can automatically launch an application residing on the host or on a network, which is accessible by the host. The USB peripheral device has a USB interface and a controller, which is operative to execute instructions for sending and receiving messages through the USB interface. The controller is further operative, when executing the instructions, to send to a host a stream of emulated keystrokes, which emulated keystrokes cause the host to generate and execute a startup script. Embodiments of the invention include a USB peripheral device able to control a host and a method of using a USB peripheral device to control a host. | 2009-07-02 |
| 20090172220 | METHOD FOR TRANSMITTING AUDIO STREAMS AND AUDIO STREAM TRANSMITTING SYSTEM THEREOF - A method for transmitting audio streams includes providing a USB bus, and transmitting an audio stream through the USB bus by utilizing a bulk transfer mode. The method further includes providing a buffering module, buffering the audio stream in the buffering module to generate a buffered audio stream, performing a digital-to-analog conversion on the buffered audio stream to generate an analog playback signal, and performing an analog-to-digital conversion on an analog recording signal to generate the audio stream. | 2009-07-02 |
| 20090172221 | DATA TRANSFER SYSTEM AND DATA TRANSFER METHOD - The configuration of a system including a lot of receiving side devices can be simplified. The system includes a driver | 2009-07-02 |
| 20090172222 | KVM switch and remote system - A KVM switch which is connected between a plurality of servers, and a client to which a keyboard, a mouse, a display, and a speaker are connected, and switches a server connected to the client, the KVM switch including: a sound input portion that inputs sound data emitted from each server; an abnormal sound determination portion that determines whether the input sound data is an abnormal sound; and a notification portion that notifies the client of abnormality detection when it is determined that the input sound data is the abnormal sound. | 2009-07-02 |
| 20090172223 | Method and Apparatus for Distributing Configuration Files in a Distributed Control System - The invention described herein provides a system and method for distributing and applying a configuration file from a master device ( | 2009-07-02 |
| 20090172224 | DATA TRANSMITTER AND DATA RECEIVER - A data transmitter includes: a packetization unit receiving primary data from a data processor and packetizing the primary data; a high-speed transmission unit transmitting a data packet obtained from the packetization to a display device in a high-speed mode; and a low-speed transmission unit relaying and transmitting secondary data between the data processor and the display device in a low-speed mode. Accordingly, it is possible to transmit and receive data rapidly and efficiently. | 2009-07-02 |
| 20090172225 | Method and apparatus for providing overlapping defer phase responses - A multiprocessor system in which a defer phase response method is utilized that allows for a deferring agent to interrupt the normal flow of bus transactions once it gains control of system interface bus. The deferring agent is allowed to look ahead to determine if a continuous stream of defer phase cycles are pending transfer. If pending, the deferring agent will not release control of the bus until the pending defer phase cycles have been depleted. The look ahead feature allows expedited return of higher priority defer data, while minimizing bus dead cycles caused by interleaving defer phase cycles with normal bus traffic. | 2009-07-02 |
| 20090172226 | Data processing system and method for interconnect arbitration - A data processing system comprising a plurality of processing units (Dv | 2009-07-02 |
| 20090172227 | SERIAL ADVANCED TECHNOLOGY ATTACHMENT WRITE PROTECTION: MASS STORAGE DATA PROTECTION DEVICE - A mass storage device protection system may have a mass storage device, a processor configured to generate at least one serial write command signal to the mass storage device via a serial communication link, and a storage protector configured for communication with the processor and mass storage device, the storage protector configured to do the following: intercept the at least one serial write command signal, and determine whether the at least one serial write command signal comprises an authorized command signal or an unauthorized command signal. | 2009-07-02 |
| 20090172228 | METHOD AND SYSTEM FOR HANDLING A MANAGEMENT INTERRUPT EVENT IN A MULTI-PROCESSOR COMPUTING DEVICE - A method and system for handling a management interrupt, such as a system management interrupt (SMI) and/or a platform management interrupt (PMI), includes sequestering two or more processor cores from a plurality of processor cores to form a group of sequestered processor cores for handling the management interrupt. Generated management interrupts are directed to the group of sequestered processor cores and not to non-sequestered processor cores. At least one of the sequestered processor cores handles the management interrupt without disrupting the current operation of the non-sequestered processor cores. | 2009-07-02 |
| 20090172229 | METHODS FOR SELECTING CORES TO EXECUTE SYSTEM MANAGEMENT INTERRUPTS - A method includes directing a system management interrupt to a processor core from a plurality of processor cores of a computing device for handling based upon core load-sharing considerations. A machine readable medium includes a plurality of instruction, that in response to being executed, result in a computing device selecting a processor core of a plurality of processor cores to handle a system management interrupt and programming at least one system management register to direct the system management interrupt to the processor core selected from the plurality of processor cores for handling. An associated system is also disclosed. | 2009-07-02 |
| 20090172230 | DISTRIBUTED REAL-TIME OPERATING SYSTEM - A distributed control system and methods of operating such a control system are disclosed. In one embodiment, the distributed control system is operated in a manner in which interrupts are at least temporarily inhibited from being processed to avoid excessive delays in the processing of non-interrupt tasks. In another embodiment, the distributed control system is operated in a manner in which tasks are queued based upon relative timing constraints that they have been assigned. In a further embodiment, application programs that are executed on the distributed control system are operated in accordance with high-level and/or low-level requirements allocated to resources of the distributed control system. | 2009-07-02 |
| 20090172231 | Data processing device and bus access control method therein - A data processing device includes a computing circuit that accesses a peripheral device connected to through a internal bus, an internal bus connection circuit that is provided between the computing circuit and the internal bus, and switches an enable and a disable state of an access from the computing circuit to the internal bus, an exception notification controller that outputs an exception occurrence notification signal to the computing circuit based on an error occurred in the peripheral device, and a bus disablement controller that instructs the internal bus connection circuit to disable an access from the computing circuit to the internal bus in accordance with the notification of the exception occurrence notification signal, and instructs the internal bus connection circuit to cancel the disablement of the access in accordance with a start of an exception processing based on the exception occurrence notification signal. | 2009-07-02 |
| 20090172232 | METHOD AND SYSTEM FOR HANDLING A MANAGEMENT INTERRUPT EVENT - A method and system for handling a management interrupt, such as a system management interrupt (SMI) and/or a platform management interrupt (PMI), includes sequestering one or more processor cores for handling the management interrupt. Generated management interrupts are directed to the sequestered processor core and not to other processor cores allocated to a main partition. The sequestered processor core(s) handles the management interrupt without disrupting the current operation of the remaining processor cores. | 2009-07-02 |
| 20090172233 | METHODS AND APPARATUS FOR HALTING CORES IN RESPONSE TO SYSTEM MANAGEMENT INTERRUPTS - A method includes halting at least one processing core of a computer system in response to a system management interrupt. The method further includes handling the system management interrupt with at least one other processing core of the computer system in response to determining that the at least one processing core is halted. An associated system and machine readable medium are also disclosed. | 2009-07-02 |
| 20090172234 | APPARATUS AND METHOD FOR IDENTIFYING SYSTEM STYLE - An apparatus and a method for identifying a system style are provided. The apparatus includes a motherboard and a peripheral backplane. The motherboard is suitable for assembling other backplanes. The peripheral backplane is coupled to the motherboard not only through a signal-data interface but also through an inter-integrated circuit (I2C) bus or a system management (SM) bus. The method includes following steps. First, an identification information is stored on the peripheral backplane. Next, the motherboard reads the identification information from the peripheral backplane through the I2C bus or the SM bus. The motherboard then identifies the system style according to the identification information and is then configured accordingly. Thereby, the motherboard needs not to be configured manually and can be directly applied in different chassis systems supported by the motherboard. | 2009-07-02 |
| 20090172235 | MEGASIM CARD ADAPTER - A MegaSIM adapter is disclosed allowing a MegaSIM card to be used in a standard card slot, such as an SD or MicroSD card slot, of a host device. | 2009-07-02 |
| 20090172236 | METHOD AND SYSTEM FOR FLEXIBLY SUPPLYING POWER TO A HIGH-END GRAPHICS CARD - A method and system for flexibly supplying power to a high-end graphics card is described. The graphics system includes the high-end graphics card and also a configurable power supply module, which is physically separated to the graphics card and connected to a power source external to the graphics system. The configurable power supply module converts a first voltage from the power source to a second voltage for the graphics card, wherein the second voltage satisfies a set of power supply specifications required by the graphics card. | 2009-07-02 |
| 20090172237 | Scalable Distributed Routing Scheme for PCI Express Switches - A Peripheral Component Interconnect (PCI) Express switch is provided. The PCI Express switch includes a first routing information bus connected to the first port; a second routing information bus connected to the second port; a third routing information bus connected to the third port; two routing slaves in the first port, each dedicated to listening to one of the second and the third routing information buses; two routing slaves in the second port, each dedicated to listening to one of the first and the third routing information buses; and two routing slaves in the third port, each dedicated to listening to one of the first and the second routing information buses. | 2009-07-02 |
| 20090172238 | BRIDGE CIRCUIT - A bridge circuit includes a bus, a memory interface module, a memory control module, and an external storage control module. The memory interface module receives a memory address from a processor via a memory interface and outputs the memory address to the bus. The memory address corresponds to one of a plurality of address regions of an address space of the processor. The memory control module receives the memory address via the bus and communicates with a memory when the memory address corresponds to a first one of the plurality of address regions. The external storage control module receives the memory address via the bus and communicates with an external storage device when the memory address corresponds to a second one of the plurality of address regions. | 2009-07-02 |
| 20090172239 | Method and Device for Coupling at Least Two Independent Bus Systems - There is described a method for coupling at least two independent bus systems and to a suitable device for carrying out said method, a cycle time T | 2009-07-02 |
| 20090172240 | METHODS AND APPARATUS FOR MEDIA REDIRECTION - A method includes generating a storage device request directed to a register of a computing device that is used to access a storage device of the compute device. The method further includes determining with a media redirection device to redirect the storage device request to a storage device connected to a network. The method further includes transmitting over a host bus of the computing device a packetized message representing the storage device request from the media redirection device to a network controller. An associated apparatus is also disclosed. | 2009-07-02 |
| 20090172241 | METHOD AND APPARATUS FOR ENHANCING THE GRAPHICS CAPABILITY OF A MOBILE COMPUTING DEVICE - One embodiment of the present invention sets forth a method, which includes the steps of detecting the presence of an external graphics subsystem after the external graphics subsystem is attached to the mobile computing device, transmitting a power enable signal to the external graphics subsystem, and activating PCIe signaling channels after having received a ready signal from the external graphics subsystem to enable data communications between the mobile computing device and the external graphics subsystem. | 2009-07-02 |
| 20090172242 | SYSTEM AND METHOD FOR CONNECTING A MASTER DEVICE WITH MULTIPLE GROUPINGS OF SLAVE DEVICES VIA A LINBUS NETWORK - A LINBUS communication network comprises a microcontroller unit containing processing circuitry for performing predefined digital processing functions. LINBUS communication network hardware is located within the microcontroller unit for digitally communicating with an off-chip LINBUS device for transmitting data thereto and receiving data therefrom. A plurality of LINBUS communication network interfaces selectively connects one of a plurality of groups of slave devices to the LINBUS network communications hardware. | 2009-07-02 |
| 20090172243 | Providing metadata in a translation lookaside buffer (TLB) - In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store bits for a memory page associated with the VA-to-PA translation, where the bits indicate attributes of information in the memory page. Other embodiments are described and claimed. | 2009-07-02 |
| 20090172244 | HIERARCHICAL SECONDARY RAID STRIPE MAPPING - Methods and apparatus of the present invention include new data and parity mapping for a two-level or hierarchical secondary RAID architecture. The hierarchical secondary RAID architecture achieves a reduced mean time to data loss compared with a single-level RAID architecture. The new data and parity mapping technique provides load-balancing between the disks in the hierarchical secondary RAID architecture and facilitates sequential access. | 2009-07-02 |
| 20090172245 | DELIVERING SECURED MEDIA USING A PORTABLE MEMORY DEVICE - In some embodiments an interface of a portable memory device is used to store content information in a hidden memory region of the portable memory device. The interface is also used to store information in a visible memory region of the portable memory device. The information stored in the visible memory region allows the content information stored in the hidden memory region to be accessed. Other embodiments are described and claimed. | 2009-07-02 |
| 20090172246 | DEVICE AND METHOD FOR MANAGING INITIALIZATION THEREOF - A host may initialize itself faster by enabling an associated storage device to respond to host access commands under specified conditions before the storage device has completed its own initialization. Embodiments of the invention include a storage device, a controller, a method of servicing commands, and a method of using a host that sends access commands to a storage device. Access commands to a flash memory use logical addresses to reference the memory contents. A controller translates the logical addresses to physical addresses using a mapping table that the controller constructs in volatile memory during initialization based on data retrieved from the flash memory. An access command satisfying a predefined condition is serviced before the controller completes the construction of the mapping table. | 2009-07-02 |
| 20090172247 | CONTROLLER FOR ONE TYPE OF NAND FLASH MEMORY FOR EMULATING ANOTHER TYPE OF NAND FLASH MEMORY - A controller for one type of NAND flash memory device that emulates another type of NAND flash memory device. The controller may include a host NAND interface to receive host data from a NAND host device, and a data aggregator for aggregating the host data with complementary data, to thereby create device data that is storable in a device page of an array of NAND flash memory cells of the NAND flash memory device. After creating the device data the controller writes the device data into a device page of the NAND flash memory cells. The controller also includes a data parser to parse host data from device data when data read operations are executed by the controller. If required, the controller uses the data parser to parse complementary data from device data to create device data when data writing operations are executed by the controller. | 2009-07-02 |
| 20090172248 | MANAGEMENT OF A FLASH MEMORY DEVICE - Methods, computing devices and machine readable medium to manage sector based file system accesses to block erasable flash memory devices are disclosed. One disclosed method includes allocating erasable blocks of a flash memory device to a volume and formatting the volume of a flash memory device with a file system designed to access the flash memory device via sectors that are each smaller than an erasable block. The method also includes writing a data unit to a special block of the erasable blocks and writing a sector mapping table unit to the special block to associate the data unit with a sector of the file system. The method further includes allocating a spare block of erasable blocks to support a reclaim process. | 2009-07-02 |
| 20090172249 | DYNAMICALLY ADJUSTING CACHE POLICY BASED ON DEVICE LOAD IN A MASS STORAGE SYSTEM - A dynamic cache policy manager for a mass memory may be used to decide whether a data request is to be routed to the cache or directly to the mass memory, based on estimated delays in processing the request. The choice may be based, at least partially, on the size of the respectively queues for the cache and mass memory. For write requests, the choice may be based on how many erase blocks are available in the cache. | 2009-07-02 |
| 20090172250 | RELOCATING DATA IN A MEMORY DEVICE - Systems and methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others. | 2009-07-02 |
| 20090172251 | Memory Sanitization - Apparatus and method for memory sanitization is disclosed, including a memory, the memory including—in whole or in part—multiple layers of memory, and control logic configured to perform a sanitize operation on a portion of the memory. In one example, a third dimensional memory array can constitute at least a portion of the multiple layers of memory. The multiple layers of memory may include non-volatile two-terminal cross-point memory arrays. Each non-volatile two-terminal cross-point memory array can include a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles that can be non-destructively determined by applying a read voltage across the terminals of the two-terminal memory element. The two-terminal memory elements retain stored data in the absence of power. The non-volatile two-terminal cross-point memory arrays can be vertically stacked upon one another and may be positioned on top of a logic plane that includes active circuitry. | 2009-07-02 |
| 20090172252 | Memory device and method for performing a write-abort-safe firmware update - A memory device and method for performing a write-abort-safe firmware update are disclosed. In one embodiment, a location in a memory of a memory device for a firmware update is allocated. The firmware update is written into the allocated location in the memory. A pointer is written to the firmware update in a directory, and a pointer is written to the directory in a location in the memory that is read during boot-up. In another embodiment, a block in a memory of a memory device is allocated for updated file system data comprising a firmware update and a directory. The updated file system data is written into the allocated location in the memory. A pointer is written to the firmware update in the directory, and a pointer is written to the updated file system data in a boot block in the memory, wherein the boot block is read during boot-up. | 2009-07-02 |
| 20090172253 | Methods and apparatuses for nonvolatile memory wear leveling - Apparatuses, systems, and computer program products that enable wear leveling of nonvolatile memory devices, such as flash memory devices, are disclosed. One or more embodiments an apparatus that has a receiver and a wear leveling module. The receiver may receive low-level write requests to update direct-mapped values of nonvolatile memory. The wear leveling module may determine physical locations of the nonvolatile memory that correspond to logical locations of the write requests. Alternative embodiments may comprise systems or apparatuses that include one or more various types of additional modules, such as low-level driver modules, error correction code modules, queue modules, bad block management modules, and flash translation layer modules. Other embodiments comprise computer program products that receive a direct-mapped low-level write request, determine a physical write location of nonvolatile memory that corresponds to a logical write location of the low-level write request. | 2009-07-02 |
| 20090172254 | METHOD FOR PREVENTING READ-DISTURB HAPPENED IN NON-VOLATILE MEMORY AND CONTROLLER THEREOF - A method for preventing read-disturb happened in non-volatile memory and a controller thereof are disclosed. The non-volatile memory includes a plurality of blocks, and the blocks are grouped into at least a data group and a spare group, each block includes a plurality of pages. The method includes recording read times of at least a first block of the blocks within the data group and then renewing the original data stored in the first block when the read times of the first block is greater than a predetermined value. | 2009-07-02 |
| 20090172255 | WEAR LEVELING METHOD AND CONTROLLER USING THE SAME - A wear leveling method for a multi level cell (MLC) NAND flash memory is provided. The flash memory includes a first zone and a second zone respectively having a plurality of blocks, wherein each of the blocks includes an upper page and a lower page. The wear leveling method includes: respectively determining whether to start a block swapping operation of a wear leveling process in the first zone and the second zone of the flash memory according to different start-up conditions; and respectively performing the block swapping operation in the first zone and the second zone, wherein the blocks in the first zone are accessed by using only the lower pages, and the blocks in the second zone are accessed by using both the upper pages and the lower pages. Thereby, the lifespan of the flash memory is effectively prolonged and meaningless consumption of system resources is avoided. | 2009-07-02 |
| 20090172256 | DATA WRITING METHOD FOR FLASH MEMORY, AND FLASH MEMORY CONTROLLER AND STORAGE DEVICE THEREOF - A data writing method for a block of a multi level cell NAND flash memory including upper page addresses and lower page addresses is provided, wherein a writing speed at the lower page addresses is higher than that at the upper page addresses. The data writing method includes receiving a writing command and determining whether an address to be written with new data in the writing command is the upper page address of the block. The method also includes copying old data previously recorded on the lower page addresses of the block as an old data backup when the address to be written in the writing command is the upper page address of the block and then writing the new data to the address to be written. Thus, old data may be protected while writing data to the upper page address of the multi level cell NAND flash memory. | 2009-07-02 |
| 20090172257 | System and method for performing host initiated mass storage commands using a hierarchy of data structures - Disclosed is a mass storage system and method for breaking a host command into a hierarchy of data structures. Different types of data structures are designed to handle different phases of tasks required by the host command, and multiple data structures may be used to handle portions of the host command in parallel, thereby allowing increased performance. The disclosed embodiments include a flash memory controller designed to allow a high degree of pipelining and parallelism. | 2009-07-02 |
| 20090172258 | Flash memory controller garbage collection operations performed independently in multiple flash memory groups - A flash memory controller connected to multiple flash memory groups performs independent garbage collection operations in each group. For each group, the controller independently determines the amount of free space and performs garbage collection operations if the amount falls below a threshold. | 2009-07-02 |
| 20090172259 | Mass storage controller volatile memory containing metadata related to flash memory storage - A volatile memory associated with a mass storage controller and a flash memory module. The volatile memory includes a number of tables containing information related to the flash memory storage, including a table storing physical flash memory addresses and a plurality of tables containing metadata. | 2009-07-02 |
| 20090172260 | Flash memory controller and system including data pipelines incorporating multiple buffers - A storage controller connected to a flash memory storage module, the controller and module including multiple sets of buffers. The buffers are part of one or more pipelines through which data is moved between the storage module and one or more hosts. | 2009-07-02 |
| 20090172261 | Multiprocessor storage controller - A storage controller containing multiple processors. The processors are divided into groups, each of which handles a different stage of a pipelined process of performing host reads and writes. In one embodiment, the storage controller operates with a flash memory module, and includes multiple parallel pipelines that allow plural host commands to be handled simultaneously. | 2009-07-02 |
| 20090172262 | Metadata rebuild in a flash memory controller following a loss of power - A method of rebuilding metadata in a flash memory controller following a loss of power. The method includes reading logical address information associated with an area of flash memory, and using time stamp information to determine if data stored in the flash memory area is valid. | 2009-07-02 |
| 20090172263 | Flash storage controller execute loop - In a storage controller connected to a flash memory module, an execute loop used to carry out tasks related to reading or writing data from the module. The loop includes reading a data structure from a queue and carrying out a task specified by the data structure, unless resources required by the task are not available, in which event the loop moves on to another data structure stored in another queue. Data structures bypassed by the loop are periodically revisited, until all tasks required are completed. Data structures store state information that is updated when tasks are completed. | 2009-07-02 |
| 20090172264 | SYSTEM AND METHOD OF INTEGRATING DATA ACCESSING COMMANDS - A data accessing command integration method includes the following steps. Firstly, M data accessing commands are sequentially received through a bus, wherein N data accessing commands contained in the M data accessing commands have the same command type and comply with a sequential address relationship. Next, the N data accessing commands are re-ordered according to the addressing sequence, so that a first data corresponding to the re-ordered N data accessing commands are sequentially accessed in the data memory. | 2009-07-02 |
| 20090172265 | FLASH MEMORY DEVICE HAVING SECURE FILE DELETION FUNCTION AND METHOD FOR SECURELY DELETING FLASH FILE - Disclosed is a flash memory device having a secure flash file deletion function and a method for securely deleting a flash file. Data and object headers as actual contents of the flash file are separately stored in data blocks and header blocks. At this time, the data is encrypted and stored, and a decryption key is included in an object header and stored in a header block. When the flash file is deleted, the object header is deleted by searching the header block where the object header including the decryption key is stored. In order to search the header block, a binary tree structure is used in which a terminal node indicates an LSB of a file ID. Disclosed may be applied to an embedded system where a flash memory is used as a storage medium. In particular, disclosed is suitable for a NAND flash memory device. | 2009-07-02 |
| 20090172266 | MEMORY SYSTEM - A memory system includes a NAND flash memory including a memory block containing a plurality of pages, and a controller which controls write of data to the flash memory, and includes a scrambling circuit which converts the data into a pseudo random number, wherein the scrambling circuit includes an initial value generator which generates an initial value for every segment, an initial value shifter which shifts the initial value by N bits for every page address, a pseudo random number generator which generates a pseudo random number sequence by an M-sequence by using the initial value shifted N bits, and a random number adder which adds the pseudo random number sequence to the data. | 2009-07-02 |
| 20090172267 | REFRESH METHOD OF A FLASH MEMORY - A flash memory device includes a flash memory that stores many physical data blocks, a refresh management table that stores indications of the number of times each individual physical data block has been read, and a controller responsive to read and erase control signals from a source external to the flash memory device, and to the stored indications of the refresh management table for controlling reading, erasing and refreshing of the individual physical data blocks. In response to the number of times each individual physical data block has been read being equal to or exceeding a limit value, the controller refreshes the individual physical data block associated with the indication equaling or exceeding the limit value. | 2009-07-02 |
| 20090172268 | METHOD FOR SECURING A MICROPROCESSOR, CORRESPONDING COMPUTER PROGRAM AND DEVICE - A method is provided for securing a microprocessor containing at least one main program, which operates with at least one memory. The method includes implementing counter-measures, during which additional operations, that are not required for the main program, are implemented so as to modify the consumption of current and/or the processing time of the microprocessor. The method also includes: identification of at least one address or one memory zone of the memory(ies), called critical addresses, and which contain, or which may contain, critical data for said main program; monitoring the addressing ports of the memory(ies), so as to detect the access to the critical address(es); and activation of the step of implementing counter-measures, when an access to the critical address(es) is detected. | 2009-07-02 |
| 20090172269 | NONVOLATILE MEMORY DEVICE AND ASSOCIATED DATA MERGE METHOD - A memory system is disclosed with a nonvolatile memory adapted to store a file system containing file system information, and a controller adapted to read the file system information and perform a merge operation. | 2009-07-02 |
| 20090172270 | DEVICE, SYSTEM, AND METHOD OF MEMORY ALLOCATION - Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said DIMM to a memory page of an Operating System, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the Operating System. | 2009-07-02 |
| 20090172271 | SYSTEM AND METHOD FOR EXECUTING FULL AND PARTIAL WRITES TO DRAM IN A DIMM CONFIGURATION - In an embodiment of the invention, a host or other controller writing to multiple DRAMs in a DIMM configuration determines whether there is full write request to at least one of the multiple DRAM's and a partial write request to at least another one of the multiple DRAM's. If so, then the host parses data associated with the full write request into a first portion and a second portion. The host then outputs a first partial write command associated with the first portion and a second partial write command associated with the second portion to the DIMM. Other embodiments are described. | 2009-07-02 |
| 20090172272 | Method and a computer for storage area management - A method for storage management is provided which displays the materials on which it is determined which of the thin provisioning volume or the logical unit (LU) is to be used for storage promotion. The method is executed in a computer system having one or more host computers, one or more storage subsystems, and a management computer. The storage subsystem includes a physical disk and a disk controller. The disk controller provides the host computer with the thin provisioning volume. The management computer obtains the allocated capacity from the disk controller and the host-recognized capacity from the host computer. By subtracting the obtained allocated capacity from the host-recognized capacity, the management computer calculates an improved capacity. By dividing the calculated improved capacity by the obtained host-recognized capacity, the management computer calculates an improvement ratio and displays the calculated improvement ratio. | 2009-07-02 |
| 20090172273 | METHOD AND SYSTEM FOR DISK STORAGE DEVICES REBUILD IN A DATA STORAGE SYSTEM - In a data storage system, failed disk drives are switched temporarily off-line to be quickly rebuilt by executing a journaling/rebuild algorithm which tracks the updates to the failed disk drive into a journal structure created in a non-volatile memory. The journal information is used to update those data sections of the disk drive affected by updates after the disk drive is failed. The journal information is stored in bit maps indicating which portions of the disk drive have been updated with new data while the disk was failed. As an option, the system permits verification of data consistency on the data section of the disk drive which have not been affected by the updates. The journaling/rebuild of failed disks is applicable, among others, to RAID data storage systems. | 2009-07-02 |
| 20090172274 | STORAGE DEVICE HAVING DIRECT USER ACCESS - Various methods, devices and systems are described for providing distributed storage services. A data storage device is capable of initiating a communication session with an external entity such as a local host computer (and vice versa) coupled directly to the data storage device, a remote server computer, or directly with remote data storage devices with or without intervention by a local host computer. | 2009-07-02 |
| 20090172275 | DATA USAGE PROFILING BY LOCAL STORAGE DEVICE - A local storage device (LSD) is provided configured to have a host device (HD) in communication with the LSD. The LSD includes a memory array. The LSD is configured to characterize data access usage of the LSD by at least one program executing on the HD. The LSD is configured to monitor access to the LSD as a result of data access operations by the HD relative to the memory array of the LSD. The LSD is additionally configured to determine characteristics of the monitored access. The LSD is additionally configured to, based on characteristics of the monitored access, determine and store data on the LSD indicative of the characterized monitored access. | 2009-07-02 |
| 20090172276 | STORAGE DEVICE HAVING REMOTE STORAGE ACCESS - A method of servicing a command sent from a host device file system (HDFS) within a host device (HD) by a local storage device (LSD) in communication with the HD is described. The method includes receiving a first command at the LSD instructing the LSD to execute an operation on associated logical addresses. If the first command is associated with at least a first set of logical addresses, the method includes servicing the first command by the LSD at least by way of sending a second command to a device (RD) external to the LSD that instructs the RD to execute an operation on memory locations within the RD. If the first command is not associated with the first set of logical addresses, the method includes servicing the first command by the LSD only by way of operations executed by the LSD on memory locations within the LSD. | 2009-07-02 |
| 20090172277 | RAID LEVEL MIGRATION METHOD FOR PERFORMING ONLINE RAID LEVEL MIGRATION AND ADDING DISK TO DESTINATION RAID, AND ASSOCIATED SYSTEM - A Redundant Array of Independent Disks (RAID) level migration method for performing an online RAID level migration and adding a disk to a destination RAID is provided. First, the required information for migration is specified, and then a degraded mode is used to establish the destination RAID, and file system is built on the destination RAID. The file system of the source disk device is configured to be read-only, and all data of the source disk device are duplicated to the destination RAID. After completing file duplication, the destination RAID replaces the source disk device. The operation of the source disk device is stopped and the source disk device is added to the destination RAID. As a result, the RAID migration is accomplished. In addition, an associated RAID level migration system is further provided. | 2009-07-02 |
| 20090172278 | Method and System for Backing Up and Restoring Online System Information - A method and system for copying operating system information to said at least two storage devices, selectively hiding at least one, but not all, of the storage devices from being accessed by the operating system, and selectively revealing one or more of said hidden storage devices as needed to permit access to the information stored therein. | 2009-07-02 |
| 20090172279 | System For Accessing A Removable Non-Volatile Memory Card - A non-volatile memory interface device contains first, second, and third communication interfaces configured for first, second, and third protocols, respectively. The device also contains a memory controller that selectively communicates between the first and second communication interfaces, and between the first and third communication interfaces. The device also contains a receptacle that can receive a removable non-volatile memory card and electrically connect the card to the second and third communication interfaces. The first communication interface may be a Universal Serial Bus Interface and may be in communicatively coupled to a USB connector. The second communication interface may be an ISO 7816 interface. A communications adapter is an enclosure containing a receptacle that can receive a non-volatile memory card and a USB connector. The USB connector is communicatively coupled with the non-volatile memory card in the receptacle. The receptacle's second communication interface with the non-volatile memory card is disabled. | 2009-07-02 |
| 20090172280 | SYSTEMS AND METHODS FOR FAST STATE MODIFICATION OF AT LEAST A PORTION OF NON-VOLATILE MEMORY - A method is provided for reducing the number of writes in a non-volatile memory ( | 2009-07-02 |
| 20090172281 | Memory device and method for content virtualization - A memory device and method for content virtualization are disclosed. In one embodiment, a plurality of directories are created in the memory of the memory device, wherein each of the plurality of directories points to a same storage location of the digital content. In another embodiment, a first header for the digital content is stored in each of the different directories, wherein the first header comprises information about where to find the digital content in the memory. In yet another embodiment, the memory device comprises circuitry that receives an identification of a host device in communication with the memory device and reorganizes a directory structure of the memory in accordance with the identification of the host device, wherein the reorganization results in the digital content appearing to be located in a directory expected by the host device. | 2009-07-02 |
| 20090172282 | DIGITAL CIRCUITS AND METHODS FOR TESTING A DIGITAL CIRCUIT - Digital circuits and methods for testing a digital circuit are disclosed. One embodiment provides a digital circuit having a first plurality of storage elements, and a second plurality of storage elements. The digital circuit is operable in a first operation mode and in a second operation mode. In the first operation mode, the storage elements of the first plurality of storage elements operate according to their intended use within the digital circuit and the storage elements of the second plurality of storage elements are connected in series. In the second operation mode, the first plurality of storage elements is connected to the second plurality of storage elements to allow data exchange between the first plurality of storage elements and the second plurality of storage elements. | 2009-07-02 |
| 20090172283 | Reducing minimum operating voltage through hybrid cache design - Methods and apparatus to reduce minimum operating voltage through a hybrid cache design are described. In one embodiment, a cache with different size bit cells may be used, e.g., to reduce minimum operating voltage of an integrated circuit device that includes the cache and possibly other logic (such as a processor). Other embodiments are also described. | 2009-07-02 |
| 20090172284 | METHOD AND APPARATUS FOR MONITOR AND MWAIT IN A DISTRIBUTED CACHE ARCHITECTURE - A method and apparatus for monitor and mwait in a distributed cache architecture is disclosed. One embodiment includes an execution thread sending a MONITOR request for an address to a portion of a distributed cache that stores the data corresponding to that address. At the distributed cache portion the MONITOR request and an associated speculative state is recorded locally for the execution thread. The execution thread then issues an MWAIT instruction for the address. At the distributed cache portion the MWAIT and an associated wait-to-trigger state are recorded for the execution thread. When a write request matching the address is received at the distributed cache portion, a monitor-wake event is then sent to the execution thread and the associated monitor state at the distributed cache portion for that execution thread can be reset to idle. | 2009-07-02 |
| 20090172285 | TRACKING TEMPORAL USE ASSOCIATED WITH CACHE EVICTIONS - A method and apparatus for tracking temporal use associated with cache evictions to reduce allocations in a victim cache is disclosed. Access data for a number of sets of instructions in an instruction cache is tracked at least until the data for one or more of the sets reach a predetermined threshold condition. Determinations whether to allocate entry storage in the victim cache may be made responsive in part to the access data for sets reaching the predetermined threshold condition. A micro-operation can be inserted into the execution pipeline in part to synchronize the access data for all the sets. Upon retirement of the micro-operation from the execution pipeline, access data for the sets can be synchronized and/or any previously allocated entry storage in the victim cache can be invalidated. | 2009-07-02 |
| 20090172286 | Method And System For Balancing Host Write Operations And Cache Flushing - A method and system for balancing host write operations and cache flushing is disclosed. The method may include steps of determining an available capacity in a cache storage portion of a self-caching storage device, determining a ratio of cache flushing steps to host write commands if the available capacity is below a desired threshold and interleaving cache flushing steps with host write commands to achieve the ratio. The cache flushing steps may be executed by maintaining a storage device busy status after executing a host write command and utilizing this additional time to copy a portion of the data from the cache storage into the main storage. The system may include a cache storage, a main storage and a controller configured to determine and execute a ratio of cache flushing steps to host write commands by executing cache flushing steps while maintaining a busy status after a host write command. | 2009-07-02 |
| 20090172287 | DATA BUS EFFICIENCY VIA CACHE LINE USURPATION - Embodiments of the current invention permit a user to allocate cache memory to main memory more efficiently. The processor or a user allocates the cache memory and associates the cache memory to the main memory location, but suppresses or bypassing reading the main memory data into the cache memory. Some embodiments of the present invention permit the user to specify how many cache lines are allocated at a given time. Further, embodiments of the present invention may initialize the cache memory to a specified pattern. The cache memory may be zeroed or set to some desired pattern, such as all ones. Alternatively, a user may determine the initialization pattern through the processor. | 2009-07-02 |
| 20090172288 | Processor having a cache memory which is comprised of a plurality of large scale integration - To provide an easy way to constitute a processor from a plurality of LSIs, the processor includes: a first LSI containing a processor; a second LSI having a cache memory; and information transmission paths connecting the first LSI to a plurality of the second LSIs, in which the first LSI contains an address information issuing unit which broadcasts, to the second LSIs, via the information transmission paths, address information of data, the second LSI includes: a partial address information storing unit which stores a part of address information; a partial data storing unit which stores data that is associated with the address information; and a comparison unit which compares the address information broadcast with the address information stored in the partial address information storing unit to judge whether a cache hit occurs, and the comparison units of the plurality of the second LSIs are connected to the information transmission paths. | 2009-07-02 |
| 20090172289 | CACHE MEMORY HAVING SECTOR FUNCTION - A cache memory having a sector function, operating in accordance with a set associative system, and performing a cache operation to replace data in a cache block in the cache way corresponding to a replacement cache way determined upon an occurrence of a cache miss comprises: storing sector ID information in association with each of the cache ways in the cache block specified by a memory access request; determining, upon the occurrence of the cache miss, replacement way candidates, in accordance with sector ID information attached to the memory access request and the stored sector ID information; selecting and outputting a replacement way from the replacement way candidates; and updating the stored sector ID information in association with each of the cache ways in the cache block specified by the memory access request, to the sector ID information attached to the memory access request. | 2009-07-02 |
| 20090172290 | Replacing stored content to make room for additional content - The storage of items, such as media items, in a playback device may be managed automatically without user intervention in some embodiments. An algorithm, based on heuristics, may predict which items are most likely to be used or played in the future and, based on that determination, may select the least likely to be used items for replacement. In addition, replacement may be affected by the size of space needed for additional storage versus the size of particular candidates for replacement. | 2009-07-02 |
| 20090172291 | MECHANISM FOR EFFECTIVELY CACHING STREAMING AND NON-STREAMING DATA PATTERNS - A method and apparatus for efficiently caching streaming and non-streaming data is described herein. Software, such as a compiler, identifies last use streaming instructions/operations that are the last instruction/operation to access streaming data for a number of instructions or an amount of time. As a result of performing an access to a cache line for a last use instruction/operation, the cache line is updated to a streaming data no longer needed (SDN) state. When control logic is to determine a cache line to be replaced, a modified Least Recently Used (LRU) algorithm is biased to select SDN state lines first to replace no longer needed streaming data. | 2009-07-02 |
| 20090172292 | ACCELERATING SOFTWARE LOOKUPS BY USING BUFFERED OR EPHEMERAL STORES - A method and apparatus for accelerating lookups in an address based table is herein described. When an address and value pair is added to an address based table, the value is privately stored in the address to allow for quick and efficient local access to the value. In response to the private store, a cache line holding the value is transitioned to a private state, to ensure the value is not made globally visible. Upon eviction of the privately held cache line, the information is not written-back to ensure locality of the value. In one embodiment, the address based table includes a transactional write buffer to hold addresses, which correspond to tentatively updated values during a transaction. Accesses to the tentative values during the transaction may be accelerated through use of annotation bits and private stores as discussed herein. Upon commit of the transaction, the values are copied to the location to make the updates globally visible. | 2009-07-02 |
| 20090172293 | METHODS FOR PREFETCHING DATA IN A MEMORY STORAGE STRUCTURE - A method includes detecting a cache miss. The method further includes, in response to detecting the cache miss, traversing a plurality of linked memory nodes in a memory storage structure being used to store data to determine if the memory storage structure is a binary tree. The method further includes, in response to determining that the memory storage structure is a binary tree, prefetching data from the memory storage structure. An associated machine readable medium is also disclosed. | 2009-07-02 |
| 20090172294 | Method and apparatus for supporting scalable coherence on many-core products through restricted exposure - In one embodiment, a multi-core processor having cores each associated with a cache memory, can operate such that when a first core is to access data owned by a second core present in a cache line associated with the second core, responsive to a request from the first core, cache coherency state information associated with the cache line is not updated. A coherence engine associated with the processor may receive the data access request and determine that the data is of a memory page owned by the first core and convert the data access request to a non-cache coherent request. Other embodiments are described and claimed. | 2009-07-02 |
| 20090172295 | In-memory, in-page directory cache coherency scheme - In an embodiment, the method provides receiving a memory access request for a demanded cache line from a processor of a plurality of processors; accessing coherency information associated with the demanded cache line from a memory unit by bringing in from a memory page in which the demanded cache line is stored, the memory page also including a directory line having coherency information corresponding to the demanded cache line; reading data associated with the demanded cache line in accordance with the coherency information; and returning the data to the processor. | 2009-07-02 |
| 20090172296 | Cache Memory System and Cache Memory Control Method - A cache memory system including a processing unit and a cache memory which is connected to the processing unit, wherein when a store instruction of storing write data into a certain address is executed, the cache memory system executes selectively one of, a first operation mode of allocating an area of the address to the cache memory in response to a generation of a cache miss due to an access to the address, copying data of the address of the main memory unit to the cache memory and then rewriting the copied data on the cache memory using the write data, and a second operation mode in response to a generation of a cache miss due to the access to the address and storing the write data to the cache memory without copying data of the address of the main memory unit to the allocated area on the cache memory. | 2009-07-02 |
| 20090172297 | CACHE MEMORY SYSTEM AND CACHE MEMORY CONTROL METHOD - A cache memory system that is connected to a computation device and a memory device includes: a data array that includes a plurality of blocks composed of a plurality of words; a storage unit that, with respect to a block, which stores data in at least one of said words, from among the plurality of blocks, stores an address group of the memory device that is placed in correspondence with that block; a write unit that, when an address from the computation device is not in the storage unit on receiving a write instruction from the computation device, allocates any of the plurality of blocks as a block for writing, and writes the data from the computation device to any word in the block for writing; a word state storage unit that stores word information indicating one or more words, to which the data have been written by the write unit, from among words in the block for writing; and a read unit that, upon having read the data from words indicated by the word information when receiving a read instruction from the computation device, deletes the word information. | 2009-07-02 |
