| 27th week of 2009 patent applcation highlights part 51 |
| Patent application number | Title | Published |
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| 20090170193 | STEM CELLS - The present invention relates to an isolated stem cell population wherein said stem cells are CD34+, capable of self regeneration, capable of differentiation into ectodermal, mesodermal and endodermal cells and capable of adhering to tissue-culture grade plastic as well as to methods of isolation of said cells, methods of culturing and differentiation thereof, the progeny of such methods of differentiation as well as uses, including therapeutic uses of the stem cells and their differentiated progeny. | 2009-07-02 |
| 20090170194 | TEAL FLUORESCENT PROTEINS - An isolated nucleic acid sequence encoding a non-oligomerizing Clavularia teal fluorescent protein (TFP) variant having a tyrosine-derived chromophore, and fragments and derivatives thereof. Also provided is a method for engineering the nucleic acid sequence, a vector comprising the nucleic acid sequence, a host cell comprising the vector, and use of the vector in a method for expressing the nucleic acid sequence. The present invention further provides an isolated nucleic acid, or mimetic or complement thereof, that hybridizes under stringent conditions to the nucleic acid sequence. Additionally, the present invention provides a non-oligomerizing TFP variant encoded by the nucleic acid sequence, as well as derivatives, fragments, and homologues thereof. Also provided is an antibody that specifically binds to the TFP variant. The present invention further provides a tandem dimer comprising two TFP dimers, operatively linked by a peptide linker. | 2009-07-02 |
| 20090170195 | CURCUMIN-HYALURONAN COMPOUNDS - A dissociable complex is disclosed. The dissociable complex includes at least one molecule of curcumin, at least one molecule of hyaluronic acid, and at least one linker molecule, wherein a first portion of the linker molecule is bonded to the curcumin and a second portion of the linker molecule is bonded to the hyaluronic acid. | 2009-07-02 |
| 20090170196 | CANCER TREATMENT USING C-TYPE NATRIURETIC PEPTIDE - The present invention includes a method of utilizing four peptide hormones to inhibit the growth of cancer(s). A dramatic decrease in the number of human pancreatic adenocarcinoma cells (i.e., the type of cancer with the highest mortality, with patients only surviving four months) was observed responsive to treatment. The application of the invention would be to utilize one or more of these peptide hormones alone and/or in combination to treat cancer. The ability of these peptide hormones to decrease the number of adenocarcinoma cells has implications for adenocarcinomas at other sites in the body with the majority of cancers of the breast, colon and prostate also being adenocarcinomas. Adenocarcinomas also occur in the lung and other tissues. Treatment of a wide variety of cancers in addition to adenocarcinomas is anticipated by the present invention. | 2009-07-02 |
| 20090170197 | Nucleic Acid-Mediated Treatment of Diseases or Conditions Related to Levels of Vascular Endothelial Growth Factor Receptor (VEGF-R) - The present invention relates to nucleic acid molecules such as ribozymes, DNAzymes, short interfering RNA (siRNA), short interfering nucleic acid (siNA), and antisense which modulate the synthesis, expression and/or stability of an mRNA encoding one or more receptors of vascular endothelial growth factor, such as flt-1 (VEGFR1) and/or KDR (VEGFR2). Nucleic acid molecules and methods for the inhibition of angiogenesis and treatment of cancer and other conditions associated with VEGF-R are provided, optionally in conjunction with other therapeutic agents such as interferons. | 2009-07-02 |
| 20090170198 | Differentiation of human embryonic stem cells - The present invention provides methods to promote the differentiation of pluripotent stem cells and the products related to or resulting from such methods. In particular, the present invention provides an improved method for the formation of pancreatic hormone expressing cells and pancreatic hormone secreting cells. In addition, the present invention also provides methods to promote the differentiation of pluripotent stem cells without the use of a feeder cell layer and the products related to or resulting from such methods. The present invention also provides methods to promote glucose-stimulated insulin secretion in insulin-producing cells derived from pluripotent stem cells. | 2009-07-02 |
| 20090170199 | SEPARATION AND SORTING OF DIFFERENT BIOLOGICAL OBJECTS - The present invention relates to a method for the separation of biological objects in a solution which have different viscoelastic properties, wherein said method comprises a filtration step allowing the higher viscoelastic biological objects to pass through the membrane while retaining the lower viscoelastic biological objects above the membrane, and a recovery step wherein the separated lower viscoelastic biological objects are recovered above or onto the membrane and/or the separated higher viscoelastic biological objects are recovered in the filtrate. Advantageously, the biological objects are cells. More advantageously, the recovered cells are viable cells. In one preferred embodiment, the cells are tumor cells. In another preferred embodiment, the cells are fetal cells and the method finds an application in prenatal diagnosis. | 2009-07-02 |
| 20090170200 | STEM CELL MEDIUM - A medium for culturing stem cell. The stem cell medium of the invention comprises a fetal bovine serum, one or plurality of amino acid, one or plurality of vitamin, one or plurality of growth factor, one or plurality of inorganic salt, one or plurality of antioxidant, wherein the stem cell medium has a calcium concentration of less than about 1.8 mM, and the fetal bovine serum is present in an amount of less than about 10% by volume of the medium. The stem cell medium of the invention can maintain the proliferative and self-renewal capacity of the stem cells and keep stem cells at a steady stage. | 2009-07-02 |
| 20090170201 | COMPOSITIONS AND METHODS OF MAKING EMBRYONIC STEM CELLS - The invention relates to cell proliferation, cell differentiation, male infertility, male fertility and to compositions and methods involved therein. | 2009-07-02 |
| 20090170202 | Nucleic acids that enhance the synthesis of 2-acetyl-1-pyrroline in plants and fungi - The aromatic compound 2-acetyl-1-pyrroline-is the major potent flavor component of all aromatic rice. This present invention provides transgenic rice plants in which 2-acetyl-1-pyrroline is synthesized at a level greater than in naturally occurring non-aromatic varieties. The transgenic plants have reduced expression of the Os2AP gene and protein, resulting in an aromatic phenotype. | 2009-07-02 |
| 20090170204 | Novel cosmetic designs and products using intronic RNA - The present invention relates to a method and composition for generating a non-naturally occurring intron and its components capable of being processed into small hairpin RNA (shRNA) and/or microRNA (miRNA) molecules by skin cells and thus inducing specific gene silencing effects on skin pigment-related genes and/or aging-causing genes in the cells. The gene silencing effects so obtained are not only useful for lightening and whitening skin colors but also useful for suppressing unwanted aging gene activities in skins. | 2009-07-02 |
| 20090170205 | METHOD OF MAINTENANCE AND EXPANSION OF HEMATOPOIETIC STEM CELLS - [Problem] Provided are a method of maintaining/expanding hematopoietic stem cells, a hematopoietic stem cell population obtained by the method, a hematopoietic function ameliorating agent based on administration of the hematopoietic stem cell population to a living organism, and the like. | 2009-07-02 |
| 20090170206 | METHOD FOR HOMOLOGOUS RECOMBINATION IN EUKARYOTIC CELLS - We disclose a method to construct eukaryotic cells having a target sequence in a chromosomal DNA sequence replaced by a desired replacement sequence, comprising: modifying a parent eukaryotic cell with a preference for NHR to provide a eukaryotic cell having an increased HR/NHR ratio as compared to the parent cell, providing a DNA molecule comprising a first DNA fragment comprising a desired replacement sequence flanked at its 5′ and 3′ sides by DNA sequences substantially homologous to sequences of the chromosomal DNA flanking the target sequence and a second DNA fragment comprising an expression cassette comprising a gene encoding a selection marker operably linked to regulatory sequences functional in the eukaryotic cell, transforming the modified eukaryotic cells with the DNA molecule, selecting transformed progeny cells having the DNA molecule inserted into the chromosome, deselecting transformed progeny cells having the DNA molecule inserted into the chromosome via NHR by expression of the selection marker, and obtaining cells wherein the target sequence in the chromosomal DNA sequence is replaced by the desired replacement sequence. | 2009-07-02 |
| 20090170207 | REFERENCE PH SENSOR, PREPARATION AND APPLICATION THEREOF - A reference pH sensor, the preparation and application thereof. The reference pH sensor is an extended gate field effect transistor (EGFET) structure and comprises a metal oxide semiconductor field effect transistor (MOSFET) on a semiconductor substrate, a sensing unit comprising a substrate, a solid-state conductive sensing layer on the substrate, and a polypyrrole layer on the solid-state conductive sensing layer, and a metal wire connecting the MOSFET and the sensing unit. | 2009-07-02 |
| 20090170208 | Biomarkers for ovarian cancer - The present invention provides protein-based biomarkers and biomarker combinations that are useful in qualifying ovarian cancer status in a patient. In particular, it has been found that the biomarkers set forth in Table 1 are biomarkers for ovarian cancer. The biomarkers can be detected by SELDI mass spectrometry. | 2009-07-02 |
| 20090170209 | HYDROGEL CHEMICAL SENSOR - An apparatus and method for detecting an analyte wherein a member may respond to mechanical stress induced by a volume change of a sensitive hydrogel upon sensing an analyte and wherein the mechanical stress may be detected by a detector. | 2009-07-02 |
| 20090170210 | MEASURING DEVICE, MEASURING APPARATUS AND METHOD OF MEASURING - The measuring device of the invention includes: a first container and a second container for holding a sample; and an optical measurement part for carrying out an optical measurement. The first container has a first sample supply inlet for supplying a sample containing an analyte to the first container and at least one electrode. The second container has a second sample supply inlet for supplying the sample to the second container and a reagent holding part for holding a reagent for the optical measurement. | 2009-07-02 |
| 20090170211 | SENSING SWITCH AND DETECTING METHOD USING THE SAME - Provided are a sensing switch and a sensing method using the same. The sensing switch includes: a substrate; a supporter on the substrate; a sensing plate that is connected to a side of the supporter and is in parallel with the substrate by a predetermined distance; a receptor binding region on an upper surface of an end portion of the sensing plate; an electric or magnetic field generation device that induces deflection of the sensing plate when a receptor bound to the receptor binding region is selectively bound to an electrically or magnetically active ligand; and a pair of switching electrodes that are separated by a predetermined distance and is connected when the sensing plate contacts the substrate due to the deflection of the sensing plate. A target material need not be labelled, a signal processing of a fluorescent or electrical detection signal using an analysis apparatus is not required, and a signal can be directly decoded by confirming whether a current flows through the switch. | 2009-07-02 |
| 20090170212 | RAPID MAGNETIC BIOSENSOR - The present invention relates to methods and (bio)sensor systems. Herein, magnetic fields are applied in order to transport magnetic particles laterally over a sensor surface with analyte specific probes. The methods of the invention allow the specific binding of magnetic particles to the sensor surface, while aspecific and unbound particles are removed. | 2009-07-02 |
| 20090170213 | High-Throughput Screening of Enantiomeric Excess (EE) - The present invention provides a method for high-throughput screening of enantiomeric excess (ee), comprising synthesizing a sensor made from an aggregate of gold nanoparticles whose surfaces have been elaborated with a chiral “host” that includes two optically pure binaphthol groups linked together by a diethanolamine bridge that is tethered via nitrogen to its associated gold nanoparticle, and in which aggregate the individual particles are held together by a bridging chiral “di-guest,” which contains an amino acid functionality at both ends and which interacts with the surface-bound hosts through hydrogen bonds. To screen, one adds a chiral analyte, which may be the product of an asymmetric catalytic reaction, or some other chiral species, in the form of a scalemic solution to a solution containing the aforemeritioned aggregate wherein one enantiomer of the analyte competes effectively with the “di-guest” for the “host,” while the other does not, and wherein a diastereoselective dispersion of the aggregate occurs, which brings about a large shift in the naked-eye-visible plasmon resonance absorption band of the gold nanoparticles, from a long wavelength for the aggregated nanoparticles to a shorter wavelength for the dispersed particles, and wherein the extent of the colour change is indicative of the degree to which the aggregate is dispersed and provides a rapid and effective measure of the ee of the chiral analyte. | 2009-07-02 |
| 20090170214 | Luminescent Reporter Modality for Analyzing an Assay - An optical analysis flow system and a method of assay analysis includes a means for facilitating activation of a luminescent material coupled to particles entrained within a fluid assay, wherein the means is arranged such that the activation of the luminescent material is conducted at a site along a flow path of the fluid assay prior to an examination zone of the optical analysis flow system. The method further includes measuring luminescent light emitting from the particles as they flow through the examination zone. Another method of assay analysis includes respectively measuring different types of luminescent light emission from a first set and a second set of particles comprising a fluid assay. An optical analysis system includes at least two distinct means for respectively facilitating the activation of at least two different luminescent materials coupled to particles of a fluid assay. | 2009-07-02 |
| 20090170215 | Selection of non-small-cell lung cancer patients for treatment with monoclonal antibody drugs targeting EGFR pathway - Methods using mass spectral data analysis and a classification algorithm provide an ability to determine whether a non-small-cell lung cancer (NSCLC) patient is likely to benefit from a monoclonal antibody drug targeting an epidermal growth factor receptor pathway. A mass spectrum is obtained from a sample (e.g. blood sample) from the patient. One or more predefined pre-processing steps are performed on the mass spectrum. Values of selected features in the spectrum at one or more predefined m/z ranges are obtained after the pre-processing steps have been performed. Such values are used in a classification algorithm using a training set comprising class-labeled spectra produced from samples from other patients to identify the patient as being likely to benefit from treatment with the drug. | 2009-07-02 |
| 20090170216 | Selection of colorectal cancer patients for treatment with drugs targeting EGFR pathway - Methods using mass spectral data analysis and a classification algorithm provide an ability to determine whether a colorectal cancer (CRC) patient is likely to benefit from a drug targeting an epidermal growth factor receptor pathway, such as monoclonal antibody EGFR inhibitors. | 2009-07-02 |
| 20090170217 | DEVICE FOR SAMPLE PRETREATMENT, REACTOR SHEET, AND METHOD OF SAMPLE ANALYSIS - An object of the present invention is to introduce a sample solution into the minute and hydrophobic inside of a reactor for a pretreatment while avoiding bubble formation. According to the present invention, a reactor that has at least one portion having a width of 90% or less of its whole width between an inflow opening and an outflow opening is constructed on a planar substrate. | 2009-07-02 |
| 20090170218 | METHODS FOR DETECTION OF CYCLOSPORIN A - Methods and reagents are disclosed for determining the presence and/or amount of cyclosporin A in a medium suspected of containing cyclosporin A. In the method a combination is provided in a medium. The combination comprises (i) the sample, (ii) a first member of a signal producing system (sps) associated with a first support wherein the first sps member is capable of activating a second member of the sps and wherein the first support is associated with a first member of a specific binding pair, and (iii) the second sps member associated with a second support wherein the second sps member is activatable by the first sps member. The second support comprises either (I) cyclosporin C or cyclosporin A and the combination further comprises a conjugate of an antibody for cyclosporin A and a second member of the specific binding pair or (II) antibody for cyclosporin A and the combination further comprises a conjugate of cyclosporin A and a second member of the specific binding pair. The combination is subjected to conditions for binding of cyclosporin A to the antibody for cyclosporin A. The first sps member is activated and the amount of signal generated by the second sps member is detected. The amount of signal is related to the presence and/or amount of cyclosporin A in the sample. | 2009-07-02 |
| 20090170219 | Nucleic acid capable of binding to immunoglobulin G and use thereof - The present invention provides a novel aptamer for IgG and a method for utilizing the same and the like. More specifically, the present invention provides an aptamer that binds to an Fc region of IgG (e.g., human IgG); a complex comprising an aptamer and a functional substance bound thereto (e.g., affinity substance, labeling substance, enzyme, drug, toxin, drug delivery vehicle); a solid phase carrier with an aptamer or complex immobilized thereon; medical equipment comprising a solid phase carrier; a method for antibody purification comprising adsorbing an IgG antibody to a solid phase carrier, and eluting the adsorbed IgG antibody with an eluent; a method for producing a purified antibody, comprising preparing an IgG antibody and purifying the prepared IgG antibody with a solid phase carrier and the like. | 2009-07-02 |
| 20090170220 | BISPECIFIC CAPTURING MOLECULE - A capturing molecule having an association containing a plurality of polypeptide chains that specifically bind to different sites of a target substance, characterized in that each of the polypeptide chains has a domain having a hypervariable loop structure at a binding site binding to the target substance and an association portion for forming the association, and the polypeptide chains are associated via the association portions present in the polypeptide chains. | 2009-07-02 |
| 20090170221 | Etch residue reduction by ash methodology - Methods for forming dual damascene interconnect structures are provided. The methods incorporate an ashing operation comprising a first ash operation and a second overash operation. The ashing operation is performed prior to etching of an etch stop layer. The operation removes residue from a cavity formed during formation of the interconnect structure and facilitates better CD control without altering the cavity profiles. | 2009-07-02 |
| 20090170222 | CONTROL OF IMPLANT CRITICAL DIMENSIONS USING AN STI STEP HEIGHT BASED DOSE OFFSET - A method for semiconductor processing is provided, wherein a semiconductor wafer having undergone polishing is provided. The semiconductor wafer has an active region positioned between one or more moat regions, wherein the one or more moat regions have an oxide disposed therein. A top surface of the active region is recessed from a top surface of the moat region, therein defining a step having a step height associated therewith. A step height is measured, and a photoresist is formed over the semiconductor wafer. A modeled step height is further determined, wherein the modeled step height is based on the measured step height and a desired critical dimension of the photoresist. A dosage of energy is determined for patterning the photoresist, wherein the determination of the dosage of energy is based, at least in part, on the modeled step height. The photoresist is then patterned using the determined dosage of energy. | 2009-07-02 |
| 20090170223 | METHODS FOR CALIBRATING A PROCESS FOR GROWING AN EPITAXIAL SILICON FILM AND METHODS FOR GROWING AN EPITAXIAL SILICON FILM - Methods are provided for calibrating a process for growing an epitaxial silicon-comprising film and for growing an epitaxial silicon-comprising film. One method comprises epitaxially growing a first silicon-comprising film on a first silicon substrate that has an adjacent non-crystalline-silicon structure that extends from said first silicon substrate. The step of epitaxially growing uses hydrochloric acid provided at a first hydrochloric acid flow rate for a first time period. A morphology of the first film relevant to the adjacent non-crystalline-silicon structure is analyzed and a thickness of the first film is measured. The first flow rate is adjusted to a second flow rate based on the morphology of the first film. The first time period is adjusted to a second time period based on the second flow rate and the thickness. A second silicon-comprising film on a second silicon substrate is epitaxially grown for the second time period using the second flow rate. | 2009-07-02 |
| 20090170224 | PROCESS FOR FABRICATION OF NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE - The present invention relates to a process for fabrication of a nitride semiconductor light emitting device comprising a substrate, a nitride semiconductor layer on the substrate and electrodes on the nitride semiconductor, the process for fabrication of a nitride semiconductor light emitting device being characterized by device working by laser, followed by etching treatment and then electrode formation. | 2009-07-02 |
| 20090170225 | METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE - A method for manufacturing a semiconductor light emitting device includes forming an insulating film on a semiconductor substrate, the insulating film having an opening therein, forming a Pd electrode in the opening and on the insulating film, and removing the portion of the Pd electrode on the insulating film by the application of a physical force to the portion, while leaving the Pd electrode in the opening. | 2009-07-02 |
| 20090170226 | Package for a Semiconductor Light Emitting Device - A semiconductor light emitting device package includes a substrate with a core and a copper layer overlying the core. The light emitting device is connected to the substrate directly or indirectly through a wiring substrate. The core of the substrate may be, for example, ceramic, Al | 2009-07-02 |
| 20090170227 | MASK AND CONTAINER AND MANUFACTURING - The present invention provides a large mask with a high mask accuracy for conducting selective deposition on a substrate with a large surface area. In accordance with the present invention, the mask body is fixed in a fixing position disposed on a line passing through a thermal expansion center in the width of the mask frame. Further, in accordance with the present invention, the substrate and mask body are fixed and deposition is carried out by moving the deposition source in the X direction or Y direction. A method comprising moving the deposition source in the X direction or Y direction is suitable for deposition on large substrates. | 2009-07-02 |
| 20090170228 | METHOD OF FORMING PATTERN HAVING STEP DIFFERENCE AND METHOD OF MAKING THIN FILM TRANSISTOR AND LIQUID CRYSTAL DISPLAY USING THE SAME - A method of forming a pattern having a step difference and a method of making a thin film transistor and an LCD device using the method of forming the pattern. The method of forming a pattern having a step difference includes forming a first pattern having a predetermined shape in a first printing roll, rotating the first printing roll on a substrate to transfer the first pattern onto the substrate, forming a second pattern having a predetermined shape in a second printing roll, and rotating the second printing roll on the substrate onto which the first pattern is transferred, to transfer the second pattern onto the substrate. | 2009-07-02 |
| 20090170229 | METHOD FOR PRODUCING A MODULATED GRATING FOR AN OPTIMAL REFLECTION SPECTRUM - Method for producing a modulated grating for an optimal reflection spectrum, which grating is a multiple wavelength reflector. The method includes the following steps: a) Determining wavelengths to be reflected b) Calculating a preliminary grating c) Comparing the reflection spectrum r | 2009-07-02 |
| 20090170230 | MANUFACTURING METHOD OF DISPLAY APPARATUS AND MANUFACTURING APPARATUS - A manufacturing method including applying a light emitting material solution for forming a light emitting function layer of the light emitting elements each of which has any one of a plurality of luminescent colors which carry out a color display arranged along a plurality of rows and along a plurality of columns on a substrate to a light emitting element forming region on the substrate in which the light emitting elements of a plurality of columns are formed, in an order that the light emitting material solution is not continuously applied to the light emitting element forming regions in adjacent columns among the plurality of columns and in an applying amount which is set so as to correspond to each of the luminescent colors. | 2009-07-02 |
| 20090170231 | METHOD OF PRODUCING MECHANICAL COMPONENTS OF MEMS OR NEMS STRUCTURES MADE OF MONOCRYSTALLINE SILICON - The invention concerns a method of producing at least one mechanical component of a MEMS or NEMS structure from a monocrystalline silicon substrate, comprising the steps of:
| 2009-07-02 |
| 20090170232 | METHOD FOR MANUFACTURING IAMGE SENSOR - In a method for manufacturing an image sensor, an interlayer insulating layer including a metal line is formed on a semiconductor substrate. A lower electrode layer is formed on the metal line such that the lower electrode is connected with the metal line. A photoresist pattern corresponding to the metal line is formed on the lower electrode layer. The lower electrode layer is etched using the photoresist pattern to form a lower electrode connected with the metal line. The photoresist pattern is stripped using a solvent containing fluorine. | 2009-07-02 |
| 20090170233 | METHOD FOR FABRICATING CMOS IMAGE SENSOR - A method for fabricating a CMOS image sensor for preventing corrosion of a metal pad. The method for fabricating the CMOS image sensor can include sequentially forming a dielectric film, a metal pad having an opening, and a first passivation film on a semiconductor substrate having a scribe lane and a pixel region defined therein, forming a color filter layer on the first passivation film at the pixel region, forming an overcoat layer on the entire surface of the semiconductor substrate, including the metal pad, to reduce the step difference between the scribe lane and the pixel region, forming a micro lens on the overcoat layer at the pixel region, forming a photo resist to expose the overcoat layer at the scribe lane, performing an etching process on the entire surface of the semiconductor substrate to etch the overcoat layer at the scribe lane, and removing the photo resist by a cleaning process. | 2009-07-02 |
| 20090170234 | Image Sensor and Method for Manufacturing Thereof - Disclosed is a method for manufacturing an image sensor. The method includes a process for removing foreign matter from a non-device area of a wafer before forming contacts in a device area of the wafer. According to an embodiment, an insulating layer formed in the non-device area is removed by performing a first process with respect to the non-device area. Then, a contact can be formed in the insulating layer in the device area. | 2009-07-02 |
| 20090170235 | Method for Manufacturing Image Sensor - A method for manufacturing an image sensor includes forming a photolithography key in a scribe lane of a first substrate over which circuitry is formed in an active region. A photodiode is formed on an active region of a second substrate. The second substrate is bonded to the first substrate such that the photodiode is electrically connected to the circuitry. The photolithography key in the scribe lane of the first substrate is opened. A pattern is formed on the active region of the bonded second substrate using the opened photolithography key on/over the first substrate. | 2009-07-02 |
| 20090170236 | MANUFACTURING METHOD OF IMAGE SENSOR - A manufacturing method of an image sensor includes forming lower electrodes over a semiconductor substrate having metal wires and an interlayer insulating film formed thereover; removing a photoresist polymer produced by the formation of the lower electrodes by performing a primary treatment using a first substance; and then removing an electrode polymer produced by the formation of the lower electrodes by performing a secondary treatment using a second substance. | 2009-07-02 |
| 20090170237 | Printed organic logic circuits using an organic semiconductor as a resistive load device - A method of forming an organic inverter includes providing a first metal layer having a first portion for coupling a source of an OFET to a first power supply voltage, a second portion for coupling a drain of the OFET to an output terminal and a first load resistor terminal, and a third portion for coupling a second load resistor terminal to a second power supply voltage, providing a semiconductor layer for overlapping a portion of the first and second first metal layer portions to form an OFET active area, and for overlapping a portion of the second and third metal layer portions to form a toad resistor, providing a dielectric layer for overlapping the active area of the OFET and the semiconductor area of the load resistor to isolates the first metal layer and semiconductor area from the second metal layer, and providing a second metal layer for overlapping the active area of the OFET to form a gate of the OFET and an input terminal. | 2009-07-02 |
| 20090170238 | Printed organic logic circuits using a floating gate transister as a load device - A method of forming an organic inverter includes providing a first metal layer having a first portion for coupling a source of a first OFET to a first power supply voltage, a second portion for coupling a drain of the first OFET to an output terminal and to a source of a second OFET, and a third portion for coupling a drain of the second OFET to a second power supply voltage, providing a semiconductor layer for overlapping a portion of the first and second first metal layer portions to form a first OFET active area, and for overlapping a portion of the second and third metal layer portions to form a second OFET active area, providing a dielectric layer for overlapping the active area and isolates the first metal layer and semiconductor layer from the second metal layer, and providing a second metal layer for overlapping the active area of the first OFET to form a gate of the first OFET and an input terminal, and for overlapping the active area of the second OFET to form a floating gate for the second OFET. | 2009-07-02 |
| 20090170239 | UTILIZING APERTURE WITH PHASE SHIFT FEATURE IN FORMING MICROVIAS - A method, comprises drilling a set of one or more microvias in a semiconductor package with an aperture, wherein drilling the set of microvias comprises to use an aperture that has a phase shift region to reduce a spot size of a drilling beam that is used to form the set of microvias. | 2009-07-02 |
| 20090170240 | Optimized Circuit Design Layout for High Performance Ball Grid Array Packages - A method of laying out traces for connection of bond pads of a semiconductor chip to a printed wiring board or the like and the layout. There is provided a substrate having top and bottom surfaces with a plurality of rows and columns of vias extending therethrough from the top surface to the bottom surface and having a solder ball secured at the bottom surface to each via. A plurality of pairs of traces is provided on the top surface, each trace of each pair of traces extending to a different one of the vias and extending to vias on a plurality of the rows and columns, each of the traces of each pair being spaced from the other trace by a ball pitch, being maximized for identity in length and being maximized for parallelism and spacing. Each of the traces of a pair is preferably be further maximized for identity in cross-sectional geometry. A differential signal pair is preferably applied to at least one of a pair of traces. The layout can further include a further surface between the top and bottom surfaces insulated from the top and bottom surfaces, a plurality of the traces being disposed on the further surface. | 2009-07-02 |
| 20090170241 | Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier - A semiconductor device is made by forming contact pads on a sacrificial carrier. The contact pads may be formed on a pillar. A semiconductor die is mounted to electrically connect to the contact pads with solder bumps or wire bonds. The semiconductor die is encapsulated with molding compound. The sacrificial carrier is removed. A backside interconnect structure has a first conductive layer formed over the molding compound to electrically connect to the contact pads. A first insulating layer is formed over the first conductive layer. A portion of the first insulating layer is removed to expose the first conductive layer. Solder material is deposited in electrical contact with the first conductive layer. The solder material is reflowed to form a solder bump. A wire bond electrically connects to a contact pad. A front-side interconnect structure can be formed through the molding compound to the contact pads. | 2009-07-02 |
| 20090170242 | System-in-Package Having Integrated Passive Devices and Method Therefor - A method of manufacturing a semiconductor device involves providing a substrate, forming a first passivation layer over the substrate, and forming an integrated passive circuit over the substrate. The integrated passive circuit can include inductors, capacitors, and resistors. A second passivation layer is formed over the integrated passive circuit. System components are mounted to the second passivation layer and electrically connect to the second conductive layer. A mold compound is formed over the integrated passive circuit. A coefficient of thermal expansion of the mold compound is approximately equal to a coefficient of thermal expansion of the system component. The substrate is removed. An opening is etched into the first passivation layer and solder bumps are deposited over the opening in the first passivation layer to electrically connect to the integrated passive circuit. A metal layer can be formed over the molding compound or first passivation layer for shielding. | 2009-07-02 |
| 20090170243 | Stacked Integrated Circuit Module - The present invention provides an improvement on the use of flexible circuit connectors for electrically coupling IC devices to one another in a stacked configuration by use of the flexible circuit to provide the connection of the stacked IC module to other circuits. Use of the flexible circuit as the connection of the IC module allows the flexible circuit to provide strain relief and allows stacked IC modules to be assembled with a lower profile than with previous methods. The IC module can be connected to external circuits through the flexible circuit connectors by a variety of means, including solder pads, edge connector pads, and socket connectors. This allows for IC devices to occupy less space then with previous methods, which is beneficial in modules such as memory modules with multiple, stacked memory devices. | 2009-07-02 |
| 20090170244 | METHOD FOR MANUFACTURING A FLIP CHIP PACKAGE - A method for manufacturing a flip chip package uses a dipping method to cohere liquid-state stannum onto a plurality of gold bumps of a chip. The gold bumps are correspondingly connected to a plurality of first pads of a substrate so as to connect the chip and the substrate. Finally, a protecting gel layer is disposed between the substrate and the chip, and covers the gold bumps. By utilizing the manufacturing method of the invention, the production cost can be reduced, and the manufacturing method of the invention can apply to processes in which the bump pitch is less than 60 microns. In addition, through the manufacturing method of the invention, the gold bumps are strongly joined with the first pads. Moreover, the manufacturing method of the invention can apply to various processes, so the application has a wide range of uses. | 2009-07-02 |
| 20090170245 | ELECTRONIC APPARATUS MANUFACTURING METHOD - An electronic apparatus manufacturing method comprises applying a first adhesive agent to a mounting portion, a first heating, in such a way that connection pads and bumps, come into contact, by pressing a heating head against a non-mounting surface of the electronic component, heating the electronic component, hardening the first adhesive agent, affixing the mounting substrate and electronic component, filling a space between the mounting substrate and the electronic component with a second adhesive agent under reduced pressure, and a second heating step of,, from being under reduced pressure to being under atmospheric pressure, by pressing the heating head against the non-mounting surface of the electronic component, heating the electronic component, as well as hardening the second adhesive agent, melting the connection pads, and joining the connection pads and the bumps. | 2009-07-02 |
| 20090170246 | FORMING A 3-D SEMICONDUCTOR DIE STRUCTURE WITH AN INTERMETALLIC FORMATION - A method for forming a semiconductor structure includes forming a first contact pad on a first die, wherein the first contact pad comprises a first metal element, forming a metal over the first contact pad, wherein the metal comprises a second metal element, and the second metal element is different from the first metal element. The method further includes rapidly reflowing a portion of the metal to form a thin intermetallic layer. The method further includes attaching the first contact pad of the first die to a second contact pad of a second die, wherein attaching comprises heating the first contact pad and the second contact pad to reflow the metal to form an intermetallic layer such that substantially all of the metal formed over the first contact pad is used as part of the intermetallic layer. | 2009-07-02 |
| 20090170247 | MAGNETIC PARTICLES FOR LOW TEMPERATURE CURE OF UNDERFILL - Electronic devices and methods for fabricating electronic devices are described. One embodiment includes a method comprising providing a first body and a second body, and electrically coupling the first body to the second body using a plurality of solder bumps, wherein a gap remains between the first body and the second body. The method also includes placing an underfill material into the gap between the first body and the second body, the underfill material comprising magnetic particles in a polymer composition. The method also includes curing the underfill material in the gap by applying a magnetic field powered by alternating current, to induce heat in the magnetic particles, wherein the heat in the magnetic particles heats the polymer composition, and the magnetic field is applied for a sufficient time to cure the polymer composition. Other embodiments are described and claimed. | 2009-07-02 |
| 20090170248 | METHOD FOR MANUFACTURING THIN FILM TRANSISTOR - A method for manufacturing a thin film transistor with improved current characteristics and high electron mobility. According to the method, when an amorphous silicon thin film is crystallized into a polycrystalline silicon thin film by metal-induced crystallization, annealing conditions of the amorphous silicon thin film and the amount of a metal catalyst doped into the amorphous silicon thin film are optimized to reduce the regions of a metal silicide distributed at grain boundaries of the polycrystalline silicon thin film. In addition, oxygen (O | 2009-07-02 |
| 20090170249 | Compound semiconductor device and method for fabricating the same - The compound semiconductor device comprises an i-GaN buffer layer | 2009-07-02 |
| 20090170250 | TRANSISTOR OF SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a transistor of a semiconductor device and method of fabricating the same. The transistor includes: an epitaxy substrate disposed on a semi-insulating substrate and having a buffer layer, a first Si planar doping layer, a first conductive layer, a second Si planar doping layer, and a second conductive layer, which are sequentially stacked, the second Si planar doping layer having a doping concentration different from that of the first Si planar doping layer; a source electrode and a drain electrode diffusing into the first Si planar doping layer to a predetermined depth and disposed on both sides of the second conductive layer to form an ohmic contact; and a gate electrode disposed on the second conductive layer between the source and drain electrodes and being in contact with the second conductive layer. In this structure, both isolation and switching speed of the transistor can be increased. Also, the maximum voltage limit applied to the transistor is increased due to increases in gate turn-on voltage and threshold voltage and a reduction in parallel conduction element. As a result, the power handling capability of the transistor can be improved, thus improving a high-power low-distortion characteristic and an isolation characteristic. | 2009-07-02 |
| 20090170251 | Fabrication of germanium nanowire transistors - In general, in one aspect, a method includes using the Germanium nanowire as building block for high performance logic, memory and low dimensional quantum effect devices. The Germanium nanowire channel and the SiGe anchoring regions are formed simultaneously through preferential Si oxidation of epitaxial Silicon Germanium epi layer. The placement of the germanium nanowires is accomplished using a Si fin as a template and the germanium nanowire is held on Si substrate through SiGe anchors created by masking the two ends of the fins. High dielectric constant gate oxide and work function metals wrap around the Germanium nanowire for gate-all-around electrostatic channel on/off control, while the Germanium nanowire provides high carrier mobility in the transistor channel region. The germanium nanowire transistors enable high performance, low voltage (low power consumption) operation of logic and memory devices. | 2009-07-02 |
| 20090170252 | Formation method of metallic compound layer, manufacturing method of semiconductor device, and formation apparatus for metallic compound layer - A formation method of a metallic compound layer includes preparing, in a chamber, a substrate having a surface on which a semiconductor material of silicon, germanium, or silicon germanium is exposed, and forming a metallic compound layer, includes: supplying a raw material gas containing a metal for forming a metallic compound with the semiconductor material to the chamber; heating the substrate to a temperature at which the raw material gas is pyrolyzed; and forming a metallic compound layer by reaction of the metal with the semiconductor material so that no layer of the metal is deposited on the substrate. A manufacturing method of a semiconductor device employs this formation method of a metallic compound layer. | 2009-07-02 |
| 20090170253 | Method of manufacturing semiconductor device - The present invention relates to a method of manufacturing a semiconductor device, in which a gate electrode is formed in a T-shape in order to increase the size of a top surface of the gate electrode, thereby providing a stable silicide forming condition and preventing contact misalignment. | 2009-07-02 |
| 20090170254 | Method of Manufacturing a Semiconductor Device - In a method of manufacturing a semiconductor device, a first gate electrode and a second gate electrode are formed in a first area and a second area of a substrate. Non-crystalline regions are formed in the first area of the substrate adjacent the first gate electrode. A layer having a first stress is formed on the substrate and the first and the second gate electrodes. A mask is formed on a first portion of the layer in the first area of the substrate to expose a second portion of the layer in the second area. The second portion is etched to form a sacrificial spacer on a sidewall of the second gate electrode. The second area of the substrate is partially etched using the mask, the second gate electrode and the sacrificial spacer, to form recesses in the second area of the substrate adjacent the second gate electrode. Patterns having a second stress are formed in the recesses. | 2009-07-02 |
| 20090170255 | INTEGRATED CIRCUIT MODIFICATION USING WELL IMPLANTS - A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being disposed adjacent to active regions of a first conductivity type. The well forming an electrical path between the active regions regardless of any reasonable voltage applied to the integrated circuit structure. | 2009-07-02 |
| 20090170256 | ANNEALING METHOD FOR SIGE PROCESS - A method of forming a transistor comprising forming a gate structure over an n-type semiconductor body and forming recesses substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown in the recesses and a silicon cap layer is formed over the silicon germanium. Further introduction of impurities into the silicon germanium to increase the melting point thereof and implanting p-type source/drain regions in the semiconductor body is included in the method. The method concludes with performing a high temperature thermal treatment. | 2009-07-02 |
| 20090170257 | METHOD OF MANUFACTURING MOS TRANSISTOR - A method of manufacturing a transistor may include: forming a first well over a silicon substrate; forming a first mask pattern over the silicon substrate and using the formed first mask pattern to form a second well; removing the first mask pattern; forming a second mask pattern over the silicon substrate and using the formed second mask pattern to form a first drift region; removing the second mask pattern; forming a third mask pattern and using the formed third mask pattern to form a second drift region; removing the third mask pattern; forming a field oxide film over the silicon substrate; and introducing first conductive impurity ions into an upper surface of the silicon substrate by channel ion implantation. | 2009-07-02 |
| 20090170258 | METHODS FOR FULL GATE SILICIDATION OF METAL GATE STRUCTURES - One embodiment relates to a method of fabricating an integrated circuit. In the method, p-type polysilicon is provided over a semiconductor body, where the p-type polysilicon has a first depth as measured from a top surface of the p-type polysilicon. An n-type dopant is implanted into the p-type polysilicon to form a counter-doped layer at the top-surface of the p-type polysilicon, where the counter-doped layer has a second depth that is less than the first depth. A catalyst metal is provided that associates with the counter-doped layer to form a catalytic surface. A metal is deposited over the catalytic surface. A thermal process is performed that reacts the metal with the p-type polysilicon in the presence of the catalytic surface to form a metal silicide. Other methods and devices are also disclosed. | 2009-07-02 |
| 20090170259 | ANGLED IMPLANTS WITH DIFFERENT CHARACTERISTICS ON DIFFERENT AXES - One embodiment relates to a method of forming an integrated circuit. In this method, at least one dopant species of a first conductivity type is implanted in a first manner along a first axis to form first pocket implant regions extending at least partially under some gates. At least one dopant species of the first conductivity type is then implanted in a second manner that differs from the first manner along a second axis that is laterally rotated with respect to the first axis to form second pocket implant regions extending at least partially under other gates. | 2009-07-02 |
| 20090170260 | Non-Volatile Memory Cell Circuit With Programming Through Band-To-Band Tunneling And Impact Ionization Gate Current - Electronic circuitry is described having a first transistor having a first gate dielectric located between an electrically floating gate and a semiconductor substrate. The first injection current flows through the first gate dielectric to establish a first amount of electrical charge on the gate electrode. The electronic circuitry also includes a second transistor having a second gate dielectric located between the gate electrode and the semiconductor substrate. A band-to-band tunneling current flows between valence and conduction bands of the second transistor to create a second injection current that flows through the second gate dielectric to establish the first amount of electrical charge on the gate electrode. Non-volatile memory cell circuits having the above described circuitry are also described. | 2009-07-02 |
| 20090170261 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING 4F2 TRANSISTOR - Provided is a method for manufacturing a semiconductor device having a 4F2 transistor. In the method, a gate stack is formed on a semiconductor substrate. A first interlayer dielectric including a contact hole which includes a first region and second regions Spacer layers are formed on both sides of the gate stack and a portion of the second region. Landing plugs are formed on the contact hole, a portion of the semiconductor substrate exposed by a thickness of the spacer layer, and a lateral side of the trench. A second interlayer dielectric is formed to separate the landing plug. The bit line contact plug is connected to a first portion of the landing plug that extends to the lateral side of the trench. The bit line stack is connected to the bit line contact plug. The storage node contact plug is connected to the first portion and a second portion of the landing plug located at a corresponding position in a diagonal direction. | 2009-07-02 |
| 20090170262 | VIRTUAL GROUND MEMORY ARRAY AND METHOD THEREFOR - A virtual ground memory array (VGA) is formed by a storage layer over a substrate with a conductive layer over the storage layer. The conductive layer is opened according to a patterned photoresist layer. The openings are implanted to form source/drain lines in the substrate, then filled with a layer of dielectric material. Chemical mechanical polishing (CMP) is then performed until the top of the conductive layer is exposed. This leaves dielectric spacers over the source/drain lines and conductive material between the dielectric spacers. Word lines are then formed over the conductive material and the dielectric spacers. As an alternative, instead of using a conductive layer, a sacrificial layer is used that is removed after the CMP step. After removing the sacrificial portions, the word lines are formed. In both cases, dielectric spacers reduce gate/drain capacitance and the distance from substrate to gate is held constant across the channel. | 2009-07-02 |
| 20090170263 | METHOD OF MANUFACTURING FLASH MEMORY DEVICE - Disclosed is a method of manufacturing a flash memory device. With this method, the surface area of a floating gate is increased by using a buffer film or a dummy pattern, without increasing the size of the flash memory device. Therefore, a coupling ratio is increased, and as a result, programming and erasure speed can be improved. | 2009-07-02 |
| 20090170264 | Method of producing semiconductor device - A silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. A first conductive type impurity is diffused in the silicon carbide substrate. A method of producing a semiconductor device includes preparing the silicon carbide substrate forming a first conductive type impurity diffused region on the first main surface therein; preparing a silicon substrate having a third main surface and a fourth main surface opposite to the third main surface, said silicon substrate including a thermal oxidation film formed on the third main surface; and attaching the third main surface to the first main surface via the thermal oxidation film. | 2009-07-02 |
| 20090170265 | Method of Fabricating a Recess Gate Type Transistor - A semiconductor device having recess gates and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having inverse triangular recesses formed therein; a gate insulating film having a designated thickness formed on the semiconductor substrate; gate electrodes formed on the gate insulating film so that the gate electrodes fill the inverse triangular recesses and protrude from the surface of the semiconductor substrate; and first and second junction regions formed in the semiconductor substrate and opposed to each other so that the corresponding one of the gate electrodes is interposed therebetween. | 2009-07-02 |
| 20090170266 | METHOD FOR SIMULTANEOUSLY MANUFACTURING SEMICONDUCTOR DEVICES - Methods for manufacturing semiconductor devices simultaneously to implement low-voltage and high-voltage devices in a single chip. In one example embodiment, a method includes various acts. An isolation layer is formed on a wafer. A gate oxide layer and a lower gate poly are sequentially formed on a first low-voltage transistor region. A first poly oxide layer is formed. A nitride layer is formed on the first poly oxide layer. The nitride layer and the first poly oxide layer are etched. A field oxide layer is formed by selectively oxidizing portions exposed by the etching. A second poly oxide layer is formed. Gate patterns of each transistor region are completed by vapor-depositing an upper gate poly on a high-voltage transistor region, the first low-voltage transistor region and a second low-voltage transistor region. A source and drain region are formed. | 2009-07-02 |
| 20090170267 | Tri-gate patterning using dual layer gate stack - In general, in one aspect, a method includes forming an n-diffusion fin and a p-diffusion fin in a semiconductor substrate. A high dielectric constant layer is formed over the substrate. A first work function metal layer is created over the n-diffusion fin and a second work function metal layer, thicker than the first, is created over the n-diffusion fin. A silicon germanium layer is formed over the first and second work function metal layers. A ploysilicon layer is formed over the silicon germanium layer and is polished. The ploysilicon layer over the first work function metal layer is thicker than the ploysilicon layer over the second work function metal layer. A hard mask is patterned and used to etch the ploysilicon layer and the silicon germanium layer to create gate stacks. The etch rate of the silicon germanium layer is faster over the first work function metal layer. | 2009-07-02 |
| 20090170268 | PROCESS FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING EMBEDDED EPITAXIAL REGIONS - A process for fabricating a semiconductor device, such as a strained-channel transistor, includes forming epitaxial regions in a substrate in proximity to a gate electrode in which the surface profile of the epitaxial regions is defined by masking sidewall spacers adjacent the gate electrode. The epitaxial regions are formed by depositing an epitaxial material into cavities selectively etched into the semiconductor substrate on either side of the gate electrode. The masking sidewall spacers limit the thickness of the epitaxial deposited material in proximity of the gate electrode, such that the upper surface of the epitaxial material is substantially the same as the principal surface of the semiconductor substrate. Doped regions are formed in the channel region beneath the gate electrode using an angled ion beam, such that doping profiles of the implanted regions are substantially unaffected by surface irregularities in the epitaxially-deposited material. | 2009-07-02 |
| 20090170269 | HIGH VOLTAGE MOSFET DEVICES CONTAINING TIP COMPENSATION IMPLANT - Semiconductor devices and methods for making semiconductor devices are described in this application. The semiconductor devices comprise a MOSFET device in a semiconductor substrate, with the MOSFET device containing source and drain regions with a tip implant region near the surface of the substrate. The tip implant region contains a tip compensation implant region located under the gate of the MOSFET device that overlaps with the source and drain. The tip compensation implant region reduces the dopant concentration in this gate-drain overlap region, while maintaining a graded drain-well junction profile, thereby reducing the band to band tunneling and increasing the drain breakdown voltage. Other embodiments are described. | 2009-07-02 |
| 20090170270 | INTEGRATION SCHEMES TO AVOID FACETED SIGE - Semiconductor devices and fabrication methods are provided in which disposable gates are formed over isolation regions. Sidewall structures, including disposable sidewall structures, are formed on sidewalls of the disposable gates. An epitaxially grown silicon germanium is formed in recesses defined by the sidewalls. The process provides a compressive strained channel in the device without faceting of the epitaxially grown silicon germanium. | 2009-07-02 |
| 20090170271 | TRANSISTOR AND METHOD OF FORMING THE SAME - According to some embodiments of the invention, a fin type transistor includes an active structure integrally formed with a silicon substrate. The active structure includes grooves that form blocking regions under source/drain regions. A gate structure is formed to cross the upper face of the active structure and to cover the exposed side surfaces of the lateral portions of the active structure. An effective channel length of a fin type transistor may be sufficiently ensured so that a short channel effect of the transistor may be prevented and the fin type transistor may have a high breakdown voltage. | 2009-07-02 |
| 20090170272 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a first insulating layer, a capacitor, an adhesive layer, and an intermediate layer. The first insulating layer may include a first insulating film. The first insulating layered structure has a first hole. The capacitor is disposed in the first hole. The capacitor may include bottom and top electrodes and a capacitive insulating film. The capacitive insulating film is sandwiched between the bottom and top electrodes. The adhesive layer contacts with the bottom electrode. The adhesive layer has adhesiveness to the bottom electrode. The intermediate layer is interposed between the adhesive layer and the first insulating film. The intermediate layer contacts with the adhesive layer and with the first insulating film. The intermediate layer has adhesiveness to the adhesive layer and to the first insulating film. | 2009-07-02 |
| 20090170273 | Dual layer hard mask for block salicide poly resistor (BSR) patterning - In general, in one aspect, a method includes forming a semiconductor substrate having an N+ diffusion region, a shallow trench isolation (STI) region adjacent to the N+ diffusion region, and a blocked salicide poly resistor (BSR) region over the STI region. An oxide layer is over the substrate. A nitride layer is formed over the oxide layer and is annealed. A resist layer is patterned on the annealed nitride layer, wherein the resist layer covers a portion of the BSR region. The annealed nitride layer is etched using the resist layer as a pattern. The resist layer is removed and the oxide layer is etched using the annealed nitride layer as a pattern. Germanium pre-amorphization is implanted into the substrate, wherein the oxide and the annealed nitride layers protect a portion of the BSR region from the implanting. | 2009-07-02 |
| 20090170274 | METHOD OF FORMING METAL TRENCH PATTERN IN THIN-FILM DEVICE - A method of forming a metal trench pattern in a thin-film device includes a step of depositing an electrode film on a substrate or on a base layer, a step of forming a resist pattern layer having a trench forming portion used to make a trench pattern, on the deposited electrode film, a step of forming a metal layer for filling spaces in the trench forming portion and for covering the trench forming portion, by performing plating through the formed resist pattern layer using the deposited electrode film as an electrode, a step of planarizing at least a top surface of the formed metal layer until the trench forming portion of the resist pattern layer is at least exposed, and a step of removing the exposed trench forming portion of the resist pattern layer. | 2009-07-02 |
| 20090170275 | Method for Manufacturing a Semiconductor Device - A method for manufacturing a semiconductor device includes forming a spin-on-carbon (SOC) film that facilitates a low temperature baking process, can prevent collapse of vertical transistors while forming a bit line, thereby providing a more simple manufacturing method and improving manufacturing yields. | 2009-07-02 |
| 20090170276 | Method of Forming Trench of Semiconductor Device - The present invention relates to a method of forming trenches of a semiconductor device. According to the method, a hard mask pattern is formed on a semiconductor substrate so that an isolation region of the semiconductor substrate is opened. First trenches are formed in the isolation region by performing a first etch process employing the hard mask pattern. A spacer is formed on sidewalls of the first trenches. Second trenches, having a depth deeper than that of the first trenches, are formed in the isolation region by performing a second etch process employing the hard mask pattern. | 2009-07-02 |
| 20090170277 | IMPLANT DAMAGE OF LAYER FOR EASY REMOVAL AND REDUCED SILICON RECESS - A method for semiconductor processing is provided, wherein a removal of one or more layers is aided by structurally weakening the one or more layers via ion implantation. A semiconductor substrate is provided having one or more primary layers formed thereon, and a secondary layer is formed over the one or more primary layers. One or more ion species are implanted into the secondary layer, therein structurally weakening the secondary layer, and a patterned photoresist layer is formed over the secondary layer. Respective portions of the secondary layer and the one or more primary layers that are not covered by the patterned photoresist layer are removed, and the patterned photoresist layer is further removed. At least another portion of the secondary layer is removed, wherein the structural weakening of the secondary layer increases a removal rate of the at least another portion of the secondary layer. | 2009-07-02 |
| 20090170278 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device is provided that can comprise: forming a hard mask on a semiconductor substrate; forming a trench by etching the semiconductor substrate using the hard mask; performing a Chemical Mechanical Polishing (CMP) process after insulating film is buried in the trench; removing the hard mask; forming a protective film on the semiconductor substrate including a moat region of the semiconductor substrate adjacent to the insulating film, the moat region being further projected than the insulating film; implanting impurity ion onto the semiconductor substrate on which the protective film is formed; and removing the protective film using cleansing solution through a cleansing process before a gate insulating film is formed in an active region of the semiconductor substrate. | 2009-07-02 |
| 20090170279 | METHOD OF PREPARING ACTIVE SILICON REGIONS FOR CMOS OR OTHER DEVICES - A method of preparing active silicon regions for CMOS devices includes providing a structure including a silicon substrate ( | 2009-07-02 |
| 20090170280 | Method of Forming Isolation Layer of Semiconductor Device - A method of forming isolation layers of a semiconductor device, comprising providing a semiconductor substrate in which a tunnel dielectric layer and a conductive layer are formed in active regions having two ends and trenches are formed in isolation regions; rounding both ends of each active region by performing an O | 2009-07-02 |
| 20090170281 | METHOD OF FORMING ISOLATION LAYER OF SEMICONDUCTOR - The present invention relates to a method of forming an isolation layer of a semiconductor memory device. According to a method of fabricating a semiconductor memory device in accordance with an aspect of the present invention, a tunnel insulating layer and a charge trap layer are formed over a semiconductor substrate. An isolation trench is formed by etching the charge trap layer and the tunnel insulating layer. A passivation layer is formed on the entire surface including the isolation trench. A first insulating layer is formed at a bottom of the isolation trench. Portions of the passivation layer, which are oxidized in the formation process of the first insulating layer, are removed. A second insulating layer is formed on the entire surface including the first insulating layer. | 2009-07-02 |
| 20090170282 | Method of Forming Isolation Layer in Semiconductor Device - A method of forming isolation layer in a semiconductor device, comprising forming a trench on an isolation region of a semiconductor substrate by etching utilizing an isolation mask; forming a first insulating layer on a lower portion of the trench; forming a second insulating layer on the semiconductor substrate including the first insulating layer; etching the second insulating layer to increase an aspect ratio on the isolation region; and forming a third insulating layer on a peripheral region of the second insulating layer to fill moats formed on the second insulating layer with the third insulating layer. | 2009-07-02 |
| 20090170283 | Method of Fabricating Non-Volatile Memory Device - A method of fabricating a non-volatile memory device, A tunnel insulating layer, a floating gate, and a pad nitride layer is formed on a semiconductor substrate. A isolation region of the semiconductor substrate is formed by etching to a predetermined depth, and a liner insulating layer is formed on an entire surface of the resulting trench for device isolation. A filling insulation layer is formed on the liner insulating layer to fill the trench and a first etching process is performed on the filling insulation layer and the liner insulating layer. The surface of semiconductor is recessed by performing a second etching process on the filling insulation layer. A capping layer is formed on an entire surface of the result formed by the second etching process. The device isolation layer of a concave shape is formed by performing an etching process on the capping layer. | 2009-07-02 |
| 20090170284 | Adhesive Composition, Adhesive Sheet and Production Process for Semiconductor Device - The object of the present invention is to provide an adhesive composition which can form a thinner adhesive layer, which has good storage stability and which can actualize high package reliability even when exposed to severe reflow conditions in a semiconductor package in which a semiconductor chip being reduced in a thickness is mounted, and an adhesive sheet having an adhesive layer comprising the adhesive composition. | 2009-07-02 |
| 20090170285 | Method for manufacturing bonded wafer - The present invention provides a method for manufacturing a bonded wafer by an ion implantation delamination method, the method including at least the steps of bonding a base wafer with a bond wafer having a microbubble layer formed by ion implantation, delaminating the wafers along the micro bubble layer as a boundary, and removing a periphery of a thin film formed on the base wafer by the delamination step, wherein at least the thin-film periphery removal step after the delamination step is performed by dry etching that supplies an etching gas from a nozzle, and the dry etching is performed by adjusting an inner diameter of the gas-jetting port of the nozzle, and a distance between the gas-jetting port of the nozzle and a surface of the thin film. As a result of this, there is provided the method for manufacturing the bonded wafer, in which removal of the thin-film periphery can be easily performed and a removal width is also reproducibly obtained well in the thin-film periphery removal step, and degradation in quality of the thin film can be effectively prevented. | 2009-07-02 |
| 20090170286 | METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor substrate is manufactured in which a plurality of single crystal semiconductor layers is fixed to a base substrate having low heat resistance such as a glass substrate with a buffer layer interposed therebetween. A plurality of single crystal semiconductor substrates is prepared, each of which includes a buffer layer and a damaged region which is formed by adding hydrogen ions to each semiconductor substrate and contains a large amount of hydrogen. One or more of these single crystal semiconductor substrates is fixed to a base substrate and irradiated with an electromagnetic wave having a frequency of 300 MHz to 300 GHz, thereby being divided along the damaged region. Fixture of single crystal semiconductor substrates and electromagnetic wave irradiation are repeated to manufacture a semiconductor substrate where a required number of single crystal semiconductor substrates are fixed onto the base substrate. | 2009-07-02 |
| 20090170287 | METHOD FOR MANUFACTURING SOI SUBSTRATE - A single crystal semiconductor substrate and a base substrate are prepared; a first insulating film is formed over the single crystal semiconductor substrate; a separation layer is formed by introducing ions at a predetermined depth through a surface of the single crystal semiconductor substrate; plasma treatment is performed on the base substrate so as to planarize a surface of the base substrate; a second insulating film is formed over the planarized base substrate; a surface of the first insulating film is bonded to a surface of the second insulating film by making the surface of the single crystal semiconductor substrate and the surface of the base substrate face each other; and a single crystal semiconductor film is provided over the base substrate with the second insulating film and the first insulating film interposed therebetween by performing separation at the separation layer. | 2009-07-02 |
| 20090170288 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - After a semiconductor element is formed and before resin sealing is performed, a surface of a scribe line between the adjacent semiconductor elements of a semiconductor wafer is scraped thinly. A laser is irradiated on a broken layer of the surface of the scribe line thus scraped thinly to recrystallize the broken layer. | 2009-07-02 |
| 20090170289 | WAFER DIVIDING METHOD - A laser beam is applied to an intersection area of each second street of a wafer by using a dicing apparatus to thereby form a first modified layer along the intersection area. Thereafter, the wafer is divided along each first street intersecting each second street at right angles to obtain a plurality of wafer strips. Thereafter, the laser beam is applied along the remaining area of each second street other than the intersection area to form a second modified layer along the remaining area of each second street. Thereafter, an external force is applied to each wafer strip in which the first and second modified layers have been formed along each second street, thereby dividing each wafer strip along each second street to obtain a plurality of devices. | 2009-07-02 |
| 20090170290 | SEMICONDUCTOR MANUFACTURING METHOD OF DIE PICK-UP FROM WAFER - A manufacturing method of a semiconductor device comprising the steps of: affixing a die attach film and a dicing film to a back surface of a semiconductor wafer: thereafter dicing the semiconductor wafer and the die attach film to divide the semiconductor wafer into a plurality of semiconductor chips: thereafter pulling the dicing film from the center toward the outer periphery of the dicing film with a first tensile force to cut the die attach film chip by chip; and thereafter picking up the semiconductor chips together with the die attach film while pulling the dicing film from the center toward the outer periphery of the dicing film with a second tensile force smaller than the first tensile force. | 2009-07-02 |
| 20090170291 | Method of fabricating an organic thin film transistor - An organic thin film transistor that prevents the surface of an organic semiconductor layer from being damaged and reduces turn-off current, a method of fabricating the same, and an organic light-emitting device incorporating the organic thin film transistor. The organic thin film transistor includes a substrate, source and drain electrodes arranged on the substrate, a semiconductor layer contacting the source and drain electrodes and comprising a channel region, a protective film arranged on the semiconductor layer and having a same pattern as the semiconductor layer, the protective film comprising a laser-absorbing material, a gate insulating film arranged between the gate and the source and drain electrodes, a gate electrode arranged on the gate insulating film and a separation pattern arranged within the semiconductor layer and within the protective film, the separation pattern adapted to define the channel region of the semiconductor layer. | 2009-07-02 |
| 20090170292 | Method for producing semiconductor substrate and semiconductor substrate - A production method for a semiconductor substrate for producing a high quality SGOI substrate | 2009-07-02 |
| 20090170293 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate, forming a second semiconductor layer on the first semiconductor layer, etching the second semiconductor layer and the first semiconductor layer to form a first groove passing through the second semiconductor layer and the first semiconductor layer, forming a support in the first groove, etching the second semiconductor layer to form a second groove that exposes the first semiconductor layer, forming a cavity between the second semiconductor layer and the semiconductor substrate by etching the first semiconductor layer through the second groove, forming a semiconductor film in the cavity, and thermally oxidizing the semiconductor film. | 2009-07-02 |
