| 27th week of 2009 patent applcation highlights part 34 |
| Patent application number | Title | Published |
|---|
| 20090168487 | CYCLING TO MITIGATE IMPRINT IN FERROELECTRIC MEMORIES - One embodiment of the present invention relates to a method for reducing the imprint of a ferroelectric memory cell. The method comprises storing a memory data state in the ferroelectric memory cell. An event will trigger the evaluation of signal margin on a memory cell. If the memory cell is identified to have a weak signal, the memory cell is exercised. Exercising comprises either performing one or more data read/re-write events or performing one or more simulated data read and data write events of an alternating high data state and a low data state to the memory cell associated with the weak data bit. Both the lifetime retention testing and the memory data state exercising are performed in the background of normal memory operation. Other methods and circuits are also disclosed. | 2009-07-02 |
| 20090168488 | Method to Improve Ferroelectronic Memory Performance and Reliability - One embodiment of the present invention relates to a method by which the imprint of a ferroelectric random access memory (FRAM) array is reduced. The method begins when an event that will cause imprint to the memory array is anticipated by an external agent to the device comprising the chip. The external agent sends a command to the control circuitry that the data states are to be written to a particular data state. Upon receiving a signal the control circuitry writes all of the ferroelectric memory cells in the FRAM array to a preferred memory data state. The memory data states are held in the preferred data state for the entire duration of the event to minimize imprint of the FRAM memory cells. When the event ends the external agent sends a command to the control circuitry to resume normal memory operation. Other methods and circuits are also disclosed. | 2009-07-02 |
| 20090168489 | FERROELECTRIC MEMORY DEVICES WITH PARTITIONED PLATELINES - One embodiment relates to a ferroelectric memory device. The ferroelectric memory device includes a segment of contiguous ferroelectric memory cells arranged in rows and columns. A row of ferroelectric memory cells includes a common wordline that allows access to the memory cells of the row and also includes at least two platelines associated with the row. At least one of the at least two platelines is associated with adjacent columns of ferroelectric memory cells within the row. The row of ferroelectric memory cells includes another word line which is not associated with the at least two platelines. Other methods and systems are also disclosed. | 2009-07-02 |
| 20090168490 | FERROELECTRIC MEMORY CELL WITH ACCESS TRANSMISSION GATE - One embodiment relates to an integrated circuit that includes a ferroelectric memory cell. The ferroelectric memory cell includes a ferroelectric capacitor having a first plate and a second plate. The first plate is associated with a storage node of the ferroelectric memory cell, and the second plate associated with a plateline. The ferroelectric memory cell also includes a complementary transmission gate configured to selectively couple the storage node to a bitline as a function of a wordline voltage and a complementary wordline voltage. Bias limiting circuitry selectively alters voltage on the storage node as a function of the wordline voltage or the complementary wordline voltage. Other methods, devices, and systems are also disclosed. | 2009-07-02 |
| 20090168491 | MEMORY CELL THAT EMPLOYS A SELECTIVELY FABRICATED CARBON NANO-TUBE REVERSIBLE RESISTANCE-SWITCHING ELEMENT AND METHODS OF FORMING THE SAME - In some aspects, a method of fabricating a memory cell is provided that includes (1) fabricating a steering element above a substrate; and (2) fabricating a reversible-resistance switching element coupled to the steering element by selectively fabricating carbon nano-tube (CNT) material above the substrate. Numerous other aspects are provided. | 2009-07-02 |
| 20090168492 | Two terminal nonvolatile memory using gate controlled diode elements - A nonvolatile memory cell includes a gate controlled diode steering element and a resistivity switching element. | 2009-07-02 |
| 20090168493 | SEMICONDUCTOR MEMORY DEVICE WITH STACKED MEMORY CELL AND METHOD OF MANUFACTURING THE STACKED MEMORY CELL - In a semiconductor memory device and method, resistive-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices comprising a resistive-change memory. Each resistive-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of resistive-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the resistive-change memory cells of each of the resistive-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the resistive-change memory cells. | 2009-07-02 |
| 20090168494 | Semiconductor device having resistance based memory array, method of operation, and systems associated therewith - In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write circuit configured to write to the non-volatile memory cell array, and a control circuit. The control circuit is configured to store at least one erase indicator. The erase indicator is associated with at least a portion of the non-volatile memory cell array and indicates a logic state. The control circuit is configured to control the write circuit to write the logic state indicated by the erase indicator in the non-volatile memory cell array during an erase operation of the associated portion of the non-volatile memory cell array. | 2009-07-02 |
| 20090168495 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF WRITING INTO SEMICONDUCTOR MEMORY DEVICE - In the semiconductor memory device having a resistance memory element, a first transistor having a drain terminal connected to one end of the resistance memory element and a source terminal connected to a ground voltage, and a second transistor having source terminal connected to the resistance memory element, when a write voltage is applied to the resistance memory element via the second transistor to switch the resistance memory element from a low resistance state to a high resistance state, a voltage is controlled to be a value which is not less than a reset voltage and less than a set voltage by applying to a gate terminal of the second transistor a voltage which is not less than a total of the reset voltage and a threshold voltage of the second transistor and is less than a total of the set voltage and the threshold voltage. | 2009-07-02 |
| 20090168496 | Memory Cell Having Improved Write Stability - A method is provided for writing to a memory cell having a read access circuit that is separate and isolatable from a write access circuit. The method comprises providing a logic state to be written to the memory cell onto a write bit line coupled to the memory cell through the write access circuit, changing a write word line that controls the write access circuit from a deactivated low voltage state to an activated high voltage state, and changing a read word line that controls the read access circuit from an activated low voltage state to a deactivated high voltage state, wherein the change in voltage on the read word line provides a voltage boost to the voltage on the write word line caused by the electrical coupling between the read word line and the write word line to provide write assist to the memory cell during a write operation. | 2009-07-02 |
| 20090168497 | Memory Leakage Control Circuit and Method - In one embodiment, a static random access memory (SRAM) is operable with first voltage and second voltages and comprises a plurality of SRAM cells arranged in rows and columns, each SRAM cell being coupled to a respective wordline, respective complementary bitlines, and a source line and a control circuit connected between the source line and the second voltage. The control circuit is selectively operable in a working mode in which data in the plurality of SRAM cells can be accessed and a shutdown mode in which the source line is allowed to float to a level that is substantially equal to the first voltage. | 2009-07-02 |
| 20090168498 | Spacer patterned augmentation of tri-gate transistor gate length - In general, in one aspect, a method includes forming a semiconductor substrate having N-diffusion and P-diffusion regions. A gate stack is formed over the semiconductor substrate. A gate electrode hard mask is formed over the gate stack. The gate electrode hard mask is augmented around pass gate transistors with a spacer material. The gate stack is etched using the augmented gate electrode hard mask to form the gate electrodes. The gate electrodes around the pass gate have a greater length than other gate electrodes. | 2009-07-02 |
| 20090168499 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of cell arrays, each cell array containing a plurality of word lines, a plurality of bit lines crossing the word lines, and memory cells connected at intersections of the word lines and bit lines, the cell arrays arranged along the bit line; a plurality of bit line gates provided between the cell arrays and each operative to establish a connection between the bit lines in adjacent cell arrays; and a controlling circuit operative to form a data transfer path via the connection between the bit lines formed through the bit line gate when the controlling circuit accesses to the memory cell. | 2009-07-02 |
| 20090168500 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a sub array including a plurality of memory cells each holding data arranged therein; a memory cell array including a plurality of the sub arrays arranged therein; paired bit lines including a first bit line and a second bit line connected to each of the sub arrays; and a write/read circuit arranged to correspond to each of the sub arrays, writing data to the sub array, and reading data from the sub array, wherein a pair of the sub array and the write/read circuit is repeatedly arranged along the paired bit lines, allowing the data to be transferred via the write/read circuit and the paired bit lines, | 2009-07-02 |
| 20090168501 | Magnetic memory and method for writing to magnetic memory - Provided is a magnetic random access memory employing spin torque magnetization reversal having a small write current value is applied. The memory includes: a switching element the conduction of which is controlled by a gate electrode, and three magnetoresistance effect elements connected to the switching element in series. Each magnetoresistance effect element may be a TMR element or a GMR element that includes a multilayered film composed of a fixed layer, a non-magnetic layer and a free layer. The central element serves as a storage element. The magnetoresistance effect elements are manufactured such that an absolute value of current necessary for changing a magnetization direction of at least one of the magnetoresistance effect elements located at both ends is larger than an absolute value of current necessary for changing a magnetization direction of the central magnetoresistance effect element. | 2009-07-02 |
| 20090168502 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device that enables high-speed data read and reduces the area of a drive circuit for activating a word line. By signal transmission through a common word line having a low resistance and coupled at a plurality of points to a word line, it is possible to read data at high speed. Further, since the common word line is provided common to a plurality of memory blocks, a word line driver can be provided common to the memory blocks. Further, by disposing a latch circuit, corresponding to a sub-digit line, for holding the active state of the common word line, it is possible to transmit a row selection signal during data write through the common word line and thereby reduce a metal wiring layer. | 2009-07-02 |
| 20090168503 | Phase change memory with bipolar junction transistor select device - A phase change memory may be organized with a global word line coupled to a plurality of blocks, each with a plurality of phase change memory cells arranged in rows and columns. Thus, one global word line may be common to a plurality of blocks. The global word line may be coupled to a word line decoder that is responsible for pulling the word line to ground. Each of the blocks, on the other hand, is coupled to a bitline selector through a bitline. Each block may have its own local word line coupled to the global word line. In some cases, this architecture reduces the minimum capacity of the memory. | 2009-07-02 |
| 20090168504 | Phase change memory apparatus having an improved cycling endurance and programing method therefor - A phase change memory apparatus includes a phase change memory array in which a plurality of phase change memory devices are arranged, and a pulse generator that supplies a writing current pulse, an erasure current pulse, and a reverse repair current pulse to the phase change memory devices in the phase change memory array. The reverse repair current pulse has opposite direction to the writing current pulse and the erasure current pulse of the phase change memory devices, and is of such a size that resultant Joule heat and electromigration move the elements of the reverse repair current pulse. The reverse repair current pulse has a width equal to or more than a smaller one of duration of a normal writing operation and duration of a normal erasure operation. | 2009-07-02 |
| 20090168505 | SEMICONDUCTOR DEVICE - A phase change memory capable of highly reliable operations is provided. A semiconductor device has a memory array having a structure in which memory cells are stacked including memory layers using a chalcogenide material and diodes, and initialization conditions and write conditions are changed according to the layer in which a selected memory cell is positioned. The initialization conditions and write conditions (herein, reset conditions) are changed according to the operation by selecting a current mirror circuit according to the operation and by a control mechanism of a reset current in a voltage select circuit and the current mirror circuit. | 2009-07-02 |
| 20090168506 | CLOSE SHAPED MAGNETIC MULTI-LAYER FILM COMPRISING OR NOT COMPRISING A METAL CORE AND THE MANUFACTURE METHOD AND THE APPLICATION OF THE SAME - Each layer in the magnetic multilayer film is a closed ring or oval ring and the magnetic moment or flux of the ferromagnetic film in the magnetic unit is in close state either clockwise or counterclockwise. A metal core is put in the geometry center position in the close-shaped magnetic multilayer film. The cross section of the metal core is a corresponding circular or oval. A MRAM is made of the closed magnetic multilayer film with or without a metal core. The close-shaped magnetic multilayer film is formed by micro process method. The close-shaped magnetic multilayer film can be used broadly in a great variety of device that uses a magnetic multilayer film as the core, such as MRAM, magnetic bead in computer, magnetic sensitive sensor, magnetic logic device and spin transistor. | 2009-07-02 |
| 20090168507 | Method of programming cross-point diode memory array - A method of programming a nonvolatile memory array including a plurality of nonvolatile memory cells, a plurality of bit lines, and a plurality of word lines, wherein each memory cell comprises a diode, or a diode and a resistivity switching element is disclosed. The method includes both bias programming the memory cells of the device. | 2009-07-02 |
| 20090168508 | Static random access memory having cells with junction field effect and bipolar junction transistors - A static random access memory (SRAM) device can include at least one SRAM cell having storage section that includes at least a first junction field effect transistor (JFET) with a gate terminal formed from a semiconductor layer deposited on a substrate surface. The storage section can also include at least a first storage node that provides a potential corresponding to a stored data value. The SRAM cell further includes a first access section that includes at least a first bipolar junction transistor (BJT) having an emitter formed from the semiconductor layer. | 2009-07-02 |
| 20090168509 | Ultra low voltage, low leakage, high density, variation tolerant memory bit cells - Methods and apparatus to provide ultra low voltage, low leakage, high density, and/or variation tolerant memory bit cells are described. In one embodiment, each of the cross-coupled invertors of a memory cell may include a plurality of p-channel transistors. Other embodiments are also described. | 2009-07-02 |
| 20090168510 | Method of operating non-volatile memory device - The present invention relates to an operation of a non-volatile memory device. According to a method of operating a non-volatile memory device in accordance with an aspect of the present invention, a first program operation is performed by applying a first program voltage to word lines of memory cells, constituting a memory block. As a result of the first program operation, threshold voltages of the memory cells are firstly measured. A second program operation is performed using a second program voltage, which is increased as much as a difference between a first threshold voltage, that is, a lowest voltage level of the firstly measured threshold voltages and a second threshold voltage, that is, an intermediate voltage level of the firstly measured threshold voltages. The second program operation is repeatedly performed by increasing the second program voltage as much as the difference between the first and second threshold voltages until the lowest threshold voltage becomes higher than a program verify voltage. A pass voltage is then set by reflecting a first voltage level, that is, a difference between a program voltage applied in a last program execution step and the first program voltage. | 2009-07-02 |
| 20090168511 | Flash memory device and reading method thereof - Disclosed is a flash memory device including a memory cell array having memory cells arranged at intersections of word lines and bit lines, such that one bit line is associated with a plurality of memory cells connected in series, a voltage generator configured to generate at least a first selection voltage, a row selection circuit configured to drive the non-selected word lines based on at least the first non-selected voltage, and a control logic circuit configured to control the voltage generator and the row selection circuit, such that the voltage generator generates at least the first non-selection voltage based on a location of a selected memory cell in the plurality of memory cells. | 2009-07-02 |
| 20090168512 | NONVOLATILE MEMORY - A nonvolatile memory wherein remaining lifetimes of memory cells can be accurately determined is provided, the nonvolatile memory includes: plural memory cell groups, assigned with respective addresses, arranged for respective words and used for storing one word of data; plural dummy cell groups also assigned the respective addresses and having different ranks of rewriting lifetimes; a writing circuit which, when writing data into a memory cell group having a given address, also writes the data into a dummy cell group having the same address at the same time; a lifetime recognizing circuit which recognizes an estimated number of past writing times by determining whether each dummy cell group can be successfully accessed; and a control section which controls operations of the memory cell groups and the dummy cell groups in response to an externally given command. | 2009-07-02 |
| 20090168513 | MULTIPLE LEVEL CELL MEMORY DEVICE WITH IMPROVED RELIABILITY - The reliability of multiple level cells in a memory device should be increased by programming the ends of the series strings of memory cells differently than the remaining quantity of memory cells of the series string. The end cells closest to select gate source and select gate drain transistors can be programmed as single level cells while the remaining cells of the string are programmed as multiple level cells. Another embodiment can program only one or more cells at the source end of the series string as single level cells. Still another embodiment can skip programming of the cells at either only the source end or both the source end and the drain end of the series string. | 2009-07-02 |
| 20090168514 | SEMICONDUCTOR MEMORY DEVICE PROVIDED WITH MEMORY CELLS HAVING CHARGE STORAGE LAYER AND CONTROL GATE - A semiconductor memory device includes a memory cell, a source line, and a source line control circuit. The memory cell includes a charge storage layer and a control gate and is capable of holding 2 levels or more levels of data. The source line is electrically connected to a source of the memory cell. The source line control circuit detects a current passed to the source line and controls a potential of the source line in accordance with a detected current amount in a reading operation or a verification operation of the data. | 2009-07-02 |
| 20090168515 | Semiconductor Memory Device for Storing Multivalued Data - Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining the first memory cells in the bit line direction. | 2009-07-02 |
| 20090168516 | Method for Generating Soft Bits in Flash Memories - Information stored as physical states of cells of a memory is read by setting each of one or more references to a respective member of a first set of values and reading the physical states of the cells according to the first set. Then, at least some of the references are set to respective members of a second set of values, and the physical states of the cells are read according to the second set. At least one member of the second set is different from any member of the first set, so that the two readings together read the physical states of the cells with higher resolution than the first reading alone. | 2009-07-02 |
| 20090168517 | Read and volatile NV standby disturb - A method of operating a nonvolatile memory circuit having a plurality of transistors arranged in series between a voltage/current source node and recall sink node includes asserting a gate bias on an isolation transistor between the source node and a charge storage transistor during nonvolatile STANDBY. | 2009-07-02 |
| 20090168518 | CHIP SELECT CONTROLLER AND NON-VOLATILE MEMORY DEVICE INCLUDING THE SAME - A chip select controller for a non-volatile memory device includes a first chip enable signal transfer unit, a second chip enable signal transfer unit, a first chip select pad, a second chip select pad, a third chip select pad and a chip select unit. The first chip enable signal transfer unit buffers first and second chip enable signals according to a control signal. The second chip enable signal transfer unit buffers third and fourth chip enable signals according to the control signal. The first chip select pad is configured to transfer a first chip select signal. The second chip select pad is configured to transfer a second chip select signal. The third chip select pad is configured to transfer the second chip select signal. The chip select unit addresses a specific chip according to the first chip select signal and the second chip select signal. | 2009-07-02 |
| 20090168519 | Architecture of a nvDRAM array and its sense regime - A process of operating a memory array includes performing all volatile and nonvolatile operations on an nvDRAM cell array via a single data interface and using only DRAM-level signals on the data interface. | 2009-07-02 |
| 20090168520 | 3T high density NVDRAM cell - A memory circuit includes a single transistor storing both volatile and nonvolatile bit charges. | 2009-07-02 |
| 20090168521 | 5T high density NVDRAM cell - A memory circuit includes a high voltage region providing storage of a nonvolatile bit, and a low voltage region providing at least partial storage of a volatile bit. The high and low voltage regions are isolated from one another and formed by a plurality of transistors in series between a current source and a bit line. | 2009-07-02 |
| 20090168522 | SEMICONDUCTOR MEMORY DEVICE WITH IMPROVED ECC EFFICIENCY - Memory cells store k bits of data (k is a natural number not less than 2) into a single cell. A number n of data storage circuits store externally supplied k bits of data to write data into the memory cells. A control circuit inputs the data on a first page, a second page, . . . , a k-th page to every h (h≦n) of the data storage circuits and then writes the data in the n data storage circuits into the memory cells. | 2009-07-02 |
| 20090168523 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device includes: a memory cell array; a bad block position data register area defined in the memory cell array to store bad block position data; an address decoder circuit configured to select a block in the cell array; and bad block flag latches disposed in the address decoder circuit, bad block flags being set in the bad block flag latches in accordance with the bad block position data read out the bad block position data register area, wherein the bad block position data in the bad block position data register area are defined by such a bit position assignment scheme that one bit is assigned to one block under the condition that block positions in the cell array and column positions in one page are set in one-to-one correspondence. | 2009-07-02 |
| 20090168524 | WEAR LEVEL ESTIMATION IN ANALOG MEMORY CELLS - A method for operating a memory includes applying at least one pulse to a group of analog memory cells, so as to cause the memory cells in the group to assume respective storage values. After applying the pulse, the respective storage values are read from the memory cells in the group. One or more statistical properties of the read storage values are computed. A wear level of the group of the memory cells is estimated responsively to the statistical properties. | 2009-07-02 |
| 20090168525 | Flash memory controller having reduced pinout - Disclosed is a flash memory controller connected to a flash memory module. The pin-out of the flash memory controller combines ready-busy and chip-select signals. In one embodiment, the flash memory module is made up of a set of banks, each consisting of a plurality of devices, with each bank sharing a single chip-select/ready-busy connection to the controller. | 2009-07-02 |
| 20090168526 | FLASH MEMORY DEVICE HAVING DUMMY CELL - A nonvolatile semiconductor memory device includes a string selection transistor coupled to a bit line. The device also includes a plurality of memory cells coupled in series to the string selection transistor, wherein at least one of the memory cells is configured to be in a programmed state during an erase procedure of the plurality of memory cells. | 2009-07-02 |
| 20090168527 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a memory cell array having a plurality of word lines and a plurality of bit lines, and at least first and second page buffers to which the plurality of bit lines are connected. The plurality of word lines are divided into first and second word lines and the first and second word lines are arranged in positions corresponding to the at least first and second page buffers. | 2009-07-02 |
| 20090168528 | FLASH MEMORY DEVICE AND DATA I/O OPERATION METHOD THEREOF - A flash memory device comprises a memory cell array, an input buffer unit, an output driver unit, first and second page buffer units, and first and second data handling units. The memory cell array includes two or more memory banks. During a data input operation, the first and second data handling units respectively receive first and second input data from the input buffer unit, and transfer the first and second input data to the first and second page buffers alternately after receiving the external address signals. During a data output operation, the first and second data handling units respectively receive first and second output data from the first and second page buffer units, and transfer the first and second input data to the output driver unit alternately after receiving the external address signals, so that the output driver unit outputs the first and second input data to the external device alternately. | 2009-07-02 |
| 20090168529 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE, METHOD FOR MANUFACTURING THE SAME, AND NONVOLATILE MEMORY ARRAY - A floating gate made of polysilicon is provided on a semiconductor substrate through the medium of a gate insulator. A side-wall insulating film is provided on each side wall of the floating gate. A first impurity diffusion layer, which occupies a space within the semiconductor substrate, is provided separately apart from the floating gate by a predetermined distance. A second impurity diffusion layer, which occupies a space within the semiconductor substrate, overlaps with the floating gate. Electrons are injected into the floating gate by applying a high voltage to the second impurity diffusion layer in capacitive coupling with the floating gate. | 2009-07-02 |
| 20090168530 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF READING DATA THEREFROM - A semiconductor memory device comprises a first memory cell array having a first plane which is composed of a plurality of blocks each having a plurality of memory cells, a sense circuit which reads data the memory cells, a sequencer which receives control signals from outside, a first address register, and a second address register which receives an output address from the first address register and outputs an address signal in response to an address control signal from the sequencer. In reading from the memory cells, the sequencer reads a page n in accordance with the address stored in the second address register, then transfers an address stored in the first address register to the second address register concurrently with outputting data read from the page n to outside and reads data from an arbitrary page m in accordance with the address transferred to the second address register. | 2009-07-02 |
| 20090168531 | METHOD FOR PROGRAMMING A MEMORY STRUCTURE - A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure includes respectively providing a first gate biasing voltage and a second gate biasing voltage to the first memory cell and the second memory cell, boosting the absolute value of a channel voltage of the first memory cell to generate electron and hole pairs at the drain of the second memory cell through gate-induced drain leakage or band-to-band tunneling, and injecting the electron of the generated electron and hole pairs into the charge storage device of the first memory cell to program the first memory cell. | 2009-07-02 |
| 20090168532 | NONVOLATILE MEMORY DEVICES THAT UTILIZE DUMMY MEMORY CELLS TO IMPROVE DATA RELIABILITY IN CHARGE TRAP MEMORY ARRAYS - A charge trap flash memory device includes a flash memory array having at least a first page of charge trap memory cells therein electrically coupled to a first word line. The first page of charge trap memory cells includes a plurality of addressable memory cells configured to store data to be retrieved during read operations and a plurality of immediately adjacent non-addressable “dummy” memory cells configured to store dummy data that is not retrievable during the read operations. The plurality of dummy memory cells include at least one auxiliary dummy memory cell that operates as a buffer against lateral hole transfer within a charge trap layer of the array. | 2009-07-02 |
| 20090168533 | THREE-DIMENSIONAL MEMORY DEVICE AND PROGRAMMING METHOD - A programming method and a three-dimensional memory device are disclosed. The three-dimensional memory device includes a stacked plurality of layers, each layer having a memory array, and each memory array having a string of memory cells. The programming method includes, for each unselected string associated with an unselected layer in the plurality of layers, charging the channel of memory cells associated with unselected string with a shut-off voltage, and thereafter programming a selected string associated with a selected layer in the plurality of layers. | 2009-07-02 |
| 20090168534 | THREE-DIMENSIONAL MEMORY DEVICE WITH MULTI-PLANE ARCHITECTURE - Disclosed is a 3D memory device including a first plane having a first mat formed on a first layer and a third mat formed on a second layer disposed over the first layer, the first and third mats sharing a bit line, and a second plane having a second mat formed on the first layer and a fourth mat formed on the second layer. The second and fourth mats share a bit line. Each one of the first through fourth mats includes a plurality of blocks and a block associated with the first plane is simultaneously accessed with a block of the second plane. | 2009-07-02 |
| 20090168535 | NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A non-volatile memory device includes a memory cell array and a controller. The memory cell array includes memory cells for data storage and a plurality of flag cells. The flag cells indicate program states of the memory cells for each of a plurality of word lines. The controller determines the program states of the memory cells by employing the flag cells and controls a pass voltage provided to a corresponding word line according to the determined program states. | 2009-07-02 |
| 20090168536 | METHOD OF PROGRAMMING NON-VOLATILE MEMORY DEVICE - A method of programming a non-volatile memory device includes applying a power supply voltage to a drain select line, applying a high level voltage to a drain-side pass word line or a source-side pass word line, and applying a pass voltage to unselected word lines and a program voltage to a selected word line. The high level voltage is applied to the drain-side pass word line or the source-side pass word line before applying the pass voltage to the unselected word lines and the program voltage to the selected word line. | 2009-07-02 |
| 20090168537 | METHOD OF PROGRAMMING A NON-VOLATILE MEMORY DEVICE - A method of programming a non-volatile memory device includes applying a first pass voltage to word lines in a direction of a source select line based on a first word line selected for a program operation, wherein the word lines do not include a second word line adjacent to the first word line in a direction of the source select line; and applying a first voltage, a program voltage and a second pass voltage when the first pass voltage reaches a given level. The first voltage is applied to the second word line, the program voltage is provided to the first word line, and the second pass voltage is applied to word lines in a direction of a drain select line on the basis of the first word line. | 2009-07-02 |
| 20090168538 | Method of Programming Non-Volatile Memory Device - A programming method of a non-volatile memory device may include providing a memory device in which a first word line is preprogrammed in an erase operation of a memory block, pre-programming a second word line according to a program command, and programming the first word line. | 2009-07-02 |
| 20090168539 | Semiconductor integrated circuit and unstable bit detection method for the same - A semiconductor integrated circuit including a nonvolatile memory cell is provided with a detection/word line voltage control circuit for sequentially supplying two or more mutually different unstable bit detecting voltages to a control gate of the nonvolatile memory cell to cause the nonvolatile memory cell to output a plurality of pieces of readout data, and an OK/NG determination circuit for comparing the plurality of pieces of readout data to determine whether the nonvolatile memory cell is stable or not. | 2009-07-02 |
| 20090168540 | Low Noise Sense Amplifier Array and Method for Nonvolatile Memory - In sensing a page of nonvolatile memory cells with a corresponding group of sense modules in parallel, as each high current cell is identified, it is locked out from further sensing while others in the page continued to be sensed. The sense module involved in the locked out is then in a lockout mode and becomes inactive. A noise source from the sense module becomes significant when in the lockout mode. The noise is liable to interfere with the sensing of neighboring cells by coupling through its bit line to neighboring ones. The noise can also couple through the common source line of the page to affect the accuracy of ongoing sensing of the cells in the page. Improved sense modules and method isolate the noise from the lockout sense module from affecting the other sense modules still active in sensing memory cell in the page. | 2009-07-02 |
| 20090168541 | ELECTRICAL ERASABLE PROGRAMMABLE MEMORY TRANSCONDUCTANCE TESTING - A test method determines if an array of a Flash EEPROM circuit has a bit cell with a transconductance (gm) that is deficient. The method preconditions all bit cells of the array to a particular programmed state and then determines whether any of the bit cells exhibit undesirable operating characteristics by reading each bit cell to determine whether its transconductance is less than desirable. | 2009-07-02 |
| 20090168542 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device capable of reading and verifying a negative threshold cell by biasing a source line and a well line to a positive voltage. The nonvolatile semiconductor memory device includes a precharge circuit which precharges a bit line to the same voltage as that of the source line in reading and verifying the negative threshold cell. | 2009-07-02 |
| 20090168543 | METHOD OF OPERATING A NON-VOLATILE MEMORY DEVICE - A method of operating a non-volatile memory device changes a read voltage by determining a degree that threshold voltages of memory cells are changed and overlap each other. The method of operating the non-volatile memory device includes performing a least significant bit (LSB) program of memory cells and determining a first error rate, performing a most significant bit (MSB) program of the memory cells and determining a second error rate, and setting a read voltage corresponding to a value at which the first and second error rates are minimum values. | 2009-07-02 |
| 20090168544 | ERASE METHOD AND SOFT PROGRAMMING METHOD OF NON-VOLATILE MEMORY DEVICE - An erase method and a soft programming method of a non-volatile memory device includes performing an erase operation on a memory cell block; applying a pass voltage to a memory cell adjacent to a select transistor of the memory cell block; applying a soft program voltage to the remaining memory cells of the memory cell block; and performing a soft program operation. | 2009-07-02 |
| 20090168545 | Semiconductor Device and Method of Fabricating the Same - Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device can include a first wafer including a light emitting diode (LED), a second wafer including a flash cell formed corresponding to the LED, and a conductive via that electrically connects the first wafer to the second wafer. | 2009-07-02 |
| 20090168546 | Semiconductor memory device and method for operating the same - A semiconductor memory device includes a first buffering unit configured to buffer a first clock for an address signal and a command to be input in synchronization with the first clock, a second buffering unit configured to buffer a second clock for a data signal to be in synchronization with the second clock to output a buffered second clock having the same frequency as the first clock, a data output circuit configured to output an internal data in response to the buffered second clock, a delay unit configured to delay the buffered second clock by a predetermined time, and a phase detector configured to detect a phase difference of an output clock of the delay unit and the output clock of the first buffering unit, and to output the detection result. | 2009-07-02 |
| 20090168547 | APPARATUS AND METHODS FOR A DATA INPUT CIRCUIT FOR A SEMICONDUCTOR MEMORY APPARATUS - A data input circuit for a semiconductor memory apparatus includes a data latch block that, according to a data strobe signal, latches data and outputs the latched data; a data output controlling unit that determines a phase difference between the data strobe signal and a clock signal, and activates a data output control signal; and a data delay block that, when the data output control signal is activated, delays the data output from the data latch block for a predetermined time, and outputs the delayed data. | 2009-07-02 |
| 20090168548 | DATA OUTPUT CIRCUIT IN SEMICONDUCTOR MEMORY APPARATUS - A data output circuit in a semiconductor memory apparatus includes a first data driving unit configured to generate a first driving data at a first timing, a first buffering unit configured to generate a first output data by buffering the first driving data, a second data driving unit configured to generate a second driving data at a second timing that is different from the first timing, and a second buffering unit configured to generate a second output data by buffering the second driving data. | 2009-07-02 |
| 20090168549 | Data output buffer circuit and semiconductor memory device includig the same - The example embodiments provide a data output buffer circuit which includes a pre-driver configured to adjust a slew rate of an input signal, a main driver configured to output signal supplied from the pre-driver, and a ZQ calibration circuit configured to control the pre-driver so as to decrease the slew rate when an operation voltage increases, and increase the slew rate when the operation voltage is decreased. | 2009-07-02 |
| 20090168550 | Output port, microcomputer and data output method - An output port circuit includes a plurality of output buffers; a plurality of first holding circuits configured to hold output data to be outputted to the plurality of output buffers; a plurality of second holding circuits configured to hold output data to be outputted to the plurality of first holding circuits; and a plurality of third holding circuits configured to hold bit pattern data for individually setting whether the output data of the plurality of second holding circuits are latched by the plurality of first holding circuits. Data input to the plurality of second holding circuits and data input to the plurality of third holding circuits are controlled at a same timing. | 2009-07-02 |
| 20090168551 | LOW VOLTAGE SENSE AMPLIFIER AND SENSING METHOD - Systems and methods of sensing a data state coupled to a digit line and for coupling a digit line to a sense amplifier. In sensing the data state coupled to the digit line, the digit line is coupled to a sense node and driving voltages provided to the sense amplifier. The data state is latched in response to the driving voltages. In coupling the digit line to a sense amplifier, the digit line is coupled to the sense amplifier for a first time period and decoupled from the sense amplifier for a second time period. The digit line is coupled to the sense amplifier at a controlled rate following the second time period. | 2009-07-02 |
| 20090168552 | Semiconductor memory device and method for operating the same - A semiconductor memory device includes an edge detector configured to receive two pairs of complementary clocks to detect edges of the clocks, a comparator configured to compare output signals of the edge detector to detect whether clocks of the same pair have a phase difference of 180 degrees and detect whether clocks of different pairs have a phase difference of 90 degrees, a control signal generator configured to generate a control signal for controlling phases of the clocks according to an output signal of the comparator, and a phase corrector configured to correct phases of the clocks in response to the control signal. | 2009-07-02 |
| 20090168553 | Semiconductor memory device and method of operating the same - Semiconductor memory device and method of operating the same includes an enable signal generator configured to generate first and second enable signals having activation timings determined in response to activation of an active command, the first enable signal being deactivated after a first time from a deactivation timing of the active command, and the second enable signal being deactivated after a second time longer than the first time from the deactivation timing of the active command. Internal voltage generators are configured to generate internal voltages. At least one of the internal voltage generators is turned on/off in response to the first enable signal, and at least one other of the internal voltage generators is turned on/off in response to the second enable signals. | 2009-07-02 |
| 20090168554 | LOW COUPLE EFFECT BIT-LINE VOLTAGE GENERATOR - A bit-line voltage generator is provided. The bit-line voltage generator includes a discharge enhanced bias source and a switch unit. The switch unit includes a clamp transistor having a source, a gate connected to the discharge enhanced bias source, and a drain receiving a voltage; a switch transistor having a gate receiving a control signal, a drain connected to the source of the clamp transistor, and a source connected to a memory array, wherein a parasitic capacitor exists between the gate and the source of the clamp transistor; a resistor having a first terminal connected to the drain of the switch transistor, and a second terminal connected to ground; and a capacitor having a first terminal connected to the drain of the switch transistor, and a second terminal connected to ground, wherein a charge in the parasitic capacitor, when the switch transistor is turned on, is almost identical to that when the switch transistor is turned off, so that a couple effect between the switch unit and the discharge enhanced bias source is reduced, thereby stabilizing a bias applied to the memory array. | 2009-07-02 |
| 20090168555 | Delay circuit and semiconductor memory device having the same - A delay circuit is capable of securing a constant delay time in spite of a process variation as well as voltage and temperature variations. Using the delay circuit that secures a sensing margin time in spite of process, voltage and temperature variations, a semiconductor memory device is capable of amplifying desired data within a preset RAS to CAS delay (tRCD). The delay circuit includes a delay unit including a current source controlled by a bias voltage, a delay time of the delay unit being changed depending on current amount of the current source, and a bias voltage generating unit configured to divide a power supply voltage using a first resistor to generate the bias voltage, wherein the delay unit includes a second resistor inserted into a current path of the current source. | 2009-07-02 |
| 20090168556 | SEMICONDUCTOR MEMORY DEVICE FOR GENERATING BACK-BIAS VOLTAGE WITH VARIABLE DRIVING FORCE - A semiconductor memory device is capable of maintaining a predetermined back-bias voltage level regardless of operation modes of the semiconductor memory device, by generating a back-bias voltage with driving force changed according to the operation modes. The semiconductor memory device includes an active pumping control signal generating unit for generating an active pumping control signal in response to a plurality of active signals, a voltage detecting unit for detecting a voltage level of a back-bias voltage terminal to output a detection signal, an oscillator for generating an oscillation signal oscillating at a predetermined frequency in response to the detection signal, and a charge pumping unit for performing a charge pumping operation in response to the oscillation signal by controlling a force of driving the back-bias voltage terminal in response to the active pumping control signal. | 2009-07-02 |
| 20090168557 | Ultra wide voltage range register file circuit using programmable triple stacking - Methods and apparatus relating to expanding the operational voltage range of data storage circuits are described. In an embodiment, low voltage data storage circuit operation is improved by driving a transistor with a control word line programmable circuit. Other embodiments are also described. | 2009-07-02 |
| 20090168558 | 1-TRANSISTOR TYPE DRAM DRIVING METHOD WITH AN IMPROVED WRITE OPERATION MARGIN - A 1-transistor type DRAM driving process writes a data bit that corresponds to a level applied to a bit line. A first hold period holds data by deactivating a word line of an NMOS transistor and precharging a source and bit line. After the first hold period, a complex operation period operates the NMOS transistor and a bipolar transistor by activating the word line of the NMOS transistor, shifting the source line voltage to a ground voltage, and shifting the bit line voltage to a corresponding multi level bit voltage level. After the complex operation period, a bipolar transistor operation period operates only the bipolar transistor by deactivating the word line of the NMOS transistor. After the bipolar transistor operation period, a second hold period holds the data by precharging the source and bit lines of the NMOS transistor and the bit level applied to the bit line is written. | 2009-07-02 |
| 20090168559 | METHOD OF AND APPARATUS FOR READING DATA - Provided are an apparatus and a method of capturing data by using a data transition of a data signal. The method includes detecting a data transition of a data signal input from an external source, generating a pulse signal corresponding to the detected data transition, and capturing the data signal by using the generated pulse signal as a trigger. Accordingly, stable capturing of data can be performed without changes in margins even when data bits of the read data enter a controller at different times due to skews. | 2009-07-02 |
| 20090168560 | CIRCUIT AND METHOD FOR CONTROLLING LOCAL DATA LINE IN SEMICONDUCTOR MEMORY DEVICE - The present invention relates to a semiconductor memory device, and more particularly, to a circuit and method for controlling local data lines, which can reduce loading on local data lines LIO. The circuit and method for controlling local data lines in accordance with the present invention is characterized by having different line loading of local data lines depending on positions of cell mats. In addition, local data lines between arrays are connected by a switch. Accordingly, the switch is turned on/off by address information about cell mat arrays, thereby preventing unnecessary line loading of local data lines to completely remove unnecessary loading. Moreover, the present invention reduces line loading, thereby improving data processing speed. | 2009-07-02 |
| 20090168561 | TEST ENTRY CIRCUIT AND METHOD FOR GENERATING TEST ENTRY SIGNAL - Test entry circuit and method for generating test entry signal including a first source signal generator configured to receive a test signal through a pad to generate a first mode source signal for a first test mode, a second source signal generator configured to count activation transitions of the test signal to generate a second mode source signal for a second test mode and an entry signal generator configured to receive the first and second mode source signals to generate a first test mode entry signal for entering the first test mode and a second test mode entry signal for entering the second test mode. | 2009-07-02 |
| 20090168562 | SEMICONDUCTOR DEVICE, INFORMATION CONTROL METHOD AND ELECTRONIC DEVICE - A semiconductor device includes a first memory unit, a second memory unit, and a determination unit receiving a first signal permitting a write operation to one of the first memory unit and the second memory unit, and a second signal indicating whether the write operation of information to the first memory unit is finished, wherein the determination unit outputs a signal prohibiting a write operation to the second memory unit, if the second signal indicates the write operation of the information is finished. | 2009-07-02 |
| 20090168563 | Apparatus, system, and method for bitwise deskewing - A system and method for bitwise deskew. A DQS timing is used as reference, the delays of a plurality of transmission wires are calibrated with reference to a DQS line timing. Other embodiments are described and claimed. | 2009-07-02 |
| 20090168564 | Strobe signal controlling circuit - A strobe signal controlling circuit is provided which includes an initial write controller configured to outputs a write pulse signal, which is activated in a write command, in synchronization with a clock signal, a DQS signal outputting unit configured to outputs a write DQS signal by synchronizing an output signal of the initial write controller to the clock signal, a control signal generator configured to generates a control signal in response to the output signal of the initial write controller, and a reset signal generator configured to responds to a reset signal and a DQS enable signal to output a reset signal to the DQS signal outputting module in synchronization with the control signal. | 2009-07-02 |
| 20090168565 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - Semiconductor memory device and method for operating the same comprise an auxiliary driver configured to output an internal strobe signals generated corresponding to a read command as a plurality of auxiliary strobe signal in response to a control signal, wherein the auxiliary driver bypass a first output auxiliary strobe signal, and delay to output the rest of the auxiliary strobe signal among the outputted auxiliary strobe signal and a strobe signal generator for driving the auxiliary strobe signal to output the delayed auxiliary strobe signal as a data strobe signals. | 2009-07-02 |
| 20090168566 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device adjusts an activation timing and pulse width of a pin strobe signal according to a power supply voltage variation, and thereby loads data on a pipelatch properly and prevents an activation period of a pin strobe signal from falling out of a period for valid data. The semiconductor memory device includes a voltage detector configured to detect a level of a power supply voltage to output a detection signal, a pin strobe signal transfer path configured to transfer a pin strobe signal determining an input timing of data to a pipelatch, a delay controller configured to control a delay value of the pin strobe signal transfer path in response to the detection signal, and a pulse width modulator configured to modulate a pulse width of the pin strobe signal in response to the detection signal. | 2009-07-02 |
| 20090168567 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device can ensure a sufficient margin between a column select signal and a column address signal when a delay time of the column select signal is increased to improve an address access time during a write operation. The semiconductor memory device includes a discrimination signal generating circuit configured to generate a discrimination signal activated in a write operation of the device, and a selective delay circuit configured to selectively delay a column address in response to the discrimination signal. | 2009-07-02 |
| 20090168568 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device can output data according to a predetermined data output timing, in spite of a high frequency of system clock, even when a delay locked loop is disabled. The semiconductor memory device includes a delay locked loop configured to perform a delay locking operation on an internal clock to output delay locked clock, and a data output control unit configured to determine a data output timing, according to whether the delay locked loop is enabled or disabled, in response to a read command. | 2009-07-02 |
| 20090168569 | Method and device for redundancy replacement in semiconductor devices using a multiplexer - A redundancy replacement scheme for a semiconductor device repairing a faulty memory cell in a column select line group with a spare memory cell in the column select line group based on a physical or logical address of the selected row. | 2009-07-02 |
| 20090168570 | REDUNDANCY CIRCUIT USING COLUMN ADDRESSES - A redundancy circuit includes an address redundancy circuit block that compares column address information of a defective memory cell and an external input column address and outputs a redundancy column activation signal, and an input/output (IO) redundancy circuit block that, in response to IO fuse information, which is information about a sub-block where a column line of the defective memory cell is arranged, and the redundancy column activation signal, controls whether or not to activate a global IO line connected to an IO pad of the sub-block. | 2009-07-02 |
| 20090168571 | DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD OF DETERMINING REFRESH CYCLE THEREOF - Provided are a dynamic random access memory device having reduced power consumption and a method of determining a refresh cycle of the dynamic random access memory device. The method includes: selecting one or more monitoring bits during first through n-th self refresh cycles, where “n” is a natural number equal to or greater than one; detecting whether the monitoring bits have errors during (n+1)-th through m-th self refresh cycles, where “m” is a natural number equal to or greater than n+1; and adjusting an (m+1)-th self refresh cycle according to whether the monitoring bits have errors. | 2009-07-02 |
| 20090168572 | SEMICONDUCTOR MEMORY - In a semiconductor memory having a plurality of memory banks that can be independently accessed, remedying bit registers that are substituted for defective memory cells are respectively provided for memory banks in a one-to-one relationship. Also, means for sharing the plurality of remedying bit registers in each memory bank is arranged. | 2009-07-02 |
| 20090168573 | ADAPTIVE MEMORY ARRAY VOLTAGE ADJUSTMENT - In some embodiments a sensor is to sense a temperature of a memory occurring in the memory during active use of the memory. A controller is to adjust a voltage supply of the memory during active use of the memory in response to the sensed temperature. In some embodiments a monitor is to monitor errors occurring in a memory during active use of the memory, and a controller is to adjust a voltage supply of the memory during active use of the memory in response to the monitored errors. Other embodiments are described and claimed. | 2009-07-02 |
| 20090168574 | METHOD OF DRIVING 1-TRANSISTOR TYPE DRAM HAVING AN NMOS OVERLAIN ON TOP OF AN SOI LAYER - Driving a 1-transistor DRAM composed of an NMOS on top of a SOI layer such that the 1-transistor DRAM has a corresponding parasitic bipolar transistor component includes precharging, shifting, and deactivating steps. Implementing these steps can result in enhancing the performance of reading, writing and storing binary logic information within the 1-transistor DRAM memory device. | 2009-07-02 |
| 20090168575 | DEVICE AND METHOD TO REDUCE SIMULTANEOUS SWITCHING NOISE - By reducing a cumulative number of drivers changing values during a transition, the cumulative current change may be reduced, along with the simultaneous switching noise effects. Also, a reduced cumulative current change can also reduce voltage fluctuations in ground and/or power planes of a chip, thereby minimizing potential improper logic functions due to voltage dips or spikes. In one implementation, the method includes reading values of a first state of a first set of bits of a first word and obtaining a projected value of a second state of each of the first set of bits. If the first switching noise cumulative effect can be reduced by changing the projected values of the second state of the first set of bits, an alternate set of values having at least one value differing from the projected values of the second state is determined to reduce the first switching noise cumulative effect. | 2009-07-02 |
| 20090168576 | SEMICONDUCTOR MEMORY DEVICE - A memory includes: first sense amplifiers arranged in a first interval of an arrangement of memory cell arrays, each being connected to first bit lines corresponding to two memory cell arrays provided at both sides of the first sense amplifier; second sense amplifiers arranged in a second interval of the arrangement of the memory cell arrays, each being connected to second bit lines corresponding to two memory cell arrays at both sides of the second sense amplifier; edge arrays provided beside both ends of an arrangement of the memory cell arrays, the edge arrays generating only the reference data; and edge sense amplifiers provided between the arrangement of the memory cell arrays and the edge arrays, wherein the edge sense amplifier detects data from the memory cell array at one end of the memory cell arrays based on the reference data from one of the edge arrays. | 2009-07-02 |
| 20090168577 | SEMICONDUCTOR STORAGE DEVICE, AND DATA READING METHOD - A semiconductor storage device comprises of a memory cell connected to a plate line and a bit line, a potential shift circuit which is connected to a bit line, temporarily changes in output voltage corresponding to the voltage change of the bit line when a voltage is applied to the plate line, and then outputs a voltage before the application of the voltage to the plate line, a charge transfer circuit for transferring charge stored on the potential shift circuit corresponding to the temporary output voltage change of the potential shift circuit, and a charge accumulation circuit for generating a read voltage from a memory cell after accumulating the transferred charge. | 2009-07-02 |
| 20090168578 | Dummy cell for memory circuits - A memory cell array includes reference cells each associated with a plurality of data cells of the array. | 2009-07-02 |
| 20090168579 | RANDOM ACCESS MEMORY DATA RESETTING METHOD - A random access memory data resetting method is provided. The method includes following steps. First, a state machine resetting signal is provided to a RAM. Next, the state machine resetting signal is extended for a predetermined time period. Afterwards, a data resetting operation is executed in the RAM within the predetermined time period. | 2009-07-02 |
| 20090168580 | FUSE MONITORING CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE - A fuse monitoring circuit for a semiconductor device includes a repair fuse unit including a number of fuses to which a repair address is programmed, and configured to output fuse state signals corresponding to the connection states of the respective fuses in response to a fuse initialization signal. A serial fuse monitoring unit is configured to output a fuse state monitoring signal corresponding to each fuse state signal selected by an applied address in response to a serial monitoring test mode signal. Also, a parallel fuse monitoring unit is configured to output a repair monitoring signal by comparing an applied address and the repair address in response to a parallel monitoring test mode signal. An output unit is configured to output the fuse state monitoring signal and the repair monitoring signal to an output pad in response to an output control signal. | 2009-07-02 |
| 20090168581 | FUSE MONITORING CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE - A fuse monitoring circuit for a semiconductor memory device includes a fuse repair unit including a plurality of fuses each programmed with at least one repair address, configured to receive a fuse reset signal and to output a plurality of fuse state signals each corresponding to a connection state of one of the fuses, a fuse monitoring unit configured to receive a monitoring enable signal and to output a plurality of fuse state monitoring signals each corresponding to a corresponding one of the fuse state signals, each of the fuse state signals corresponding to one of a plurality of addresses, and an output unit configured to receive an output control signal and to output the fuse state monitoring signals to an output pad. | 2009-07-02 |
| 20090168582 | Internal voltage generating circuit and semiconductor memory device using the same - Disclosed is an internal voltage generating circuit. The internal voltage generating circuit comprises a voltage divider for generating a level signal by voltage-dividing first internal voltage, a pull-down signal generator for generating a pull-down signal, which has a level adjusted according to a temperature, in response to the level signal, a pull-up signal generator for generating a pull-up signal, which has a level adjusted according to the temperature, in response to the level signal, and a driving unit for driving second internal voltage in response to the pull-down signal and the pull-up signal. Driving force of the driving unit for driving the second internal voltage is changed according to the temperature. | 2009-07-02 |
| 20090168583 | Internal voltage generator of semiconductor memory device - An internal voltage generator of a semiconductor memory device generates pumping voltages (VPP, VBB, etc.) as internal voltages, which is capable of improving a charge pumping scheme. The internal voltage generator includes a plurality of charge pumping units for generating a pumping voltage by performing a charge pumping operation according to a plurality of pumping enable signals, and a pumping controller for controlling a number of the pumping enable signals to be activated according to a level of a fed-back pumping voltage. | 2009-07-02 |
| 20090168584 | SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF - A semiconductor memory device includes a clock synchronizing unit for receiving a first power voltage through a first power voltage terminal, and an additional power voltage providing unit for additionally providing a second power voltage to the first power voltage terminal for a predetermined period after leaving a power down mode. | 2009-07-02 |
| 20090168585 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes a voltage detector configured to detect a level of an external power supply voltage and an internal voltage generator configured to generate an internal voltage in response to an active signal and drive an internal voltage terminal with a driving ability corresponding to an output signal of the voltage detector. A method for operating the semiconductor memory device includes detecting a level of an external power supply voltage, based on a first target level, to output a detection signal; and generating an internal voltage in response to an active signal, and driving an internal voltage terminal with a driving ability corresponding to the detection signal. | 2009-07-02 |
| 20090168586 | CIRCUIT TO CONTROL VOLTAGE RAMP RATE - A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory cell in an incremental manner to control the overall voltage across the gate oxide. Voltage above a transfer threshold voltage, such as above a tunneling threshold voltage, is applied in a stepwise charge transfer manner to or from the floating gate up to a voltage limit that is below the thin oxide damage threshold. Controlling the overall voltage avoids oxide breakdown and enhances reliability. | 2009-07-02 |
