| 27th week of 2009 patent applcation highlights part 22 |
| Patent application number | Title | Published |
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| 20090167287 | METHOD FOR DISTINGUISHING A FIRST GROUP OF WIRES FROM OTHER WIRES OF A MULTI-WIRE CABLE, TEST CONNECTOR FOR USE IN THIS METHOD AND A KIT COMPRISING SUCH A MULTI-WIRE CABLE AND TEST CONNECTOR - The present invention relates to a method for distinguishing a first group of wires from other wires of a multi-wire cable, i.e. a method for identifying those wires of a multi-wire cable which belong to one group. Moreover, the present invention relates to a test connector for use in the method referred to before. Finally the present invention relates to a kit including a multi-wire cable with a connector and a mating test connector for performing the identification method. | 2009-07-02 |
| 20090167288 | Formation of Layers of Amphiphilic Molecules - To form a layer separating two volumes of aqueous solution, there is used an apparatus comprising elements defining a chamber, the elements including a body of non-conductive material having formed therein at least one recess opening into the chamber, the recess containing an electrode. A pre-treatment coating of a hydrophobic fluid is applied to the body across the recess. Aqueous solution, having amphiphilic molecules added thereto, is flowed across the body to cover the recess so that aqueous solution is introduced into the recess from the chamber and a layer of the amphiphilic molecules forms across the recess separating a volume of aqueous solution introduced into the recess from the remaining volume of aqueous solution. | 2009-07-02 |
| 20090167289 | Monitoring a Protective Device Arranged Upstream of a Switching Device - There is described a method and a system for monitoring a protective apparatus, which is connected upstream of a switching device and is connected to the switching device via at least one main current path. The wiring complexity for monitoring of the protective apparatus is minimized. This is achieved by virtue of the fact that the sate of the protective apparatus is determined by a tap of the at least one main current path at or in the switching device by means of an evaluation unit. As a result of this direct evaluation of the switching state of the protective organ on the switching device, the wiring which until now has been required for an addition auxiliary switch on the protective device is dispensed with a possible fault source also being minimized along with the wiring complexity. For this purpose, the proposed solution is also independent of the physical design (branch-oriented or row-oriented, distance between the devices) in a switchgear cabinet. | 2009-07-02 |
| 20090167290 | SYSTEM, METHOD, AND APPARATUS FOR MONITORING CHARACTERISTICS OF RF POWER - A system and method for monitoring RF power is described. In one embodiment the system samples RF power that is generated by an RF generator to obtain RF signals that include information indicative of electrical characteristics at a plurality of particular frequencies that fall within a frequency range. The RF signals are digitized to obtain a stream of digital RF signals that include information indicative of electrical characteristics at the plurality of particular frequencies, and the information indicative of electrical characteristics is successively transformed, for each of the plurality of particular frequencies, from a time domain into a frequency domain. | 2009-07-02 |
| 20090167291 | Method And Apparatus For Monitoring Voltage In A Meter Network - Methods and systems are provided for monitoring input voltages to meters that are in a wireless metering network. A plurality of entries can be created that include voltage-related information, such as a maximum input voltage or a minimum input voltage. Each meter can further determine whether the input voltage is beyond a predetermined threshold voltage for a duration that might indicate a voltage irregularity in the network. Each meter in the network can be monitored by a collector, which can communicate information to a data collection server. | 2009-07-02 |
| 20090167292 | Current Measuring Apparatus - A current measuring apparatus is disclosed. The current measuring apparatus comprises a power supply unit, an impedance setting module, and a current measuring unit. The power supply unit is adapted to provide an electric power to an electronic apparatus. The impedance setting module is adapted to provide at least one impedance value to the electronic apparatus so that the electronic apparatus is able to be activated in response to the electric power and the impedance value. The current measuring unit is adapted to show a current consumption value of the electronic apparatus under the activated state. | 2009-07-02 |
| 20090167293 | DIFFERENTIAL PROBE DEVICE FOR MEASURING ELECTRICAL DIFFERENTIAL SIGNALS AND METHODS FOR MEASURING SIGNALS USING A DIFFERENTIAL PROBE DEVICE - A differential probe device is provided that has a scissor-type configuration that allows the inter-tip ground path length to be very short, thereby ensuring that the probe device will have a small ground inductance. Providing the probe device with a small ground inductance ensures that the ground inductance will not cause the bandwidth of the probe device to be unduly limited, even at higher frequencies. The configuration of the probe device also enables the ground areas on the arms to remain in continuous contact over the range of available span widths between the tips, which also helps to ensure that the ground inductance is kept small and generally fixed. Also, the configuration of the probe device enables the proximal ends of the probe arms to be kept small in size to accommodate DUT layouts having small test features and/or test features that are close together. | 2009-07-02 |
| 20090167294 | TEST HANDLER, METHOD FOR LOADING AND MANUFACTURING PACKAGED CHIPS, AND METHOD FOR TRANSFERRING TEST TRAYS - A test handler, a packaged chip loading method, a test tray transferring method, and a packaged chip manufacturing method are provided. The test handler may include a loading unit, a chamber system, an unloading unit, at least one rotating unit and a transferring unit. The loading unit may include a loading buffer disposed to be movable along a moving path formed over a loading position and a loading picker to perform a loading process on the test tray located at the loading position. The chamber system having the packaged chips connected to a hi-fix board and tested. The unloading unit may include an unloading picker to perform an unloading process on the test tray located at an unloading position. The at least one rotating unit may be disposed between the loading unit and the unloading unit to rotate the test tray transferred from the loading unit from a horizontal posture to a vertical posture, and to rotate the test tray transferred from the chamber system from a vertical posture to a horizontal posture. The transferring unit may transfer the test tray. | 2009-07-02 |
| 20090167295 | PORTABLE ELECTRONIC DEVICE WITH ELECTRONIC COMPASS AND METHOD FOR CALIBRATING COMPASS - A calibrating method for a portable electronic device having azimuth device such as an electronic compass is disclosed. The calibrating method can be achieved by checking at least one sensor in the portable device incorporating the electronic compass configured in the portable device, so as to effectively detect and verify a temporary abnormal magnetic field caused by a stylus movement. When the electronic compass detects an abnormal magnetic field, the operation status of the sensor is checked for any change existence. If the operation status of the sensors changes, the abnormal magnetic field is verified as a temporary magnetic filed due to the movement of the stylus, in which case the electronic compass passes the calibration and goes on detecting the geomagnetic field according to its default setting value. | 2009-07-02 |
| 20090167296 | RESOLVER APPARATUS AND ANGLE DETECTION DEVICE AND METHOD OF RESOLVER - A resolver apparatus having a high detection precision detecting angle signals from signals detected at a resolver ( | 2009-07-02 |
| 20090167297 | OPTICAL FIBER SYSTEM AND METHOD FOR WELLHOLE SENSING OF FLUID FLOW USING DIFFRACTION EFFECT OF FARADAY CRYSTAL - A system and method for optically determining the rate and/or direction of fluid flow in a conduit within wellholes, using the diffraction effect of Faraday crystals through which continuous light is transmitted within optical fibers. | 2009-07-02 |
| 20090167298 | SYSTEM AND METHOD FOR THE NONDESTRUCTIVE TESTING OF ELONGATE BODIES AND THEIR WELDBOND JOINTS - An arrangement for testing an elongated body | 2009-07-02 |
| 20090167299 | METAL DETECTION DEVICE - There is provided a metal detection device capable of effectively detecting a metal mixed in food or the like by generating AC magnetic field simultaneously tuned to respective frequencies by a single transmission coil in response to frequency components of different frequencies without switching an element by a switch or the like. Constituent elements constituting magnetic field generation means ( | 2009-07-02 |
| 20090167300 | MAGNETIC CRASH SENSOR - At least one time-varying signal is applied to a plurality of coil elements in cooperative relationship with and spanning different portions of a vehicle. The coil elements generate an associated plurality of magnetic field components that interact with the vehicle. At least one detection circuit generates a detected signal responsive to signal components from the coil elements so as to provide for detecting a change in a magnetic condition of the vehicle. | 2009-07-02 |
| 20090167301 | INTEGRATED CIRCUIT INCLUDING A MAGNETIC FIELD SENSITIVE ELEMENT AND A COIL - An integrated circuit includes a die and a first magnetic field sensitive element formed on the die. The integrated circuit includes a first coil formed on the die and around the first magnetic field sensitive element. | 2009-07-02 |
| 20090167302 | Time-Lapsed Diffusivity Logging for Monitoring enhanced Oil Recovery - The use of time-lapsed NMR diffusivity measurements in an observation well is disclosed. The observation well is cased in the zone of interest with non-magnetic and non-conductive casing that is invisible to the NMR tool. Second, because NMR measurements have a dead zone in front of the antenna depending on the spatial variation of the fixed magnet strength, for example about 2.7 inches, a distance between the casing and the formation is reduced to less than the dead zone length by drilling the observation well at small deviation of about 5° and running the casing without centralizers. Both the casing and the pad-type NMR tool will follow the low side of the borehole, ensuring the measurement volume of the NMR tool is inside the formation and beyond the annulus. With the appropriate observation well completion, time-lapse diffusivity measurements with pad-type NMR tools can address several shortcomings in the current practice of monitoring EOR processes that rely upon changes in density and hydrogen index (HI). Various uses of NMR imaging in wells cased with non-metallic casing are also disclosed. | 2009-07-02 |
| 20090167303 | Method and Apparatus for Magnetic Resonance Analysis - A method of magnetic resonance analysis of a body having therein at least one molecular species and water is disclosed. The method comprises, subtracting magnetic resonance signals induced by a second radiofrequency pulse sequence from magnetic resonance signals induced by a first radiofrequency pulse sequence followed by a evolution period. The first radiofrequency pulse sequence is selected so as to suppress magnetization for the water while preserving a generally longitudinal magnetization to the at least one molecular species. The second radiofrequency pulse sequence being selected so as to suppress transverse and longitudinal magnetization for both the water and the at least one molecular species. | 2009-07-02 |
| 20090167304 | APPARATUS AND METHOD FOR VARYING MAGNETIC FIELD STRENGTH IN MAGNETIC RESONANCE MEASUREMENTS - Apparatus and method for varying field strength in a magnetic resonance system while keeping a relatively uniform magnetic field distribution. In an embodiment, a two-pole, generally u-shaped magnet assembly generates a static and uniform magnetic field. The magnet assembly includes two facing magnet poles separated by an air gap. Holes may be formed with the magnet poles. The field control rods may be placed at a pre-determined distance into these holes and symmetrically or asymmetrically moved across each magnet poles in a controlled manner to change the magnetic field strength while keeping the uniform magnetic field distribution. Maximum magnetic field strength may occur when the rods are removed. Minimum magnetic field strength may occur when the rods are fully inserted. | 2009-07-02 |
| 20090167305 | MRI test fixture - In one example, a magnetic resonance imaging (“MRI”) system comprises a magnetic resonance imaging assembly defining a gap region, a transmitting coil proximate the gap region, and at least one test coil separate from the transmitting coil. The at least one coil is mechanically coupled to the assembly during imaging and the at least one test coil is selectively electrically coupled to the assembly to collect test data. The at least one coil may be coupled to a test fixture coupled to the assembly. The test fixture may be deployable from a first position to a second position for collection of test data. The at least one coil may comprise a first test coil and a second test coil. Methods are also disclosed. | 2009-07-02 |
| 20090167306 | FOLDED GRADIENT TERMINAL BOARD END CONNECTOR - A folded gradient terminal board end connector includes a multi-layer terminal connection board having a plurality of connection paths and vias configured to provide intercrossing between a plurality of folded gradient coils and further to provide symmetry between the plurality of folded gradient coils without spatial interference between folded portions of the plurality of folded gradient coils to optimize the folded gradient coil efficiency. | 2009-07-02 |
| 20090167307 | FERROMAGNETIC DETECTION ENHANCER - An apparatus for increasing the ability to detect ferromagnetic objects by increasing the magnetization of the objects. The apparatus includes at least one coil to generate a magnetic field positioned in the area of the object to be detected. The apparatus includes an electrical energy storage capacitor bank capable of quickly releasing stored energy. The apparatus includes a high speed, high current electronic switch capable of quickly transferring the stored energy from the capacitor bank to the coil thereby producing in the coil a short duration, single polarity magnetic field pulse. The apparatus includes a sample and hold circuit capable of acquiring magnetic field sensor data during periods when the pulsed magnetic field is not present. The apparatus includes a microprocessor controller to control timing and sequence of the magnetic pulse generation and the sensor data sample and hold process. The apparatus may be for portal handheld or head mounted applications. | 2009-07-02 |
| 20090167308 | METHOD AND SYSTEM FOR MONITORING AN UNDERGROUND ELECTRIC CABLE - In a method and system for monitoring an underground cable in a site of interest, multiple samples of magnetic field data and corresponding location data are collected periodically over a sampling period of extended time. The magnetic field data samples and corresponding location data are processed to determine respective topologies of one or more current-carrying conductors in the site and for each of the conductors respective magnetic field data relating to each sampled point are integrated with respect to a predetermined parameter of the respective conductor so as compute an integrated contribution of each sampled span along the respective conductor. The data relating to different conductors in the site are output in a manner that allows determination of a conductor for which the parameter changes during the sampling period. | 2009-07-02 |
| 20090167309 | Method of and Apparatus for Measuring Tensor Resistivity - An induction or propagation apparatus for performing measuring the tensor resistivity of a sample of matter includes a non-conductive, generally cylindrical tubular member adapted to receive the matter therein, a triaxial transmitter, at least one triaxial receiver, and an electronic module. The electronic module is adapted to energize the triaxial transmitter, control acquisition of signals by the at least one triaxial receiver, and perform anisotropic measurements and analysis. The triaxial transmitter and the at least one triaxial receiver are disposed on the generally cylindrical tubular member in axial spaced relationship. | 2009-07-02 |
| 20090167310 | CHARACTERIZATION OF FORMATIONS USING ELECTROKINETIC MEASUREMENTS - A method for characterization of a formation that includes inducing fluid motion in a formation while making electronic measurements. | 2009-07-02 |
| 20090167311 | Adaptive Array Wireless Communication Apparatus and Method of Same - An adaptive array wireless communication apparatus able to suitably select antenna elements, small in amount of processing, fast in convergence speed, and suitable for transmission/reception, and a method of the same, which controls the directionalities of array antenna elements based on array weights, controls an antenna element selecting unit 23 so that the antenna elements are intermittently determined, and adjusts a period of determination of the antenna elements based on information of the antenna elements determined at a controlling unit 26. | 2009-07-02 |
| 20090167312 | SHORT CIRCUIT DETECTION FOR BATTERIES - A method and apparatus for short circuit detection for batteries. Some embodiments of a method include receiving a battery pack in a system, where the battery pack is rechargeable and includes multiple battery cell blocks, each cell block including one or more battery cells. The voltages of the plurality of cell blocks are monitored. Upon shutting down the system, the voltages of the plurality of cell blocks are logged to generate a set of logged voltage values. Upon restarting the system, the current voltage values of the cell blocks are measured. A determination whether any of the battery cells of the battery pack has developed a short circuit is made based at least in part on a comparison of the current voltage values with the set of the logged voltage values. | 2009-07-02 |
| 20090167313 | ELECTROSTATIC DISCHARGE EVENT AND TRANSIENT SIGNAL DETECTION AND MEASUREMENT DEVICE AND METHOD - An electrostatic discharge (ESD) event and transient signal detection and measurement device and method are described. The device and method are able to distinguish between an ESD event and other non-ESD events. | 2009-07-02 |
| 20090167314 | Method and Device for Detecting Ground Faults in a Supply Cable - A method for detecting a ground fault of a multi-phase energy supply cable carrying alternating current includes determining an average potential of the energy supply cable, entering the average potential or a variable derived therefrom into an evaluation unit, and comparing the average potential or the variable derived from the average potential with a threshold value in the evaluation unit. Ground faults are detected reliably and less expensively by presuming a ground fault if the comparison indicates that the value of the average potential or the variable derived therefrom has fallen below the threshold. | 2009-07-02 |
| 20090167315 | High voltage cable testing method - A method of testing a cabling system is disclosed. The method may include discharging an input filter capacitor associated with an accessory component, charging an accessory bus capacitor to a desired voltage level, and connecting the accessory bus capacitor to the input filter capacitor. The method may also include continuously monitoring a voltage waveform associated with the accessory bus capacitor. The method may further include determining a difference between the voltage waveform and a nominal voltage profile, and detecting a fault if the difference is greater than a threshold value. | 2009-07-02 |
| 20090167316 | MOTHERBOARD TESTING APPARATUS - A motherboard testing apparatus for automatically turning on or off a motherboard includes a pulse signal generating circuit for outputting a pulse signal, a first control circuit for outputting a first control signal to an I/O controller on the motherboard according to the pulse signal, and a second control circuit. The first control circuit outputs a low level first control signal when it receives a low level pulse signal, the I/O controller turns the motherboard on when it receives the low level first control signal. The second control circuit outputs a second control signal to the first control circuit which controls the motherboard to turn on again when the first control circuit receives the low level pulse signal a next time. | 2009-07-02 |
| 20090167317 | Apparatus And Method For Test, Characterization, And Calibration Of Microprocessor-Based And Digital Signal Processor-Based Integrated Circuit Digital Delay Lines - A circuit board with a processing unit and a delay line with a controllable number of delay elements fabricated thereon includes apparatus for testing and calibrating the delay line elements. In the test mode, a calibrated pulse is delayed by the delay line while determining the logic state of pulse at two times, the interval between the two times being the same as the pulse width. By adding delay elements, the period of the calibrated pulse as a function of number of delay elements can determine the delay of each delay element. In the calibration mode, the delay line is configured as a ring oscillator and the frequency of the ring oscillator as a function of number of delay elements provides the time delay for the individual elements. | 2009-07-02 |
| 20090167318 | VOLTAGE VARIANCE TESTER - An exemplary voltage variance tester includes a first to a third testing circuits each comprising an adjustable power source and an electrical switch; a first to a third signal generators providing a first to a third signals respectively; a connector having a first to a third terminals connected to the first to the third testing circuits respectively for receiving the adjustable power sources, a fourth to a sixth terminals connected to the first to the third signal generators for receiving the first to the third signals, and a seventh terminal; and a control circuit connected to the seventh terminal of the connector for receiving a power on signal to turn on the first to third electrical switch, wherein, voltage variances of the motherboard are tested by adjusting the first to the third adjustable power sources. | 2009-07-02 |
| 20090167319 | TEST APPARATUS FOR DETERMINING IF ADJACENT CONTACTS ARE SHORT-CIRCUITED AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES THAT INCLUDE SUCH TEST APPARATUS - A test apparatus includes a plurality of pairs of test contacts on a semiconductor substrate; a first test structure which includes a plurality of first test interconnection layers and a first body interconnection layer that is electrically connected to the first test interconnection layers, each of the first test interconnection layers being electrically connected to at least one test contact; and a second test structure which includes a plurality of second test interconnection layers and a second body interconnection layer that is electrically connected to the second test interconnection layers, each of the second test interconnection layers being electrically connected to at least one test contact. | 2009-07-02 |
| 20090167320 | Test method for a variable capacitance measuring system - A method for testing a variable capacitance measurement system including a fixed voltage source, a variable capacitance sensor, and a circuit to process information output by this sensor. The method connects an electrically controllable electronic simulation device to replace the variable capacitance sensor, models the electrophysical behaviour of the sensor, and tests the system. | 2009-07-02 |
| 20090167321 | Method and Apparatus for Determining an Interfering Field Strength in an Aircraft - The disclosed embodiments relates to a method and an apparatus for determining the interfering field strength in an aircraft and the impairment of an electric system in the aircraft including cables between the outer shell and the interior paneling of the fuselage for transmitting signals within the aircraft. | 2009-07-02 |
| 20090167322 | SYSTEMS AND METHOD FOR CLASSIFYING A SUBSTANCE - A method for classifying a substance is provided. The method includes transmitting an electromagnetic signal at the substance, measuring a portion of the electromagnetic signal reflected by the substance, determining a reflection coefficient of the substance using the measured portion of the electromagnetic signal, and outputting a classification of the substance based on the determined reflection coefficient. | 2009-07-02 |
| 20090167323 | Dynamic Range Recovery for Pulse-Modulated Measurements - A system composed of an RF input, a receiver system and, connected in series between the RF input and the receiver, an amplifier, a gate switch and a bandpass filter. The receiver system is operable to determine the characteristic of the DUT based on an RF input signal received from the DUT. The amplifier receives and amplifies the RF input signal to generate an amplified signal at a power level that exceeds the maximum input power of the receiver system. The bandpass filter is configured to select from the gated signal a selected signal comprising a wanted frequency component. The band-pass filter has a rise-time in relation to the ON time of the gate switch such that the selected signal has a maximum power that does not exceed the maximum input power of the receiver system. In another embodiment, the system additionally comprises a mixer interposed between the RF input and the amplifier. | 2009-07-02 |
| 20090167324 | ELECTRIC POTENTIAL SENSOR - The invention provides an electric potential sensor, comprising at least one detection electrode arranged for capacitive coupling with a sample under test and for generating a measurement signal, and a sensor amplifier adapted to receive the measurement signal as input and to supply an amplified detection signal as output. Input impedance enhancing means provide a high input impedance to the sensor amplifier for increasing the sensitivity of the electrode to reduced electric potentials, and feedback means apply a coherent feedback signal to the input of the sensor amplifier for enhancing the signal to noise ratio of the sensor. | 2009-07-02 |
| 20090167325 | PULSED CAPACITANCE MEASURING CIRCUITS AND METHODS - Capacitance measuring circuits and methods apply electrical charge pulses to ramp voltage signals across a voltage threshold, and use the number of pulses to determine the capacitance. Capacitances at multiple locations can be measured by storing a pulse counter value in a register associated with each voltage signal channel as that voltage signal crosses the threshold. Effects of electrode resistance on the capacitance measurements can be mitigated by using charge pulses to ramp the voltage signals and waiting for signal quiescence between pulses. | 2009-07-02 |
| 20090167326 | TIME-SLOPED CAPACITANCE MEASURING CIRCUITS AND METHODS - Time-sloped capacitance measuring circuits use the time to ramp voltage signals between reference levels to determine an unknown capacitance, where the ramping time is determined by the cumulative whole number of clock cycles counted during voltage signal ramping over multiple ramp cycles. Measurement resolution can be improved by adjusting a starting voltage level for subsequent voltage signal ramps by an amount that compensates for incremental voltage ramping during a terminal clock cycle of a previous voltage signal ramp. | 2009-07-02 |
| 20090167327 | THERMAL EFFECT AND OFF-CENTER LOAD COMPENSATION OF A SENSOR - A method and system of thermal effect and off-center load compensation of a sensor are disclosed. In one embodiment, a sensor includes a first conductive surface and a second conductive surface substantially parallel to the first conductive surface, a processing and communication zone of the first conductive surface and the second conductive surface having circuitry to enable communication with an external system (e.g., using a Universal Serial Bus (USB) interface) and a sensing area having partially a ceramic substrate surrounding a sensor surface and a reference surface of the first conductive surface and the second conductive surface. The sensor may include a set of electrical leads that enable the sensing area to communicate with the processing and communication zone and with external devices, and a guard ring surrounding the first conductive surface and the second conductive surface to minimize an effect of stray capacitance. | 2009-07-02 |
| 20090167328 | FLUID MEASURING APPARATUS - The invention provides a fluid measuring apparatus, which includes a collector, a sensing circuit, and an electrochromic device electrically connected to the sensing circuit. When the concentration of a fluid flowing through the collector and between the sensing circuit varies, the color of the electrochromic device changes accordingly. Further, the electrochromic device includes an electrochromic material, and the sensing circuit includes a first electrode and a second electrode, wherein the first and the second electrodes are disposed in the collector and the electrochromic material is disposed on the first electrode. When the concentration of an electrolytic solution flowing between the first electrode and the second electrode varies, the color of the electrochromic material changes accordingly. | 2009-07-02 |
| 20090167329 | METHODS AND APPARATUS FOR OPEN LAMP DETECTION IN ELECTRONIC CIRCUITS - Methods and apparatus for open lamp detection in electronic circuits are disclosed. An example apparatus to perform open circuit detection associated with an electrical component included in a device disclosed herein comprises a sampling circuit to attempt to pull a sampling current through the electrical component during initialization of the device, a comparator to compare a result produced by the sampling circuit to a reference value, and a timing circuit to cause the sampling circuit to attempt to pull the sampling current through the electrical component and to cause an output of the comparator to be stored after the comparator has compared the result produced by the sampling circuit to the reference value. | 2009-07-02 |
| 20090167330 | Systems and arrangements for sensing current with a low loss sense element - In some embodiments, the arrangement includes a sense element to convey a current from a source to a load and a compensation element located proximate to the sense element. The compensation element has a resistance that changes proportional to a change in temperature of the sense element. In several embodiments, the arrangement further includes an operational amplifier having a first input connected to the sense element, a second input connected to the compensation element and an output that provides an output signal that biases a current through the compensation element in response to a voltage across the sense element. In such embodiments, the bias current provides an output signal proportional to the conveyed current and the compensation element provides temperature compensation for the output signal. Other embodiments are also disclosed. | 2009-07-02 |
| 20090167331 | Testing apparatus and method for detecting a contact deficiency of an electrically conductive connection - A testing apparatus and a method for detecting a contact deficiency of an electrically conductive connection. The testing apparatus comprises a measuring chamber, in which several system elements of the connection that are connected in an electrically conductive fashion are positioned, a heat radiator that is supplied with energy and the transferred thermal radiation of which is emitted into the measuring chamber and directed toward the region of the system elements that, after having been heated, generate a thermal field of the insulated and the metallic system components of these connected system elements, a thermal (image) acquisition unit for optically capturing the generated thermal field and for realizing a signal conversion into a thermal image of the connected system elements, and a thermal (image) reproduction unit for the visual reproduction of the converted thermal image. | 2009-07-02 |
| 20090167332 | ELECTRICAL PROBE - Methods, devices, and systems for probing electrical circuits without loading the circuits are described herein. One embodiment of an electrical probe includes a coaxial cable having an inner conductor and an outer conductor, an extension portion of the inner conductor extending beyond the outer conductor at a probe end of the cable. The electrical probe includes a conductive whisker having a first portion separated from and extending a distance along the extension portion such that the first portion and the extension portion form a first capacitor and a second portion having a probe tip for receiving an input test signal from a circuit node under test. | 2009-07-02 |
| 20090167333 | Wafer level testing - A wafer comprises a kerf region and a test chip. The kerf is a region in a wafer designated to be destroyed by chip dicing. The test chip is located within the kerf region and is configured to provide parametric data for a wafer fabrication process of a head. The test chip comprises a shield portion of a first shield layer electrically coupled to an element, a first pad within a second shield layer electrically coupled to the element, and a second pad within the second shield layer electrically coupled to the shield portion. | 2009-07-02 |
| 20090167334 | Controlled Impedance Structures for High Density Interconnections - An interconnection structure suitable for use as an IC package, probe head or other electrical termination of high density where uninterrupted controlled impedance is desired is described. | 2009-07-02 |
| 20090167335 | Probe Card - Provided is a probe card capable of surely bringing probes into contact with a contact object regardless of a temperature environment of a test. To achieve the object, the probe card includes a plurality of probes that are made of a conductive material and come into contact with electrode pads of a semiconductor wafer to input or output an electric signal; a probe head that houses and holds the probes; a substrate that has a wiring pattern corresponding to the circuitry; and a space transformer that is stacked on the probe head, changes a space of the wiring pattern of the substrate and thus relays wires, and has electrode pads provided on a surface on a side opposed to the probe head in association with the relayed wires. Both ends of the probes come into contact with portions near the centers of the electrodes pads of the semiconductor wafer and the space transformer under an environment having an average temperature of a lowest temperature and a highest temperature in testing the semiconductor wafer. | 2009-07-02 |
| 20090167336 | METHOD AND APPARATUS FOR DYNAMIC CHARACTERIZATION OF RELIABILITY WEAROUT MECHANISMS - A method and apparatus for dynamic characterization of reliability wearout mechanisms is disclosed. The system comprises an integrated circuit incorporating a device under test to be measured, structure for inputting a waveform to the device under test for a first predetermined time interval, structure for disabling the inputting of the waveform to the device under test, structure for measuring one or more fundamental parameters of the device under test after a second predetermined time interval, and structure for calculating an aging estimate of the device under test without the influence of recovery effect based on the one or more measured fundamental parameters. The time between stressing and measurement is precisely controlled, providing for repeatable experiments, and serves to minimize measurement error caused by recovery effects. | 2009-07-02 |
| 20090167337 | Semiconductor integrated circuit device which has first chip and second chip accessed via the first chip and test method thereof - A semiconductor integrated circuit device includes a first chip including an internal circuit, and a second chip capable of being accessed only via the first chip, and a test processor circuit electrically connected internally via the first chip, for accessing the second chip from an external terminal and testing the second chip, and a test circuit where an input/output buffer is installed for signals for accessing the second chip within the test processor circuit, and a bypass line installed for transferring signals from the first chip to the second chip and avoiding the input/output buffer within the test processor circuit, and a switch which switches between signal transfer path via the input/output buffer, and a signal transfer path via the bypass line. | 2009-07-02 |
| 20090167338 | TEST PATTERN FOR ANALYZING CAPACITANCE OF INTERCONNECTION LINE - Disclosed is a test pattern for analyzing capacitances of interconnection lines that accounts for parasitic capacitance components. The test pattern includes a first metal line having a comb-type structure including a plurality of tines, a second metal line having a comb-type structure including a plurality of tines engaged with the tines of the first metal line, a first probe pad switchably connected to the first metal line, and a second probe pad switchably connected to the second metal line. Switchable connections between the first metal line and the first probe pad and between the second metal line and the second probe pad may be provided by first and second switch terminals, respectively. The test pattern enables a capacitance measurement that accounts for parasitic capacitance components of pads and portions of interconnection lines leading from the pads, which otherwise interfere with accurate measurement of capacitances of the interconnection lines. | 2009-07-02 |
| 20090167339 | Contactless Testing of Wafer Characteristics - Systems and methods are provided for contactless testing of a wafer containing at least one integrated circuit. A test component responds to a supply voltage to indicate at least one property of the wafer. A voltage source wirelessly receives power from an external source and produces the supply voltage. A reference generator generates a reference voltage, having a known magnitude, from the supply voltage. A voltage evaluation component modifies the response of the test component as to represent a magnitude of the supply voltage. | 2009-07-02 |
| 20090167340 | SEMICONDUCTOR CHIP TEST APPARATUS AND TESTING METHOD - A semiconductor chip test apparatus includes a plurality of power supply units, each supplying power to a semiconductor chip having a power input terminal, and a tester configured to measure an output current of at least one of the plurality of power supply units, and to generate a switching control signal when the measured output current is greater than a predetermined current. The semiconductor chip test apparatus also includes a plurality of relays each arranged between a common ground of the tester and a different ground of the semiconductor chip. Further, the semiconductor chip test apparatus includes a relay controller, such as a control bit generator, configured to selectively close one or more of the plurality of relays in response to the switching control signal from the tester. | 2009-07-02 |
| 20090167341 | SYSTEM AND METHOD FOR TESTING A LIQUID CRYSTAL PANEL - A method for testing a liquid crystal panel is provided. The method simulates an outside force endured by the liquid crystal panel when the liquid crystal panel is assembled as a finished product, so that unqualified liquid crystal panels can be detected before the finished product is put into use. | 2009-07-02 |
| 20090167342 | ANALOG PROCESSOR COMPRISING QUANTUM DEVICES - Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices. | 2009-07-02 |
| 20090167343 | MINIMIZING LEAKAGE IN LOGIC DESIGNS - Devices and methods are disclosed for logic gate devices to provide reduced leakage while improving performance. The device is configured for low leakage logic application where high threshold voltage devices are used to reduce leakage at the expense of reduced logic speed. Better performance is achieved than a high threshold voltage stack. | 2009-07-02 |
| 20090167344 | DATA OUTPUT DRIVING CIRCUIT OF SEMICONDUCTOR APPARATUS - A data output driving circuit for a semiconductor apparatus can include a code multiplier configured to multiply a received first code by a multiplication factor determined in response to a control signal and generating a second code; a signal line configured to transmit the second code; and a plurality of data output drivers commonly connected to the signal line and changed in an impedance thereof in response to the second code. | 2009-07-02 |
| 20090167345 | Reading configuration data from internal storage node of configuration storage circuit - Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data. | 2009-07-02 |
| 20090167346 | RECONFIGURABLE CIRCUIT, CONFIGURATION METHOD AND PROGRAM - The present invention is intended to provide a reconfigurable circuit, a configuration method and a program capable of significantly shortening the configuration time without increasing the area of the chip of the circuit. The reconfigurable circuit equipped with a configuration chain having multiple serial connection registers, comprises first connecting means for connecting the registers inside a first serial connection register and the registers inside a second serial connection register in series, and second connecting means for connecting the registers inside the first serial connection register and the registers inside the second serial connection register in parallel, wherein duplication is made possible by using the second connecting means as bypasses. | 2009-07-02 |
| 20090167347 | USING PROGRAMMABLE LATCH TO IMPLEMENT LOGIC - A logic circuit is disclosed that includes a latch for enhancing the circuit logic capacity. The circuit includes a logic block comprising a plurality of logic inputs and at least one logic output, the logic output generating a logic function of the plurality of logic inputs; a first latch input to provide a data state to store in the latch is coupled to said at least one output of logic block; a global latch input to change the stored data state of the latch couple by a programmable method to a local input; and a latch output, wherein when the local input is coupled to the global latch input, the latch output generates logic function of the logic output and the local input. | 2009-07-02 |
| 20090167348 | PROGRAMMABLE LATCH BASED MULTIPLIER - A programmable logic circuit is disclosed that includes a latch for enhancing the circuit logic capacity. In a multiplier configuration, the circuit comprises a logic block; and a latch having a latch output coupled to a logic block input, wherein the latch output computes an AND function of a first and second latch input. | 2009-07-02 |
| 20090167349 | PROGRAMMABLE LOGIC BASED LATCHES AND SHIFT REGISTERS - A latch is described, comprising: a first programmable logic element (LE); and a second programmable logic element (LE); and an output of the first LE adapted to directly couple to a first input of the second LE; and an output of the second LE coupled to a first input of the first LE; and a first common input coupled to a second input of the first and second LE; and a second common input coupled to a third input of the first and second LE. | 2009-07-02 |
| 20090167350 | PROGRAMMABLE LOGIC BASED LATCHES AND SHIFT REGISTERS - Disclosed is a programmable logic device adapted to implement a shift register, the device comprising: a logic block comprised of: a latch having an input; and a logic element having an output capable of coupling to an adjacent logic block and the latch input, wherein the output is coupled to the adjacent logic block and decoupled from the latch input; and an interconnect coupled to the latch and adapted to transmit the latch output to an input of the logic element. In the device, the logic element is configured as a route through for the latch output to couple to the adjacent logic block. | 2009-07-02 |
| 20090167351 | CO-PROCESSOR HAVING CONFIGURABLE LOGIC BLOCKS - A co-processor system is provided that includes an array of configurable logic blocks (CLBs). Each CLB including a plurality of look-up tables and a plurality of adders. Each CLB may be dynamically reconfigurable to perform a plurality of logical functions. | 2009-07-02 |
| 20090167352 | Field programmable gate arrays using resistivity sensitive memories - Field programmable gate arrays using resistivity-sensitive memories are described, including a programmable cell comprising a configurable logic, a memory connected to the configurable logic to provide functions for the configurable logic, the memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element, an input/output logic connected to the configurable logic and the memory to communicate with other cells. The memory elements may be two-terminal resistivity-sensitive memory elements that store data in the absence of power. The two-terminal memory elements may store data as plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory element and data can be written to the two-terminal memory elements by applying a write voltage across the terminals. The memory can be vertically configured in one or more memory planes that are vertically stacked upon each other and are positioned above a logic plane. | 2009-07-02 |
| 20090167353 | State machines using resistivity-sensitive memories - State machines using resistivity-sensitive memory elements are disclosed. The state machine includes a next state logic comprising a non-volatile memory including a resistivity-sensitive memory element and receiving an input, a state storage device connected to the next state logic including a connection to provide a state of the state machine to the next state logic, and an output connect to the state register to output the state of the state machine. The resistivity-sensitive memory elements may be two-terminal resistivity-sensitive memory elements. The two-terminal resistivity-sensitive memory elements may store data as a plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory elements, and new data can be written by applying a write voltage across the terminals. The two-terminal resistivity-sensitive memory elements retain stored data in the absence of power and may be configured into a two-terminal cross-point memory array. | 2009-07-02 |
| 20090167354 | Non-Sequentially Configurable IC - Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes at least fifty configurable circuits arranged in an array having a plurality of rows and a plurality of columns. Each configurable circuit for configurably performing a set of operations. At least a first configurable circuit reconfigures at a first reconfiguration rate. The first configurable circuit performs a different operation each time the first configurable circuit is reconfigured. The reconfiguration of the first configurable circuit does not follow any sequential progression through the set of operations of the first configurable circuit. | 2009-07-02 |
| 20090167355 | High performance pulsed buffer - An integrated circuit ( | 2009-07-02 |
| 20090167356 | MONOLITHICALLY INTEGRATED MULTIPLEXER-TRANSLATOR-DEMULTIPLEXER CIRCUIT AND METHOD - A monolithically integrated multiplexer-translator-demultiplexer and a method for multiplexing and translating an electrical signal or demultiplexing and translating an electrical signal. A multiplexer and a demultiplexer are monolithically integrated with a translator. Circuits that operate at different voltage supply levels from each other may be coupled to the multiplexer and a circuit that operates at a different voltage supply level from the circuits coupled to the multiplexer or that operates at the same voltage supply level as at least one of the circuits coupled to the multiplexer is coupled to the demultiplexer. The monolithically integrated multiplexer-translator-demultiplexer selects a signal from one of the circuits coupled to the multiplexer, translates its voltage level and provides the translated signal level as an output signal. Alternatively, the monolithically integrated multiplexer-translator-demultiplexer creates demultiplexed signals from an electrical signal and translates the voltage levels of the demultiplexed signals. | 2009-07-02 |
| 20090167357 | EXTENDING DRIVE CAPABILITY IN INTEGRATED CIRCUITS UTILIZING PROGRAMMABLE-VOLTAGE OUTPUT CIRCUITS - An integrated circuit (IC) includes an output driver circuit portion that is electrically configurable, via a configuration input, to operate in either a first mode or a second mode corresponding to an indication of a condition of the IC, such as a supply voltage indication, the first mode and the second mode having different drive characteristics. A configuration interface circuit portion as part of the improved IC is adapted to selectively override the configuration input to configure operation of the output driver circuit portion in either the first mode or the second mode based on a drive strength control input, regardless of the condition of the IC. | 2009-07-02 |
| 20090167358 | FULLY INTERRUPTIBLE DOMINO LATCH - A domino latch is provided that comprises a forward path circuit and a feedback path circuit. The feedback path includes a plurality of keeper transistors, an inverter, and at least one interrupt transistor to cut off the feedback path circuit and prevent signal contention on the output node between the feedback path circuit and the forward path circuit. | 2009-07-02 |
| 20090167359 | CURRENT MODE LOGIC CIRCUIT AND CONTROL APPARATUS THEREFOR - Embodiments relate to a current mode logic circuit, which may include a first NMOS transistor whose drain may be coupled to a first load and whose gate may be coupled to an input terminal through which data may be inputted, a second NMOS transistor whose drain may be coupled to a second load and gate may be coupled to an input terminal through which a negative reference voltage may be applied, and a third NMOS transistor whose drain may be coupled to a source of each of the first and the second NMOS transistors and whose gate may be coupled to an input terminal through which a reference voltage may be applied. Bulk biases of the first, second, and third NMOS transistors may be independently adjusted to control at least one of a leakage current and an operation speed of the NMOS transistors. | 2009-07-02 |
| 20090167360 | Apparatus, circuit and method of monitoring performance - An apparatus includes a first sequential circuit which captures an input signal according to a first clock signal, a second sequential circuit which captures the input signal according to a second clock signal and outputs the captured input signal to a logic circuit, the second clock signal being modulated so that a period of the second clock signal is shorter than that of the first clock signal, a third sequential circuit which captures an output signal of the logic circuit according to the second clock signal, and a verification circuit which verifies whether an output signal of the first sequential circuit and an output signal of the third sequential circuit match with each other. | 2009-07-02 |
| 20090167361 | HIGH-SPEED AMPLITUDE DETECTOR WITH A DIGITAL OUTPUT - An amplitude detection circuit using a sinusoidal input signal inputs to produce a digital output (a one or zero) is described. The circuit uses an input field effect transistor (FET) with a gate load coupled to a gate of the input FET. A drain load may be coupled to a drain of the input FET. A source load may be coupled to a source of the input FET. A controllable variable current generator provides a current to the source of the input FET, biasing the source of the input FET to a reference voltage. An input signal conductor may be coupled to the gate of the input FET. Other embodiments are described. | 2009-07-02 |
| 20090167362 | COMPARATOR - A comparator is provided. In a first period, input terminal of the pre-amplifier is coupled to a first voltage. A first terminal of the first capacitor is coupled to the second input terminal of the pre-amplifier. A second terminal of the first capacitor is coupled to the first input voltage in the first period, and is coupled to the second input voltage in the second period. The second capacitor is coupled between the output terminal of the pre-amplifier and an input terminal of the gain unit. The switch is coupled between the input terminal and an output terminal of the gain unit. An input terminal of the latch is coupled to the output terminal of the gain unit. The latch outputs a comparison result. | 2009-07-02 |
| 20090167363 | REDUCTION OF SIGNAL SKEW - Skew is reduced by extracting the AC component of an input signal and superimposing it on a common reference voltage to produce a resulting voltage. The resulting voltage is provided as an input to a comparator, which compares it to the reference voltage to provide a final output. Thus, all signals fed to a system, in accordance with an embodiment, are referenced at the same DC level and hence, skew is reduced. | 2009-07-02 |
| 20090167364 | CURRENT SAMPLING METHOD AND CIRCUIT - A current sampling circuit including a current sampling transistor, a capacitor arrangement between the gate and source of the current sampling transistor and an amplifier provided in a feedback loop between the gate and source of the current sampling transistor. A switch controls the circuit to sample a gate-source voltage corresponding to a current being sampled onto the capacitor arrangement. The capacitor arrangement comprises a first capacitor circuit for sampling a gate source voltage in a first sampling phase and a second capacitor circuit, with the first and second capacitor circuits arranged for together sampling the gate source voltage in a second sampling phase. The operating point of the amplifier is shifted between the first and second phases based on the gate source voltage sampled in the first sampling phase. | 2009-07-02 |
| 20090167365 | METHOD FOR REGULATING A VOLTAGE AND CIRCUIT THEREFOR - A regulator circuit and a method for regulating an output voltage. The regulator circuit includes an undervoltage protection stage capable of operating in a plurality of operating modes. In one mode, the undervoltage protection stage compensates for a low undervoltage appearing in the output voltage and in another mode it compensates for a large undervoltage appearing in the output voltage. When the output voltage has a low undervoltage, a portion of the current from a current source is routed to a feedback network to balance the input voltages of the undervoltage protection stage and to place the voltage regulator in a steady state operating mode. When the output voltage has a large undervoltage, the undervoltage protection stage turns on a current sourcing transistor that cooperates with the current from the current source to quickly charge a compensation capacitor and increase the power appearing at the output of the voltage regulator. | 2009-07-02 |
| 20090167366 | Audio clock regenerator with precise parameter transformer - It is difficult to implement a conventional phase lock loop circuit in a sink device within an HDMI system because the low frequency input causes the conventional phase lock loop circuit to absorb unnecessary noise during a long waiting period. Therefore, the present invention provides a low jitter clock regenerator comprises: an input clock; a divider to divide said input clock into a slower clock; a phase lock loop circuit to regenerate said slower clock to a reference clock; and a parameter transformer to tune said divider and said phase lock loop circuit to increase the adjustment speed of said phase lock loop circuit. The present invention also provides a method to reorganize parameters in order to create new parameters which are better suitable for a clock recovery circuit in a sink device within an HDMI system. | 2009-07-02 |
| 20090167367 | Frequency Synthesizer - An object of the present invention provides a frequency synthesizer having a broad frequency entraining range which can finely set a frequency over a broad band by a novel principle. | 2009-07-02 |
| 20090167368 | PRE-DRIVER CIRCUIT HAVING A POST-BOOST CIRCUIT - A pre-driver is provided that includes a pre-boost circuit and a post-boost circuit. The post-boost circuit may include a pulse generator circuit to provide a feedback to be used to control an output of the pre-driver. | 2009-07-02 |
| 20090167369 | LVDS OUTPUT DRIVER - An output driver is disclosed. The output driver has a pair of differential outputs coupled to a first supply voltage via a pair of load devices and comprises a current source, a pair of low voltage transistors, a pair of high voltage transistors, and a resistor. The current source has one end coupled to a second supply voltage. Each of the low voltage transistors has a first terminal coupled to the other end of the current source, a second terminal receiving a low voltage signal, and a third terminal. Each of the high voltage transistors has a first terminal coupled to the third terminal of a corresponding one of the low voltage transistors, a second terminal coupled to a bias voltage and a third terminal coupled to the output. The resistor is connected between the third terminals of the high voltage transistors. | 2009-07-02 |
| 20090167370 | Output Buffer - An output buffer includes at least a first and a second stage, wherein each stage is formed by respective first transistors and second transistors coupled in series with each other between a first and a second voltage reference. The coupled first and second transistors have a common conduction terminal connected to an output terminal of the output buffer. An input terminal of the buffer is connected to control terminals of the transistors of the first stage through a first open loop driving circuit. A second feedback driving circuit is connected between the input terminal and the control terminals of the transistors of the second stage. The second feedback driving circuit includes a current detector operating to detect a maximum in the value of the current drawn by and supplied to the output buffer. A comparison block, having a threshold value, detects current in excess of the threshold value and processes information coming from the current detector to regulate an output impedance value of the output buffer. The current detector includes a duplicated structure which replicates a portion of the buffer circuit without altering the performances of the buffer itself. | 2009-07-02 |
| 20090167371 | CAPACITIVE LOAD DRIVING CIRCUIT - It is aimed to reduce the area of an output circuit in a capacitive load driving circuit capable of high voltage output, such as a PDP scan driver for driving a plasma display panel. To achieve this, there are provided an arbitrary number of N-type MOS transistors | 2009-07-02 |
| 20090167372 | Automatic Adjustment Circuit, and Filter Circuit - An automatic adjustment circuit comprises a replica ( | 2009-07-02 |
| 20090167373 | MULTI-PHASE FREQUENCY DIVIDER - A multi-phase frequency divider comprises dynamic inverters connected in a ring and the intermediate nodes around the ring are stabilized with cross-coupled latches. Clock input pulses enable each dynamic inverter's output and will force a corresponding change-of-state in the cross-coupled latches. The multi-phase output is presented in parallel on all the latches. | 2009-07-02 |
| 20090167374 | Jitter-Free Divider - A system and method are provided for jitter-free fractional division. The method accepts a first plurality of first signal phases, each phase having a first frequency. To make the division jitter-free, a phase is selected subsequent to deselecting a previous phase selection. The selected phase is divided by the integer N, supplying a second signal with a second frequency. Using the second signal as a clock, a first plurality of counts is triggered in series, and the counts are used to select a corresponding phase. The first signal may separate neighboring phases by 90 degrees. Then, for (N+0.25), a first count triggers a second count and selects the first phase, the second count triggers a third count and selects the second phase, the third count triggers a fourth count and selects the third phase, and the fourth count trigger the first count and selects the fourth phase. | 2009-07-02 |
| 20090167375 | Signal Generation System - A signal generation system maintains a phase relationship between output signals of first and second signal generators even when the sampling clock frequency is changed. The signal generators are coupled via a communication means including a dedicated cable where the delay amount of the communication means is known and fixed. The first signal generator provides sampling clock, sequence clock and trigger/event signals to the second signal generator and CPUs of the generators share information via the cable. When the frequency of the sampling clock is changed, the CPU of the first or second signal generator calculates the clock number of the frequency changed sampling clock equivalent to the delay amount of the communication means. A delay circuit of the first signal generator | 2009-07-02 |
| 20090167376 | SYSTEM AND METHOD FOR PULSE EDGE SYNCHRONIZATION - A system and method for pulse edge synchronization, According to an embodiment, a first series of PWM signals that may drive a first device wherein each pulse in this series has a rising edge and a falling edge. The system and method further includes a second series of PWM signals that may drive a second device wherein each pulse in the second series of pulses also has a rising edge and a falling edge. These series of pulses are then synchronized such that each rising edge in the first series occurs simultaneous to a falling edge in the second series and vice versa. Such a system and method reduces the level of acoustic noise generated between the two motors. Further, synchronizing the rising and falling edges of the PWM pulses reduces and often eliminates stray EMI. | 2009-07-02 |
| 20090167377 | Semiconductor storage device and resetting method for a semiconductor storage device - An exemplary aspect of an embodiment of the present invention is a semiconductor storage device including a power-on reset generator that outputs a first reset signal in accordance with a level of a power supply voltage, a command decoder that moves to a mode set state in accordance with input of an external control pin and outputs mode set information in accordance with a command input from an address pin, an MRS controller that outputs a mode reset signal (MRSPON signal) in accordance with the mode set information, and a reset circuit that outputs a second reset signal initializing each circuit of an operation control section in accordance with the mode reset signal and the first reset signal. | 2009-07-02 |
| 20090167378 | Method and System for Providing a Power-On Reset Pulse - Provided are a method and system for providing a power-on reset pulse. The system includes a level detector configured to receive an input signal and produce, at least indirectly, a reset signal when the input signal reaches a predetermined level. The system also includes a counter having counting characteristics and configured to receive the reset signal and a clock signal. The counter produces a delayed signal in accordance with the counting characteristics, the clock signal, and the received reset signal. | 2009-07-02 |
| 20090167379 | Method and Apparatus for Digital VCDL Startup - Methods and apparatus are provided fox improved startup of a voltage controlled delay loop that has an injection clock and a return clock. A control signal is determined for a plurality of delay elements in a voltage controlled delay loop by obtaining a histogram count of a number of occurrences of at least one predefined logic value for a plurality of delay settings of the voltage controlled delay loop; determining a histogram count that approximately corresponds to an alignment of at least one edge in the injection and return clocks; and determining the control signal based on the determined histogram count that approximately corresponds to the alignment. The control signal can be, for example, a delay control current or a delay control voltage. The voltage controlled delay loop can be started using the determined control signal. The histogram count can be obtained for a plurality of PVT combinations and the control signal can then be determined for each PVT combination. The determined control signal can optionally be stored in a table for each of the plurality of PVT combinations | 2009-07-02 |
| 20090167380 | System and method for reducing EME emissions in digital desynchronized circuits - A system includes first and second synchronous circuits and an asynchronous circuit configured to receive input from the first synchronous circuit and to send output to the second synchronous circuit. First and second variable clock generators are configured to drive the first and second synchronous circuit. A delay circuit is configured in a pathway from the first variable clock generator to the second variable clock generator, the delay circuit being configured to add a delay to the pathway based upon a processing time or an expected processing time of the asynchronous circuit. The delay circuit is further configured to induce additional uneven delay into the pathway. The additional uneven delay disperses local current absorption, thereby decreasing overall electro magnetic emissions of the system. | 2009-07-02 |
| 20090167381 | Time Measurement of Periodic Signals - A system for measuring a time between a first periodic signal and a second periodic signal. The second signal has a frequency higher than a frequency of the first signal. According to one embodiment, the system includes an electronic circuit for determining an approximation of the time based on a period of the second signal and for determining an adjustment to the approximation based on the second signal and a third signal corresponding to the second signal and aligned with the first signal. The length of the adjustment is less than the period of the second signal. | 2009-07-02 |
| 20090167382 | PLL Apparatus - It is an object of the present invention to provide a PLL apparatus realizing extremely high frequency stability. | 2009-07-02 |
| 20090167383 | Method for Generating a Clock Frequency - A method and apparatus generates a clock frequency dependent on a reference clock signal and has a phase locked loop configuration. A multiplexer is connected into the transmission path of the respective incoming input signal, to which the corresponding input signal is fed directly, on the one hand, and in delayed fashion, on the other hand. The common clock signal used is a system clock signal, independent of the reference clock signal and the local clock signal and whose frequency is higher by a factor of at least “5” than the frequency of the reference clock signal and of the local clock signal, respectively. The temporal spacing between the edges of the undelayed clock signal, and of the delayed clock signal, is set such that it is greater than the temporal spacing of the sampling pulses of the phase detector that are predetermined by the system clock signal. | 2009-07-02 |
| 20090167384 | Dividing circuit and phase locked loop using the same - The PLL includes a selection signal generator configured to output a selection signal varying in response to a first clock signal, and a first dividing circuit configured to divide an externally input reference clock signal by a division ratio and output a first division signal. The first dividing circuit selects one of a plurality of edges of the reference clock signal applied for at least one cycle of the first division signal in response to the selection signal, and synchronizes and generates the first division signal on the basis of the selected edge of the reference clock signal. A second dividing circuit is configured to receive an output clock signal, divide the output clock signal by a division ratio, and output a second division signal. The second dividing circuit selects one of the edges of the reference clock signal applied for at least one cycle of the second division signal in response to the selection signal, and synchronizes and generates the second division signal on the basis of the selected edge of the reference clock signal. A synchronous signal output portion is configured to detect a phase difference between the first and second division signals, generate a control voltage corresponding to the phase difference, and output the output clock signal having a frequency corresponding to the control voltage. | 2009-07-02 |
| 20090167385 | PHASE LOCKED LOOP DEVICE AND CONTROL METHOD THEREOF - A phase locked loop device is provided. The phase locked loop device includes a phase/frequency detector, a charge pump, a low pass filter, a voltage-controlled oscillator, and a control unit. The phase/frequency detector generates a compared signal corresponding to a phase difference between a reference clock signal and a feedback clock signal. The charge pump coupled to the phase/frequency detector generates a pump current according to the compared signal. The low pass filter coupled to the charge pump generates an operating voltage corresponding to the pump current. The voltage-controlled oscillator coupled to the low pass filter generates an output clock signal in response to the operating voltage. The control unit coupled to the low pass filter and the voltage-controlled oscillator constrains the operating voltage to a predetermined voltage level when the frequency of the output clock signal is out of a predetermined frequency range. | 2009-07-02 |
| 20090167386 | Charge pumping circuit, clock synchronization circuit having the charge pumping circuit, and method for operating the clock synchronization circuit - A charge pumping circuit includes a first charge pump configured to perform a charge pumping operation on an output terminal in response to a first pumping control signal, an auxiliary charge pumping controller configured to generate a second pumping control signal activated during a predetermined section of an activation period of the first pumping control signal and a second charge pump configured to perform a charge pumping operation on the output terminal in response to the second pumping control signal. | 2009-07-02 |
