| 27th week of 2009 patent applcation highlights part 16 |
| Patent application number | Title | Published |
|---|
| 20090166686 | Edge-Contacted Vertical Carbon Nanotube Transistor - A vertical device geometry for a carbon-nanotube-based field effect transistor has one or multiple carbon nanotubes formed in a trench. | 2009-07-02 |
| 20090166687 | Image Sensor and Method for Manufacturing the Same - An image sensor and a method for manufacturing the same may include a gate on a semiconductor substrate, a photodiode on the semiconductor substrate at a first side of the gate, a floating diffusion region on the semiconductor substrate at a second side of the gate, in which the second side is opposite to the first side, a channel under the gate, the channel connecting the photodiode with the floating diffusion region, and a barrier region under the photodiode. | 2009-07-02 |
| 20090166688 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - An image sensor includes an interlayer dielectric including metal lines disposed on a semiconductor substrate; first conductive regions formed on a crystalline semiconductor substrate which is bonded to the semiconductor substrate, and connected with the metal lines; second conductive regions formed between the respective first conductive regions; first conductive-type high-density dopant regions adjoining the first conductive regions, being formed on the crystalline semiconductor substrate; and second conductive-type high-density dopant regions adjoining the second conductive regions, being formed between the respective first conductive-type high-density dopant regions. | 2009-07-02 |
| 20090166689 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - An image sensor includes a first substrate, readout circuitry, an electrical junction region, a metal interconnection and an image sensing device. The readout circuitry is formed on and/or over the first substrate and the electrical junction region is formed in the first substrate and electrically connected to the readout circuitry. The metal interconnection is electrically connected to the electrical junction region. The image sensing device is formed on and/or over the metal interconnection. | 2009-07-02 |
| 20090166690 | Image Sensor and Method of Manufacturing the Same - An image sensor and manufacturing method thereof are provided. The image sensor can include a gate, a channel region, a first p-type doped region, a second p-type doped region, an n-type doped region, and a floating diffusion region. The gate can be disposed on a semiconductor substrate, and the channel region can be disposed in the semiconductor substrate under the gate. The first p-type doped region can be disposed at a side of the gate and can be adjacent to the channel region. The second p-type doped region can be disposed under the first p-type doped region and spaced apart from the gate. The n-type doped region can be disposed under the first and second p-type doped regions, and the floating diffusion region can be disposed at another side of the gate. | 2009-07-02 |
| 20090166691 | Image Sensor and Method of Manufacturing the Same - Image sensors and manufacturing methods thereof are provided. An image sensor according to an embodiment comprises a second conductive type diffusion layer formed on a first conductive type substrate; a device isolating layer formed in the second conductive type diffusion layer to isolate the second conductive type diffusion layer according to unit pixel; a gate formed on the second conductive type diffusion layer; a first conductive type area formed on a surface of the second conductive type diffusion layer at one side of the gate; a first conductive type well area formed in the second conductive type diffusion layer at the other side of the gate; and a floating diffusion area formed in the first conductive type well area. | 2009-07-02 |
| 20090166692 | CMOS IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - A CMOS image sensor may include a dielectric layer formed on a semiconductor substrate, first and second passivation layers sequentially formed on the whole surface of the dielectric layer, a planarization layer, a color filter layer, and an overcoating layer and a microlens sequentially formed on the second passivation layer. The CMOS image sensor may further include a plurality of metal pads arranged on the dielectric layer to surround the microlens, a water barrier formed on the dielectric layer between the microlens and the metal pads, and first and second open parts exposing the metal pads and the water barrier. | 2009-07-02 |
| 20090166693 | Image Sensor and Manufacturing Method Thereof - An image sensor and manufacturing method thereof are provided. The image sensor can include a gate on a semiconductor substrate, first and second p-type doping areas below the gate, a third p-type doping area adjacent to the first p-type doping area, and a fourth p-type doping area adjacent to the third p-type doping area. An n-type doping area can be provided in the semiconductor substrate such that at least a portion of the n-type doping area is disposed below the first, third, and fourth p-type doping areas. A floating diffusion area can be provided adjacent to the second p-type doping area. | 2009-07-02 |
| 20090166694 | Image Sensor and Method for Manufacturing the Same - An image sensor and a method for manufacturing the same are provided. In the image sensor, a semiconductor substrate has a pixel region and a peripheral region defined by a first device isolation layer. First and second photodiode patterns are formed on the pixel region and are connected to lower metal lines to first and second readout circuitries. The first photodiode pattern performs as an active photodiode and the second photodiode pattern functions as a dummy pixel. The dummy pixel can measure leakage current. | 2009-07-02 |
| 20090166695 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SENSOR - A method for manufacturing an image sensor having a peripheral circuit unit and a pixel unit includes forming a device isolation layer that defines an active area in the pixel area, on a semiconductor substrate, forming a gate pattern on the active area of the semiconductor substrate, forming a photodiode area at one side of the gate pattern in the semiconductor substrate, vapor-depositing a plurality of dielectric layers on the whole surface of the substrate including the gate pattern, forming a spacer at lateral sides of the gate pattern by removing part of the plurality of dielectric layers by dry etching, and removing the other dielectric layer disposed between the lowermost dielectric layer and the uppermost dielectric layer by wet etching, while leaving a lowermost dielectric layer among the plurality of dielectric layers on the substrate where a floating diffusion area will be formed. | 2009-07-02 |
| 20090166696 | CMOS Image Device with Local Impurity Region - According to a CMOS image device and a method of manufacturing same, dark current is decreased by a local impurity region. The image device includes a semiconductor substrate, and a transfer gate formed on a predetermined portion of the semiconductor substrate and electrically insulated from the semiconductor substrate. A photodiode is formed in the semiconductor substrate on one side of the transfer gate, and a floating diffusion region is formed on the semiconductor substrate in the other side of the transfer gate. A local impurity region of a first conductivity type is formed to be partially overlapped the transfer gate between the photodiode and the floating diffusion region. | 2009-07-02 |
| 20090166697 | Semiconductor Device and Method of Fabricating the Same - Disclosed are a semiconductor device and method of fabricating the same. The semiconductor device includes a floating gate on a semiconductor layer; a first contact on the floating gate; a MIM capacitor including a lower electrode, an insulating layer, and an upper electrode on the first contact; a second contact on a drain region of the semiconductor layer; a metal island on the second contact; a via on the metal island; and a bit line on the via. | 2009-07-02 |
| 20090166698 | CAPACITOR AND METHOD OF MANUFACTURING THE SAME - A capacitor with a mixed structure of a Metal Oxide Semiconductor (MOS) capacitor and a Poly-silicon Insulator Poly-silicon (PIP) capacitor includes a substrate and a diffusion junction region formed over the substrate. A high concentration diffusion junction region may be formed in a portion of the diffusion junction region. An oxide layer may be formed over the substrate, the oxide layer having an opening that exposes a portion of the high concentration diffusion junction region. A first polysilicon plate may be formed over a portion of the oxide layer and spaced from the opening, and a nitride layer may be formed over a portion of the first polysilicon plate. A sidewall may be formed over a side of the first polysilicon layer, over a side of the nitride layer, and over a portion of the oxide layer between the side of the polysilicon layer and the opening. A second polysilicon plate may be formed over the nitride layer, over the sidewall, and over the high concentration diffusion junction region. | 2009-07-02 |
| 20090166699 | Semiconductor Constructions - In some embodiments, an opening is formed through a first material, and sidewall topography of the opening is utilized to form a pair of separate anistropically etched spacers. The spacers are utilized to pattern lines in material underlying the spacers. Some embodiments include constructions having one or more openings which contain steep sidewalls joining to one another at shallow sidewall regions. The constructions may also contain lines along and directly against the steep sidewalls, and spaced from one another by gaps along the shallow sidewall regions. | 2009-07-02 |
| 20090166700 | SINGLE TRANSISTOR MEMORY CELL WITH REDUCED RECOMBINATION RATES - A semiconductor fabrication method includes forming a semiconductor structure including source/drain regions disposed on either side of a channel body wherein the source/drain regions include a first semiconductor material and wherein the channel body includes a migration barrier of a second semiconductor material. A gate dielectric overlies the semiconductor structure and a gate module overlies the gate dielectric. An offset in the majority carrier potential energy level between the first and second semiconductor materials creates a potential well for majority carriers in the channel body. The migration barrier may be a layer of the second semiconductor material over a first layer of the first semiconductor material and under a capping layer of the first semiconductor material. In a one dimensional migration barrier, the migration barrier extends laterally through the source/drain regions while, in a two dimensional barrier, the barrier terminates laterally at boundaries defined by the gate module. | 2009-07-02 |
| 20090166701 | One transistor/one capacitor dynamic random access memory (1T/1C DRAM) cell - In general, in one aspect, a method includes forming a semiconductor fin. A first insulating layer is formed adjacent to the semiconductor fin. A second insulating layer is formed over the first insulating layer and the semiconductor fin. A first trench is formed in the second insulating layer and the first insulating layer therebelow. The first trench is filed with a polymer. A third insulating layer is formed over the polymer. A second trench is formed in the third insulating layer, wherein the second trench is above the first trench and extends laterally therefrom. The polymer is removed from the first trench. A capacitor is formed within the first and the second trenches. | 2009-07-02 |
| 20090166702 | TRENCH-TYPE SEMICONDUCTOR DEVICE STRUCTURE - A trench-type semiconductor device structure is disclosed. The structure includes a semiconductor substrate, a gate dielectric layer and a substrate channel structure. The semiconductor substrate includes a trench having an upper portion and a lower portion. The upper portion includes a conductive layer formed therein. The lower portion includes a trench capacitor formed therein. The gate dielectric layer is located between the semiconductor substrate and the conductive layer. The substrate channel structure with openings, adjacent to the trench, is electrically connected to the semiconductor substrate via the openings. | 2009-07-02 |
| 20090166703 | MEMORY DEVICE WITH A LENGTH-CONTROLLABLE CHANNEL - A memory device is provided. The memory device includes a substrate, a trench having an upper portion and a lower portion formed in the substrate, a trench capacitor formed in the lower portion of the trench, a collar dielectric layer formed on a sidewall of the trench capacitor and extending away from a top surface of the substrate, a first doping region formed on a side of the upper portion of the trench in the substrate for serving as source/drain, a conductive layer formed in the trench and electrically connected to the first doping region, a top dielectric layer formed on conductive layer, a gate formed on the top dielectric layer, an epitaxy layer formed on both sides of the gate and on the substrate and a second doping area formed on a top of the epitaxy layer for serving as source/drain. | 2009-07-02 |
| 20090166704 | NON-VOLATILE STORAGE WITH SUBSTRATE CUT-OUT AND PROCESS OF FABRICATING - Shallow trench isolation regions are positioned between NAND strings (or other types of non-volatile storage). These isolation regions include sections that form concave cut-out shapes in the substrate for the NAND string (or other types of non-volatile storage). The floating gates (or other charge storage devices) of the NAND strings hang over the sections of the isolation region that form the concave cut-out shape in the substrate. To manufacture such a structure, a two step etching process is used to form the isolation regions. In the first step, isotropic etching is used to remove substrate material in multiple directions, including removing substrate material underneath the floating gates. In the second step, anisotropic etching is used to create the lower part of the isolation region. | 2009-07-02 |
| 20090166705 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THEREOF - In a nonvolatile semiconductor memory device, second conductivity type source and drain regions are formed separately from each other in a first conductivity type semiconductor region on a surface thereof. A second conductivity type semiconductor region is formed in the first conductivity type semiconductor region arranged between the source and drain regions and is formed separately from the source and drain regions. A first gate insulating film is formed on the semiconductor substrate arranged between the source and drain regions. A floating gate is formed on the first gate insulating film. An intermediate gate insulating film is formed on the floating gate. A control gate is formed on the floating gate over the intermediate gate insulating film. | 2009-07-02 |
| 20090166706 | Semiconductor Device and Method of Manufacturing the Same - A semiconductor device according to an embodiment of the present invention has a bit line and a word line. The device includes a substrate which is provided with first trenches extending in a bit-line direction and has side surfaces forming sidewalls of the first trenches, the substrate being provided with bird's beaks at upper edges of the side surfaces, a first gate insulator formed on the substrate between the first trenches, a floating gate formed on the first gate insulator between the first trenches and located between second trenches extending in a word-line direction, the floating gate not being provided with bird's beaks at lower edges of side surfaces facing the first trenches, a second gate insulator formed on the floating gate between the second trenches, and a control gate formed on the second gate insulator between the second trenches. | 2009-07-02 |
| 20090166707 | FLASH MEMORY DEVICE AND METHOD FOR MANUFACTURING THE DEVICE - A flash memory device and a method for manufacturing the device includes forming a device isolation layer in a semiconductor substrate defining active regions, forming a control gate layer over the entire upper surface of the semiconductor substrate, forming a gate mask over the control gate layer, the gate mask being used to provide gate lines on the device isolation layer with grooves at positions opposite each other, and forming the grooves by etching the control gate layer using the gate mask as an etching mask, and forming the gate lines on the device isolation layer. A common source line can be more easily defined during a SAS process including photography and etching processes, and a reduced source resistance can be accomplished, resulting in an improvement in characteristics of the flash memory device. | 2009-07-02 |
| 20090166708 | Nonvolatile semiconductor memory with erase gate and its manufacturing method - A nonvolatile semiconductor memory device includes a semiconductor substrate, a select gate formed above the semiconductor substrate, a floating gate formed above the semiconductor substrate and an erase gate positioned lower than an upper surface of the floating gate, and opposite an edge of a lower surface of the floating gate. | 2009-07-02 |
| 20090166709 | Flash Memory Device and Method of Fabricating the Same - A flash memory device and method of fabricating thereof. In accordance with the method of the invention, a tunnel dielectric layer and an amorphous first conductive layer are formed over a semiconductor substrate. An annealing process to change the amorphous first conductive layer to a crystallized first conductive layer is performed. A second conductive layer is formed on the crystallized first conductive layer. A first etch process to pattern the second conductive layer is performed. A second etch process to remove an oxide layer on the crystallized first conductive layer is performed. A third etch process to pattern the amorphous first conductive layer is performed. | 2009-07-02 |
| 20090166710 | NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory device includes: a semiconductor substrate; and a memory cell. The memory cell includes: a source region and a drain region formed at a distance from each other on the semiconductor substrate; a tunnel insulating film formed on a channel region of the semiconductor substrate, the channel region being located between the source region and the drain region; a charge storage film formed on the tunnel insulating film; a charge block film formed on the charge storage film; and a control electrode that is formed on the charge block film. The control electrode includes a Hf oxide film or a Zr oxide film having at least one element selected from the first group consisting of V, Cr, Mn, and Tc added thereto, and having at least one element selected from the second group consisting of F, H, and Ta added thereto. | 2009-07-02 |
| 20090166711 | Tunnel Insulating Layer of Flash Memory Device and Method of Forming the Same - The present invention discloses a tunnel insulating layer in a flash memory device and a method of forming the same, the method according to the present invention comprises the steps of forming a first oxide layer on a semiconductor substrate through a first oxidation process; forming a nitride layer on an interface between the semiconductor substrate and the first oxide layer through a first nitridation process; forming a second nitride layer on the first oxide layer through a second nitridation process; forming a second oxide layer on the second nitride layer through a second oxidation process; and forming a third nitride layer on the second oxide layer through a third nitridation process. | 2009-07-02 |
| 20090166712 | NANOCRYSTAL NON-VOLATILE MEMORY CELL AND METHOD THEREFOR - A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces. | 2009-07-02 |
| 20090166713 | Semiconductor Device and Method of Fabricating the Same - Provided are a semiconductor device and a method of fabricating the same. The semiconductor device comprises a plurality of device isolation layers disposed in a semiconductor substrate, the device isolation layers extending in a word line direction and spaced apart from each other; a plurality of floating gate devices extending in a bit line direction perpendicular to the device isolation layer and spaced apart from each other; a source region and a drain region disposed at sides of the floating gate device; an insulation layer disposed on the floating gate device and the source region, and a polysilicon line extending in the word line direction and connected to the drain region. | 2009-07-02 |
| 20090166714 | Non-volatile memory device - A non-volatile memory device includes field insulating layer patterns on a substrate to define an active region of the substrate, upper portions of the field insulating layer patterns protruding above an upper surface of the substrate, a tunnel insulating layer on the active region, a charge trapping layer on the tunnel insulating layer, a blocking layer on the charge trapping layer, first insulating layers on upper surfaces of the field insulating layer patterns, and a word line structure on the blocking layer and first insulating layers. | 2009-07-02 |
| 20090166715 | Scalable Interpoly Dielectric Stacks With Improved Immunity To Program Saturation - A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking dielectric comprises a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored, the siliconoxide consuming material having consumed at least part of the upper layer. | 2009-07-02 |
| 20090166716 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first oxide-nitride-oxide (ONO) layer in which a block oxide, a tunnel oxide and a trap nitride are stacked sequentially on one side of a semiconductor substrate; a second oxide-nitride-oxide (ONO) layer in which the block oxide, the tunnel oxide and the trap nitride are stacked sequentially on the other side of the semiconductor substrate; a third oxide formed between the first ONO layer and the second ONO layer; a silicon gate formed on the first ONO layer, the second ONO layer and the third oxide; and a source region and a drain region formed on the surface of the semiconductor substrate of both sides of the silicon gate. | 2009-07-02 |
| 20090166717 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - Embodiments relate to a nonvolatile memory device and a method for manufacturing the same. According to embodiments, a nonvolatile memory device may include a tunnel ONO film having an oxide film, a nitride film, and an oxide film stacked on and/or over a semiconductor substrate. It may also include a trap nitride film formed on and/or over the tunnel ONO film, a blocking oxide film formed on and/or over the trap nitride film and having a high-dielectric film with a higher dielectric constant than a dielectric constant of a SiO | 2009-07-02 |
| 20090166718 | METHOD OF PREDICTING DRAIN CURRENT IN MOS TRANSISTOR - Embodiments relate to a method of predicting a drain current that may accurately predict drain current in a linear region, a saturation region, and a breakdown region by modeling a drain current in the breakdown region, in which inconsistency occurs when a drain current depending on a drain voltage is calculated by a related are BSIM3-based modeling scheme, by an expression with a ternary operator, and adding the modeled drain current to the result of a related art BSIM3-based modeling scheme. | 2009-07-02 |
| 20090166719 | LDMOS SEMICONDUCTOR DEVICE MASK - Embodiments relate to an LDMOS semiconductor device mask that may reduce current leakage under a gate-off condition. According to embodiments, an LDMOS semiconductor device mask may include a moat mask to define a moat region, an NDT mask to define an N drift region, a PDT mask to define a P drift region, and a gate mask to form a gate. According to embodiments, a PDT mask may be configured to expose a field region of a semiconductor device. | 2009-07-02 |
| 20090166720 | SEMICONDUCTOR DEVICE, METHOD FOR OPERATING A SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having at least a pn-junction arranged in the semiconductor substrate. At least a field electrode is arranged at least next to a portion of the pn-junction, wherein the field electrode is insulated from the semiconductor substrate. A switching device is electrically connected to the field electrode and adapted to apply selectively and dynamically one of a first electrical potential and a second electrical potential, which is different to the first electrical potential, to the field electrode to alter the avalanche breakdown characteristics of the pn-junction. | 2009-07-02 |
| 20090166721 | QUASI-VERTICAL GATED NPN-PNP ESD PROTECTION DEVICE - Fashioning a quasi-vertical gated NPN-PNP (QVGNP) electrostatic discharge (ESD) protection device is disclosed. The QVGNP ESD protection device has a well having one conductivity type formed adjacent to a deep well having another conductivity type. The device has a desired holding voltage and a substantially homogenous current flow, and is thus highly robust. The device can be fashioned in a cost effective manner by being formed during a BiCMOS or Smart Power fabrication process. | 2009-07-02 |
| 20090166722 | High voltage structures and methods for vertical power devices with improved manufacturability - This invention discloses a semiconductor power device disposed on a semiconductor substrate supporting an epitaxial layer as a drift region composed of an epitaxial layer. The semiconductor power device further includes a super-junction structure includes a plurality of doped sidewall columns disposed in a multiple of epitaxial layers. The epitaxial layer have a plurality of trenches opened and filled with the multiple epitaxial layer therein with the doped columns disposed along sidewalls of the trenches disposed in the multiple of epitaxial layers. | 2009-07-02 |
| 20090166723 | SEMICONDUCTOR DEVICE WITH VERTICAL CHANNEL TRANSISTOR AND LOW SHEET RESISTANCE AND METHOD FOR FABRICATING THE SAME - A memory device includes a substrate, a plurality of wordlines arranged over the substrate, a plurality of pillars formed over the substrate between the wordlines, a gate electrode surrounding external walls of the pillars to be connected to the wordlines, and an insulation layer for insulating one sidewall of each wordline from the gate electrode. | 2009-07-02 |
| 20090166724 | Semiconductor Device and Method for Manufacturing the Same - Disclosed is a vertically arranged semiconductor device. The semiconductor device can include a semiconductor substrate comprising a first conductive type buried layer, a first conductive type drift region formed on the first conductive type buried layer, and a second conductive type well formed on the first conductive type drift region. A gate insulating layer and a gate electrode can be formed in regions of the substrate from which the first conductive type drift region and the second conductive type well are selectively removed. A first conductive type source region can be formed at sides of the gate electrode. A n insulating layer can be formed on the semiconductor substrate including the gate electrode and can include a trench formed through the insulating layer and a portion of the second conductive type well. A barrier layer can be formed in the trench and a source contact including tungsten and aluminum can be deposited in the trench. A drain electrode layer can be formed on a bottom surface of the substrate below the first conductive type buried layer. | 2009-07-02 |
| 20090166725 | VERTICAL TRANSISTOR AND METHOD FOR FORMING THE SAME - A vertical transistor includes a semiconductor substrate provided with a pillar type active pattern over the surface thereof. A first tensile layer is formed over the semiconductor substrate and around the lower end portion of the pillar type active pattern, and a second tensile layer is formed over the upper end portion of the pillar type active pattern so that a tensile stress is applied in a vertical direction to the pillar type active pattern. A first junction region is formed within the surface of the semiconductor substrate below the first tensile layer and the pillar type active pattern. A gate is formed so as to surround at least a portion of the pillar type active pattern. A second junction region is formed within the upper end portion of the pillar type active pattern. | 2009-07-02 |
| 20090166726 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - There are provided a method of manufacturing a semiconductor device which is capable of narrowing only the width of a Fin channel while maintaining the widths of source and drain regions, and a semiconductor device. The method of manufacturing a semiconductor device is a method of manufacturing a Fin type transistor, including: forming STI region | 2009-07-02 |
| 20090166727 | POWER SEMICONDUCTOR HAVING A LIGHTLY DOPED DRIFT AND BUFFER LAYER - A power semiconductor element having a lightly doped drift and buffer layer is disclosed. One embodiment has, underneath and between deep well regions of a first conductivity type, a lightly doped drift and buffer layer of a second conductivity type. The drift and buffer layer has a minimum vertical extension between a drain contact layer on the adjacent surface of a semiconductor substrate and the bottom of the deepest well region which is at least equal to a minimum lateral distance between the deep well regions. The vertical extension can also be determined such that a total amount of dopant per unit area in the drift and buffer layer is larger then a breakdown charge amount at breakdown voltage. | 2009-07-02 |
| 20090166728 | Structure and Method for Forming Shielded Gate Trench FET with Multiple Channels - A field effect transistor (FET) includes a pair of trenches extending into a semiconductor region. Each trench includes a first shield electrode in a lower portion of the trench and a gate electrode in an upper portion of the trench over but insulated from the shield electrode. First and second well regions of a first conductivity type laterally extend in the semiconductor region between the pair of trenches and abut sidewalls of the pair of trenches. The first and second well regions are vertically spaced from one another by a first drift region of a second conductivity type. The gate electrode and the first shield electrode are positioned relative to the first and second well regions such that a channel is formed in each of the first and second well regions when the FET is biased in the on state. | 2009-07-02 |
| 20090166729 | POWER SEMICONDUCTOR HAVING A LIGHTLY DOPED DRIFT AND BUFFER LAYER - A power semiconductor element having a lightly doped drift and buffer layer is disclosed. One embodiment has, underneath and between deep well regions of a first conductivity type, a lightly doped drift and buffer layer of a second conductivity type. The drift and buffer layer has a minimum vertical extension between a drain contact layer on the adjacent surface of a semiconductor substrate and the bottom of the deepest well region which is at least equal to a minimum lateral distance between the deep well regions. The vertical extension can also be determined such that a total amount of dopant per unit area in the drift and buffer layer is larger then a breakdown charge amount at breakdown voltage. | 2009-07-02 |
| 20090166730 | SiC semiconductor device having bottom layer and method for manufacturing the same - A SiC semiconductor device includes: a substrate; a drift layer on the substrate; a trench on the drift layer; a base region in the drift layer sandwiching the trench; a channel between the base region and the trench; a source region in the base region sandwiching the trench via the channel; a gate electrode in the trench via a gate insulation film; a source electrode coupled with the source region; a drain electrode on the substrate opposite to the drift layer; and a bottom layer under the trench. An edge portion of the bottom layer under a corner of a bottom of the trench is deeper than a center portion of the bottom layer under a center portion of the bottom of the trench. | 2009-07-02 |
| 20090166731 | VERTICAL-TYPE FIELD-EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF - A vertical-type FET includes: a semiconductor layer having a plurality of trenches; a gate electrode partially embedded in the trenches; and a base region and a source region that are formed in the semiconductor layer between adjacent trenches. The gate electrode includes: a plurality of first gate structures respectively formed in the plurality of trenches, wherein each first gate structure has a protruding portion protruding from the trench and an embedded portion embedded in the trench; and a second gate structure formed to connect between the protruding portions of adjacent first gate structures. The embedded portion is formed on a side wall of the trench through a first insulating film. The second gate structure is formed on the source region through a second insulating film thicker than the first insulating film. | 2009-07-02 |
| 20090166732 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment of the present invention has a transistor section which includes a trench gate type transistor, and a gate line section which includes a part provided between transistor sections. The device includes a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, a base layer formed in the semiconductor layer, and provided with trenches in the transistor section and the gate line section, the trenches in the transistor section extending in a first direction parallel to a direction in which the transistor extends, the trenches in the bit line section extending in a second direction perpendicular to the first direction, and the trenches in the transistor section penetrating the base layer to reach the semiconductor layer, a source layer formed in the semiconductor layer in the transistor section, the source layer being located on the base layer, a gate insulator formed on surfaces of the base layer and the semiconductor layer exposed to the trenches in the transistor section and the gate line section, and on an upper surface of the base layer between the trenches in the gate line section, a gate line layer formed on the gate insulator, and including a part buried in the trenches in the transistor section, an inter layer dielectric formed on the gate line layer, and a source line layer formed on the inter layer dielectric, and electrically connected to the source layer in the transistor section. | 2009-07-02 |
| 20090166733 | Semiconductor Device and Manufacturing Method Thereof - A method of manufacturing a semiconductor device including forming a first conductive-type buried layer in a substrate; forming a first conductive-type drift area on the first conductive-type buried layer; forming a gate insulating layer and gate electrodes by selectively removing the first conductive-type drift area; forming a first oxide layer on the substrate and gate electrodes; implanting second conductive-type impurity ions into the substrate; forming a nitride layer on the first oxide layer; forming a second conductive-type well by diffusing the second conductive-type impurity ions while forming a second oxide layer; removing the nitride layer, the second oxide layer, and portions of the first oxide layer; forming first conductive-type source areas at sides of the gate electrode(s); forming a dielectric layer on the oxide layer; forming a trench in the dielectric layer and the oxide layer; forming a source contact in the trench; and forming a drain. | 2009-07-02 |
| 20090166734 | TRENCH GATE MOSFET AND METHOD FOR FABRICATING THE SAME - A trench gate MOSFET and a fabrication method thereof includes forming a first epitaxial layer over a semiconductor substrate, and then forming a second epitaxial layer formed over the first epitaxial layer, and then forming a body region over the second conductive type second epitaxial layer, and then forming a circular cross-section in a portion of the body region by performing an ion implantation process on the body region such that a bottom area thereof has a circular cross-section. | 2009-07-02 |
| 20090166735 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a method of manufacturing a semiconductor device having a shared contact for connection between a source/drain region and a gate electrode. After formation of a gate electrode via a gate insulating film on a semiconductor substrate, a top surface of the substrate is covered with a cover film. After removal of the cover film from at least one of sidewall surface of the gate electrode and a part of the top surface of the substrate adjacent to the sidewall surface, a semiconductor layer is epitaxially grown on a top surface of an exposed substrate to electrically connect the substrate and the at least one sidewall surface of the gate electrode. Then, a source/drain region is formed in a top surface part of the substrate or the semiconductor layer using the gate electrode as a mask. | 2009-07-02 |
| 20090166736 | LATERAL DOUBLE DIFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A lateral double diffused metal oxide semiconductor a lateral double diffused metal oxide semiconductor (LDMOS) transistor which may include a first conductive type semiconductor substrate and a shallow trench isolation film defining an active region in the substrate. A second conductive type body region may be disposed over a portion of the top of the semiconductor substrate. A first conductive type source region may be disposed in the top of the body region. A first conductive type extended drain region may be disposed over a portion of the top of the semiconductor substrate and spaced from the body region. A gate dielectric film covers surfaces of the second conductive type body region and first conductive type source region and a portion of the top of the first conductive type semiconductor substrate. A gate conductive film may extend from the first conductive type source region, over the gate dielectric film, over the shallow trench isolation film, and inside the shallow trench isolation film. Therefore, embodiments prevent the disturbance in flow of current in an on-state by the STI, making it possible to obtain improved on-state resistance characteristics. | 2009-07-02 |
| 20090166737 | Method for Manufacturing a Transistor - A method for manufacturing a transistor is disclosed, which is capable of improving matching characteristics of regions within a transistor or among transistors on a wafer, from wafer-to-wafer, or from lot-to-lot. The method includes forming a photoresist pattern on a semiconductor substrate including an isolation layer, forming a drift region by implanting first and second dopant ions using the photoresist pattern as a mask, forming a gate oxide layer on the semiconductor substrate, forming a poly gate on the gate oxide layer, forming source and drain regions a predetermined distance from the poly gate, and forming a silicide layer on the above structure. | 2009-07-02 |
| 20090166738 | RAM CELL INCLUDING A TRANSISTOR WITH FLOATING BODY FOR INFORMATION STORAGE HAVING ASYMMETRIC DRAIN/SOURCE EXTENSIONS - In a floating body storage transistor, the dopant concentration at the emitter side of the parasitic bipolar transistor may be significantly increased on the basis of a tilted implantation process, while maintaining a desired graded dopant profile at the collector side. Consequently, voltages for reading and writing of the FB storage transistor may be reduced, thereby also reducing the amount of die area consumed by respective boost converters. In addition, reliability of the FB transistor, as well as the retention time, may be increased. | 2009-07-02 |
| 20090166739 | Semiconductor Device - In order to obtain substantially the same operating speed of a p-type MOS transistor and an n-type MOS transistor forming a CMOS circuit, the n-type MOS transistor has a three-dimensional structure having a channel region on both the (100) plane and the (110) plane and the p-type MOS transistor has a planar structure having a channel region only on the (110) plane. Further, both the transistors are substantially equal to each other in the areas of the channel regions and gate insulating films. Accordingly, it is possible to make the areas of the gate insulating films and so on equal to each other and also to make the gate capacitances equal to each other. | 2009-07-02 |
| 20090166740 | Reduced mask configuration for power mosfets with electrostatic discharge (ESD) circuit protection - A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body implant ion block layer for blocking implanting body ions to enter into the semiconductor substrate below the body implant ion block layer. In an exemplary embodiment, the electrostatic discharge (ESD) polysilicon layer on top of the semiconductor substrate further covering a scribe line on an edge of the semiconductor device whereby a passivation layer is no longer required manufacturing the semiconductor device for reducing a mask required for patterning the passivation layer. | 2009-07-02 |
| 20090166741 | REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE USING SPACER PROCESSING TECHNIQUES - Reducing external resistance of a multi-gate device using spacer processing techniques is generally described. In one example, a method includes depositing a sacrificial gate electrode to one or more multi-gate fins, the one or more multi-gate fins comprising a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions, patterning the sacrificial gate electrode such that the sacrificial gate electrode material is coupled to the gate region and substantially no sacrificial gate electrode is coupled to the source and drain regions of the one or more multi-gate fins, forming a dielectric film coupled to the source and drain regions of the one or more multi-gate fins, removing the sacrificial gate electrode from the gate region of the one or more multi-gate fins, depositing spacer gate dielectric to the gate region of the one or more multi-gate fins wherein substantially no spacer gate dielectric is deposited to the source and drain regions of the one or more multi-gate fins, the source and drain regions being protected by the dielectric film, and etching the spacer gate dielectric to completely remove the spacer gate dielectric from the gate region area to be coupled with a final gate electrode except a remaining pre-determined thickness of spacer gate dielectric to be coupled with the final gate electrode that remains coupled with the dielectric film. | 2009-07-02 |
| 20090166742 | REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE BY INCORPORATION OF A PARTIAL METALLIC FIN - Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin is generally described. In one example, an apparatus includes a semiconductor substrate and one or more fins of a multi-gate transistor device coupled with the semiconductor substrate, the one or more fins having a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions where the gate region of the one or more fins includes a semiconductor material and where the source and drain regions of the one or more fins include a metal portion and a semiconductor portion, the metal portion and the semiconductor portion being coupled together. | 2009-07-02 |
| 20090166743 | INDEPENDENT GATE ELECTRODES TO INCREASE READ STABILITY IN MULTI-GATE TRANSISTORS - Independent gate electrodes for multi-gate transistors are generally described. In one example, an apparatus includes a semiconductor fin, one or more multi-gate pull down (PD) gate stacks coupled with the semiconductor fin, the one or more PD gate stacks including a PD gate electrode, and one or more multi-gate pass gate (PG) gate stacks coupled with the semiconductor fin, the one or more PG gate stacks including a PG gate electrode, the PG gate electrode having a greater threshold voltage than the PD gate electrode. | 2009-07-02 |
| 20090166744 | Semiconductor device with deep trench structure - Disclosed herein is a semiconductor device with a deep trench structure for effectively isolating heavily doped wells of neighboring elements from each other at a high operating voltage. The semiconductor device with a deep trench structure includes a semiconductor substrate in which a first conductivity type well and a second conductivity type well having conductivity opposite to that of the first conductivity type well are formed, a gate oxide film and a gate electrode laminated on each of the first conductivity type well and the second conductivity type well, second conductivity type drift regions formed on both sides of the gate electrode formed on the first conductivity type well, first conductivity type drift regions formed on both sides of the gate electrode formed on the second conductivity type well, and a first isolation layer having a trench structure deeper than the first and second conductivity type wells and isolating the first conductivity type well and the second conductivity type well from each other. | 2009-07-02 |
| 20090166745 | SEMICONDUCTOR DEVICE AND PHOTOMASK - Shared contact holes SC | 2009-07-02 |
| 20090166746 | SEMICONDUCTOR DEVICE - A semiconductor device has a first and a second active regions of a first conductivity type disposed on a semiconductor substrate, a third and a fourth active regions of a second conductivity type disposed on the semiconductor substrate, the second and the fourth active regions having sizes larger than those of the first and the third active regions respectively, a first electroconductive pattern disposed adjacent to the first active region and having a first width, a second electroconductive pattern disposed adjacent to the second active region and having a second width larger than the first width, a third electroconductive pattern disposed adjacent to the third active region and having a third width; and a fourth electroconductive pattern disposed adjacent to the fourth active region and having a fourth width smaller than the third width. | 2009-07-02 |
| 20090166747 | FORMATION OF METAL GATE ELECTRODE USING RARE EARTH ALLOY INCORPORATED INTO MID GAP METAL - Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. A rare earth-rare earth alloy incorporated metal nitride layer is formed above a gate dielectric. This process provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting NMOS transistors. | 2009-07-02 |
| 20090166748 | Semiconductor device and method of manufacturing the same - A semiconductor device including a silicon substrate and a field effect transistor including a gate insulating film on the silicon substrate, a gate electrode on the gate insulating film, and source/drain regions formed in the substrate on opposite sides of the gate electrode, wherein the gate electrode includes a silicide layer containing an Ni | 2009-07-02 |
| 20090166749 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes n- and p-type semiconductor regions separately formed on a substrate, an interlayer insulator formed on the substrate and having first and second trenches formed to reach the n- and p-type regions. There are further included first and second gate insulators formed inside of the first and second trenches, a first metal layer formed inside of the first trench via the first gate insulator, a second metal layer formed in a thickness of 1 monolayer or more and 1.5 nm or less inside of the second trench via the second gate insulator, a third metal layer formed on the second metal layer and containing at least one of a simple substance, a nitride, a carbide and an oxide of at least one metal element of alkaline earth metal elements and group III elements, first and second source/drain regions formed on the n- and p-type regions. | 2009-07-02 |
| 20090166750 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor wafer, a source region and a drain region formed within the semiconductor wafer, a gate electrode formed on the semiconductor wafer between the source region and the drain region, an interlayer film formed on the semiconductor wafer and the gate electrode, and a dummy floating pattern embedded into the interlayer film, having a film containing metal or a metallic compound having tensile stress or compressive stress and formed to be spaced from the semiconductor wafer and the gate electrode. | 2009-07-02 |
| 20090166751 | Image sensor and method for manufacturing the same - A method for manufacturing a CMOS transistor includes preparing a silicon substrate provided with a first buried layer, a second buried layer and a body, vertically forming device-isolation films inside the body, forming a first-type well inside the body arranged on the first buried layer, and vertically forming a first source and drain region inside the first-type well, forming a second-type well inside the body arranged on the second buried layer, and vertically forming a second source and drain region inside the second-type well, and vertically forming a recessed gate between the first-type well and the second-type well. | 2009-07-02 |
| 20090166752 | Semiconductor Devices and Methods of Manufacture Thereof - A first gate dielectric of a first transistor is disposed over a workpiece in a first region, and a second gate dielectric of a second transistor is disposed over the workpiece in a second region. The second gate dielectric comprises a different material than the first gate dielectric. A first dopant-bearing metal comprising a first dopant is disposed in recessed regions of the workpiece proximate the first gate dielectric, and a second dopant-bearing metal comprising a second dopant is disposed in recessed regions of the workpiece proximate the second gate dielectric. A first doped region comprising the first dopant is disposed in the workpiece adjacent the first dopant-bearing metal. A second doped region comprising the second dopant is disposed in the workpiece adjacent the second dopant-bearing metal. The dopant-bearing metals and the doped regions comprise source and drain regions of the first and second transistors. | 2009-07-02 |
| 20090166753 | Semiconductor Device and Method of Manufacturing Such a Device - The invention relates to a semiconductor device ( | 2009-07-02 |
| 20090166754 | CIRCUIT DEVICE AND METHOD OF FORMING A CIRCUIT DEVICE HAVING A REDUCED PEAK CURRENT DENSITY - In a particular embodiment, a method of forming a field effect transistor (FET) device having a reduced peak current density is disclosed. The method includes forming a field effect transistor (FET) device on a substrate. The FET device includes a drain terminal, a source terminal, a gate terminal, and a body terminal. The method further includes depositing a plurality of metal contacts along a width of a gate terminal of the FET device and forming a wire trace to contact each of the plurality of metal contacts to reduce a gate resistance along the width of the gate terminal. | 2009-07-02 |
| 20090166755 | GROWTH OF UNFACETED SIGE ALONG A SEMICONDUCTOR DEVICE WIDTH - Semiconductor devices and fabrication methods are provided in which disposable gates are formed over isolation regions. Sidewall structures, including disposable sidewall structures, are formed on sidewalls of the disposable gates. An epitaxially grown silicon germanium is formed in recesses defined by the sidewalls. The process provides a compressive strained channel in the device without faceting of the epitaxially grown silicon germanium. | 2009-07-02 |
| 20090166756 | MOS Transistor and Semiconductor Integrated Circuit - A MOS transistor includes plural transistor cell blocks arranged adjacently in parallel to one another, wherein the plural transistor cell blocks are configured to have plural transistor cells, plural boundaries that are parallel to the plural transistor cells, and plural back gates arranged at the plural boundaries, each of the plural transistor cell blocks has two boundaries of the plural boundaries, wherein the plural transistor cells have a substantially striped shape, and each of the plural transistor cell blocks includes: at least one drain; plural sources; and plural extended gates, wherein each of the plural transistor cells is formed from one of the plural extended gates sandwiched by one of at least one drain and one of the plural sources, one of the plural sources is adjacent to one of two boundaries, and another one of the plural sources is adjacent to another one of two boundaries. | 2009-07-02 |
| 20090166757 | STRESS ENGINEERING FOR SRAM STABILITY - A design structure embodied in a machine readable medium is provided for use in the design, manufacturing, and/or testing of Ics that include at least one SRAM cell. In particular, the present invention provides a design structure of an IC embodied in a machine readable medium, the IC including at least one SRAM cell with a gamma ratio of about 1 or greater. In the present invention, the gamma ratio is increased with degraded pFET device performance. Moreover, in the inventive IC, there is no stress liner boundary present in the SRAM region and ion variation for all devices is reduced as compared to that of a conventional SRAM structure. The present invention provides a design structure of an IC embodied in a machine readable medium, the IC comprising at least one static random access memory cell including at least one nFET and at least one pFET; and a continuous relaxed stressed liner located above and adjoining the at least one nFET and the at least one pFET. | 2009-07-02 |
| 20090166758 | INTEGRATED CIRCUIT STRUCTURE WITH ELECTRICAL STRAP - A method of forming an IC is presented. The method includes providing a substrate having a plurality of transistors formed thereon. The transistors have gate stack, source and drain regions. An electrical strap is formed and in contact with at least a portion of at least one sidewall of the gate stack of a first transistor to provide a continuous electrical flowpath over a gate electrode of the first transistor and the source or drain region of a second transistor. | 2009-07-02 |
| 20090166759 | Transistor Having Raised Source/Drain Self-Aligned Contacts And Method Of Forming Same - A transistor structure and a method of forming same. The transistor structure includes: a semiconductor substrate having a gate-side surface; a gate disposed on the gate-side surface, the gate extending above the gate-side surface by a first height; a semiconductor extension disposed on the gate-side surface and extending above the gate-side surface by a second height larger than the first height, the semiconductor extension including a diffusion region having a diffusion surface located at the second height; and a diffusion contact element electrically coupled to the diffusion surface. | 2009-07-02 |
| 20090166760 | Semiconductor Device and Method of Manufacturing the Same - Disclosed are a semiconductor device and a manufacturing method thereof. The semiconductor device includes a gate electrode in a first trench in a semiconductor substrate, a ground area in a second trench facing the gate electrode, and source and drain areas in third and fourth trenches at ends of the gate electrode, respectively. A transistor having a micro-size is obtained, so that a semiconductor chip having a micro-size and a high integration degree may be realized. | 2009-07-02 |
| 20090166761 | FIELD EFFECT TRANSISTOR STRUCTURE WITH AN INSULATING LAYER AT THE JUNCTION - A method of making a FET includes forming a gate structure ( | 2009-07-02 |
| 20090166762 | MONITORING PATTERN OF SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A monitoring pattern of a semiconductor device and a method for fabricating the same, capable of increasing an area utilization rate. The monitoring pattern of a semiconductor device includes a gate electrode formed on a semiconductor substrate provided with an isolation film, a spacer formed on one sidewall of the gate electrode, an LDD region formed on the surface of the semiconductor substrate, a salicide formed over the entire surface of the semiconductor substrate in a region other than the region provided by the spacer, an interlayer dielectric film formed over the entire surface of the semiconductor substrate, contacts, each passing through the interlayer dielectric film arranged on the salicide, and a metal line arranged on the interlayer dielectric film, while being connected to the contacts. | 2009-07-02 |
| 20090166763 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Embodiments relate to a semiconductor device having a minimized on-resistance. According to embodiments, a semiconductor device may include at least one of the following: a first conductive type well formed on and/or over a semiconductor substrate, a second conductive type body region formed within the first conductive type well a first conductive type source region formed on and/or over the surface of the body region, a first conductive type drain region formed on and/or over the surface of the first conductive type well. Further, according to embodiments, a semiconductor device may include a field insulation layer positioned between the first conductive type source region and the first conductive type drain region and a gate electrode formed on and/or over the field insulation layer. The source region may be formed at a lower position than the drain region. | 2009-07-02 |
| 20090166764 | TRANSISTOR AND FABRICATING METHOD THEREOF - A transistor and fabricating method thereof includes sequentially forming a gate oxide layer and a poly gate over an active area of a semiconductor substrate, forming a drift region in the active area adjacent to the poly gate, and then forming a source/drain by simultaneously implanting impurity ions of various types into the drift region at a lower depth profile than that of the drift region. | 2009-07-02 |
| 20090166765 | MOS TRANSISTOR AND METHOD FOR MANUFACTURING THE TRANSISTOR - A MOS transistor and a method for manufacturing the transistor that may include forming a gate pattern on and/or over an active area of a semiconductor substrate defined as the active area and a field area, and silicide blocking films at each side of the gate pattern and partially over the uppermost surface of the gate pattern the silicide blocking films including first and second silicide blocking film portions formed spaced apart and extending in parallel to each other, and third and fourth silicide blocking film portions connected to the first and second silicide blocking film portions and formed spaced apart and extending in parallel to each other and perpendicular to the first and second silicide blocking film portions. With such a structural design, a high voltage transistor and middle voltage transistor having a reduced pitch size may be formed, thereby reducing the overall chip size. | 2009-07-02 |
| 20090166766 | METAL OXIDE SEMICONDUCTOR TRANSISTOR WITH Y SHAPE METAL GATE - A metal oxide semiconductor (MOS) transistor with a Y structure metal gate is provided. The MOS transistor includes a substrate, a Y structure metal gate positioned on the substrate, two doping regions disposed in the substrate on two sides of the Y structure metal structure, a spacer, an insulating layer positioned outside the spacer, a dielectric layer positioned outside the insulating layer and a bevel edge covering the spacer. The spacer has a vertical sidewall, and the vertical sidewall surrounds a recess. A part of the Y structure metal gate is disposed in the recess, and a part of the Y structure metal gate is positioned on the bevel edge. | 2009-07-02 |
| 20090166767 | Semiconductor device and method for manufacturing the same - It is possible to prevent the deterioration of device characteristic as much as possible. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided above the semiconductor substrate and containing a metal, oxygen and an additive element; a gate electrode provided above the gate insulating film; and source/drain regions provided in the semiconductor substrate on both sides of the gate electrode. The additive element is at least one element selected from elements of Group 5, 6, 15, and 16 at a concentration of 0.003 atomic % or more but 3 atomic % or less. | 2009-07-02 |
| 20090166768 | Semiconductor device with metal silicides having different phases - A fully silicided gate with a selectable work function includes a gate dielectric over the substrate, a first metal silicide layer over the gate dielectric, and a second metal silicide layer wherein the first metal silicide has a different phase then the second metal silicide layer. The metal silicide layers comprises at least one alloy element. The concentration of the alloy element on the interface between the gate dielectric and the metal silicide layers influence the work function of the gate. | 2009-07-02 |
| 20090166769 | METHODS FOR FABRICATING PMOS METAL GATE STRUCTURES - Methods of forming a microelectronic structure are described. Those methods may include forming a gate dielectric layer on a substrate, forming a metal gate layer on the gate dielectric layer, and then forming a polysilicon layer on the metal gate layer in situ, wherein the metal gate layer is not exposed to air. | 2009-07-02 |
| 20090166770 | METHOD OF FABRICATING GATE ELECTRODE FOR GATE OF MOSFET AND STRUCTURE THEREOF - A method of fabricating a gate electrode for a gate of a metal oxide semiconductor field effect transistor (MOSFET), where the transistor has a structure incorporating a gate disposed on a substrate. The substrate comprises a source-drain region. The gate includes a gate electrode disposed on a gate dielectric and surrounded by a spacer. The gate electrode includes a capping layer of polysilicon (poly-Si) and a thin polycrystalline intermixed silicon-germanium (SiGe) layer superposed on the gate dielectric. The thin polycrystalline intermixed silicon-germanium (SiGe) layer may be formed by a high-temperature ultrafast melt-crystalization annealing process. The melt-crystallization process of the intermixed silicon-germanium provides an active dopant concentration that reduces the width of a depletion region formed at an interface of the polycrystalline intermixed silicon-germanium (SiGe) layer and the gate dielectric. | 2009-07-02 |
| 20090166771 | DEVICE COMPRISING A SENSOR MODULE | 2009-07-02 |
| 20090166772 | MICRO-ELECTRO-MECHANICAL SYSTEMS (MEMS) DEVICE AND PROCESS FOR FABRICATING THE SAME - A micro-electro-mechanical systems (MEMS) device includes a back-plate substrate, having an intended region formed with a plurality of perforating holes. A first structural dielectric layer, disposed on the back-plate substrate, wherein the dielectric layer having an opening above the intended region. An etching stop layer, disposed over the first structural dielectric layer. A second structural dielectric layer, formed over the back-plate substrate. The etching stop layer and the second structural dielectric layer form at least a part of a micro-machine diaphragm, and cover over the opening of the first structural dielectric layer to form a chamber between the micro-machine diaphragm and the back-plate substrate. | 2009-07-02 |
| 20090166773 | Magnetic memory cell and magnetic random access memory - Provided is a reliable nonvolatile memory with a lower power consumption. A ferromagnetic interconnection which is magnetized antiparallel or parallel to a magnetization direction of a ferromagnetic pinned layer in a giant magnetoresistive device or a tunnel magnetoresistive device constituting the magnetic memory cell, is connected to a ferromagnetic free layer with a non-magnetic layer being interposed in between, the ferromagnetic free layer serving as a recording layer. Thereby, the magnetization of the recording layer is switched by use of a spin transfer torque. | 2009-07-02 |
| 20090166774 | WIRE BONDING METHOD AND SEMICONDUCTOR DEVICE - First and second semiconductor chips are arranged side by side on a package base. A plurality of electrode pads with exposed Al films are formed at regular intervals on the first and second semiconductor chips. An Au bump is formed on each electrode pad of the second semiconductor chip. Each electrode pad of the first semiconductor chip is paired with each electrode pad of the second semiconductor chip. The electrode pads of each pair are equally spaced, and interconnected with a gold wire by wire bonding. In the wire bonding process, ball bonding is performed to the electrode pad of the first semiconductor chip as a first target, and stitch bonding is performed to the Au bump on the electrode pad of the second semiconductor chip as a second target. | 2009-07-02 |
| 20090166775 | METHOD FOR MANUFACTURING IMAGE SENSOR - Embodiments relate to an image sensor and a method for manufacturing an image sensor. According to embodiments, a method may include forming a semiconductor substrate including a pixel part and a peripheral part, forming an interlayer dielectric film including a metal wire on and/or over the semiconductor substrate, forming photo diode patterns on and/or over the interlayer dielectric film and connected to the metal wire in the pixel part, forming a device isolation dielectric layer on and/or over the interlayer dielectric film including the photo diode patterns, forming a first via hole on and/or over the device isolation dielectric layer to partially expose the photo diode patterns, and forming a second via hole on and/or over the device isolation dielectric layer to expose the metal wire in the peripheral part. According to embodiments, vertical integration of transistor circuitry and a photo diode may be achieved. | 2009-07-02 |
| 20090166776 | IMAGE SENSOR AND FABRICATING METHOD THEREOF - An image sensor includes an insulating interlayer including a metal line on a semiconductor substrate, a photodiode pattern provided on the insulating interlayer to be connected to the metal line, the photodiode pattern separated per unit pixel by a gap area, a device isolation insulating layer provided on the insulating interlayer including the photodiode pattern and the gap area, a contact hole provided to the device isolation insulating layer to expose the photodiode pattern and a neighbor photodiode pattern, and a contact plug provided to the contact hole to be connected to a plurality of the photodiode patterns. | 2009-07-02 |
| 20090166777 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - Embodiments relate to an image sensor and a method of manufacturing an image sensor. According to embodiments, an image sensor may include a gate over a semiconductor substrate, a first impurity region over the semiconductor substrate, a second impurity region over the semiconductor substrate, the second impurity region being shallower than the first impurity region, and a third impurity region formed in the first impurity region, and bent toward the gate at a predetermined angle. According to embodiments, the third impurity region may be an n-type impurity region. According to embodiments, an area of a photodiode may be increased and a transfer efficiency of electrons generated from a photodiode may be increased. | 2009-07-02 |
| 20090166778 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - Embodiments relate to an image sensor and a method for manufacturing the same. According to embodiments, a semiconductor substrate may include a pixel part and a peripheral part. A photo diode pattern may be formed over the pixel part having a height that is greater than a height of a surface of an interlayer dielectric film over the peripheral part. A device isolation film and a metal layer may be provided over the photodiode and over interlayer dielectric film over the peripheral part. A planarization layer may be provided and may compensate for a height difference so that a first metal film pattern connected to the photo diode pattern and a second metal film pattern connected to the metal wire in peripheral part may be simultaneously formed by patterning the planarization layer and metal film. | 2009-07-02 |
| 20090166779 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - Embodiments relate to an image sensor and a method of manufacturing an image sensor. According to embodiments, an image sensor may include a first substrate, a photodiode, and an ion implantation isolation layer. According to embodiments, circuitry including a metal interconnection may be disposed over the first substrate. A photodiode may be provided in a crystalline semiconductor layer bonded to the first substrate, and electrically connected to the metal interconnection. The ion implantation isolation layer may be provided in the photodiode. | 2009-07-02 |
| 20090166780 | PROCESS FOR PRODUCING SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR SUBSTRATE FOR SOLAR APPLICATION AND ETCHING SOLUTION - Provided is: a process for producing safely at low cost a semiconductor substrate excellent in photoelectric transduction efficiency, in which a fine uneven structure suitable for a solar cell can be formed uniformly with desired size on the surface of the semiconductor substrate; a semiconductor substrate for solar application in which a uniform and fine pyramid-shaped uneven structure is provided uniformly within the surface thereof, and an etching solution for forming a semiconductor substrate having a uniform and fine uneven structure. A semiconductor substrate is etched with the use of an alkali etching solution containing at least one kind selected from the group consisting of carboxylic acids having a carbon number of 1 to 12 and having at least one carboxyl group in a molecule, and salts thereof, to thereby form an uneven structure on the surface of the semiconductor substrate. | 2009-07-02 |
| 20090166781 | EMI SHIELDING FOR IMAGER DEVICES - A module that provides EMI shielding for imager devices is disclosed which includes a die comprising an imager device and a plurality of contact pads, a stack positioned above the imager device, the stack comprising at least one lens, a conductive layer positioned above the stack, the conductive layer comprising at least one light opening, and a plurality of wire bonds, each of which conductively couples the conductive layer to one of the contact pads on the die. A method of providing EMI shielding for an imager module is also disclosed which includes conductively coupling a conductive layer of the module to a plurality of contact pads on an imager die and forming an encapsulant material that encapsulates at least the plurality of wire bonds, the conductive layer and the contact pads. | 2009-07-02 |
| 20090166782 | WAFER PROCESSING - Methods, devices, and systems for wafer processing are described herein. One method of wafer processing includes modifying a peripheral edge of a wafer to create a number of edge surfaces substantially perpendicular to a number of dicing paths and dicing the wafer along the number of dicing paths. In one or more embodiments, the method includes modifying the peripheral edge of the wafer with a first tool and dicing the wafer with a second tool different from the first tool. | 2009-07-02 |
| 20090166783 | SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING THE SAME, AND CAMERA AND ELECTRONIC APPARATUS USING THE SAME - A method of manufacturing a solid-state imaging device is provided. The method includes: forming an insulating layer extending over an effective pixel region where a plurality of pixels each having a photoelectric conversion element is arranged and a peripheral area adjacent to the effective pixel region; forming an opening in the insulating layer located immediately above the photoelectric conversion element on the effective pixel region; forming a dummy opening in the insulating layer on the peripheral region; and forming a buried layer on the insulating layer to fill the opening and the dummy opening formed in the insulating layer. | 2009-07-02 |
| 20090166784 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - Gold bumps are located over electrode pads of a solid imaging device and an adhesive is formed over the gold bumps. A transparent plate is supported by the gold bumps and is made to adhere over the solid imaging device by the adhesive. The gold bumps and an electrode and wiring pattern formed over a circuit board are connected by gold wires. At this time the gold wires are approximately parallel to the circuit board near portions where the gold wires and the gold bumps are connected. As a result, it is easy to locate the transparent plate over the portions where the gold wires and the gold bumps are connected. By locating the adhesive over the portions where the gold wires and the gold bumps are connected, the solid imaging device can be made small and light. As a result, a smaller lighter semiconductor device is fabricated. | 2009-07-02 |
| 20090166785 | Semiconductor Device with Optical Sensor and Method of Forming Interconnect Structure on Front and Backside of the Device - A semiconductor package has a semiconductor die with an optically active region which converts light to an electrical signal. An expansion region is formed around the semiconductor die. A through hole via (THV) is formed in the expansion region. Conductive material is deposited in the THV. A passivation layer is formed over the semiconductor die. The passivation layer allows for passage of light to the optically active region of the semiconductor die. A glass layer is applied to the passivation layer. A first RDL is electrically connected between the THV and a contact pad of the semiconductor die. Additional RDLs are formed on a front and back side of the semiconductor die. An under bump metallization (UBM) layer is formed over and electrically connected to the intermediate conduction layer. Solder material is deposited on the UBM and reflowed to form a solder bump. | 2009-07-02 |
