| 27th week of 2009 patent applcation highlights part 15 |
| Patent application number | Title | Published |
|---|
| 20090166586 | Long After-Glow Photoluminescent Material - The present invention provides a photoluminescent material comprising a composition of: aL. bm. cAL. dSi. pP. O. :fR Formula (I) wherein L is selected from Na and/or K; M is a divalent metal selected from one or more of the group consisting of Sr, Ca, Mg and Ba; Al, Si, P and O represent their respective elements; R is selected from one or more rare earth element activators; and wherein the variables a, b, c, d, p and f are: 0.0| 2009-07-02 | |
| 20090166587 | METHOD OF PREPARING FLUORESCENT BODY PRECURSOR - To produce fluorescent bodies providing high brightness and high energy efficiency, a method of preparing a fluorescent body precursor is provided to enable an activator having a large ionic radius to be doped arbitrarily. | 2009-07-02 |
| 20090166588 | Petroleum Coke Compositions for Catalytic Gasification - Particulate compositions are described comprising an intimate mixture of a petroleum coke, coal and a gasification catalyst, where the gasification catalyst is loaded onto at least the coal for gasification in the presence of steam to yield a plurality of gases including methane and at least one or more of hydrogen, carbon monoxide, and other higher hydrocarbons are formed. Processes are also provided for the preparation of the particulate compositions and converting the particulate composition into a plurality of gaseous products. | 2009-07-02 |
| 20090166589 | TRANSPARENT CONDUCTIVE SUBSTRATE - The invention provides a transparent conductive substrate using allyl ester heat-curable resin, comprising a compound having a group represented by formula (2) as terminus and a group represented by formula (3) as repeating unit, | 2009-07-02 |
| 20090166590 | FUSED THIOPHENE ACENES AND ORGANIC SEMICONDUCTORS MADE THEREFROM - This invention relates to fused thiophene acene compounds and their use in organic semiconductors. The compounds exhibit useful electronic properties such as high mobility and high on/off ratio. The compounds can be used in electronic devices such as field effect transistors (FETs), display devices, light-emitting diodes, photovoltaic cells, photo-detectors, and memory cells. Also provided are methods for making the fused thiophene acenes. | 2009-07-02 |
| 20090166591 | Thin Film Production - A method of producing a thin film comprising uniformly dispersed carbon nanotubes, the method comprising the steps of: adapting a molecular semiconductor to make it soluble; adapting the molecular semiconductor to facilitate the formation of a high degree of molecular order and frontier orbital overlap between adjacent molecules; adapting carbon nanotubes to make them soluble; combining the soluble carbon nanotubes and the soluble molecular semiconductor in a solvent to form a solution; producing the thin film from the solution. | 2009-07-02 |
| 20090166592 | Liquid mixture, structure, and method of forming structure - The present invention provides a structure composed substantially only of carbon nanotubes each having a functional group, the structure being obtained by using a liquid mix characterized by including: the carbon nanotubes; and a crosslinking agent capable of prompting a crosslinking reaction with the functional group. The structure has a network structure in which the carbon nanotubes are surely connected to each other. The present invention also provides a method of forming the structure. | 2009-07-02 |
| 20090166593 | Antistatic Thermoplastic Resin Composition - An antistatic thermoplastic resin composition includes a thermoplastic resin, an anionic antistatic agent, and a conductive metal oxide. The antistatic thermoplastic resin composition has enough antistatic properties to form various shapes of product, and it is particularly applicable for the production of housings of electro-electronic products or delivery trays for manufacturing an electro-electronic product. | 2009-07-02 |
| 20090166594 | 1,2-BIS(3-METHYLPHENOXY)ETHANE COMPOSITION AND THERMAL RECORDING MEDIA MADE BY USING THE SAME - In a thermal recording medium including a basic chromogenic dye, a developer and a sensitizer, a composition for a thermal recording medium which composition contains 50 ppm to 5.0 mass % of 1-(3-methylphenoxy)-2-(4-methylphenoxy)ethane and/or 1,2-bis(4-methylphenoxy)ethane in 1,2-bis(3-methylphenoxy)ethane is used as said sensitizer, whereby the 1,2-bis(3-methylphenoxy)ethane compound is remarkably improved in milling property in the preparation of the above sensitizer, and a thermal recording medium is provided without impairing the colorability, etc., such as thermal colorability. | 2009-07-02 |
| 20090166595 | ENHANCED CHEMILUMINESCENT LIGHTING FORMULATION AND ELEMENT - A chemiluminescent formulation includes an oxalate solution including a dye and an activator solution including polyethylene oxide. The oxalate solution and the activator solution are mixed to form a chemiluminescent mixture. Chemiluminescent energy in the form of light is emitted after mixing. The polyethylene oxide substantially increases the light output from the chemiluminescent mixture compared to a non-polyethylene oxide containing formulation. | 2009-07-02 |
| 20090166596 | Disposer installation tool - A tool is used to elevate and hold a garbage disposer against a sink fixture during removal and/or installation of a garbage disposer. The tool includes a flat base including a notch opening through a corner of a rectilinear base to allow an electric cord to pass around the tool. A flat load supporting platform includes a similar notch. A screw jack force applying mechanism allows the platform to be raised relative to the base. The tool works equally well with the base down or with the platform down so the user doesn't have to turn the tool over for it to work. | 2009-07-02 |
| 20090166597 | FIBER DROP INSTALLATION DEVICE - An optical fiber installation device may include a housing having a drop receiving channel extending therethrough. A drive wheel may be rotatably positioned in the housing and configured to rotatably engage a fiber optic drop provided in the drop receiving channel. The housing may include an air pathway for applying a first flow of pressurized air from an air source to the drive wheel. The first flow of pressurized air may cause the drive wheel to rotate and propel the fiber optic drop through the drop receiving channel. | 2009-07-02 |
| 20090166598 | METAL FENCE POST AND FENCE SYSTEM - A metal fence post for use with a wood fence system and a method of constructing a wood fence. The fence post comprises an elongated post member and a bracket attached thereto to support rails and pickets. The post member is of the type commonly available as vineyard posts and signposts, having a back wall and a pair of outwardly sloping sidewalls with short wing flanges attached thereto. The back wall and sidewalls form a channel. The bracket has a center section and a pair of outwardly sloping sidewalls that each have outwardly extended flanges. The flanges are generally in the same plane and in spaced apart relation to the center section. The center section of the bracket is received in the channel, placing the flanges in abutting relation with the wing flanges. A portion of the fence post is exposed so as to enhance the aesthetics of the fence. | 2009-07-02 |
| 20090166599 | Fence - A fence has a connecting member to join an upper fence and a lower fence together. The connecting member consists of an upper fastening bar transversely positioned on the bottom of each post of the up per fence, a lower fastening bar also transversely positioned on the top of each post of the lower fence, and a connecting tube that is cut with an inserting groove in its bottom and plural holes bored on its top respectively for each post of the upper fence to insert. Two positioning segments are formed inside the connecting tube to respectively fix with the upper fastening bar and the lower fastening bar. A connecting pin has its two ends respectively inserted into each post of the upper fence and also each post of the lower fence to keep the two posts joined together. Thus, the fence can be easily assembled and raised with its height without discarding original posts. | 2009-07-02 |
| 20090166600 | INTEGRATED CIRCUIT DEVICES HAVING A STRESS BUFFER SPACER AND METHODS OF FABRICATING THE SAME - Integrated circuit devices include an integrated circuit substrate and an insulating layer on the integrated circuit substrate. A contact hole penetrates the insulating layer. A vertical diode is in the contact hole and a stress buffer spacer is provided between the vertical diode and the insulating layer. Methods of forming the integrated circuit devices are also provided. | 2009-07-02 |
| 20090166601 | Non-volatile programmable variable resistance element - A phase-change memory element exhibits a non-uniform temperature profile in the phase-change material, resulting in a non-uniform temperature profile. The non-uniform temperature profile causes non-uniform growth of a programmed volume, resulting in a gradual R-I characteristic. The phase-change material may be a chalcogenide material. | 2009-07-02 |
| 20090166602 | PHASE-CHANGE MEMORY DEVICE CAPABLE OF IMPROVING CONTACT RESISTANCE AND RESET CURRENT AND METHOD OF MANUFACTURING THE SAME - A phase-change memory device and a method of manufacturing the same, wherein the phase-change memory device includes a semiconductor substrate having a switching device, a phase-change layer formed on the semiconductor substrate having the switching device to change a phase thereof as the switching device is driven, and a bottom electrode contact in contact with the switching device through a first contact area and in contact with the phase-change layer through a second contact area, which is smaller than the first contact area. | 2009-07-02 |
| 20090166603 | METHOD OF FORMING A SMALL CONTACT IN PHASE-CHANGE MEMORY - A method of fabricating a phase-change memory cell is described. The cross-sectional area of a contact with a phase-change memory element within the cell is controlled by a width and an exposed length of a bottom electrode. The method allows the formation of very small phase-change memory cells. | 2009-07-02 |
| 20090166604 | RESISTANCE TYPE MEMORY DEVICE - A resistance type memory device is provided. The resistance type memory device includes a first and a second conductors and a metal oxide layer. The metal oxide layer is disposed between the first and the second conductors, and the resistance type memory device is defined in a first resistivity. The resistance type memory device is defined in a second resistivity after a first pulse voltage is applied to the metal oxide layer. The resistance type memory device is defined in a third resistivity after a second pulse voltage is applied to the metal oxide layer. The second resistivity is greater than the first resistivity, and the first resistivity is greater than the third resistivity. | 2009-07-02 |
| 20090166605 | PHASE CHANGE MEMORY ELEMENTS USING SELF-ALIGNED PHASE CHANGE MATERIAL LAYERS AND METHOS OF MAKING AND USING SAME - A phase change memory element and method of forming the same. The memory element includes a substrate supporting a first electrode. An insulating material element is positioned over the first electrode, and a phase change material layer is formed over the first electrode and surrounding the insulating material element such that the phase change material layer has a lower surface that is in electrical communication with the first electrode. The memory element also has a second electrode in electrical communication with an upper surface of the phase change material layer. | 2009-07-02 |
| 20090166606 | Nitride Semiconductor Light Emitting Device and Fabrication Method Thereof - Provided is a nitride semiconductor light emitting device including: a first nitride semiconductor layer; an active layer formed above the first nitride semiconductor layer; and a delta doped second nitride semiconductor layer formed above the active layer. According to the present invention, the optical power of the nitride semiconductor light emitting device is enhanced, optical power down phenomenon is improved and reliability against ESD (electro static discharge) is enhanced. | 2009-07-02 |
| 20090166607 | Nitride Semiconductor Light Emitting Element - Provided is a nitride semiconductor light emitting element having an improved carrier injection efficiency from a p-type nitride semiconductor layer to an active layer by simple means from a viewpoint utterly different from the prior art. A buffer layer | 2009-07-02 |
| 20090166608 | Light emitting semiconductor device and fabrication method for the light emitting semiconductor device - A semiconductor light emitting device and a fabrication method for the semiconductor light emitting device whose outward luminous efficiency improved are provided and the semiconductor light emitting device includes a substrate; a protective film placed on the substrate; an n-type semiconductor layer which is placed on the substrate pinched by a protective film and on the protective film, and is doped with an n-type impurity; an active layer placed on the n-type semiconductor layer, and a p-type semiconductor layer placed on the active layer and is doped with a p-type impurity. | 2009-07-02 |
| 20090166609 | MEMORY CELL THAT EMPLOYS A SELECTIVELY FABRICATED CARBON NANO-TUBE REVERSIBLE RESISTANCE-SWITCHING ELEMENT FORMED OVER A BOTTOM CONDUCTOR AND METHODS OF FORMING THE SAME - In some aspects, a method of fabricating a memory cell is provided that includes (1) fabricating a first conductor above a substrate; (2) selectively fabricating a carbon nano-tube (CNT) material above the first conductor; (3) fabricating a diode above the CNT material; and (4) fabricating a second conductor above the diode. Numerous other aspects are provided. | 2009-07-02 |
| 20090166610 | MEMORY CELL WITH PLANARIZED CARBON NANOTUBE LAYER AND METHODS OF FORMING THE SAME - In some aspects, a method of fabricating a memory cell is provided that includes (1) fabricating a first conductor above a substrate; (2) fabricating a carbon nano-tube (CNT) material above the first conductor; (3) depositing a dielectric material onto a top surface of the CNT material; (4) planarizing the dielectric material to expose at least a portion of the CNT material; (5) fabricating a diode above the first conductor; and (6) fabricating a second conductor above the CNT material and the diode. Numerous other aspects are provided. | 2009-07-02 |
| 20090166611 | Organic Transistor and Manufacturing Method Thereof - [Problems] To provide an organic transistor which can achieve a reduced leak current from a gate electrode. | 2009-07-02 |
| 20090166612 | Techniques for Device Fabrication with Self-Aligned Electrodes - This invention relates to the fabrication of electronic devices, such as thin-film transistors, in particular thin-film transistors in which patterning techniques are used for definition of electrode patterns that need to be accurately aligned with respect to underlying electrodes. The fabrication technique is applicable to various patterning techniques, such as laser ablation patterning or solution-based, direct-write printing techniques which are not capable of forming structures with a small linewidth, and/or that cannot be positioned very accurately with respect to previously deposited patterns. We thus describe self-aligned gate techniques which are applicable for both gate patterning by a subtractive technique, in particular selective laser ablation patterning, and gate patterning by an additive technique such as printing. The techniques facilitate the use of low-resolution gate patterning. | 2009-07-02 |
| 20090166613 | Composition for Forming Gate Insulating Layer of Organic Thin-Film Transistor and Organic Thin Film Transistor Using the Same - The present invention relates to a composition for forming a gate insulating layer of an organic thin film transistor comprising polyarylate, and an organic thin film transistor comprising a gate insulating layer, which is formed using the composition, in contact with an organic semiconductor channel. | 2009-07-02 |
| 20090166614 | FLUORINATED RYLENETETRACARBOXYLIC ACID DERIVATIVES AND USE THEREOF - The present invention relates to fluorinated rylenetetracarboxylic acid derivatives, to a process for their preparation and to their use, especially as n-type semiconductors. | 2009-07-02 |
| 20090166615 | ORGANIC LIGHT-EMITTING ELEMENT AND DISPLAY DEVICE - An organic light-emitting element has an anode, a cathode, and a layer including an organic compound between the anode and the cathode. The layer including the organic compound has at least one tetracyano compound represented by at least one of Formula (1) or (2) below. | 2009-07-02 |
| 20090166616 | OXIDE SEMICONDUCTOR DEVICE AND SURFACE TREATMENT METHOD OF OXIDE SEMICONDUCTOR - Oxygen defects formed at the boundary between the zinc oxide type oxide semiconductor and the gate insulator are terminated by a surface treatment using sulfur or selenium as an oxygen group element or a compound thereof, the oxygen group element scarcely occurring physical property value change. Sulfur or selenium atoms effectively substitute oxygen defects to prevent occurrence of electron supplemental sites by merely applying a gas phase or liquid phase treatment to an oxide semiconductor or gate insulator with no remarkable change on the manufacturing process. As a result, this can attain the suppression of the threshold potential shift and the leak current in the characteristics of a thin film transistor. | 2009-07-02 |
| 20090166617 | INTEGRATED CIRCUIT AND METHOD FOR OPERATING - An integrated circuit and a method for operating an integrated circuit is disclosed. One embodiment provides a semi-conductor component, an electronic system, and a method for operating an integrated circuit. A method for operating an integrated circuit provides applying a voltage to a line or a connection in accordance with data to be input. A current is applied to the line or the connection in accordance with data to be output. | 2009-07-02 |
| 20090166618 | TEST STRUCTURE FOR MONITORING PROCESS CHARACTERISTICS FOR FORMING EMBEDDED SEMICONDUCTOR ALLOYS IN DRAIN/SOURCE REGIONS - By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished. | 2009-07-02 |
| 20090166619 | TEST PATTERN OF SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a test pattern for a semiconductor device includes the steps of forming, on a semiconductor substrate, a moat mask pattern including plural moat lines patterned in a comb-shape and etching a portion of the semiconductor substrate exposed by the moat mask pattern, to form a trench. The method further includes gap-filling the trench with an insulation material to form a field separator, planarizing the semiconductor substrate having the field separator formed thereon, and forming a poly comb pattern on the planarized semiconductor substrate. The poly comb pattern is formed such that the moat lines are arranged between lines of the poly comb pattern. | 2009-07-02 |
| 20090166620 | SEMICONDUCTOR CHIP - In a semiconductor chip in which external connection pads are arranged in three or more rows in a staggered configuration at the peripheral portion thereof, a first pad which is arranged in the outermost row is used as a power supply pad or a ground pad for an internal core circuit. To the first pad, a second pad which is arranged in the second outermost row is connected with a metal in the same layer as a pad metal. The resistance of a power supply line to the internal core circuit has a value of the parallel resistance of a resistance from the first pad and a resistance from the second pad, which is by far lower than the resistance from the first pad. Therefore, it is possible to prevent circuit misoperation resulting from an IR drop in the power supply of the internal core circuit. | 2009-07-02 |
| 20090166621 | RESISTANCE-BASED ETCH DEPTH DETERMINATION FOR SGT TECHNOLOGY - A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test portion of the material layer thereby defining a test structure that lies underneath the resist mask. The resist mask does not cover the trench. The material is isotropically etched and a signal related to a resistance change of the test structure is measured. A lateral undercut D | 2009-07-02 |
| 20090166622 | PLASMA PROCESSING APPARATUS AND SEMICONDUCTOR ELEMENT MANUFACTURED BY SUCH APPARATUS - When a flow rate of a diluent gas is larger than a flow rate of a reaction gas, a reaction gas introducing tube ( | 2009-07-02 |
| 20090166623 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A first interconnection is formed along a groove of a substrate and on a bottom surface of the groove, and has a first thickness. A second interconnection is electrically connected to the first interconnection and has a second thickness larger than the first thickness. An acceleration sensing unit is electrically connected to the second interconnection. A sealing unit has a portion opposed to the substrate with the first interconnection therebetween, and surrounds the second interconnection and the acceleration sensing unit on the substrate. A cap is arranged on the sealing unit to form a cavity on a region of the substrate surrounded by the sealing unit. Thereby, airtightness of the cavity can be ensured and also an electric resistance of the interconnection connected to the acceleration sensing unit can be reduced. | 2009-07-02 |
| 20090166624 | CRYSTALLIZATION APPARATUS, CRYSTALLIZATION METHOD, PHASE MODULATION ELEMENT, DEVICE AND DISPLAY APPARATUS - A phase modulation element according to the present invention has a first area having a first phase value based on a phase modulation unit having a predetermined size and a second area having a second phase value based on the phase modulation unit having the predetermined size, and each phase distribution is defined by a change in area shares of the first area and the second area depending on each position. | 2009-07-02 |
| 20090166625 | MOS DEVICE STRUCTURE - The present invention provides a method for forming a metal-oxide-semiconductor (MOS) device and the structure thereof. The method includes at least the steps of forming a silicon germanium layer by the first selective epitaxy growth process and forming a cap layer on the silicon germanium layer by the second selective epitaxy growth process. Hence, the undesirable effects caused by ion implantation can be mitigated. | 2009-07-02 |
| 20090166626 | PRODUCING METHOD FOR CRYSTALLINE THIN FILM - A method for producing a crystalline film by melting and resolidifying a film, characterized in preparing a film having a specific region and obtained either by (A) a step of forming a film in which a “specific region” and an “region continuous to a periphery of the specific region and different in thickness from the specific region” co-exist, or by (B) a step of irradiating a film with an electromagnetic wave or particles having a mass in mutually different conditions between a specific region and a peripheral region thereof, and melting and resolidifying at least a part of the film. As the spatial position of the specific region can be exactly and easily controlled, it is possible to obtain a crystalline film in which a crystal grain is formed in a desired position. | 2009-07-02 |
| 20090166627 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - An image sensor may include a first substrate having circuitry including wires and a silicon layer formed on and/or over the first substrate to selectively contact the wires. The image sensor may include photodiodes bonded to the first substrate while contacting the silicon layer and electrically connected to the wires. Each unit pixel may be implemented having complicated circuitry without a reduction in photosensitivity. Additional on-chip circuitry may also be implanted in the design. | 2009-07-02 |
| 20090166628 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - An image sensor includes a first substrate having a circuitry including a wire formed therein and a photodiode formed above the circuitry. An unevenness is formed at the top of the photodiode. The unevenness may, for example, be formed by selectively etching the top of the photodiode and may act to maximize light absorption by the photodiode. | 2009-07-02 |
| 20090166629 | REDUCING GATE CD BIAS IN CMOS PROCESSING - A method of forming an integrated circuit having an NMOS transistor and a PMOS transistor is disclosed. The method includes performing pre-gate processing in a NMOS region and a PMOS region over and/or in a semiconductor body, and depositing a polysilicon layer over the semiconductor body in both the NMOS and PMOS regions. The method further includes performing a first type implant into the polysilicon layer in one of the NMOS region and PMOS region, and performing an amorphizing implant into the polysilicon layer in both the NMOS and PMOS regions, thereby converting the polysilicon layer into an amorphous silicon layer. The method further includes patterning the amorphous silicon layer to form gate electrodes, wherein a gate electrode resides in both the NMOS and PMOS regions. | 2009-07-02 |
| 20090166630 | Array substrate of liquid crystal display and method for fabricating the same - A thin film transistor (TFT) for a liquid crystal display device includes a gate electrode, a source electrode, a drain electrode, an active region including a first semiconductor layer and a second semiconductor layer interposed within the first semiconductor layer, and an ohmic contact layer formed on the active region, wherein the source and drain electrodes are formed on the ohmic contact layer. | 2009-07-02 |
| 20090166631 | THIN FILM TRANSISTOR AND DISPLAY DEVICE INCLUDING THE SAME - One object of the present invention is reduction of off current of a thin film transistor. Another object of the present invention is improvement of electric characteristics of the thin film transistor. Further, another object of the present invention is improvement of image quality of the display device including the thin film transistor. The thin film transistor includes a semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or a conductive film which is provided over a gate electrode with the gate insulating film interposed therebetween and which is provided in an inner region of the gate electrode so as not to overlap with an end portion of the gate electrode, a film covering at least a side surface of the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film, a pair of wirings formed over the film covering the side surface of the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or the conductive film. | 2009-07-02 |
| 20090166632 | GATE DRIVER-ON-ARRAY STRUCTURE AND DISPLAY PANEL - A gate driver-on-array structure integrated in a display panel includes a bar-like conductive layer, a semiconductor layer, first conductive patterns, second conductive patterns, a first electrode line and a second electrode line. The bar-like conductive layer has a plurality of regions. The semiconductor layer is disposed within the regions of the bar-like conductive layer. The first conductive patterns and the second conductive patterns are disposed on the semiconductor layer and located within the regions. The bar-like conductive layer is located between the first electrode line and the second electrode line. The first electrode line and the second electrode line are respectively spaced from the bar-like conductive layer by a first distance and a second distance. The GOA structure has first connectors connected to the corresponding first conductive patterns and the first electrode line, and second connectors connected to the second conductive patterns and the second electrode line. | 2009-07-02 |
| 20090166633 | ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - In an array substrate capable of improving the quality of displayed images and a method for manufacturing the array substrate, the array substrate includes a base substrate, a first conductive pattern including a gate line and a first light-blocking pattern, a semiconductor layer overlapping the light-blocking pattern, a second conductive pattern including a data line and a storage line overlapping the first light-blocking pattern, and a pixel electrode overlapping the storage line to form a storage capacitor. The first conductive pattern may further include a second light-blocking pattern overlapping the semiconductor layer which is formed under the data line. The first and second light-blocking patterns block light proceeding toward the semiconductor layer formed under the storage line and under the data line, respectively, so that the semiconductor layer may be prevented from being excited by light energy. | 2009-07-02 |
| 20090166634 | PIXEL STRUCTURE AND MANUFACTURING METHOD THEREOF - A pixel structure including a gate, a gate dielectric layer, a patterned semiconductor layer having a channel area disposed above the gate, a patterned dielectric layer having an etching-stop layer disposed above the gate and a number of bumps, a patterned metal layer having a reflective pixel electrode, a source and a drain, an overcoat dielectric layer, and a transparent pixel electrode sequentially disposed on a substrate is provided. The source and the drain respectively cover portions of the channel area. The reflective pixel electrode connects the drain and covers the bumps to form an uneven surface. The overcoat dielectric layer disposed on a transistor constituted by the gate, the gate dielectric layer, the patterned semiconductor layer, the source and the drain has a contact opening exposing a portion of the reflective pixel electrode. The transparent pixel electrode is electrically connected to the reflective pixel electrode through the contact opening. | 2009-07-02 |
| 20090166635 | ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - An array substrate includes a base substrate, a gate line, a gate insulation layer, a data line, a thin-film transistor (“TFT”) and a pixel electrode. The gate line includes a gate covering line formed in a first direction on the base substrate and a gate main line protruded from the gate covering line. The gate insulation layer is formed on the base substrate to cover the gate line. The data line is formed on the gate insulation layer in a second direction crossing the first direction. The TFT is electrically connected to the gate line and the data line. The pixel electrode is electrically connected to the TFT. Therefore, a gate line is thicker than a gate covering line and a gate main line having a low resistance is further formed, so that a gate signal may be quickly transferred along the gate line without a signal delay. | 2009-07-02 |
| 20090166636 | THIN FILM TRANSISTOR, METHOD OF FABRICATING THE SAME, AND ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE HAVING THE TFT - A thin film transistor (TFT), a method of fabricating the same, and display device having the TFT of which the TFT includes a metal catalyst layer disposed on a substrate, a semiconductor layer disposed on the metal catalyst layer, a gate insulating layer disposed on the entire surface of the substrate, a gate electrode disposed on the gate insulating layer at a position corresponding to the semiconductor layer, an interlayer insulating layer disposed on the entire surface of the substrate, and source and drain electrodes disposed on the interlayer insulating layer and connected to the semiconductor layer, wherein the metal catalyst layer includes one of carbon, nitrogen, and halogen. The thin film transistor includes a poly-Si layer that may be formed to a smaller thickness than in conventional deposition methods thereby producing a TFT in which the remaining amount of metal catalyst in a semiconductor layer is reduced. | 2009-07-02 |
| 20090166637 | DISPLAY APPARATUS WITH STORAGE ELECTRODES HAVING CONCAVO-CONVEX FEATURES - A display apparatus includes a substrate; a first insulating layer formed on the substrate and having an upper surface including a concavo-convex area including one or more concave features and one or more convex features; a first storage electrode overlaying the upper surface and a side surface of the first insulating layer and having an upper surface including a concavo-convex area including one or more concave features and one or more convex features, each concave feature of the first storage electrode overlying at least one respective concave feature of the first insulating layer, each convex feature of the first storage electrode overlying at least one respective convex feature of the first insulating layer; a second insulating layer formed on the first storage electrode; and a second storage electrode formed on the second insulating layer which separates the second storage electrode from the underlying first storage electrode. | 2009-07-02 |
| 20090166638 | DISPLAY DEVICE AND ELECTRONIC DEVICE PROVIDED WITH THE SAME - An object is to suppress decrease in luminance and appearance of flicker of a still image and to control a threshold voltage of a transistor for driving an EL element even in a state where the EL element continues to emit light for a certain period. An n-channel transistor and a p-channel transistor are provided as driving transistors for driving a light-emitting element, and a polarity of a potential which is supplied from a data line is reversed every given period and supplied to gates of the driving transistors in each pixel, whereby the threshold voltages of the driving transistors are controlled and change of luminance of the light-emitting element due to the threshold voltage shifts of the driving transistors can be reduced. | 2009-07-02 |
| 20090166639 | ACTIVE FIELD EMISSION SUBSTRATE AND ACTIVE FIELD EMISSION DISPLAY - An active field emission substrate including a thin film transistor (TFT) substrate and a field emission device substrate is provided. The TFT substrate has a plurality of TFTs, and each TFT at least includes a source, a drain, and a gate. The field emission device substrate is disposed on the TFT substrate and has a plurality of conductive channels and a plurality of field emission sources. Each conductive channel passes through the field emission device substrate and is electrically connected with each field emission source. Moreover, each conductive channel in the field emission device substrate is electrically conducted with the source or the drain of each TFT in the TFT substrate. The active field emission substrate is made up of two substrates fabricated by separate processes, so the procedures can be simplified and the yield can be improved. | 2009-07-02 |
| 20090166640 | Copper wire, method for fabricating the same, and thin film transistor substrate with the same - The present invention relates to a copper wire in a semiconductor device in which a barrier layer is formed for improving adhesion of a copper wire without any additional fabricating step; a method for fabricating the same, and a flat panel display device with the same. The copper wire includes a barrier layer formed on an underlying structure, and a copper conductive layer on the barrier layer, wherein the barrier layer includes at least one of a Cu | 2009-07-02 |
| 20090166641 | Thin film transistor, method of fabricating a thin film transistor and flat panel display device having the same - A thin film transistor (TFT) includes a substrate, a transparent semiconductor layer on the substrate, the transparent semiconductor layer including zinc oxide and exhibiting a charge concentration of about 1×10 | 2009-07-02 |
| 20090166642 | Compound semiconductor epitaxial substrate and method for producing the same - There are provided a higher-performance compound semiconductor epitaxial substrate having improved electron mobility characteristics and its production method. The compound semiconductor epitaxial substrate includes a channel layer in which electrons travel and an epitaxial layer on each of a front side and a back side of the channel layer, wherein a total p-type carrier concentration A (/cm | 2009-07-02 |
| 20090166643 | LIGHT EMITTING AND IMAGE SENSING DEVICE AND APPARATUS - There is provided a light emitting and image sensing device for a scene. The device is formed in a semiconductor substrate and comprises a photosensor component for sensing an image of the scene. The photosensor component is responsive to incident light from the scene and provides an electrical signal representative of the image. There is also a photoemitter component for emitting a light signal representative of the electrical signal, and a coupling component connecting the photosensor component with the photoemitter component. | 2009-07-02 |
| 20090166644 | MONOLITHIC LIGHT EMITTING DEVICE AND DRIVING METHOD THEREFOR - A monolithic light-emitting device and driving method therefore includes a plurality of light-emitting diodes, array-arranged monolithically on a single substrate. Thie light-emitting diodes include a pn junction-containing semiconductor material and a phosphor-containing layer passing light emitted from the semiconductor material, absorbing part, or whole of the light for conversion into light having a different wavelength. The array is constituted of a light-emitting diode group consisting of m (m≧2) pieces of the light-emitting diode, the light emitting diode group being constituted of N types (N≧2, providing N≦m) of light-emitting diodes, each having either one of preset N types of light-emitting spectrum patterns. An average light-emitting spectrum from the whole array can be changed by regulating a power supplied to the light-emitting diodes for each light-emitting diode group sorted according to the type of the light-emitting spectrum pattern. | 2009-07-02 |
| 20090166645 | LIGHT EMITTING DIODE HAVING A THERMAL CONDUCTIVE SUBSTRATE AND METHOD OF FABRICATING THE SAME - Disclosed are a light emitting diode having a thermal conductive substrate and a method of fabricating the same. The light emitting diode includes a thermal conductive insulating substrate. A plurality of metal patterns are spaced apart from one another on the insulating substrate, and light emitting cells are located in regions on the respective metal patterns. Each of the light emitting cells includes a P-type semiconductor layer, an active layer and an N-type semiconductor layer. Meanwhile, metal wires electrically connect upper surfaces of the light emitting cells to adjacent metal patterns. Accordingly, since the light emitting cells are operated on the thermal conductive substrate, a heat dissipation property of the light emitting diode can be improved. | 2009-07-02 |
| 20090166646 | LIGHT-EMITTING ELEMENT HAVING PNPN-STRUCTURE AND LIGHT-EMITTING ELEMENT ARRAY - A light-emitting element including a light-emitting thyristor and a Schottky barrier diode is provided. A Schottky barrier diode is formed by contacting a metal terminal to a gate layer of a three-terminal light-emitting thyristor consisting of a PNPN-structure. A self-scanning light-emitting element array may be driven at 3.0V by using such a Schottky barrier diode as a coupling diode of a diode-coupled self-scanning light-emitting element array. | 2009-07-02 |
| 20090166647 | Multi-wavelength LED array package module and method for packaging the same - A method for packaging a multi-wavelength LED array package module includes: forming at least one concave groove on a drive IC structure; arranging a multi-wavelength LED array set in the at least one concave groove; solidifying a plurality of liquid conductive materials to form a plurality of conductive elements that is electrically connected between the drive IC structure and the multi-wavelength LED array set by a printing, a coating, a stamping, or a stencil printing process; arranging the drive IC structure on a PCB with at least one input/output pad; and then forming a conductive structure that is electrically connected between the drive IC structure and the at least one input/output pad. | 2009-07-02 |
| 20090166648 | Multi-wavelength light-emitting module with high density electrical connections - A multi-wavelength light-emitting module with high density electrical connections includes a drive IC structure and a multi-wavelength LED array structure. The drive IC structure has a drive IC unit formed on a top surface thereof. The multi-wavelength LED array structure is disposed on the top surface of the drive IC structure, and the multi-wavelength LED array structure has a conductive trace unit formed on an outer surface thereof and electrically connected to the drive IC unit. | 2009-07-02 |
| 20090166649 | Nitride Semiconductor Light Emitting Device and Fabrication Method Thereof - The present invention relates to a nitride semiconductor light emitting device including: a substrate having a predetermined pattern formed on a surface thereof by an etch; a protruded portion disposed on a non-etched region of the substrate, and having a first buffer layer and a first nitride semiconductor layer stacked thereon; a second buffer layer formed on the etched region of the substrate; a second nitride semiconductor layer formed on the second buffer layer and the protruded portion; a third nitride semiconductor layer formed on the second nitride semiconductor layer; an active layer formed on the third nitride semiconductor layer to emit light; and a fourth nitride semiconductor layer formed on the active layer. According to the present invention, the optical extraction efficiency of the nitride semiconductor light emitting device can be enhanced. | 2009-07-02 |
| 20090166650 | LIGHT-EMITTING DEVICE OF GROUP III NITRIDE-BASED SEMICONDUCTOR AND MANUFACTURING METHOD THEREOF - A light-emitting device of Group III nitride-based semiconductor comprises a substrate, a first Group III nitride layer and a second Group III nitride layer. The substrate comprises a first surface and a plurality of convex portions protruding from the first surface. Each convex portion is surrounded by a part of the first surface. The first Group III nitride layer is jointly formed by lateral growth starting at top surfaces of the convex portions. The second Group III nitride layer is formed on the first surface, wherein a thickness of the second Group III nitride layer is less than a height of the convex portion. Moreover, the first Group III nitride layer and the second Group III nitride layer are made of a same material. | 2009-07-02 |
| 20090166651 | LIGHT-EMITTING DEVICE WITH INORGANIC HOUSING - The present invention relates to a light-emitting device comprising at least one light-emitting diode, which emits light, and a housing arranged to receive at least a portion of said light. The housing comprises a translucent inorganic material and is provided with at least one recess, which comprises positioning and orientating means. The at least one light-emitting diode is arranged in the at least one recess and is positioned and orientated by said positioning and orientating means, and a translucent inorganic contact layer material is arranged between the at least one light-emitting diode and the housing in the at least one recess to receive at least portion of the light and to connect said light-emitting diode to said housing. | 2009-07-02 |
| 20090166652 | White LED, Backlight Using the Same, and Liquid Crystal Display Device - Disclosed are a white LED, which has color reproducibility comparable with that of a cold-cathode tube and improved brightness, and a backlight and a liquid crystal display device comprising the white LED. The white LED comprises at least one light emitting element selected from ultraviolet light emitting diodes, purple light emitting diodes, ultraviolet light emitting lasers, and purple light emitting lasers, and a phosphor layer. The phosphor layer comprises a green phosphor satisfying formula 1, a blue phosphor satisfying formula 2 or 3, and a red phosphor satisfying formula 4 or 5:
| 2009-07-02 |
| 20090166653 | INCORPORATING REFLECTIVE LAYERS INTO LED SYSTEMS AND/OR COMPONENTS - A light emitting apparatus includes a support having circuitry disposed thereon, at least one light emitting diode (LED) chip mounted on the support and in electrical communication with the circuitry and a reflective layer on the support adjacent the at least one chip. | 2009-07-02 |
| 20090166654 | LIGHT-EMITTING DIODE WITH INCREASED LIGHT EFFICIENCY - A novel light-emitting diode structure is proposed wherein the epitaxial layers are cleaved to micro-units to suppress transverse propagation of light generated in active layer and improve light extraction efficiency. Further enhancement in light output will be obtained by introducing a light extraction layer with microstructures or directly structuring the top surface of each micro-unit. Another advantage of the method is effective thermal dissipation due to the hollowed-out pattern and possible buried heat conductive materials. | 2009-07-02 |
| 20090166655 | LIGHT-EMITTING DIODE STRUCTURE - An LED structure includes a first conductive body, a first insulating body on the first conductive body, a second conductive body on the first insulating body, and an LED. The first conductive body has a conducting portion upward projected from the insulating body and the second conductive body, so that a conducting section at a top of the conducting portion is exposed at the insulating sleeve portion. The LED is mounted on the conducting section of the first conductive body and electrically connected to the second conductive body. With these arrangements, the LED structure may be mounted on a power supply board without the need of distinguishing the polarities of electrodes, and can therefore be easily mounted to and dismounted from the power supply board and be conveniently replaced when necessary. | 2009-07-02 |
| 20090166656 | LIGHT EMITTING DIODE - A light emitting diode (LED) ( | 2009-07-02 |
| 20090166657 | LIGHT EMITTING DEVICE - A light emitting device includes a substrate provided with a conductor wiring, a light emitting element mounted on the substrate and a light reflecting resin member configured and arranged to reflect light emitted from the light emitting element. The light emitting device also includes at least one of an electrically conductive wire electrically connecting the conductor wiring and the light emitting element, an exposed region of the substrate on which the conductor wiring is not disposed, and a protective element mounted on the conductor wiring. At least a part of the electrically conductive wire, the exposed region or the protective element is buried in the light reflecting resin member. | 2009-07-02 |
| 20090166658 | LIGHT EMITTING DIODES INCLUDING TWO REFLECTOR LAYERS - A light emitting diode includes a diode region having a gallium nitride based n-type layer, an active region and a gallium nitride based p-type layer. A first reflector layer is provided on the gallium nitride based p-type layer, and a second reflector layer is provided on the gallium nitride based n-type layer. Bonding layers, a mounting support, a wire bond and/or transparent oxide layers also may be provided. | 2009-07-02 |
| 20090166659 | High Efficiency Group III Nitride LED with Lenticular Surface - A light emitting diode is disclosed having a vertical orientation with an ohmic contact on portions of a top surface of the diode and a mirror layer adjacent the light emitting region of the diode. The diode includes an opening in the mirror layer beneath the geometric projection of the top ohmic contact through the diode that defines a non-contact area between the mirror layer and the light emitting region of the diode to encourage current flow to take place other than at the non-contact area to in turn decrease the number of light emitting recombinations beneath the ohmic contact and increase the number of light emitting recombinations in the more transparent portions of the diode. | 2009-07-02 |
| 20090166660 | Lead frame for LED - A lead frame for LED is disclosed to include a body defining an accommodation chamber, a first bracket frame that has a first bottom base mounted in the accommodation chamber and a first connection leg and a second connection respectively extended from the first bottom base to the outside of the body and bent into shape, and a second bracket frame that has a second bottom base mounted in the accommodation chamber and a third connection leg and a fourth connection leg respectively extended from the second bottom base to the outside of the body and bent into shape. | 2009-07-02 |
| 20090166661 | Light-emitting diode packaging structure and module and assembling method thereof - A light-emitting diode packaging structure, a packaging module and the assembling method thereof are disclosed. The assembling method comprises the steps of: providing a light-emitting diode, wherein the light-emitting diode has two electrode leads; providing two metal plates, wherein each of the metal plates has at least a clamping portion; holding the electrode leads against the metal plates respectively; and bending the clamping portion of each of the metal plates to fix the electrode leads on the metal plates. Further, a plurality of light-emitting diodes are allowed to be mounted on the metal plates to form the light-emitting diode packaging module. | 2009-07-02 |
| 20090166662 | III-Nitride Semiconductor Light Emitting Device - The present disclosure relates to a III-nitride semiconductor light emitting device comprising: a plurality of III-nitride semiconductor layers with an active layer generating light by recombination of holes and electrons; and a branch electrode provided with an arm extended from the p-side bonding pad toward the n-side electrode and two fingers branched off toward the n-side electrode from the arm. | 2009-07-02 |
| 20090166663 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A nitride semiconductor light-emitting device includes, a support substrate | 2009-07-02 |
| 20090166664 | HIGH POWER LIGHT EMITTING DIODE PACKAGE AND MANUFACTURING METHOD THEREOF - There is provided a high power LED package and a method of manufacturing the same. The method includes: forming at least one chip mounting part and at least one through hole in a metal plate; forming an insulating layer of a predetermined thickness on an entire outer surface of the metal plate; forming an electrode part to be electrically connected to a light emitting chip mounted on the chip mounting part; and cutting the metal plate along a trimming line to separate the package. The LED package is free from thermal impact resulting from different thermal coefficients among components, thus ensuring stable heat radiation characteristics in a high temperature atmosphere. Also, the LED package is minimized in optical loss to improve optical characteristics. In addition, the LED package is simplified in a manufacturing and assembly process and thus can be manufactured in mass production at a lower cost. | 2009-07-02 |
| 20090166665 | Encapsulated optoelectronic device - The invention provides an optoelectronic device (e.g. a LED device) and method thereof. The device includes an optoelectronic component at least partially surrounded by an encapsulant comprising a silicone such as an aliphatic silicone and an adhesion promoter. The optoelectronic device exhibits improved properties such as adhesion and structural integrity, UV and thermal stability, and long term stability under accelerated aging conditions. | 2009-07-02 |
| 20090166666 | Semiconductor device - An exemplary semiconductor device is provided. The semiconductor device includes a semiconductor stacked layer and a conductive structure. The conductive structure is located on the semiconductor stacked layer. The conductive structure includes a bottom portion and a top portion on opposite sides thereof. The bottom portion is in contact with the semiconductor stacked layer. A ratio of a top width of the top portion to a bottom width of the bottom portion is less than 0.7. The conductive structure can be a conductive dot structure or a conductive line structure. | 2009-07-02 |
| 20090166667 | Substrate for Light-Emitting Diode, and Light-Emitting Diode - A substrate for light-emitting diodes, which uses no fluorescent powder, enables formation of a good light-emitting diode element, resulting in less deterioration, transmits light of the light-emitting diode element, emits light by utilizing a part of the transmitted light, and allows the transmitted light and newly emitted light to be mixed and emitted, is provided. | 2009-07-02 |
| 20090166668 | Nitride Semiconductor Light Emitting Device - There is provided a nitride semiconductor light emitting device having high internal quantum efficiency by accelerating recombination radiation while employing a multiple quantum well structure in which each of well layers has a relatively large thickness. The nitride semiconductor light emitting device is provided with a nitride semiconductor lamination portion ( | 2009-07-02 |
| 20090166669 | NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A nitride semiconductor light emitting device and a method of manufacturing the same, which can prevent crystal defects such as dislocation while ensuring uniform current spreading into an active layer. The nitride semiconductor light emitting device includes a first n-nitride semiconductor layer formed on a substrate, a first intermediate pattern layer formed on the first n-nitride semiconductor layer, the first intermediate pattern layer having a nanoscale dot structure made of Si compound, a second n-nitride semiconductor layer formed on the first n-nitride semiconductor layer, a second intermediate pattern layer formed on the second n-nitride semiconductor layer, the second intermediate pattern layer having a nanoscale dot structure made of Si compound, which is electrically insulating, a third n-nitride semiconductor layer formed on the second n-nitride semiconductor layer, an active layer formed on the third n-nitride semiconductor layer, and a p-nitride semiconductor layer formed on the active layer. | 2009-07-02 |
| 20090166670 | Anthracene-based compound and organic light emitting device employing the same - Provided are an anthracene-based compound represented by Formula 1 or 2 and an organic light emitting device employing the same: | 2009-07-02 |
| 20090166671 | ESD protection circuit - The present invention relates a technique using a silicon controlled rectifier (SCR) in a rail based non-breakdown (RBNB) ESD protection device that protects a micro chip from ESD stress. | 2009-07-02 |
| 20090166672 | Sawtooth electric field drift region structure for power semiconductor devices - This invention discloses a semiconductor power device formed in a semiconductor substrate. The semiconductor power device further includes rows of multiple horizontal columns of thin layers of alternate conductivity types in a drift region of the semiconductor substrate where each of the thin layers having a thickness to enable a punch through the thin layers when the semiconductor power device is turned on. In a specific embodiment the thickness of the thin layers satisfying charge balance equation q*N | 2009-07-02 |
| 20090166673 | Lateral Bipolar Transistor With Compensated Well Regions - Conduction between source and drain or emitter and collector regions is an important characteristic in transistor operation, particularly for lateral bipolar transistors. Accordingly, techniques that can facilitate control over this characteristic can mitigate yield loss by promoting the production of transistors that have an increased likelihood of exhibiting desired operational performance. As disclosed herein, well regions are established in a semiconductor substrate to facilitate, among other things, control over the conduction between the source and drain regions of a lateral bipolar transistor, thus mitigating yield loss and other associated fabrication deficiencies. Importantly, an additional mask is not required in establishing the well regions, thus further mitigating (increased) costs associated with promoting desired device performance. | 2009-07-02 |
| 20090166674 | Ultraviolet light receiving element - In an ultraviolet light receiving element using a group III nitride semiconductor, the ultraviolet light receiving element having an enhanced light receiving sensitivity is provided. An electron is excited from a valence band to a conduction band | 2009-07-02 |
| 20090166675 | STRAIN ENGINEERING IN SEMICONDUCTOR COMPONENTS - This disclosure relates to strain engineering to improve the performance of semiconductor components that include a strained region of the semiconductor substrate. The disclosure involves the amorphization of the target region and the recrystallization of the atomic lattice whilst imposing a strain on the region. The region so formed will form a strained lattice, wherein the strain is uniformly distributed throughout the region, and which retains the intrinsic strain even if the source of the mechanical strain is removed. The disclosure includes methods for forming semiconductor substrates having strained regions (such as semiconductor components having a strained channel region) and semiconductor components formed thereby, as well as variations having various properties and advantages. | 2009-07-02 |
| 20090166676 | SIGE DEVICE WITH SIGE-EMBEDDED DUMMY PATTERN FOR ALLEVIATING MICRO-LOADING EFFECT - A semiconductor device with dummy patterns for alleviating micro-loading effect includes a semiconductor substrate having thereon a middle annular region between an inner region and an outer region; a SiGe device on the semiconductor substrate within the inner region; and a plurality of dummy patterns provided on the semiconductor substrate within the middle annular region. At least one of the dummy patterns contains SiGe. | 2009-07-02 |
| 20090166677 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a semiconductor substrate; a diode having a cathode formed on a first surface side of the semiconductor substrate and an anode formed on a second surface side of the semiconductor substrate; and a transistor formed over the semiconductor substrate. The transistor includes a semiconductor layer laminate formed over the semiconductor substrate, a source electrode and a drain electrode that are formed spaced apart from each other over the semiconductor layer laminate, and a gate electrode formed between the source electrode and the drain electrode. The source electrode is electrically connected to the anode, and the drain electrode is electrically connected to the cathode. | 2009-07-02 |
| 20090166678 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device | 2009-07-02 |
| 20090166679 | INTEGRATED CIRCUIT AND MANUFACTURING PROCESS FACILITATING SELECTIVE CONFIGURATION FOR ELECTROMAGNETIC COMPATIBILITY - An integrated circuit (IC) having a selectively-designated electromagnetic compatibility (EMC) performance characteristic. The IC includes an IC die having an input or output (I/O) node. A first I/O cell of a first type associated with the I/O node provides a first EMC performance characteristic, and a second I/O cell of a second type associated with the I/O node provides a second EMC performance characteristic different from the first EMC performance characteristic. A first bonding pad is electrically coupled with the first I/O cell, and a second bonding pad is electrically coupled with the second I/O cell. The IC die can be packaged into a packaged IC having an I/O pin corresponding to the I/O node. The I/O pin is wired to one of either the first bonding pad or the second bonding pad, but not to the other, such that a pinout for the I/O node is preferentially provided having one of either the first EMC performance characteristic or the second EMC performance characteristic. | 2009-07-02 |
| 20090166680 | Unity beta ratio tri-gate transistor static radom access memory (SRAM) - In general, in one aspect, a method includes forming N-diffusion and P-diffusion fins in a semiconductor substrate. A P-diffusion gate layer is formed over the semiconductor substrate and removed from the N-diffusion fins. A pass-gate N-diffusion gate layer is formed over the semiconductor substrate and removed from the P-diffusion fins and pull-down N-diffusion fins. A pull-down N-diffusion layer is formed over the semiconductor substrate. | 2009-07-02 |
| 20090166681 | MOS Transistor and Semiconductor Device - According to one embodiment of the present invention, a MOS transistor includes a semiconductor layer including a source region, a drain region, and a channel region disposed between the source region and the drain region. A gate structure is arranged above the channel regions. A source wiring structure is arranged above the source region and is connected to the source region. A drain wiring structure is arranged above the drain region and is connected to the drain region. The width of the source wiring structure is larger than the width of the drain wiring structure, and the height of the source wiring structure is smaller than the height of the drain wiring structure, or vice versa. | 2009-07-02 |
| 20090166682 | METHODS AND APPARATUS FOR FORMING MEMORY LINES AND VIAS IN THREE DIMENSIONAL MEMORY ARRAYS USING DUAL DAMASCENE PROCESS AND IMPRINT LITHOGRAPHY - The present invention provides systems, apparatus, and methods for forming three dimensional memory arrays using a multi-depth imprint lithography mask and a damascene process. An imprint lithography mask for manufacturing a memory layer in a three dimensional memory is described. The mask includes a translucent material formed with features for making an imprint in a transfer material to be used in a damascene process, the mask having a plurality of imprint depths. At least one imprint depth corresponds to trenches for forming memory lines and at least one depth corresponds to holes for forming vias. Numerous other aspects are disclosed. | 2009-07-02 |
| 20090166683 | FLEXIBLE LAYOUT FOR INTEGRATED MASK-PROGRAMMABLE LOGIC DEVICES AND MANUFACTURING PROCESS THEREOF - Integrated mask-programmable device, having a plurality of metal levels including a top metal level, a bottom metal level and a first intermediate metal level formed between the top and bottom metal levels, and a plurality of via levels arranged between the bottom and the first intermediate metal levels and between the first intermediate and the top metal levels and connecting each metal level to adjacent metal levels. The plurality of metal levels forms a first, a second and at least a third terminal, the top and bottom metal levels having at least two metal regions, and the first intermediate metal level having at least three metal regions. The first terminal is connected to third terminal or the second terminal is connected to the third terminal by modifying a single metal or via level. | 2009-07-02 |
| 20090166684 | PHOTOGATE CMOS PIXEL FOR 3D CAMERAS HAVING REDUCED INTRA-PIXEL CROSS TALK - A CMOS photodetector pixel formed of a substrate, an epitaxial layer above the substrate including a first region having the same polarity but a lower impurity concentration as that of the substrate, and a gate arrangement including a first gate that forms a charge accumulation region in the epitaxial layer when the gate is energized, wherein the charge accumulation region extends deeper toward the substrate than in conventional constructions. The epitaxial layer includes a shielding structure for absorbing electrons generated therein by photons impinging on the pixel, except electrons generated close to the charge accumulation region. The shielding structure may have opposite polarity from that of the substrate, including a first portion under the first gate, and a second portion extending upward from the first portion at the margin of the pixel. Alternatively, the shielding structure may have the same polarity as the substrate, but a lower impurity concentration. | 2009-07-02 |
| 20090166685 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to one embodiment includes: a semiconductor substrate; a first impurity diffusion suppression layer formed on the semiconductor substrate for suppressing diffusion of a channel impurity; an impurity channel layer formed on the first impurity diffusion suppression layer and containing the channel impurity; a second impurity diffusion suppression layer formed on the impurity channel layer for suppressing diffusion of the channel impurity; a channel layer formed on the second impurity diffusion suppression layer; a gate insulating film formed on the channel layer; and a gate electrode formed on the gate insulating film. | 2009-07-02 |
