26th week of 2021 patent applcation highlights part 62 |
Patent application number | Title | Published |
20210201935 | SYSTEMS AND METHODS TO DETERMINE WHETHER TO UNMUTE MICROPHONE BASED ON CAMERA INPUT - In one aspect, a device includes at least one processor and storage accessible to the at least one processor. The storage includes instructions that may be executable by the at least one processor to receive input from a camera in communication with the at least one processor and to determine, based on the input from the camera, whether a user is currently speaking. The instructions may also be executable to present a notification regarding whether to unmute at least one microphone accessible to the at least one processor responsive to a determination that the user is currently speaking. | 2021-07-01 |
20210201936 | BACKGROUND NOISE ESTIMATION AND VOICE ACTIVITY DETECTION SYSTEM - A method includes selecting a frame of an audio signal. The method further includes determining a first power spectral density (PSD) distribution of the frame. The method further includes generating a first reference PSD distribution indicating an estimate of background noise in the frame based on a non-linear weight, a second reference PSD distribution of a previous frame of the audio signal, and a second PSD distribution of the previous frame. The method further includes determining whether voice activity is detected in the frame based on the first PSD distribution of the frame and the first reference PSD distribution. | 2021-07-01 |
20210201937 | ADAPTIVE DETECTION THRESHOLD FOR NON-STATIONARY SIGNALS IN NOISE - Techniques for target input detection, including receiving input data, dividing the input data into data blocks, determining a detection feature value for a first data block, determining a detection threshold based on a set of detection feature statistics determined for a background sampling time period, and determining a target signal has been received based on a comparison between the detection feature value for the first data block to the detection threshold. | 2021-07-01 |
20210201938 | REAL-TIME PITCH TRACKING BY DETECTION OF GLOTTAL EXCITATION EPOCHS IN SPEECH SIGNAL USING HILBERT ENVELOPE - A technique, suitable for real-time processing, is disclosed for pitch tracking by detection of glottal excitation epochs in speech signal. It uses Hilbert envelope to enhance saliency of the glottal excitation epochs and to reduce the ripples due to the vocal tract filter. The processing comprises the steps of dynamic range compression, calculation of the Hilbert envelope, and epoch marking. The Hilbert envelope is calculated using the output of a FIR filter based Hilbert transformer and the delay-compensated signal. The epoch marking uses a dynamic peak detector with fast rise and slow fall and nonlinear smoothing to further enhance the saliency of the epochs, followed by a differentiator or a Teager energy operator, and amplitude-duration thresholding. The technique is meant for use in speech codecs, voice conversion, speech and speaker recognition, diagnosis of voice disorders, speech training aids, and other applications involving pitch estimation. | 2021-07-01 |
20210201939 | AUTOMATIC TONEARM LIFTER - An automatic tonearm lifter for use in a turntable that includes a main body and a tonearm rotatably mounted on the main body. The tonearm lifter includes a casing adapted to be fixedly mounted to the main body of the turntable, a lifting unit adapted to be mounted to the main body, adapted for supporting the tonearm, movable relative to the casing along a vertical axis, and non-rotatable about the axis relative to the casing, and a rotating unit including a threaded seat that is rotatable about the axis and that is threadably engaging the lifting unit, and a driving module that is connected to the threaded seat and that is operable to drive rotation thereof, thereby moving the lifting unit along the axis. | 2021-07-01 |
20210201940 | MAGNETIC DISK DEVICE AND WRITE PROCESSING METHOD - According to one embodiment, a magnetic disk device includes a disk having a first area, and a second area to which data is temporary written, a head including a write head which writes data to the disk, and an assisting element which generates energy which improves write performance of the write head, and a controller which writes data to the first area by supplying energy having a first value to the assisting element, and writes data to the second area by supplying energy having a second value different from the first value to the assisting element. | 2021-07-01 |
20210201941 | MAGNETIC HEAD SLIDER, MAGNETIC HEAD ASSEMBLY AND MAGNETIC DISC DEVICE - According to one embodiment, a magnetic head slider includes a slider body, a magnetic recording/reproducing element provided on the slider body, a thermally conductive first protective layer provided on at least a part of a total of air bearing surfaces of the slider body and the magnetic recording/reproducing element, having a thermal conductivity of 200 W/(m·K) or higher and a second protective layer provided on the first protective layer. | 2021-07-01 |
20210201942 | NEAR FIELD TRANSDUCERS INCLUDING PLATINUM GROUP ALLOYS - Heat assisted magnetic recording (HAMR) devices that includes a near field transducer, the near field transducer including alloys of a first element selected from: platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), and osmium (Os); and a second element selected from; hafnium (Hf), niobium (Nb), tantalum (Ta), titanium (Ti), vanadium (V), and zirconium (Zr). | 2021-07-01 |
20210201943 | Magnetic Sensor Array with Single TMR Film Plus Laser Annealing and Characterization - The present disclosure generally relates to a Wheatstone bridge array that has four resistors. Each resistor includes a plurality of TMR films. Each resistor has identical TMR films. The TMR films of two resistors have reference layers that have an antiparallel magnetic orientation relative to the TMR films of the other two resistors. To ensure the antiparallel magnetic orientation, the TMR films are all formed simultaneously and annealed in a magnetic field simultaneously. Thereafter, the TMR films of two resistors are annealed a second time in a magnetic field while the TMR films of the other two resistors are not annealed a second time. | 2021-07-01 |
20210201944 | MAGNETIC RECORDING MEDIUM AND MAGNETIC STORAGE DEVICE - A magnetic recording medium includes a substrate; a soft magnetic underlayer laminated on the substrate; an amorphous barrier layer laminated on the soft magnetic underlayer; and a magnetic recording layer laminated on the amorphous barrier layer, wherein the soft magnetic underlayer includes Fe, B, Si, and one or more elements selected from the group consisting of Nb, Zr, Mo, and Ta, wherein the amorphous barrier layer includes Si, W, and one or more elements selected from the group consisting of Nb, Zr, Mo, and Ta, and wherein the magnetic recording layer includes an alloy having an L1 | 2021-07-01 |
20210201945 | MAGNETIC TAPE, MAGNETIC TAPE CARTRIDGE, AND MAGNETIC TAPE APPARATUS - A magnetic tape in which a minimum value of TDStens among five TDStens measured respectively at a temperature of 16° C. and a relative humidity of 20%, a temperature of 16° C. and a relative humidity of 80%, a temperature of 26° C. and a relative humidity of 80%, a temperature of 32° C. and a relative humidity of 20% and a temperature of 32° C. and a relative humidity of 55% is 1.43 μm/N or more, a ratio of a change of TDStens to a change of a relative humidity obtained from the five TDStens is 0.005 μm/N/% or less, and a ratio of a change of TDStens to a change of a temperature obtained from the five TDStens is 0.020 μm/N/° C. or less. | 2021-07-01 |
20210201946 | ALUMINIUM ALLOY SUBSTRATE FOR MAGNETIC DISK, METHOD FOR FABRICATING THE SAME, AND MAGNETIC DISK COMPOSED OF ALUMINIUM ALLOY SUBSTRATE FOR MAGNETIC DISK - Provided is an aluminium alloy substrate for a magnetic disk, a method for fabricating the substrate, and a magnetic disk composed of the aluminium alloy substrate for a magnetic disk. The substrate contains an aluminium alloy composed of one or more elements selected from a group comprising 0.05 to 3.00 mass % (hereinafter abbreviated as “%”) of Fe, 0.05% to 3.00% of Mn, 0.05% to 18.00% of Si, 0.05% to 8.00% of Ni, 0.05% to 3.00% of Cr, and 0.05% to 3.00% of Zr, with a balance of Al and unavoidable impurities. The substrate has a Young modulus of 67 GPa or more in each of the 0° direction, 45° direction, and 90° direction relative to the rolling direction of the substrate. | 2021-07-01 |
20210201947 | MAGNETIC RECORDING MEDIUM, METHOD OF MANUFACTURING MAGNETIC RECORDING MEDIUM AND MAGNETIC STORAGE DEVICE - The present invention relates to a magnetic recording medium including a substrate; an underlayer laminated upon the substrate; and a magnetic layer laminated upon the underlayer, wherein the underlayer includes a first underlayer containing a compound represented by a following general formula: MgO | 2021-07-01 |
20210201948 | HOLOGRAPHIC DATA STORAGE DEVICE WITH SINGLE-ARM STRUCTURE - The present invention relates to a holographic data storage device with a single-arm structure, and belongs to the technical field of optical holographic storage. According to the device disclosed in the present invention, a part of a reference arm and a part of a signal arm are integrated together to form a single-arm structure, which can not only reduce the number of optical and mechanical elements, but also reduce the system volume and cost without degrading performance. In addition, a signal beam and a reference beam share the same relay lens, so that the impact of environmental interference on the two beams is equal, and the stability of the entire system is improved. | 2021-07-01 |
20210201949 | MULTIPLEXING METHOD FOR INCREASING STORAGE CAPACITY IN DISC-TYPE HOLOGRAPHIC STORAGE MEDIUM - The present invention relates to the technical field of holographic multiplexing storage, and in particular, to a multiplexing method for increasing storage capacity in a disc-type holographic storage medium. According to the method disclosed by the present invention, holograms with different grating vector directions can be overwritten and recorded in the same storage medium according to Bragg selection characteristics of volume holographic records, and the obtained holograms do not affect each other. According to the method disclosed by the present invention, on the premise of ensuring low crosstalk between data pages, the multiplexing number of shift multiplexing storage is increased by using a cross-shift multiplexing method, and the storage density is improved. | 2021-07-01 |
20210201950 | Holographic multiplexed recording method for increasing storage capacity - A holographic multiplexed recording method for increasing storage capacity is disclosed. In a holographic recording and reproducing device, the moving direction of a storage medium is not coplanar with the plane where the optical axes of signal light and reference light are located, or the relative moving direction of the storage medium and the signal light or the reference light is not coplanar with the plane where the optical axes of the signal light and the reference light are located. Through the method, a certain angle exists between the grating vector direction and the moving direction or the relative moving direction, so that the phenomenon that the grating vector directions are the same does not occur when the medium is subjected to multiplexed recording after being rotated or flipped. Not only is multiplexing number increased, but also crosstalk caused by the same grating vector direction is prevented. | 2021-07-01 |
20210201951 | STORAGE APPARATUS - A storage apparatus includes a disk-shaped recording medium, a motor configured to drive and rotate the recording medium, a head configured to read information from and write information to the recording medium, and a support member configured to support the recording medium when the recording bends in response to external vibration or shock. The support member supports the recording medium by making contact with the recording medium only when the external vibration or shock is applied to the storage apparatus. | 2021-07-01 |
20210201952 | VIDEO RECORDING METHOD AND DEVICE - Embodiments of the present application provide a video recording method and device. The method includes: receiving, by an application of a mobile terminal, a video recording instruction of a user; generating, according to a photographing scene, a video stream that can be edited according to segments, the video stream including at least one frame sequence segment; and uploading the edited video stream to a server. According to the present application, by generating a video stream consisting of at least one frame sequence segment during video recording, where the generated video stream can be edited according to segments, the error tolerance of video capture is improved, and the costs of later video editing are reduced. | 2021-07-01 |
20210201953 | IMAGE PROCESSING APPARATUS, IMAGE PROCESSING METHOD, AND PROGRAM - To realize a natural image effect and the like in a moving image. Therefore, an image processing unit includes an additional image generation unit configured to generate an additional image to be added to moving image data, and an image editing processing unit configured to perform image editing processing of adding the additional image to the moving image data, using depth information of a pixel in the moving image data to which the additional image is to be added. | 2021-07-01 |
20210201954 | MULTI-WINDOW VIEWING SYSTEM INCLUDING EDITOR FOR REACTION VIDEO AND METHOD FOR PRODUCING REACTION VIDEO BY USING SAME - A multi-window viewing system according to an embodiment includes an editor for a reaction video and a player for reproducing the reaction video generated therefrom, in which the editor including a video image input unit that inputs a first video image for producing a reaction video, a video image information input unit that inputs video image information including an Internet address of a second video image intended to be inserted into the first video image, a setting information generation unit that generates setting information including coordinates of an area in which the second video image is to be inserted and reproduced in the first video image, and information on a reproduction start time and a reproduction end time of the second video image, and a reaction video generation unit that generates a reaction video by combining the first video image, the video image information, and the setting information. | 2021-07-01 |
20210201955 | METHOD AND SYSTEM FOR DYNAMICALLY ANALYZING, MODIFYING, AND DISTRIBUTING DIGITAL IMAGES AND VIDEO - The present invention discloses a new method for analyzing, modifying, and distributing digital images and video in a quick, efficient, practical and/or cost-effective way. The method of processing video can take a different region or object and replace the pixels in the frames of the scenes that comprise the features and characteristics of the identified region or object with a different set of pixels. The replacement or other customizations of the frames and scenes lead to a naturally integrated video or image which is indistinguishable by the human eye or other visual system. In one embodiment, this invention can be used to provide different advertising elements into an image or set of images for different viewers, or to enable a viewer to control elements within a video and add their own preference or other elements. | 2021-07-01 |
20210201956 | 3D MEDIA ELEMENTS IN 2D VIDEO - The disclosed embodiment generate a 3D representation of a 2D scene depicted to two dimensional video. The 3D representation includes individual 3D media elements representing objects included in the 2D scene. 3D void segments within the 2D scene are identified based on an aggregation of the individual 3D media elements. The 3D void segments are prioritized for insertion of additional 3D media elements within the 3D void spaces based on a variety of factors including lighting present at the 3D void segment, a distance of the 3D void segment from a center of the 2D scene, a size of the 3D void segment, and a time duration the 3D void segment is present in the 2D scene. A new 3D media element in these selected for insertion into the 2D scene based on the priorities of the 3D void segments. | 2021-07-01 |
20210201957 | INFORMATION PROCESSING APPARATUS AND NON-TRANSITORY COMPUTER READABLE MEDIUM STORING PROGRAM - An information processing apparatus includes a memory, and a processor, in which the memory stores a motion picture, a subtitle set in the motion picture, and a display starting time point and a display ending time point of the subtitle, and the processor is configured to display the subtitle in the motion picture being played back in accordance with a current playback time point and display notification information for notifying a user that the current playback time point is a specific time before or after a time point at which display of the subtitle is started or ended at the specific time before or after the display starting time point or the display ending time point of the subtitle in the motion picture. | 2021-07-01 |
20210201958 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM - An information processing apparatus includes a receiving unit that receives, during or after reproduction of a video, a predetermined operation with respect to the video, an associating unit that associates the received operation with a reproduction location where the received operation has been generated in the video, and a setting unit that sets in response to the received operation an importance degree of the reproduction location associated with the received operation. | 2021-07-01 |
20210201959 | ISOLATED VIBRATION STRUCTURE FOR FAN BAY MODULE AND HDD CAGE - An isolated vibration assembly for a computing device includes a top assembly having a top plate. The assembly further includes a base assembly having a base plate that is generally parallel to and offset from the top plate. A partition assembly is positioned generally perpendicularly between the top plate and the bottom plate, with two partition plates defining an internal space. A plurality of vibration isolators is attached in an interspersed manner to one or more surfaces of the top plate, the base plate, or the two partition plates. A computing device is removably installed within the internal space, generating vibrations that are reduced when passing through the plurality of vibration isolators. | 2021-07-01 |
20210201960 | SEMICONDUCTOR DEVICE STRUCTURE - A semiconductor device structure includes a silicon substrate, a transistor, and an interconnection. The silicon substrate has a silicon surface. The transistor includes a gate structure, a first conductive region, a second conductive region, and a channel under the silicon surface. The interconnection is extended beyond the transistor and coupled to the first conductive region of the transistor. The interconnection is disposed under the silicon surface and isolated from the silicon substrate by an isolation region. | 2021-07-01 |
20210201961 | HEADER LAYOUT DESIGN INCLUDING BACKSIDE POWER RAIL - Header circuitry for a memory device includes multiple backside power rails that form distinct voltage sources for a plurality of switching devices in the header circuitry. The header circuitry includes at least one region of a first conductivity type. A first section in the first region includes one backside power rail (BPR) that forms a first voltage source that provides a first voltage. A second section in the same first region includes another BPR that forms a second voltage source that provides a second voltage that is different from the first voltage. | 2021-07-01 |
20210201962 | DATA DRIVING CIRCUIT - A data driving circuit may include a trigger circuit and a pre-driver. The trigger circuit may be configured to block a remaining signal path among a plurality of signal paths for transmitting data except for a signal path corresponding to a currently selected driving strength. The pre-driver may be configured to drive data, which are transmitted through the signal path corresponding to the currently selected driving strength, using an impedance determined in accordance with a plurality of impedance control codes. | 2021-07-01 |
20210201963 | PAGE BUFFER AND MEMORY DEVICE INCLUDING THE SAME - A page buffer includes a charging circuit, first and second storage circuits, and a selection circuit. The charging circuit charges a bit line during a precharging period. The first storage circuit determines and stores data corresponding to a state of a selected memory cell among memory cells connected to the bit line while the charging circuit charges the bit line. The second storage circuit, which is a circuit separate from the first storage circuit, determines and stores data corresponding to a state of the selected memory cell after the precharging period. The selection circuit outputs a control voltage controlling a switch element connected between the bit line and the charging circuit, and determines a magnitude of the control voltage during the precharging period, based on the data stored in the first storage circuit. | 2021-07-01 |
20210201964 | MEMORY DEVICE INCLUDING ON-DIE-TERMINATION CIRCUIT - A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip. | 2021-07-01 |
20210201965 | SEMICONDUCTOR SYSTEM AND METHOD OF OPERATING THE SAME - A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device compares a received signal with an original signal to generate a driving force control signal. The first semiconductor device also drives the original signal using a driving force in accordance with the driving force control signal to output an external transmission signal. The second semiconductor device receives the external transmission signal to generate a positive signal and a negative signal. The second semiconductor device also generates a restoration signal in response to the positive signal and the negative signal. The second semiconductor device additionally outputs the restoration signal as the external transmission signal to the first semiconductor device. | 2021-07-01 |
20210201966 | MEMORY MODULE MUTIPLE PORT BUFFER TECHNIQUES - The present disclosure provides techniques for using a multiple-port buffer to improve a transaction rate of a memory module. In an example, a memory module can include a circuit board having an external interface, first memory devices mounted to the circuit board, and a first multiple-port buffer circuit mounted to the circuit board. The first multiple-port buffer circuit can include a first port coupled to data lines of the external interface, the first port configured to operate at a first transaction rate, a second port coupled to data lines of a first plurality of the first memory devices, and a third port coupled to data lines of a second plurality of the first memory devices. The second and third ports can be configured to operate at a second transaction rate, wherein the second transaction rate is slower than the first transaction rate. | 2021-07-01 |
20210201967 | APPARATUSES INCLUDING INPUT BUFFERS AND METHODS FOR OPERATING INPUT BUFFERS - Apparatuses including input buffers and methods for operating input buffers are described. An example input buffer includes a plurality of input buffer circuits, each receiving input data and activated by a respective clock signal. An input buffer circuit includes a decision feedback equalizer (DFB) having adjustable capacitances and reference capacitances to set a reference level of the input buffer circuit. The capacitance of the adjustable capacitances may be set by a code. The DFB provides a capacitance of the adjustable capacitances to a first sense node and further provides a capacitance of the reference capacitances to a second sense node to set the reference level of the input buffer circuit. The input buffer circuit provides output data based on the input data and the reference level set by the DFE. | 2021-07-01 |
20210201968 | SEMICONDUCTOR APPARATUS AND A SEMICONDUCTOR SYSTEM CAPABLE OF ADJUSTING TIMINGS OF DATA AND DATA STROBE SIGNAL - A semiconductor apparatus includes a first receiver, a second receiver, a first delay line, and a second delay line. The first receiver receives an input signal using a first supply voltage. The first delay line delays an output of the first receiver based on a first delay control signal and a first complementary delay control signal to generate a received signal. The second receiver receives a clock signal using a second supply voltage. The second delay line delays an output of the second receiver based on a second delay control signal and a second complementary delay control signal to generate a received clock signal. Delay amounts of the first and second delay lines are complementarily changed based on the first and second supply voltages. | 2021-07-01 |
20210201969 | STORAGE DEVICE ADJUSTING A TIMING OF A DATA SIGNAL AND A DATA STROBE SIGNAL - A storage device includes a nonvolatile memory device, and a controller that exchanges a data signal with the nonvolatile memory device through a data input and output line and exchanges a data strobe signal with the nonvolatile memory device through a data strobe line. In a training operation, at least one of the nonvolatile memory device and the controller performs a coarse training of adjusting a delay of the data signal with a first stride and a fine training of adjusting the delay of the data signal with a second stride smaller than the first stride. | 2021-07-01 |
20210201970 | METHODS FOR ON-DIE MEMORY TERMINATION AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME - Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode. | 2021-07-01 |
20210201971 | APPARATUSES AND METHODS FOR SETTING A DUTY CYCLE ADJUSTER FOR IMPROVING CLOCK DUTY CYCLE - Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset. | 2021-07-01 |
20210201972 | INTEGRATED CIRCUIT - An integrated circuit includes a first array of memory cells, a second array of memory cells, a first pair of complementary data lines, a second pair of complementary data lines, and a third pair of complementary data lines. The first pair of complementary data lines extend along the first array of memory cells, and are coupled to the first array of memory cells. The second pair of complementary data lines extend along the second array of memory cells, and are coupled to the first pair of complementary data lines. The third pair of complementary data lines extend along the second array of memory cells, and are coupled to the second array of memory cells. A number of rows of memory cells in the first array of memory cells is different from a number of rows of memory cells in the second array of memory cells. | 2021-07-01 |
20210201973 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes a memory cell including a switching element and a variable resistance element, and a circuit for switching the memory cell ON, performing a first read operation on the memory cell, generating a first voltage based on the first read operation, switching the memory cell ON after first data is written to the memory cell, performing a second read operation while the memory cell is maintained to be ON when the first data is stored in the memory cell during the first read operation, performing the second read operation after the memory cell transitions from ON to OFF at least once when second data is stored in the memory cell during the first read operation, generating a second voltage based on the second read operation, and determining the data stored in the memory cell during the first read operation based on the first and second voltages. | 2021-07-01 |
20210201974 | REDUCING READ DISTURBANCE ERROR IN TAG ARRAY - A circuit for reducing read disturbance error in a tag array. The circuit includes a decoder, a plurality of m-bit comparators, and a plurality of n-bit comparators. The decoder is configured to enable access to a respective set of the tag array based on a value of an index of a requested address. Each respective m-bit comparator is configured to enable access to a respective plurality of Most Significant Bits (MSBs) of the respective set responsive to each respective Least Significant Bit (LSB) of a respective plurality of LSBs of the respective set being equal to a respective LSB of a tag of the requested address. Each respective n-bit comparator is configured to enable access to the respective set by a data bus responsive to each respective MSB of the respective plurality of MSBs being equal to a respective MSB of the tag. | 2021-07-01 |
20210201975 | POWER SUPPLY GENERATOR ASSIST - The disclosed system and method reduce on-chip power IR drop caused by large write current, to increase the write IO number or improve write throughput and to suppress write voltage ripple at the start and end of a write operation. The disclosed systems and methods are described in relation to stabilizing the bit line voltage for MRAMs, however, the disclosed systems and methods can be used to stabilize the bit line voltage of any memory configuration that draws large currents during short write pulses or, more generally, to selectively assist a power supply generator in supplying adequate power to a load at times of large power consumption. | 2021-07-01 |
20210201976 | ACCESS LINE DISTURBANCE MITIGATION - Methods, systems, and devices for access line disturbance mitigation are described to, for example, reduce voltage disturbances on deselected digit lines during a read or write operation. Memory cells of a memory device may be couplable with a write circuit including a level shifter circuit, such that changes in voltage on a selected digit line may be controlled via a level shifter circuit of a write circuit associated with a selected memory cell. The write circuit may write a logic state to the memory cell after completing a read operation. One or more write voltages may be applied to or removed from the memory cell via the level shifter circuit, which may control a slew rate of one or more voltage changes on the selected digit line. The slew rate(s) may be controlled via a current driver circuit coupled with a pull-up circuit or a pull-down circuit of the level shifter circuit. | 2021-07-01 |
20210201977 | BALANCED NEGATIVE BITLINE VOLTAGE FOR A WRITE ASSIST CIRCUIT - A circuit and method for establishing a balanced negative voltage to a near-end and far-end of a bitline having a plurality of memory cells connected to the bitline is disclosed. A MOS capacitor and a metal capacitor are connected in parallel. The MOS capacitor is connected to the near-end of the bitline through a first switch transistor. The metal capacitor is connected to the near-end of the bitline through the first switch transistor and the far end of the bitline through a second switch transistor. A falling negative boost voltage is applied to the MOS capacitor and the metal capacitor. When the switch transistors are turned on during a write operation, the MOS capacitor and the metal capacitor are both coupled to the voltage at the near-end and far-end and drive the voltage to approximately equal the boost voltage, thereby providing a balanced voltage to the bitline. | 2021-07-01 |
20210201978 | APPARATUSES AND METHODS FOR WIDE CLOCK FREQUENCY RANGE COMMAND PATHS - Apparatuses and methods for wide clock frequency range command paths are disclosed. An example apparatus includes a command decoder and a command timing circuit. The command decoder is configured to receive a command and is further configured to decode the command to provide a decoded command. The command timing circuit is configured to receive the decoded command responsive to a clock and is further configured to provide a delayed internal command having a delay relative to receiving the decoded command based on clock frequency information indicative of a clock frequency of the clock. The command timing circuit includes a plurality of command timing paths. Each of the plurality of command timing paths is configured to provide a respective delay to the decoded command for a respective range of clock frequencies. | 2021-07-01 |
20210201979 | APPARATUSES AND METHODS TO PERFORM DUTY CYCLE ADJUSTMENT WITH BACK-BIAS VOLTAGE - An exemplary semiconductor device includes a clock generator circuit configured to generate a clock signal, and a duty cycle adjustment circuit configured to receive the clock signal. The duty cycle adjustment circuit includes an adjuster circuit configured to receive a back-bias voltage and to adjust a duty cycle of the clock signal based on the back-bias voltage to provide an output dock signal. | 2021-07-01 |
20210201980 | SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a semiconductor storage device includes a first stacked portion including a first peripheral circuit and a second stacked portion above the first stacked portion. The second stacked portion including a memory cell, a word line connected to the memory cell, a bit line connected to the memory cell and the first peripheral circuit, and at least one of a second peripheral circuit connected to the bit line and a third peripheral circuit connected to the word line. The at least one of the second or third peripheral circuits including a field effect transistor having a channel layer containing an oxide semiconductor. | 2021-07-01 |
20210201981 | SEMICONDUCTOR DEVICE WITH WORD LINE DEGRADATION MONITOR AND ASSOCIATED METHODS AND SYSTEMS - Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to monitor degradations in word line characteristics. The memory device may generate a reference signal in response to an access command directed to a memory array including a plurality of word lines, in some embodiments. The memory array may include a victim word line configured to accumulate adverse effects of executing multiple access commands at the word lines of the memory array. When the degradation in the word line characteristics causes reliability issues (e.g., corrupted data), the memory array is deemed unreliable, and may be blocked from memory operations. The memory device may compare the reference signal and a signal from the victim word line to determine whether preventive measures may be appropriate to avoid (or mitigate) such reliability issues. | 2021-07-01 |
20210201982 | MEMORY DEVICE AND OPERATING METHOD THEREOF - A memory device includes a memory cell array including cell strings, respectively connected between string select lines and ground select lines, and wordlines connected to memory cells, a control logic to generate a first voltage provided to the string select lines, and a second voltage provided to the ground select lines, and to adjust voltage levels of the first and second voltages to control a channel boosting level of the cell strings, and a row decoder to provide a read voltage, a read pass voltage, and the first and second voltages to the memory cell array under control of the control logic. The control logic generates one of the first and second voltage as a pre-pulse voltage. The row decoder provides a third voltage to at least one of the wordlines. | 2021-07-01 |
20210201983 | MEMORY DEVICE INCLUDING DATA INPUT/OUTPUT CIRCUIT - A memory device includes a plurality of data input/output (I/O) groups each including data I/O circuits, each data I/O circuit comprising a transistor having a predetermined threshold voltage according to a bulk voltage supplied to a bulk terminal thereof; a control circuit suitable for generating a control signal according to a data I/O mode; and a plurality of voltage supply circuits suitable for independently supplying bulk voltages to the plurality of data I/O groups, and changing, in response to the control signal, a level of a bulk voltage corresponding to data I/O groups unused in the data I/O mode, among the plurality of data I/O groups. | 2021-07-01 |
20210201984 | ENHANCED AUTO-PRECHARGE MEMORY SCHEDULING POLICY - Disclosed embodiments relate to enhanced auto-precharge memory scheduling. In one example, a system includes a memory having a matrix of storage cells, which, responsive to a row address strobe (RAS) signal, activates a given row, responsive to a column address strobe (CAS) signal, selects storage cells in the given row, and, responsive to a combined auto-precharge (AP) and CAS signal, accesses, then closes the given row. A memory controller selects a memory request from a memory request queue, generates the RAS signal to activate a row, when another memory request to the row is enqueued, generates the CAS signal to select a storage cell, when another memory request to a same bank but a different row is enqueued, generates the combined AP and CAS signal, and, when no memory request to the same bank is enqueued, generates the CAS signal only, allowing a close timer to close the row. | 2021-07-01 |
20210201985 | METHOD FOR REFRESHING MEMORY DEVICE WHERE CONTROL CIRCUIT PERFORMS FIRST REFRESH OPERATION ON FIRST GROUP AND PERFORMS SECOND REFRESH OPERATION ON VICTIM ROW OF SECOND GROUP WITHOUT EXTERNAL COMMAND FOR VICTIM ROW REFRESH - A memory device including a memory unit and a control circuit is provided. The memory unit includes a plurality of memory banks. The memory banks are at least divided into a first group and a second group. The control circuit is coupled to the memory unit. The control circuit is configured to perform a first refresh operation on the first group and the second group. When the control circuit performs the first refresh operation on one of the first group and the second group, the control circuit performs a second refresh operation on a victim row of the other one of the first group and the second group. In addition, a method for refreshing a memory device is also provided. | 2021-07-01 |
20210201986 | MEMORY CONTEXT RESTORE, REDUCTION OF BOOT TIME OF A SYSTEM ON A CHIP BY REDUCING DOUBLE DATA RATE MEMORY TRAINING - Methods for reducing boot time of a system-on-a-chip (SOC) by reducing double data rate (DDR) memory training and memory context restore. Dynamic random access memory (DRAM) controller and DDR physical interface (PHY) settings are stored into a non-volatile memory and the DRAM controller and DDR PHY are powered down. On system resume, a basic input/output system restores the DRAM controller and DDR PHY settings from non-volatile memory, and finalizes the DRAM controller and DDR PHY settings for operation with the SOC. Reducing the boot time of the SOC by reducing DDR training includes setting DRAMs into self-refresh mode, and programing a self-refresh state machine memory operation (MOP) array to exit self-refresh mode and update any DRAM device state for the target power management state. The DRAM device is reset, and the self-refresh state machine MOP array reinitializes the DRAM device state for the target power management state. | 2021-07-01 |
20210201987 | Dynamic Refresh Rate Control - In an embodiment, a memory controller in an integrated circuit may generate refreshes for one or more DRAMs coupled to the integrated circuit according to a refresh rate. The integrated circuit may include one or more temperature sensors. A rate of change of the temperature may be determined from the temperature sensors. If the rate is greater than a threshold, the memory controller may generate refreshes according to a refresh rate specified by the DRAMs. If the rate is less than the threshold, the memory controller may generate refreshes at a reduced refresh rate. | 2021-07-01 |
20210201988 | LATCH CIRCUIT - A latch formed from a memory cell includes a clock input terminal configured to receive a clock signal, complementary first and second data terminals, and a latch circuit. The latch circuit has first and second inverters. The first inverter has an input terminal coupled to the first data terminal, and the second inverter has an input terminal coupled to the second data terminal. A first pass gate transistor is coupled between an output terminal of the second inverter and the first data terminal. A second pass gate transistor is coupled between an output terminal of the first inverter and the second data terminal. The first and second pass gate transistors each have a gate terminal coupled to the clock input terminal. The input terminal of the first inverter is not directly connected to the output terminal of the second inverter, and the input terminal of the second inverter is not directly connected to the output terminal of the first inverter. | 2021-07-01 |
20210201989 | MEMORY DEVICE - A memory device includes a memory array that includes one or more rows of memory cells and one or more columns of memory cells. The comparator circuitry is operably connected to at least one column of memory cells in the one or more columns of memory cells. The comparator circuitry includes a precompute circuit and a select circuit operably connected to the outputs of the precompute circuit. The precompute circuit is operable to precompute a comparison operation to produce a first precompute signal and a second precompute signal. The select circuit is operable to receive a first cell data signal from a memory cell in the column of memory cells. Based at least on the first cell data signal, the select circuit selects either the first precompute signal or the second precompute signal to output from the comparator circuitry as a signal read from the memory cell. | 2021-07-01 |
20210201990 | Memory Device - A memory device is provided. The memory device includes a memory cell and a bit line connected to the memory cell. A negative voltage generator is connected to the bit line. The negative voltage generator, when enabled, is operative to provide a first write path for the bit line. A control circuit is connected to the negative voltage generator and the bit line. The control circuit is operative to provide a second write path for the bit line when the negative voltage generator is not enabled. | 2021-07-01 |
20210201991 | Write Assist for a Memory Device and Methods of Forming the Same - A semiconductor memory device includes an array of memory cells arranged in a plurality of rows and columns, with each memory cell including a plurality of bit cell transistors. The semiconductor memory device further includes a plurality of write assist circuits, including one or more write assist circuits within each column of the array of memory cells, each write assist circuit configured to provide a core voltage to memory cells within the same column and to reduce the core voltage during a write operation. The array of memory cells and the plurality of write assist circuits have a common semiconductor layout. | 2021-07-01 |
20210201992 | MEMORY DEVICE, AND ELECTRONIC DEVICE INCLUDING THE SAME - A memory device includes a memory cell array including M memory cells connected to one bit line and configured to distributively store N-bit data, where N is a natural number and M is a natural number of 2 or more and N or less, the M memory cells including a first memory cell and a second memory cell having different sensing margins, and a memory controller including a page buffer, the memory controller configured to distributively store the N-bit data in the M memory cells and to sequentially read data stored in the M memory cells to obtain the N-bit data, and an operation logic configured to execute an operation using the N-bit data, the memory controller configured to provide different reading voltages to the first memory cell and the second memory cell. | 2021-07-01 |
20210201993 | MEMORY ARRAY STRUCTURES AND METHODS FOR DETERMINATION OF RESISTIVE CHARACTERISTICS OF ACCESS LINES - Memory array structures providing for determination of resistive characteristics of access lines might include a first block of memory cells, a second block of memory cells, a first current path between a particular access line of the first block of memory cells and a particular access line of the second block of memory cells, and, optionally, a second current path between the particular access line of the second block of memory cells and a different access line of the first block of memory cells. Methods for determining resistive characteristics of access lines might include connecting the particular access line of the first block of memory cells to a driver, and determining the resistive characteristics in response to a current level through that access line and a voltage level of that access line. | 2021-07-01 |
20210201994 | RRAM CIRCUIT AND METHOD - A method of forming a filament in a resistive random-access memory (RRAM) device includes applying a cell voltage across a resistive layer of the RRAM device, detecting an increase in a current through the resistive layer generated in response to the applied cell voltage, and in response to detecting the increase in the current, using a first switching device to reduce the current through the resistive layer. | 2021-07-01 |
20210201995 | THREE-STATE PROGRAMMING OF MEMORY CELLS - The present disclosure includes apparatuses, methods, and systems for three-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of three possible data states by applying a voltage pulse to the memory cell, determining whether the memory cell snaps back in response to the applied voltage pulse, and applying an additional voltage pulse to the memory cell based on the determination of whether the memory cell snaps back. | 2021-07-01 |
20210201996 | REWRITE METHOD FOR VARIABLE RESISTANCE ELEMENT, AND NON-VOLATILE STORAGE DEVICE USING VARIABLE RESISTANCE ELEMENT - Provided are a rewrite method for a variable resistance element that increases a rewrite count, and a non-volatile storage device using the variable resistance element. In the rewrite method for the variable resistance element, a variable resistance layer is disposed between a first electrode and a second electrode, and a write voltage is applied between the first electrode and the second electrode, thereby causing the resistance between the first electrode and the second electrode to reversibly change. After writing to the variable resistance element, the variable resistance element is read, the read current is measured, the measured read current is compared with a reference current, a condition of the writing is changed on the basis of the comparison results, and thereafter writing to the variable resistance element is performed again. | 2021-07-01 |
20210201997 | NON-VOLATILE STATIC RANDOM ACCESS MEMORY (nvSRAM) WITH MULTIPLE MAGNETIC TUNNEL JUNCTION CELLS - Disclosed herein are related to an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors. | 2021-07-01 |
20210201998 | NONVOLATILE SRAM - A memory device has a plurality of bit cells, each of which includes an SRAM cell having a storage node selectively connectable to a first bit line in response to a control signal received on a first word line. Each bit cell further includes an MRAM cell selectively connectable to the storage node of the SRAM cell in response to a control signal received on a second word line. | 2021-07-01 |
20210201999 | MEMORY CELL - A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors. | 2021-07-01 |
20210202000 | ARCHITECTURE FOR FAST CONTENT ADDRESSABLE MEMORY SEARCH - A search pattern is generated based on an input search word comprising a first sequence of bits. The search pattern comprises a first set of signals representing the input search word and a second set of signals representing a second sequence of bits comprising an inverse of the first sequence of bits. The search pattern is provided as input to search lines of a content addressable memory (CAM) block. The search pattern causes at least one string in the CAM block to be conductive and provide a signal to a page buffer connected to the string in response to the input search word matching a data entry stored on the string. A location of the data entry is determined based on data read from the page buffer and the location is output. | 2021-07-01 |
20210202001 | VOLTAGE GENERATION CIRCUIT AND SEMICONDUCTOR CIRCUIT INCLUDING THE VOLTAGE GENERATION CIRCUIT - A voltage generation circuit includes a driver configured to generate an internal voltage by driving an external voltage depending on a driving signal; an amplifier configured to generate the driving signal depending on a result of comparing a reference voltage and a feedback voltage; and a switch configured to delay a decrease of the internal voltage by precharging a node of the amplifier with a predetermined voltage depending on a control signal. | 2021-07-01 |
20210202002 | SEMICONDUCTOR MEMORY DEVICE WITH MEMORY CELLS EACH INCLUDING A CHARGE ACCUMULATION LAYER AND A CONTROL GATE - A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M2021-07-01 | |
20210202003 | TRACKING OPERATIONS PERFORMED AT A MEMORY DEVICE - A data structure including two or more entries is maintained, where each entry corresponds to a range of consecutive wordlines in a block of a memory device. Each entry includes an operation counter to track a number of memory access operations performed on the range of consecutive wordlines in the block of the memory device. An indication of a memory access operation pertaining to the particular wordline is received. In response to the indication of the memory access operation pertaining to the particular wordline, a determination is made whether the particular wordline is within any range of consecutive wordlines that has a corresponding entry in the data structure. In response to the particular wordline being outside of any range of consecutive wordlines that has a corresponding entry in the data structure, a new entry for a new range of consecutive wordlines that includes the particular wordline is created. | 2021-07-01 |
20210202004 | REDUNDANCY IN MICROELECTRONIC DEVICES, AND RELATED METHODS, DEVICES, AND SYSTEMS - Methods of operating a memory device are disclosed. A method may include enabling a first and second row section units a number of row section units of a memory device in response to a row address. The method may also include comparing a selected column address to a number of column addresses of defective memory cells of a first row section of the first row section unit. Moreover, in response to the selected column address matching a first column address of the number of column addresses, the method may include activating a second row section of the second row section unit, conveying a redundant column select signal to the memory array to select a redundant memory cell of the second row section. Memory devices and systems are also disclosed. | 2021-07-01 |
20210202005 | EVENT COUNTERS FOR MEMORY OPERATIONS - A counter can have a number of sensing components. Each respective sensing component can be configured to sense a respective event and can include a respective first capacitor configured to be selectively coupled to a second capacitor in response to the respective sensing component sensing the respective event. The second capacitor can be configured to be charged to a voltage by each respective first capacitor that is selectively coupled to the second capacitor. The counter can have a comparator with a first input coupled to the second capacitor and a second input coupled to a reference voltage corresponding to a threshold quantity of events. The comparator can be configured to output a signal indicative of the threshold quantity of events being sensed in response to the voltage of the second capacitor being greater than or equal to the reference voltage. | 2021-07-01 |
20210202006 | PROGRAMMING NONVOLATILE MEMORY CELLS THROUGH A SERIES OF PREDETERMINED THRESHOLD VOLTAGES - Adaptive write operations for non-volatile memories select programming parameters according to monitored programming performance of individual memory cells. In one embodiment of the invention, programming voltage for a memory cell increases by an amount that depends on the time required to reach a predetermined voltage and then a jump in the programming voltage is added to the programming voltage required to reach the next predetermined voltage. The adaptive programming method is applied to the gate voltage of memory cells; alternatively, it can be applied to the drain voltage of memory cells along a common word line. A circuit combines the function of a program switch and drain voltage regulator, allowing independent control of drain voltage of selected memory cells for parallel and adaptive programming. Verify and adaptive read operations use variable word line voltages to provide optimal biasing of memory and reference cells during sensing. | 2021-07-01 |
20210202007 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation, and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation. | 2021-07-01 |
20210202008 | APPARATUS AND METHOD FOR MANAGING PROGRAM OPERATION TIME AND WRITE LATENCY IN MEMORY SYSTEM - An operation method of a memory system may include monitoring the size of a programmable area included in each of a plurality of open blocks in which a plurality of data having different attributes are stored, respectively, and generating a first free block by performing a first erase operation on a part of a plurality of erase target blocks based on the number of first open blocks, each open block of which the programmable area has a size less than a threshold value, among the plurality of open blocks. | 2021-07-01 |
20210202009 | MANAGING SUB-BLOCK ERASE OPERATIONS IN A MEMORY SUB-SYSTEM - A processing device in a memory system receives an erase request to erase data stored at a data block of a memory device, the erase request identifying a selected sub-block of a plurality of sub-blocks of the data block for erase, each of the plurality of sub-blocks comprising select gate devices (SGDs) and data storage devices. For each sub-block of the plurality of sub-blocks not selected for erase, the processing device applies an input voltage at a bitline of the respective sub-block and applies a plurality of gate voltages to a plurality of wordlines of the respective sub-block, the plurality of wordlines are coupled to the SGDs and to the data storage devices, each voltage of the plurality of voltages applied to a successive wordline of the plurality of wordlines is less than a previous voltage applied to a previous wordline by an amount equal to a step down interval. | 2021-07-01 |
20210202010 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device, and a method of operation, include: a memory block coupled with a plurality of word lines and a plurality of bit lines; a peripheral circuit configured to perform a program operation and a read operation on the memory block; and control logic configured to control the peripheral circuit such that a word line overdrive period overlaps with a bit line overdrive period in a bit line precharge operation during at least one of the program operation and the read operation. | 2021-07-01 |
20210202011 | A SYSTEM AND METHOD OF READING TWO PAGES IN A NONVOLATILE MEMORY - Method(s) and structure(s) for a two-page read operation are described and provide a multiple page read. The two page read operation provides for reading two pages with in a block without reducing the control gates to a low voltage level. The two page read can read the first page using an incrementing voltage level at discrete steps and starting the second page read at the high state for the control gates from the first page read. The second page read then decrements the control gate voltages level through the steps. This should reduce energy consumption. The two-page read operation will also reduce the time as the time period to reset the control gates to a low state are not required in between the page read operations. | 2021-07-01 |
20210202012 | STORAGE DEVICE AND OPERATING METHOD OF STORAGE DEVICE - A storage device includes a nonvolatile memory device and a memory controller. The memory controller receives first data from the nonvolatile memory device based on a first read command, and performs error correction on the first data. When the error correction fails, the memory controller transmits a second read command and second read voltage information to the nonvolatile memory device, receives second data from the nonvolatile memory device, transmits a third read command and third read voltage information to the nonvolatile memory device, and receives third data from the nonvolatile memory device. The memory controller adjusts an offset based on the second data and the third data, transmits a fourth read command, fourth read voltage information, and the offset to the nonvolatile memory device, receives fourth data from the nonvolatile memory device, and performs a soft decision process based on the fourth data. | 2021-07-01 |
20210202013 | APPARATUS AND METHODS FOR RAPID DATA DESTRUCTION - Apparatus having a string of series-connected memory cells comprising a plurality of principal memory cells and a plurality of dummy memory cells might have a controller configured to cause the apparatus to apply a first programming pulse to a particular dummy memory cell of the plurality of dummy memory cells sufficient to increase a threshold voltage of the particular dummy memory cell to a voltage level sufficient to cause the particular dummy memory cell to remain deactivated during a read operation on the string of series-connected memory cells, and to concurrently apply a second programming pulse to each principal memory cell of the plurality of principal memory cell sufficient to increase threshold voltages of at least a portion of the plurality of principal memory cells. | 2021-07-01 |
20210202014 | VOLTAGE SWITCHING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME - A voltage switching circuit selectively transfers voltages applied to a first input terminal and a second input terminal to a first output terminal and a second output terminal. The voltage switching circuit includes a first transistor and a second transistor. The first transistor is formed on a first well on a substrate, and is coupled between the first input terminal and the first output terminal. The second transistor is formed on a second well different from the first well, and is coupled to the second input terminal. In a first mode in which a first voltage applied to the first input terminal is transferred to the first output terminal and the second output terminal, the first transistor is turned on and the second transistor is turned off. | 2021-07-01 |
20210202015 | MEMORY DEVICE - A memory device includes a charge pump connected to a power supply voltage and including a plurality of stages to output an output voltage, a stage counter configured to output a count value that incrementally increases to a number of the stages, and a regulator configured to compare the output voltage with a reference output voltage of the charge pump that is generated using the incrementally increasing count value obtained by the stage counter, and to output a pump operation signal at a time when the reference output voltage becomes greater than or equal to the output voltage, wherein the charge pump operates in response to the pump operation signal. | 2021-07-01 |
20210202016 | HIGH-VOLTAGE SHIFTER WITH DEGRADATION COMPENSATION - Discussed herein are systems and methods for compensating degradation of a transistor in a high-voltage (HV) shifter configured to transfer an input voltage to an access line, such as a global wordline. An embodiment of a memory device comprises a group of memory cells, and a HV shifter circuit including a signal transfer circuit and a compensator circuit. The signal transfer circuit includes a P-channel transistor to transfer a high-voltage input to an access line. The compensator circuit can provide a control signal to the signal transfer circuit by coupling a support voltage higher than a supply voltage (Vcc) to the signal transfer circuit for a specified time period to compensate for degradation of the P-channel transistor. The transferred high voltage is used to charge the access line to selectively read, program, or erase memory cells. | 2021-07-01 |
20210202017 | RESPONDING TO CHANGES IN AVAILABLE POWER SUPPLY - Memories having a first pool of memory cells having a first storage density and a second pool of memory cells having a second storage density greater than the first storage density, and a controller configured to cause the memory to determine whether a value of an indication of available power of a power supply for the memory is less than a threshold, and in response to determining that the value of the indication of available power is less than the threshold, increase a size of the first pool of memory cells, limit programming of data received by the memory to the first pool of memory cells, and cease movement of data from the first pool of memory cells to the second pool of memory cells, as well as apparatus including similar memories. | 2021-07-01 |
20210202018 | MULTI-STATE PROGRAMMING OF MEMORY CELLS - The present disclosure includes apparatuses, methods, and systems for multi-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of a plurality of possible data states by applying a voltage pulse to the memory cell, determining the memory cell snaps back in response to the applied voltage pulse, turning off a current to the memory cell upon determining the memory cell snaps back, and applying a number of additional voltage pulses to the memory cell after turning off the current to the memory cell. | 2021-07-01 |
20210202019 | MEMORY DEVICE INCLUDING DYNAMIC PROGRAMMING VOLTAGE - Some embodiments include apparatus and methods using access lines, first memory cells coupled to an access line of the access lines, and a control unit including circuitry. The control unit is configured to apply a first voltage to the access line; check first threshold voltages of the first memory cells after applying the first voltage; obtain offset information based on a determination that at least one of the first threshold voltages is greater than a selected voltage; generate a second voltage, the second voltage being a function of the first voltage and the offset information; and apply the second voltage to one of the access lines during an operation of storing information in second memory cells. | 2021-07-01 |
20210202020 | APPARATUS FOR DETERMINING A PASS VOLTAGE OF A READ OPERATION - Memories having a controller configured, during a pre-charge portion of a read operation, to apply a sequence of increasing voltage levels concurrently to each access line of a plurality of access lines, wherein each voltage level of the sequence of increasing voltage levels is higher than any previous voltage level of the sequence of increasing voltage levels and lower than any subsequent voltage level of the sequence of increasing voltage levels, and determine a particular voltage level of the sequence of increasing voltage levels corresponding to a point at which all memory cells of the plurality of strings of series-connected memory cells are first deemed to be activated while applying the sequence of increasing voltage levels. | 2021-07-01 |
20210202021 | MEMORY PROXIMITY DISTURB MANAGEMENT - Exemplary methods, apparatuses, and systems include a controller to manage memory proximity disturb. The controller identifies a first memory location in response to an access of a second memory location, the first memory location storing a first value. The controller updates a first disturb value by a first amount, the first disturb value representing a cumulative disturb effect on the first value in the first memory location by accesses to a first plurality of memory locations proximate to the first memory location, the first plurality of memory locations including the second memory location. | 2021-07-01 |
20210202022 | MODIFIED VERIFY SCHEME FOR PROGRAMMING A MEMORY APPARATUS - A memory apparatus and method of operation is provided. The apparatus includes memory cells coupled to a control circuit. The control circuit is configured to perform a first programming stage including iteratively programming each of the memory cells to first program states and verifying that the memory cells have a threshold voltage above one of a plurality of first verify voltages corresponding to the first program states. The first programming stage ends before all of the memory cells are verified thereby leaving a fraction of the memory cells below the one of the plurality of first verify voltages. The control circuit also performs a second programming stage including iteratively programming each of the memory cells to second program states and verifying that at least a predetermined number of the memory cells have the threshold voltage above one of a plurality of second verify voltages corresponding to the second program states. | 2021-07-01 |
20210202023 | SEMICONDUCTOR DEVICE WITH SELECTIVE COMMAND DELAY AND ASSOCIATED METHODS AND SYSTEMS - Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory device are configured to add variable delays to a command. The variable delays may be provided by a host device (e.g., a test equipment) using a test mode of the memory devices. Alternatively, the variable delays may be stored in nonvolatile memory (NVM) components of the memory devices. Further, mode registers of the memory devices may be set to indicate that the command is associated with the variable delays stored in the NVM components. Further, the memory devices may include delay components configured to add the variable delays to the command. Such variable delays facilitate staggered execution of the command across multiple memory devices so as to avoid (or mitigate) issues related to an instantaneous, large amount of current drawn from a power supply connected to the memory devices. | 2021-07-01 |
20210202024 | MEMORY REDUNDANCY REPAIR - Memories, and their operation, might include a plurality of content addressable memory (CAM) cells each for storing a respective data value, a match signal generator configured to generate an indication whether each CAM cell of the plurality of CAM cells indicates a match between its respective data value and a respective received signal value, and a plurality of storage elements each for storing a respective data value, wherein each storage element of the plurality of storage elements corresponds to a respective CAM cell of the plurality of CAM cells in a one-to-one relationship, and wherein each storage element of the plurality of storage elements is responsive to the indication of the match signal generator to generate a data signal indicative of the respective data value of that storage element if a match of their corresponding CAM cells is indicated. | 2021-07-01 |
20210202025 | MEMORY-BASED PROCESSORS - A memory chip may include: a plurality of memory banks; a data storage configured to store access information indicative of access operations for one or more segments of the plurality of memory banks; and a refresh controller configured to perform a refresh operation of the one or more segments based, at least in part, on the stored access information. | 2021-07-01 |
20210202026 | MEMORY-BASED PROCESSORS - A memory chip may include: a plurality of memory banks; a data storage configured to store access information indicative of access operations for one or more segments of the plurality of memory banks; and a refresh controller configured to perform a refresh operation of the one or more segments based, at least in part, on the stored access information. | 2021-07-01 |
20210202027 | MEMORY-BASED PROCESSORS - A memory chip may include: a plurality of memory banks; a data storage configured to store access information indicative of access operations for one or more segments of the plurality of memory banks; and a refresh controller configured to perform a refresh operation of the one or more segments based, at least in part, on the stored access information. | 2021-07-01 |
20210202028 | METHOD OF CONTROLLING OPERATION OF NONVOLATILE MEMORY DEVICE USING MACHINE LEARNING AND STORAGE SYSTEM - According to a method of controlling an operation of a nonvolatile memory device using machine learning, operating conditions of the nonvolatile memory device are determined by performing an inferring operation using a machine learning model. Training data that are generated based on feature information and error information are collected, where the error information indicate results of error correction code (ECC) decoding of the nonvolatile memory device. The machine learning model is updated by performing a learning operation based on the training data. Optimized operating conditions for individual user environments are provided by collecting training data in the storage system and performing the learning operation and the inferring operation based on the training data. | 2021-07-01 |
20210202029 | EXAMINATION OF NETWORK EFFECTS OF IMMUNE MODULATION - A software model for directed graph representation of the intercellular immune interaction network which can be used to extract mechanistic insight from immune data in order to predict the outcome of immune system perturbations, identify effective drug targets, stratify patients, and inform therapeutic selection. | 2021-07-01 |
20210202030 | ASSAY SYSTEMS FOR DETERMINATION OF FETAL COPY NUMBER VARIATION - The present invention provides processes for determining accurate risk probabilities for chromosome dosage abnormalities. Specifically, the invention provides non-invasive evaluation of genomic variations through chromosome-selective sequencing and non-host fraction data analysis of maternal samples. | 2021-07-01 |
20210202031 | METHODS AND SYSTEMS FOR AN INTEGRATED DISASSEMBLER WITH A FUNCTION-QUEUE MANAGER AND A DISASSEMBLY INTERRUPTER FOR RAPID, EFFICIENT, AND SCALABLE CODE GENE EXTRACTION AND ANALYSIS - The present invention discloses methods and systems for an integrated disassembler with a function-queue manager and a disassembly interrupter for rapid, efficient, and scalable code gene extraction and analysis. Methods include the steps of: upon receiving a target binary file, disassembling the target binary file into assembly code; extracting code fragments from the assembly code; as each code fragment is extracted, verifying each code fragment; upon availability, placing each verified code fragment in an extractor queue; and upon availability, submitting each code fragment in the extractor queue to a gene-analysis system having a code genome database. Alternatively, upon determining the extractor queue is empty or determining resources of the gene-analysis system are underutilized, transferring partially-verified code fragments to the extractor queue. Alternatively, upon receiving gene information regarding the target binary file from the gene-analysis system during disassembly, determining whether to terminate the step of disassembling based on the gene information. | 2021-07-01 |
20210202032 | METHOD OF TAGGING NUCLEIC ACID SEQUENCES, COMPOSITION AND USE THEREOF - A first aspect of the present invention relates to a method of tagging a nucleic acid molecule with a predetermined ID number, the method comprising: (a) attaching to said nucleic acid molecule a nucleic acid tag to form a tagged nucleic acid molecule, wherein said nucleic acid tag comprises one or more nucleic acid tag sub-units each consisting of groups of at least two nucleotides, wherein said nucleic acid tag is attributed said ID number by performing the following steps: (i) converting each nucleotide in said nucleic acid tag sub-units into a number ranging from 0 to 3, thereby creating numerical tag sub-units, wherein the distribution and content of the nucleotides in the nucleic acid tag sub-units has been configured to allow a finite number of numerical tag sub-units, (ii) attributing to each of said numerical tag sub-units a predetermined numerical tag element, thereby creating a numerical tag, (iii) linearly decoding said numerical tag, thereby creating said ID number. A second aspect of the present invention relates to a method for multiplex sequencing and/or demultiplexing, the method comprising the steps of: (a) multiplexing amplification of tagged nucleic acid molecules obtained according to the method of the first aspect of the present invention to generate a plurality of said tagged nucleic acid molecules, (b) pooling and parallel sequencing said plurality of tagged nucleic acid molecules, thereby generating a plurality of sequence reads, and (c) demultiplexing said plurality of sequence reads, wherein each of said sequence reads is attributed to a sample. A third aspect of the present invention is directed to a tagged nucleic acid molecule construed according to the method of the first aspect of the present invention and its use in a method for multiplex sequencing and/or demultiplexing. A fourth aspect of the present invention relates to an apparatus configured for multiplex sequencing demultiplexing, the apparatus comprising: tools for designing nucleic acid tags according to the method described in the first aspect of the present invention, tools for pooling and multiplexing a plurality of tagged nucleic acid sequences, a sequence demultiplexer, additional tools for data reproduction and post-sequencing analysis. A fifth aspect of the present invention, there is provided a method of tagging a nucleic acid molecule with a predetermined ID number, the method comprising: (a) attaching to said nucleic acid molecule a nucleic acid tag to form a tagged nucleic acid molecule, wherein said nucleic acid tag comprises one or more nucleic acid tag sub-units each consisting of groups of at least two nucleotides, wherein said nucleic acid tag is obtained from said ID number by performing the following steps: (i) linearly encoding said ID number, thereby creating a numerical tag, wherein the numerical tag comprises a plurality of numerical tag elements; (ii) attributing to each of said numerical tag elements a numerical tag sub unit, wherein the numerical tag sub-unit comprises a plurality of numbers ranging from 0 to 3; (iii) attributing to each of said numerical tag sub-units a nucleic acid tag sub-unit, thereby creating said nucleic acid tag, wherein the distribution and content of the nucleotides in the nucleic acid tag sub units has been configured to allow a finite number of numerical tag sub-units. | 2021-07-01 |
20210202033 | NOVEL MACHINE LEARNING APPROACH FOR THE IDENTIFICATION OF GENOMIC FEATURES ASSOCIATED WITH EPIGENETIC CONTROL REGIONS AND TRANSGENERATIONAL INHERITANCE OF EPIMUTATIONS - A two-step (sequential) machine learning analysis tool is provided that involves a combination of an initial active learning step followed by an imbalance class learner (ACL-ICL) protocol. This technique provides a more tightly integrated approach for a more efficient and accurate machine learning analysis. The combination of ACL and ICL work synergistically to improve the accuracy and efficiency of machine learning and can be used with any type of dataset including biological datasets. | 2021-07-01 |
20210202034 | METHODS FOR VARIANT DETECTION - The invention can be used to provide a more efficient and less error-prone method of detecting variants in DNA, such as SNPs and indels. The invention also provides a method for performing inexpensive multiplex assays. The invention also provides methods for detection of DNA sequences altered after cleavage by a targetable endonuclease, such as the CRISPR Cas9 protein from the bacterium | 2021-07-01 |