| 26th week of 2010 patent applcation highlights part 72 |
| Patent application number | Title | Published |
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| 20100169567 | DYNAMIC DISK THROTTLING IN A WIDE AREA NETWORK OPTIMIZATION DEVICE - A network device may operate to increase application performance over a wide area network. In one particular implementation, the network device may monitor accesses to a disk drive from entities and determine whether an entity is accessing the disk drive in a manner that causes a disproportionate amount of performance degradation. If so, the network device may throttle access to the disk drive for the entity. | 2010-07-01 |
| 20100169568 | COMPUTER SYSTEM, STORAGE SYSTEM AND METHOD FOR SAVING STORAGE AREA BY INTEGRATING SAME DATA - Provided is a storage system capable of saving actually used physical storage areas and of achieving a high speed in write processing. There is disclosed a computer system including a server and a storage system, in which physical storage areas of a disk drive are managed for each one or more physical blocks of predetermined sizes, and allocation of one or more physical blocks to a plurality of logical blocks of predetermined sizes is managed, and the storage system stores data written in a first logical block in a first physical block allocated to the first logical block and allocates the first physical block to a second logical block where the same data as the data stored in the first physical block is to be written. | 2010-07-01 |
| 20100169569 | STORAGE SYSTEM THAT IS CONNECTED TO EXTERNAL STORAGE - A first storage system is connected to a second storage system, and an external device within the first storage system is provided to a host as a device of the second storage system. The second storage system includes a cache control section having cache adaptors, each controlling a disk and a cache, a protocol conversion section including protocol adaptors that switch requests from the host to appropriate ones of the cache adaptors, a management adaptor, and an internal network that mutually connects the cache adaptors, the protocol adaptors and the management adaptor. The first storage system being connected to any of the protocol adaptors is connected to the second storage system. The second storage system executes a processing for the external device by the cache control section, or connects to the first storage system through the protocol conversion section without the cache control section executing processing for the external device. | 2010-07-01 |
| 20100169570 | Providing differentiated I/O services within a hardware storage controller - A device, system, and method are disclosed. In one embodiment device includes routing logic that is capable of receiving an I/O storage request from an operating system. The I/O storage request includes an input/output (I/O) data type tag that specifies a type of I/O data to be stored with the I/O storage request. The routing logic is also capable of determining, based on the I/O data type tag, which of a number of storage pools to send the I/O storage request. Each storage pool has a certain level of associated service. | 2010-07-01 |
| 20100169571 | DATA REDUNDANCY USING TWO DISTRIBUTED MIRROR SETS - A method for storing data and two sets of distributed mirrored data disposed as data stripes which permits data recovery without the necessity of parity calculations, is described. Redundant data are stored in groups of five physical hard drives which are logically segmented into stripe groups, each stripe group having three data stripe sets wherein one data stripe is protected by two distributed mirror stripes in accordance with an algorithm. The present method provides protection for all one- and two-disk failures and certain three-disk drive failures, for each physical five disk group, and retains a usable disk capacity of 33%. | 2010-07-01 |
| 20100169572 | DATA STORAGE METHOD, APPARATUS AND SYSTEM FOR INTERRUPTED WRITE RECOVERY - Embodiments of the invention include a method, apparatus and system for storing data that involves storing boundary information for data that is being written to a plurality of data storage devices. The method includes storing boundary information for a write operation of data to a plurality of data storage device, writing the data to the plurality of data storage devices and removing the recorded boundary information upon completion of the write operation of the data to the plurality of data storage devices. The boundary information can indicate the data storage device regions where particular sets of data are to be written during the write operation. If an interruption occurs during the write operation, the boundary information can be used to recover from the interruption by identifying the specific data storage device region or regions where data was being written when the interruption occurred. | 2010-07-01 |
| 20100169573 | IMAGE FORMING APPARATUS AND ACCESS REQUEST ARBITRATION METHOD FOR A RAID DRIVER - An image forming apparatus includes a RAID control unit comprising an access request queue and an access request arbitrating unit configured to store access requests to a logical disk sent from an operating system in the access request queue on the basis of fetch order determination information, and to fetch the access requests. An access arbitration method for a RAID driver comprises the steps of storing the access requests in an access request queue on the basis of fetch order determination information, converting logical disk access information contained in access information corresponding to the access requests into physical disk access information, and supplying the access information containing the physical disk access information to a RAID controller. | 2010-07-01 |
| 20100169574 | COMMUNICATION CONTROL APPARATUS AND METHOD - A communication control apparatus in a RAID device including redundant communication paths to storage devices includes a blocking unit. The blocking unit blocks configuration change notifications outputted from the storage devices to a control apparatus, which controls access to the storage devices, when a power of a communication relay device arranged on the redundant paths connecting the storage devices and the control apparatus is turned off. | 2010-07-01 |
| 20100169575 | STORAGE AREA MANAGING APPARATUS AND STORAGE AREA MANAGING METHOD - A storage area managing apparatus includes a managing unit for managing a plurality of logical volumes provided by a plurality of storage drive groups for storing data redundantly, and a rebuilding controller for generating recovery data when at least one of the drive groups is degraded on the basis of the data stored in the degraded drive group and generating a selected logical volume on the basis of the capacity of the recovery data, the rebuilding controller controlling the management unit for managing first logical volumes to correspond to a part of the plurality of storage drive groups except for the degraded drive group. The storage area managing apparatus includes a first transferring unit for transferring the recovery data to the part of the plurality of storage drive groups as indicated by the selected logical volume. | 2010-07-01 |
| 20100169576 | SYSTEM AND METHOD FOR SIFT IMPLEMENTATION AND OPTIMIZATION - A method is to implement a Scale Invariant Feature Transform algorithm in a shared memory multiprocessing system. The method comprises building differences of Gaussian (DoG) images for an input image, detecting keypoints in the DoG images; assigning orientations to the keypoints and computing keypoints descriptors and performing matrix operations. In the method, building differences of Gaussian (DoG) images for an input image and detecting keypoints in the DoG images are executed for all scales of the input image in parallel. And, orientation assignment and keypoints descriptions computation are executed for all octaves of the input image in paralle. | 2010-07-01 |
| 20100169577 | Cache control device and control method - In order to control an access request to the cache shared between a plurality of threads, a storage unit for storing a flag provided in association with each of the threads is included. If the threads enter the execution of an atomic instruction, a defined value is written to the flags stored in the storage unit. Furthermore, if the atomic instruction is completed, a defined value different from the above defined value is written, thereby displaying whether or not the threads are executing the atomic instruction. If an access request is issued from a certain thread, it is judged whether or not a thread different from the certain thread is executing the atomic instruction by referencing the flag values in the storage unit. If it is judged that another thread is executing the atomic instruction, the access request is kept standby. This makes it possible to realize the exclusive control processing necessary for processing the atomic instruction according to simple configuration. | 2010-07-01 |
| 20100169578 | CACHE TAG MEMORY - A system comprises tag memories and data memories. Sources use the tag memories with the data memories as a cache. Arbitration of a cache request is replayed, based on an arbitration miss and way hit, without accessing the tag memories. A method comprises receiving a cache request sent by a source out of a plurality of sources. The sources use tag memories with data memories as a cache. The method further comprises arbitrating the cache request, and replaying arbitration, based on an arbitration miss and way hit, without accessing the tag memories. | 2010-07-01 |
| 20100169579 | READ AND WRITE MONITORING ATTRIBUTES IN TRANSACTIONAL MEMORY (TM) SYSTEMS - A method and apparatus for monitoring memory accesses in hardware to support transactional execution is herein described. Attributes are monitor accesses to data items without regard for detection at physical storage structure granularity, but rather ensuring monitoring at least at data items granularity. As an example, attributes are added to state bits of a cache to enable new cache coherency states. Upon a monitored memory access to a data item, which may be selectively determined, coherency states associated with the data item are updated to a monitored state. As a result, invalidating requests to the data item are detected through combination of the request type and the monitored coherency state of the data item. | 2010-07-01 |
| 20100169580 | MEMORY MODEL FOR HARDWARE ATTRIBUTES WITHIN A TRANSACTIONAL MEMORY SYSTEM - A method and apparatus for providing a memory model for hardware attributes to support transactional execution is herein described. Upon encountering a load of a hardware attribute, such as a test monitor operation to load a read monitor, write monitor, or buffering attribute, a fault is issued in response to a loss field indicating the hardware attribute has been lost. Furthermore, dependency actions, such as blocking and forwarding, are provided for the attribute access operations based on address dependency and access type dependency. As a result, different scenarios for attribute loss and testing thereof are allowed and restricted in a memory model. | 2010-07-01 |
| 20100169581 | EXTENDING CACHE COHERENCY PROTOCOLS TO SUPPORT LOCALLY BUFFERED DATA - A method and apparatus for extending cache coherency to hold buffered data to support transactional execution is herein described. A transactional store operation referencing an address associated with a data item is performed in a buffered manner. Here, the coherency state associated with cache lines to hold the data item are transitioned to a buffered state. In response to local requests for the buffered data item, the data item is provided to ensure internal transactional sequential ordering. However, in response to external access requests, a miss response is provided to ensure the transactionally updated data item is not made globally visible until commit. Upon commit, the buffered lines are transitioned to a modified state to make the data item globally visible. | 2010-07-01 |
| 20100169582 | Obtaining data for redundant multithreading (RMT) execution - In one embodiment, the present invention includes a method for providing a cache block in an exclusive state to a first cache and providing the same cache block in the exclusive state to a second cache when cores accessing the two caches are executing redundant threads. Other embodiments are described and claimed. | 2010-07-01 |
| 20100169583 | MULTI-PORT MEMORY DEVICE WITH SERIAL INPUT/OUTPUT INTERFACE - A multi-port memory device includes ports, banks, a global data bus, an input/output (I/O) controller, mode register set (MRS), a clock generator, and a test I/O controller. The I/O controller transmits a test signal to the global data bus in response to a mode register enable signal. The MRS generates a test enable signal in response to the mode register enable signal and outputs a mode selection signal which determines a data transmission mode of a test I/O signal in response to the test signal. The clock generator receives an external clock and generates an internal clock based on the external clock in response to the mode selection signal. The test I/O controller inputs/outputs the test I/O signal in synchronism with the internal clock. The mode register enable signal active during a test operation mode for testing a core area of the banks. | 2010-07-01 |
| 20100169584 | SYSTEM AND METHOD FOR ERASING AND WRITING DESKTOP MANAGEMENT INTERFACE DATA UNDER A LINUX SYSTEM - A method for erasing and writing desktop management interface (DMI) data under a Linux system is provided. The method constructs a virtual 8086 mode in the Linux system for executes a PnP calling routine. The method then erase and/or write the DMI data from a management information format database (MIFD) of a basic input/output system (BIOS) in a computer using the PnP calling routine. | 2010-07-01 |
| 20100169585 | Dynamic updating of thresholds in accordance with operating conditons - In some embodiments, a memory control device includes a sensor positioned remotely from a memory device, a register to store an offset value, the offset value corresponding to a difference between a temperature reading of the sensor and an estimated actual temperature of the memory device, and a controller to control an operation of the memory device, wherein the controller is configured to read the offset value from the register and control the operation of the memory device in accordance with the offset value. The controller may be configured to dynamically update the offset value during an operation of the memory device. Other embodiments are disclosed and claimed. | 2010-07-01 |
| 20100169586 | Memory storage device and a control method thereof - The present invention discloses a control method of a memory storage device which includes a high density memory. The high density memory is composed of a plurality of MSB pages and LSB pages. The major feature of the method is such that it determines the property of data by its data length, and then decides where the data is to be written according to its property. | 2010-07-01 |
| 20100169587 | CAUSATION OF A DATA READ AGAINST A FIRST STORAGE SYSTEM TO OPTIONALLY STORE A DATA WRITE TO PRESERVE THE VERSION TO ALLOW VIEWING AND RECOVERY - Machine readable instructions, methods, and systems of causation of a data read against a first storage system to optionally store a data write to preserve the version to allow viewing and recovery are disclosed. In an embodiment, a system for providing secondary data storage and recovery services for one or more networked host nodes includes a server application for facilitating data backup and recovery services; a first data storage medium accessible to the server application; a second data storage medium accessible to the server application; and at least one client application for mapping write locations allocated by the first data storage medium to write locations represented in a logical view of the first data storage medium. | 2010-07-01 |
| 20100169588 | OPTIMIZED MEMORY MANAGEMENT FOR RANDOM AND SEQUENTIAL DATA WRITING - A method and system writes data to a memory device including writing data to varying types of physical write blocks. The method includes receiving a request to write data for a logical block address within an LBA range to the memory device. Depending on whether the quantity of valid data in the memory device meets a predetermined criteria, the data is written to a specific chaotic block, a general chaotic block, or a mapped block. The mapped block is assigned for writing data for the LBA range, the specific chaotic block is assigned for writing data for contiguous LBA ranges including the LBA range, and the general chaotic block is assigned for writing data for any LBA range. Lower fragmentation and write amplification ratios may result by using this method and system. | 2010-07-01 |
| 20100169589 | Redundant storage system using dual-ported drives - The present invention is an apparatus for providing redundant internet protocol (IP) storage. The apparatus includes an ethernet connection for connecting a plurality of users to a network having at least a first computer and a second computer, each computer having pre-boot software that controls whether the operating system is active or on standby, and wherein the pre-boot software of the first computer allows the operating system to be active and the pre-boot software of the second computer maintains the operating system on standby. Each computer is capable of running an operating system, and each computer includes a storage volume wherein each storage volume has dual ports and wherein the contents of the storage volume of the first computer is simultaneously mirrored to the storage volume of the second computer. | 2010-07-01 |
| 20100169590 | Providing backups using a portable storage device - Backing up data from a client includes providing a direct coupling between the client and a portable storage device, copying full backup data from the client to the portable storage device using the direct coupling, and performing at least one incremental backup from the client to the backup site through a network that is separate from the direct coupling. The at least one incremental backup is based on the prior full backup. The network may be the Internet. Following copying full backup data to the portable storage device, the portable storage device may be shipped from the client to the backup site. The direct coupling may be USB, Firewire, or eSATA. Only a subset of data corresponding to a backup dataset may be copied from the client to the portable storage device. | 2010-07-01 |
| 20100169591 | TIME ORDERED VIEW OF BACKUP DATA ON BEHALF OF A HOST - A method and systems of a time ordered view of backup data on behalf of a host are disclosed. In an embodiment, a method to provide a time-ordered snapshot view on behalf of a host of a specified portion of a backup of a first storage system data container stored at a second storage system includes initiating an order at the host to obtain a view of a data container. The order specifies a date and time of the ordered view. The method further includes receiving the order at a server adapted to assemble and enable access to the ordered view, and at the server, accessing the second storage system according to the date and time of the ordered view and accessing an applicable data write representing a data change to the data container. | 2010-07-01 |
| 20100169592 | GENERATING A RECOVERY SNAPSHOT AND CREATING A VIRTUAL VIEW OF THE RECOVERY SNAPSHOT - Methods, software suites, and systems of generating a recovery snapshot and creating a virtual view of the recovery snapshot are disclosed. In an embodiment, a method includes generating a recovery snapshot at a predetermined interval to retain an ability to position forward and backward when a delayed roll back algorithm is applied and creating a virtual view of the recovery snapshot using an algorithm tied to an original data, a change log data, and a consistency data related to an event. The method may include redirecting an access request to the original data based on a meta-data information provided in the virtual view. The method may further include substantially retaining a timestamp data, a location of a change, and a time offset of the change as compared with the original data. | 2010-07-01 |
| 20100169593 | Defer Separating Children in Parallel Copying Garbage Collection - Automatic memory management with a generational copy collector garbage collection algorithm running on parallel threads to perform simultaneous and independent copying and scanning. An object is scanned. It is determined whether an object referenced within the slot of the object being scanned may be copied to the same generation as the scanned object. A mark may be made to indicate that the referenced object may be copied to a different generation than the scanned object. The mark defers the copying of the referenced object. | 2010-07-01 |
| 20100169594 | GRANULAR APPLICATION DATA LIFECYCLE SOURCING FROM A SINGLE BACKUP - A system or method for granular application data lifecycle sourcing from a single backup is disclosed. In one embodiment of the method, a computer system periodically creates a primary backup copy of data stored on a storage system in order to create a plurality of primary backup copies. The computer system also periodically creates a secondary backup copy of data stored on the storage system in order to create a first plurality of secondary backup copies, wherein each of the secondary backup copies of the first plurality is created in part by copying data from a respective one of the primary backup copies. The periodicity of creating the primary backup copies, however, is distinct from the periodicity of creating the secondary backup copies of the first plurality. The computer system can also periodically create another secondary backup copy of data stored on the storage system in order to create a second plurality of secondary backup copies. Each of the secondary backup copies of the first plurality is created in part by copying data from a respective one of the primary backup copies. The periodicity of creating the primary backup copies is distinct from the periodicity of creating the secondary backup copies of the second plurality, and the periodicity of creating the secondary backup copies of the first plurality is distinct from the periodicity of creating the secondary backup copies of the second plurality. | 2010-07-01 |
| 20100169595 | STORAGE BACKUP - A storage system includes a secondary data store for backing up the primary data store, a deleted data store for retention of deleted data, and a data management application for managing the backing up of stored and deleted data of the primary data store. The deleted data store may be either separate from the secondary data store or implemented within the secondary data store. The data management application may automatically free up space for backup of data newly added to or deleted from the primary data store, by selectively removing data from the deleted data store, based application of appropriate criteria. | 2010-07-01 |
| 20100169596 | STORAGE APPARATUS, BACKUP APPARATUS, AND BACKUP METHOD - A storage apparatus includes a second volume which stores data serving as a copying source of data to be stored in a first volume, serving as a data copying destination in another storage apparatus, a session establishing unit which establishes a session between the second volume and the first volume, and a copy directing unit which directs a volume, including a free area, in the other storage apparatus such that data equivalent to the data to be stored in the first volume is copied, in response to a copy setting command issued by a server. | 2010-07-01 |
| 20100169597 | MEMORY SYSTEM - A memory system comprising a volatile memory unit, a nonvolatile memory unit, and a controller that performs data transfer between a host system and the nonvolatile memory unit via the volatile memory unit stores management information including a storage position of the data stored in the nonvolatile memory unit during a startup operation into the volatile memory unit, and performs, while updating stored management information, data management in the volatile and nonvolatile memory units based on the stored management information. The nonvolatile memory unit includes a snapshot storing area storing a snapshot which is the management information stored in the volatile memory unit at a certain point, a main log storing area storing a main log which is an update information of the management information stored in the volatile memory unit, and a backup log storing area storing a backup log having contents same as contents of the main log. The controller stores the management information of the volatile memory unit in the snapshot storing area as a snapshot when a predetermined condition is satisfied, and sequentially stores the main log in the main log storing area when the management information is changed and the backup log in the backup log storing area. | 2010-07-01 |
| 20100169598 | REMOTE STORAGE DISK CONTROL DEVICE AND METHOD FOR CONTROLLING THE SAME - A storage device system includes an information processing device, a first storage device equipped with a first storage volume, and a second storage device equipped with a second storage volume. The information processing device and the first storage device are communicatively connected to one another. Also, the first storage device and the second storage device are communicatively connected to one another. The information processing device is equipped with a first write request section that requests to write data in the first storage device according to a first communications protocol, and a second write request section that requests to write data in the second storage device according to a second communications protocol. The information processing device creates first data including a first instruction to be executed in the second storage device. | 2010-07-01 |
| 20100169599 | Security management in system with secure memory secrets - In some embodiments a Trusted Platform Module (TPM) manages a first flag that identifies whether a secure environment has ever been established. A chipset manages a second flag that identifies that there might have been secrets in memory and a reset or power failure occurred. At least one processor and/or the chipset lock, maintain a lock, and/or unlock a memory in response to the second flag. Other embodiments are described and claimed. | 2010-07-01 |
| 20100169600 | SIGNAL PROCESSOR AND SIGNAL PROCESSING SYSTEM - In a signal processor including storage sections, a start address for starting output of data from an external memory, is input from an external controller to the start address input section. The signal output section outputs a start signal based on a download start instruction from the external controller, and outputs an end signal when download is completed. The output instruction section outputs, based on the start signal, to the external memory a data output instruction of download data for a designated storage section, starting from the start address, and stops output of the data output instruction based on the end signal. The write instruction section outputs a write instruction to the storage sections that allows data writing only to the designated storage section, and the download data is written to the designated storage section when the start signal is input to the output instruction section. | 2010-07-01 |
| 20100169601 | SYSTEM FOR PROTECTING SUPERVISOR MODE DATA FROM USER CODE - A system for protecting supervisor mode data from user code having a processor which implements a register window architecture supporting as separate window stacks for supervisor and user modes with a transition window in one of the window stacks set with at least one invalid window bit in an invalid window mask of the architecture additional to an invalid window bit set for a reserved window of the invalid window mask for transitioning from the supervisor mode to the user mode, supervisor mode-only memory storing the supervisor mode window stack, and user mode accessible memory storing the supervisor and user mode window stacks. | 2010-07-01 |
| 20100169602 | Method and Apparatus for Efficient Memory Placement - A memory profiling system profiles memory objects in various memory devices and identifies memory objects as candidates to be moved to a more efficient memory device. Memory object profiles include historical read frequency, write frequency, and execution frequency. The memory object profile is compared to parameters describing read and write performance of memory types to determine candidate memory types for relocating memory objects. Memory objects with high execution frequency may be given preference when relocating to higher performance memory devices. | 2010-07-01 |
| 20100169603 | METHOD OF PROVIDING TO A PROCESSOR AN ESTIMATED COMPLETION TIME OF A STORAGE OPERATION - A method of performing a storage operation includes: receiving a storage command, estimating the completion time of the associated storage operation, and providing the estimated completion time to a processor. | 2010-07-01 |
| 20100169604 | HYBRID MEMORY DEVICE - A method is provided. The method includes receiving data and classifying received data in one of several tiers of data. The method also includes storing each tier of data on a different non-volatile memory device. | 2010-07-01 |
| 20100169605 | ARBITRARY PRECISION FLOATING NUMBER PROCESSING - Techniques for providing arbitrary precision floating number (APFN) processing are disclosed. In some aspects, an APFN store may be used to store a large number (i.e., an APFN) having many significant digits, which in turn may enable a high degree of precision in mathematical operations. An APFN module may be used to create and define the APFN store. The APFN module may enable a user to define a precision (significant digits) for the large number that corresponds to the size of an array of bytes in the APFN store that are allocated for storing the large number. In further aspects, the APFN store may be used to store additional intermediary data and a resultant. | 2010-07-01 |
| 20100169606 | PROCESSOR AND METHOD FOR USING AN INSTRUCTION HINT TO PREVENT HARDWARE PREFETCH FROM USING CERTAIN MEMORY ACCESSES IN PREFETCH CALCULATIONS - A microprocessor includes a cache memory, a prefetch unit, and detection logic. The prefetch unit may be configured to monitor memory accesses that miss in the cache and to determine whether to prefetch one or more blocks of memory from a system memory based upon previous memory accesses. The prefetch unit may be further configured to use addresses of the memory accesses that miss to calculate each next memory block to prefetch. The detection logic may be configured to provide a notification to the prefetch unit in response to detecting a memory access instruction including a particular hint. In response to receiving the notification, the prefetch unit may be configured to inhibit using an address associated with the memory access instruction including the particular hint, when calculating subsequent memory blocks to prefetch. | 2010-07-01 |
| 20100169607 | RECONFIGURABLE CIRCUIT, ITS DESIGN METHOD, AND DESIGN APPARATUS - A reconfigurable circuit design method includes an input step of inputting design data of a default configuration of a reconfigurable circuit including a plurality of processor elements which perform processing and a first generation step of generating design data obtained by modifying at least one of the processor elements in the reconfigurable circuit with the default configuration. | 2010-07-01 |
| 20100169608 | FLEXIBLE COUNTER UPDATE AND RETRIEVAL - A network device includes one or more processing units and an external memory. Each of the one or more processing units includes a centralized counter configured to perform accounting for the respective processing unit. The external memory is associated with at least one of the one or more processing units and is configured to store a group of count values for the at least one processing unit. | 2010-07-01 |
| 20100169609 | Method for optimizing voltage-frequency setup in multi-core processor systems - A method for dynamically operating a multi-core processor system is provided. The method involves ascertaining currently active processor cores, identifying a currently active processor core having a lowest operating frequency, and adjusting at least one operational parameter according to voltage-frequency characteristics corresponding to the identified processor core to fulfill a predefined functional mode, e.g. power optimization mode, performance optimization mode and mixed mode. | 2010-07-01 |
| 20100169610 | PROCESSOR - The processor according to the present invention is a processor having a forwarding function and includes an attribute information holding unit that holds attribute information regarding inhibition of writing to a register and a register write inhibition circuit that holds, when forwarding is performed, the writing of the data forwarded according to attribute information. The attribute information holding unit holds the attribute information by relating the attribute information to at least one register. Alternatively, the attribute information holding unit is a part of plural pipeline buffers and passes the attribute information along with the data to be forwarded, to a pipeline buffer in a subsequent stage. | 2010-07-01 |
| 20100169611 | BRANCH MISPREDICTION RECOVERY MECHANISM FOR MICROPROCESSORS - A system and method for reducing branch misprediction penalty. In response to detecting a mispredicted branch instruction, circuitry within a microprocessor identifies a predetermined condition prior to retirement of the branch instruction. Upon identifying this condition, the entire corresponding pipeline is flushed prior to retirement of the branch instruction, and instruction fetch is started at a corresponding address of an oldest instruction in the pipeline immediately prior to the flushing of the pipeline. The correct outcome is stored prior to the pipeline flush. In order to distinguish the mispredicted branch from other instructions, identification information may be stored alongside the correct outcome. One example of the predetermined condition being satisfied is in response to a timer reaching a predetermined threshold value, wherein the timer begins incrementing in response to the mispredicted branch detection and resets at retirement of the mispredicted branch. | 2010-07-01 |
| 20100169612 | Data-Processing Unit for Nested-Loop Instructions - A data-processing unit has a fetching circuitry ( | 2010-07-01 |
| 20100169613 | TRANSLATING INSTRUCTIONS IN A SPECULATIVE PROCESSOR - A method for use by a host microprocessor which translates sequences of instructions from a target instruction set for a target processor to sequences of instructions for the host microprocessor including the steps of beginning execution of a speculative sequence of target instructions by committing state of the target processor and storing memory stores previously generated by execution at a point in the execution of instructions at which state of the target processor is known, executing the speculative sequence of host instructions until another point in the execution of target instructions at which state of the target processor is known, rolling back to last committed state of the target processor and discarding the memory stores generated by the speculative sequence of host instructions if execution fails, and beginning execution of a next sequence of target instructions if execution succeeds. | 2010-07-01 |
| 20100169614 | PROCESSOR FOR EXECUTING HIGHLY EFFICIENT VLIW - A 32-bit instruction | 2010-07-01 |
| 20100169615 | Preloading Instructions from an Instruction Set Other than a Currently Executing Instruction Set - A preload instruction in a first instruction set is executed at a processor. The preload instruction causes the processor to preload one or more instructions into an instruction cache. The pre-loaded instructions are pre-decoded according to a second instruction set that is different from the first instruction set. The preloaded instructions are pre-decoded according to the second instruction set in response to an instruction set preload indicator (ISPI). | 2010-07-01 |
| 20100169616 | REDUCING INSTRUCTION COLLISIONS IN A PROCESSOR - An embodiment of a technique for selecting instructions for execution from an issue queue at multiple function units while reducing the chances of instruction collisions. Each function unit in a processor may include a selection logic circuit that selects a specific instruction from the issue queue for execution. In order to avoid instruction collision, a function unit may have a selection logic circuit that may select two instructions from an instruction queue: one according to a first selection technique and one according to a second selection technique. Then, by comparing the instruction selected by the first selection technique to the instruction selected by the selection logic circuit of another function unit, the instruction selected by the second technique may be used instead if there will be an instruction collision because the instruction selected by the first selection technique is the same as the instruction selected at a different function unit. | 2010-07-01 |
| 20100169617 | POWER EFFICIENT SYSTEM FOR RECOVERING AN ARCHITECTURE REGISTER MAPPING TABLE - A system for recovering an architecture register mapping table (ARMT). The system includes a first number of collection circuits and decode circuits, a second number of selection circuits, and an enable circuit. Information related to the mapping between each physical register and an appropriate architecture register is obtained from a physical register mapping table (PRMT) by one and only one collection circuit during only one of a fourth number of instruction cycles. Each decode circuit has its input coupled to the output of one different collection circuit and is capable of converting its input into a third number bit wide binary string selection code at its output. Each selection circuit is configured to receive from each selection code a bit from a bit position associated with that selection circuit. The enable circuit is configured to appropriately enable mapping of information from the PRMT to the ARMT. | 2010-07-01 |
| 20100169618 | IDENTIFYING CONCURRENCY CONTROL FROM A SEQUENTIAL PROOF - The claimed subject matter provides a system and/or a method that facilitates ensuring non-interference between multiple threads that access a shared resource. An interface can receive a portion of sequential code, wherein the portion of sequential code includes a property that is maintained and relied upon when invoked and executed by a sequential client. A synthesizer component can leverage a sequential proof related to the portion of sequential code in order to derive a concurrency control mechanism for a portion of concurrency code that maintains the property when invoked by a concurrent client, wherein the sequential proof identifies a concurrent interference at an execution point that is tolerable for the concurrent client. | 2010-07-01 |
| 20100169619 | Efficient Encoding for Detecting Load Dependency on Store with Misalignment - In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a store memory operation, and is configured to write a first even offset, a first even mask, a first odd offset, and a first odd mask corresponding to the store memory operation to the first entry. A group of contiguous memory locations are logically divided into alternately-addressed even and odd byte ranges. A given store memory operation writes at most one even byte range and one adjacent odd byte range. The first even offset identifies a first even byte range that is potentially written by the store memory operation, and the first odd offset identifies a first odd byte range that is potentially written by the store memory operation. The first even mask identifies bytes within the first even byte range that are written by the store memory operation, and wherein the first odd mask identifies bytes within the first odd byte range that are written by the store memory operation. | 2010-07-01 |
| 20100169620 | SIGNAL PROCESSING DEVICE, SIGNAL PROCESSING METHOD, AND PROGRAM - There is provided a signal processing device which is capable of suppressing the influence of a digital data process on an analog signal process without completely stopping a digital data processing circuit. A signal processing device includes an analog signal processing circuit, a digital data processing circuit, a determination section configured to determine an influence of the digital data processing circuit on the analog signal processing circuit, and a control section configured to stop a partial circuit of the digital data processing circuit or lower processing capability thereof in response to a determination result of the determination section. | 2010-07-01 |
| 20100169621 | PROCESSOR TEST APPARATUS, PROCESSOR TEST METHOD, AND PROCESSOR TEST PROGRAM - A processor test method of testing a processor includes executing each test instruction of a test instruction sequence to obtain a condition code set by a condition code setting instruction of the test instruction sequence for testing the processor; producing a condition branching instruction to add the produced condition branching instruction to the end of the condition code setting instruction of the test instruction sequence, the condition branching instruction branching to an error output instruction when a condition code that does not match the obtained condition code is supplied; and executing, by an advanced control scheme, a test instruction sequence in which the condition branching instruction is added to the test instruction sequence. | 2010-07-01 |
| 20100169622 | PROCESSOR REGISTER RECOVERY AFTER FLUSH OPERATION - An information handling system includes a processor that may perform general purpose register recovery operations after an instruction flush operation that an exception, such as a branch misprediction causes. The processor receives an instruction stream that may include multiple instructions that operate on a particular target register that stores instruction result information. The general purpose register may temporarily store instruction opcode and register bits information for use during dispatch, execution and other operations. The processor includes a recovery buffer unit for use during flush recovery operations. The processor may use recovery valid and recovery pending bits that correspond with each instruction during the register recovery from flush operation. | 2010-07-01 |
| 20100169623 | Method and System for Reducing Abort Rates in Speculative Lock Elision using Contention Management Mechanisms - Hardware-based transactional memory mechanisms, such as Speculative Lock Elision (SLE), may allow multiple threads to concurrently execute critical sections protected by the same lock as speculative transactions. Such transactions may abort due to contention or due to misidentification of code as a critical section. In various embodiments, speculative execution mechanisms may be augmented with software and/or hardware contention management mechanisms to reduce abort rates. Speculative execution hardware may send a hardware interrupt signal to notify software components of a speculative execution event (e.g., abort). Software components may respond by implementing concurrency-throttling mechanisms and/or by determining a mode of execution (e.g., speculative, non-speculative) for a given section and communicating that determination to the hardware speculative execution mechanisms, e.g., by writing it into a lock predictor cache. Subsequently, hardware speculative execution mechanisms may determine a preferred mode of execution for the section by reading the corresponding entry from the lock predictor cache. | 2010-07-01 |
| 20100169624 | Adaptive Fetch Advance Control for a Low Power Processor - A digital signal processor (DSP) includes an instruction buffer queue (IBQ) with multiple lines, as well as a modifiable fetch advance parameter to specify a fetch advance setting for the IBQ. The DSP also has a control flow module. In response to execution of a program in the DSP, the control flow module may automatically determine whether a branch has been predicted for the program, or for a portion of the program. The control flow module may automatically reduce the fetch advance parameter in response to determining that a branch has been predicted for the program. Also, the control flow module may automatically increase the fetch advance setting in response to determining that no branch has been predicted for a portion of the program. Other embodiments are described and claimed. | 2010-07-01 |
| 20100169625 | REDUCING BRANCH CHECKING FOR NON CONTROL FLOW INSTRUCTIONS - Some microprocessors check branch prediction information in a branch history table and/or a branch target buffer. To check for branch prediction information, a microprocessor can identify which instructions are control flow instructions and which instructions are non control flow instructions. To reduce power consumption in the branch history table and/or branch target buffer, the branch history table and/or branch target buffer can check for branch prediction information corresponding to the control flow instructions and not the non control flow instructions. | 2010-07-01 |
| 20100169626 | SYSTEM AND METHOD FOR A MULTI-SCHEMA BRANCH PREDICTOR - A system and method for predicting the execution of a branch of computer-executable instructions. In an embodiment, a branch predictor may include a program-counter register operable to store a program-counter value and a branch-history register operable to store a branch-history value. Additionally, the branch predictor may include a prediction hash table having a plurality of prediction values each uniquely corresponding to a plurality of memory locations. With these components, the branch predictor may generate a first prediction value that corresponds to the program-counter value and may generate a second prediction value that corresponds to a logical combination of the program-counter value and the branch-history value. With these two prediction values obtained from two different prediction schemas, the branch predictor is better suited to generate an overall prediction value based on the first and second prediction values that is more accurate than a single prediction value based upon a single prediction schema. | 2010-07-01 |
| 20100169627 | System and method for repairing a speculative global history record - A system and method are provided for updating a speculative global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts microprocessor instructions with consecutive operations, including a conditional branch operation with an associated first branch address. A speculative global history record (SGHR) of conditional branch resolutions and predictions is accessed and hashed with the first branch address, creating a first hash result. The first hash result is used to index a branch history table (BHT) of previous first branch resolutions. As a result, a first branch prediction is made, and the SGHR is updated with the first branch prediction. A non-speculative global history record (NSGHR) of branch resolutions is updated with the resolution of the first branch operation, and if the first branch prediction is incorrect, the SGHR is corrected using the NSGHR. | 2010-07-01 |
| 20100169628 | Controlling non-redundant execution in a redundant multithreading (RMT) processor - In one embodiment, the present invention includes a method for controlling redundant execution such that if an exceptional event occurs, the redundant execution is stopped, non-redundant execution is performed in one of the threads until the exceptional event has been-resolved, after which a state of the threads is synchronized, and redundant execution is continued. Other embodiments are described and claimed. | 2010-07-01 |
| 20100169629 | METHOD FOR CONFIGURING COMPUTER BY BIOS, SERVER, COMPUTER, SYSTEM STARTUP METHOD AND COMPUTER SYSTEM - A method for configuring computer by Basic Input/Output System (BIOS), a server and a computer are provided. The method comprising the steps of: setting up a connection to a server storing configuration information for the computer through a network; acquiring the configuration information for the computer from the server; and configuring the computer based on the configuration information. With the solutions according to the embodiments of the present invention, it is convenient in setting the configuration information, especially for the case where it is required to set the configuration information for a number of computers. In this way, the labor efficiency can be effectively improved and the security of the configuration information can be effectively enhanced. | 2010-07-01 |
| 20100169630 | Pre-boot Recovery of a Locked Computer System - Embodiments of the present disclosure provide methods, apparatuses, articles, and removable storage devices for pre-boot recovery of a locked computer system. Other embodiments may also be described and claimed. | 2010-07-01 |
| 20100169631 | AUTHENTICATION FOR RESUME BOOT PATH - Methods and systems to perform an authentication operation after resuming from a sleep state are presented. In one embodiment, a method includes starting a boot process from a sleep state. The method further includes providing platform services to support an authentication operation as part of the boot process and determining whether to complete the boot process based at least on results of the authentication operation. | 2010-07-01 |
| 20100169632 | Component Configuration Mechanism for Rebooting - Aspects of the invention support a component configuration mechanism when rebooting a circuit module ( | 2010-07-01 |
| 20100169633 | SYSTEM AND METHOD TO SECURE BOOT BOTH UEFI AND LEGACY OPTION ROM'S WITH COMMON POLICY ENGINE - In some embodiments, the invention involves using a policy engine during boot, in the driver execution environment (DXE) phases to authenticate that drivers and executable images to be loaded are authenticated. Images to be authenticated include the operating system (OS) loader. The policy engine utilizes a certificate database to hold valid certificates for third party images, according to platform policy. Images that are not authenticated are not loaded at boot time. Other embodiments are described and claimed. | 2010-07-01 |
| 20100169634 | SYSTEM AND METHOD FOR SELF-CLOCKING OS KERNEL BOOT - In some embodiments, the invention involves a system and method to enable a mobile device to utilize self-clocking during boot. In at least one embodiment, a platform has at least one processor core coupled to an internal timer. For an X86 processor, the internal timer may reside in an advanced programmable interrupt controller. A boot kernel executing on the platform is configured to use the internal timer early in the boot phase, when the platform is not compliant with legacy PC/AT architecture. If the platform does conform to the legacy architecture, then the boot may use an external clock for timing and clocking early in boot. In both cases, the internal timer is calibrated to the external clock before completing the boot phase. Other embodiments are described and claimed. | 2010-07-01 |
| 20100169635 | METHOD AND SYSTEM TO FACILITATE CONFIGURATION OF A HARDWARE DEVICE IN A PLATFORM - A method and system to allow the secure configuration of the configurable feature(s) of a hardware device in a platform. The configuration of the configurable feature(s) of the hardware device is performed with protection against software attacks. A management module determines that the platform is authorized to configure at least one configurable feature of the hardware device and configures each of the configurable feature(s) based on a received configuration message. | 2010-07-01 |
| 20100169636 | System and Method For a Secure I/O Interface - A security processor performs all or substantially all security and network processing to provide a secure I/O interface system to protect computing hardware from unauthorized access or attack. The security processor sends and receives all incoming and outgoing data packets for a host device and includes a packet engine, coupled to a local data bus, to process the incoming and outgoing packets. The processor further comprises a cryptographic core coupled to the packet engine to provide encryption and decryption processing for packets processed by the packet engine. The packet engine also handles classification processing for the incoming and outgoing packets. A modulo engine may be coupled to the local data bus. | 2010-07-01 |
| 20100169637 | PALETTE FOR REAL-TIME DISPLAY OF PREVIOUSLY ACCESSED DOCUMENTS - Palette for real-time display of previously accessed documents. At some of the illustrative embodiments are methods comprising rendering on a display a palette proximate to a window of a Web-Browser, the rendering by executing a software application by a processor, enabling a first mode of the palette, obtaining information pertaining to each of a series of Webpages previously accessed by the Web-Browser; and displaying within the palette at least some of the information pertaining to the Webpages and a reduced resolution image of one of the Webpages previously accessed. | 2010-07-01 |
| 20100169638 | COMMUNICATION SYSTEM HAVING MESSAGE ENCRYPTION - A system includes a communication device configured to transmit a message to an unsecured server. A secured server is in communication with the communication device, and is configured to receive the message from the communication device before the message is transmitted to the unsecured server, encrypt the message, and transmit the encrypted message to the unsecured server. | 2010-07-01 |
| 20100169639 | METHOD FOR MANAGING A GLOBALLY ACCESSIBLE OPERATIONAL DATA WAREHOUSE SYSTEM WITH IMPROVED SECURITY AND CONSUMER RESPONSE - A secure data exchange and access system, method, and architecture for allow web-based data transfer with improved security and scalability. The system incorporates and enables serialized pedigree systems while allowing security for storing, authenticating, and tracking a change of custody of a serialized item along a transfer chain. A plurality of independent databases, respectively blind to each other but for a global construct, retains pieces of information along a product supply chain. Specific encryption/decryption protocols enable secure information transfer in a number of modes including a post point of sale anti-counterfeiting system that includes a process for consumer involvement as a triggering mechanism. | 2010-07-01 |
| 20100169640 | Method and system for enterprise network single-sign-on by a manageability engine - A manageability engine (ME) receives an authentication response from a user during pre-boot authentication and registers the user with a key distribution center (KDC), indicating that the user has successfully authenticated to the PC. The KDC supplies the ME with single-sign-on credentials in the form of a Key Encryption Key (KEK). The KEK may later be used by the PC to obtain a credential used to establish secure access to Enterprise servers. | 2010-07-01 |
| 20100169641 | Trust Authority Supporting Digital Communication - A trust authority includes a network connected server executing trust service software stored in a machine-readable medium, one or more network ports for communicating on the network, and a data repository coupled to the server, the repository storing indications of trustworthiness for one or both of enterprises and agents of enterprises. Queries from remote entities, the queries pertaining to one or both of enterprises and agents, are received at the server, and the trust service software, in response to the queries, provides to the remote entities providing the queries indications of trustworthiness for the one or both of enterprises and agents. | 2010-07-01 |
| 20100169642 | Remote virtual medical diagnostic imaging viewer - A medical image and data application service provider system provides a way of remotely viewing and manipulating medical images and data for diagnostic and visualization purposes by users unconstrained by geography. Medical images and data are stored on one or more servers running application service provider software along with meta-data such as access control information, origin of information and references to related data. A set of medical data consisting related information is sent as an encrypted stream to a viewing station running client software in a secure execution environment that is logically independent of the viewing station's operating system. | 2010-07-01 |
| 20100169643 | PROOF VERIFICATION SYSTEM, PROVING DEVICE, VERIFYING DEVICE, PROOF VERIFICATION METHOD, AND PROGRAM - The proof verification system of the present invention is composed of a proving device ( | 2010-07-01 |
| 20100169644 | Message authentication code with elliptic polynomial hopping - The message authentication code with elliptic polynomial hopping provides methods for the generation of message authentication codes (MACs) utilizing elliptic curves, which are based on the elliptic curve discrete logarithm problem. The elliptic curve discrete logarithm problem is well known to be a computationally “difficult” or “hard” problem, thus providing enhanced security for the MACs. Different elliptic polynomials are used for different blocks of the same plaintext, each elliptic polynomial for each message block being selected at random using an initial secret key and a random number generator. | 2010-07-01 |
| 20100169645 | KEY TRANSPORT IN AUTHENTICATION OR CRYPTOGRAPHY - A computer system for authenticating, encrypting, and transmitting a secret communication, where the encryption key is transmitted along with the encrypted message, is disclosed. In an embodiment, a first transmitting processor encrypts a plaintext message to a ciphertext message using a data key, encrypts the data key using a key encrypting key, and sends a communication comprising the encrypted data key and the ciphertext message. A second receiving processor receives the communication and then decrypts the encrypted data key using the key encrypting key and decrypts the ciphertext message using the data key to recover the plaintext message. | 2010-07-01 |
| 20100169646 | SECURE AND EFFICIENT DOMAIN KEY DISTRIBUTION FOR DEVICE REGISTRATION - A domain key is securely distributed from a device in an existing network to a device outside the network. Each device generates the session key on its own using the first random number, the second random number, the Personal Identification Number, and the same key generation function. The device in the existing network sends the domain key encrypted with the session key to the other device. | 2010-07-01 |
| 20100169647 | Data Transmission - A method of and apparatus for transmitting data in systems such as computer networks, for example in client-server or peer-to-peer arrangements. Access to transmitted data received by a destination apparatus is limited by the provision of software code at the destination apparatus. The software code is arranged to produce a result which is a function of the state of the destination apparatus, and this result is used to access the data. The software code may be either transmitted to the destination apparatus, for example along with the data it is used to access or from a separate server, or may be generated at the destination apparatus. The method and apparatus is particularly applicable in the field of on-line gaming, wherein the transmitted data is encrypted gaming data and the result of the software code provides the access key to the encrypted data. | 2010-07-01 |
| 20100169648 | COMMUNICATION TERMINAL APPARATUS AND INFORMATION COMMUNICATION METHOD - An information communication method performed by a communication terminal apparatus, the method including: sharing a first encryption key with a first server; receiving a request for sending identification information of the communication terminal apparatus; authenticating the first server based on certificate information of the first server that is acquired while sharing the first encryption key and verification information retained in the communication terminal apparatus; encrypting the identification information of the communication terminal apparatus using a second encryption key; and encrypting, using the first encryption key, according to an authentication result, encrypted identification information of the communication terminal apparatus as generated by using the second encryption key, and transmitting resulting double-encrypted identification information of the communication terminal apparatus to the first server. | 2010-07-01 |
| 20100169649 | Image encryption for print-and-scan channels using pixel position permutation - An image encryption method that includes receiving image data based on an image, wherein the image data comprises a plurality of pixel values, and permuting a plurality of, and preferably all of, the pixel values using at least a secret key to create permuted image data. Also, an image decryption method that includes scanning a printed image to create scanned image data. The printed image is generated from permuted image data that is generated by permuting a plurality of first pixel values of first image data using at least a secret key, obtaining a plurality of second pixel values from the scanned image data, and reverse-permuting a plurality of the second pixel values using at least the secret key to create reverse-permuted scanned image data. | 2010-07-01 |
| 20100169650 | STORAGE MINIMIZATION TECHNIQUE FOR DIRECT ANONYMOUS ATTESTATION KEYS - A storage minimization technique for direct anonymous attestation (DAA) keys is presented. In one embodiment, the method includes deriving a random portion of a (DAA) private key from a device's fuse key, computing a point on an elliptical curve from the derived random portion and a master private key, and storing only one coordinate of the point in fuses within the device. Other embodiments are described and claimed. | 2010-07-01 |
| 20100169651 | Electronically Signing a Document - An electronic signature device includes a processor, a memory, a user input device including a first biometric input device, and a device interface, all communicatively connected by at least one bus. A method of personalizing the electronic signature device to a user includes receiving a digitized biometric signature of the user via the first biometric input device. A cryptographic key is generated. A biometric electronic template is generated based on the digitized biometric signature. The cryptographic key and the biometric electronic template are stored in the memory. | 2010-07-01 |
| 20100169652 | DIGITAL WATERMARKING SYSTEMS AND METHODS - Systems and methods for protecting digital content using digital watermarks and for distributing that protected digital content are described. The digital watermark contains watermark information, fingerprint information, and any other information desired by the provider of the digital content. To insert the digital watermark in the digital content, a section of the digital content is selected, whether it is a random section or a desired section (such as the first or last section), and then that section is broken into a given number of individual slides. The digital watermark is created as an additional slide or frame and then placed between the slides of that section. These individual slides, which now contain the watermark, are re-combined and then re-attached to the remainder of the digital content when desired, such as on the fly or at the time of the user's purchase of the digital content. The user (or other viewer) receives only a single packet of information for the digital content, rather than numerous packets of information, preventing compression and decompression processes from avoiding the watermark since any such compression would not only diminish the slide with the watermark on it, but also the content and render the digital content unusable. Other embodiments are described. | 2010-07-01 |
| 20100169653 | APPARATUS, METHOD, AND PROGRAM FOR DIGITAL SIGNATURE - A digital signature method to generate a signature for an electronic document, the method including: initializing a signature t of each of the document segments of electronic document and twice raising the signature t to the power of a hash value of each of the document segments and digitally signing the raised signature to produce a signature s serving as the signature of the electronic document; and revising a document segment; wherein, in the revising, to delete a document segment, the signature t is raised twice to the power of the hash value of the document segment unless the document segment is sanitization prohibited, or the signature t is raised to the power of the hash value of the document if the document segment is sanitization prohibited, and the document segment is deleted; to sanitize a document segment, the document segment is replaced with the hash value thereof. | 2010-07-01 |
| 20100169654 | METHOD FOR AUTHOR VERIFICATION AND SOFTWARE AUTHORIZATION - Embodiments of the present invention are directed to a computer-implemented method for author verification and authorization of object code. In one embodiment, program object code is linked with a plurality of data blocks to create linked object code and a MAP file. Thereafter, author verification is performed by executing a plurality of comparisons between the linked object code and the MAP file. In another embodiment, a digital signing procedure is performed on linked object code by creating a signature data block. The signature data block is then encrypted and written to the linked object code to create digitally-signed object code. In another embodiment, an application program embodied in linked object code generates a data packet. The data packet is then compared to a previously-generated signature data packet from the linked object code to determine if the linked object code is authorized. | 2010-07-01 |
| 20100169655 | BLOCKING OF UNLICENSED AUDIO CONTENT IN VIDEO FILES ON A VIDEO HOSTING WEBSITE - A system, method and various software tools enable a video hosting website to automatically identified unlicensed audio content in video files uploaded by users, and initiate a process by which the user can replace the unlicensed content with licensed audio content. An audio replacement tool is provided that enables the user to permanently mute the original, unlicensed audio content of a video file, or select a licensed audio file from a collection of licensed audio, and insert the selected in place of the original audio. Where a video file includes unlicensed audio, the video hosting website provides access to video files to a client device, along with an indication to the client device to mute the audio during playback of the video. | 2010-07-01 |
| 20100169656 | GROUP SIGNATURE SYSTEM, DEVICE, AND PROGRAM - A group signature system includes a group manager device, a signer device and a verifier device capable of communicating with each other, each device using a group signature scheme. The group manager device generates a group secret key, a group public key, a member secret key and a signer tracing information. The signer device generates an encrypted text data of the signer tracing information, and a zero-knowledge proof showing that the signer device knows the member secret key and the encrypted text data is correctly generated based on the signer tracing information. The signer device transmits, to the verifier device, a group signature composed of the encrypted text data and the zero knowledge proof, and the message. The verifier device verifies correctness of the group signature and transmits the verified result to the signer device. | 2010-07-01 |
| 20100169657 | Message authentication code with blind factorization and randomization - The message authentication code with blind factorization and randomization is a computational method for improving the security of existing Message Authentication Code (MAC) methods through the use of blind integer factorization. Further, blind randomization is used as a countermeasure to minimize collision attacks where different plaintexts produce the same MAC. | 2010-07-01 |
| 20100169658 | Elliptic curve-based message authentication code - The elliptic curve-based message authentication code is a computational method for improving the security of existing message authentication code (MAC) generating methods through the use of elliptic curve cryptography. Particularly, the message authentication codes and elliptic curve cryptography are based on an elliptic curve discrete logarithm problem, which is well known in mathematics to be a computationally hard problem. | 2010-07-01 |
| 20100169659 | GAMING CONSOLE-SPECIFIC USER AUTHENTICATION - Systems, methods, and computer program products are provided for user authentication required for conducting online financial institution transactions. The disclosed embodiments leverage the capabilities of platforms other than conventional personal computers and laptops, such as gaming consoles and wireless devices. Unique intrinsic user activities, such as controller motions or activities, built-in hardware signatures or other input data associated with a gaming console are used as the authentication mechanism, so as to provide a higher degree of security in the overall authentication process by lessening the likelihood of password replication or interception during network communication. | 2010-07-01 |
| 20100169660 | PUBLIC KEY INFRASTRUCTURE-BASED FIRST INSERTED SUBSCRIBER IDENTITY MODULE SUBSIDY LOCK - A method, telecommunication apparatus, and electronic device for securely creating an identity data block are disclosed. A secure memory | 2010-07-01 |
| 20100169661 | SIMULTANEOUS STATE-BASED CRYPTOGRAPHIC SPLITTING IN A SECURE STORAGE APPLIANCE - Methods and systems for managing I/O requests in a secure storage appliance are disclosed. One method includes receiving a plurality of I/O requests at the secure storage appliance, each I/O request associated with a block of data and a volume, each volume associated with a plurality of shares stored on a plurality of physical storage devices. The method further includes storing a plurality of blocks of data in buffers of the secure storage appliance, each of the blocks of data associated with one or more of the plurality of I/O requests. The method also includes associating a state with each of the blocks of data, the state selected from a plurality of states associated with processing of an I/O request. The method includes determining the availability of a resource in the secure storage appliance, the resource used to process an I/O request of a buffer, and, upon determining that the resource is available, applying the resource to a block of data in the buffer and updating the state associated with the block of data. | 2010-07-01 |
| 20100169662 | SIMULTANEOUS STATE-BASED CRYPTOGRAPHIC SPLITTING IN A SECURE STORAGE APPLIANCE - Methods and systems for managing data blocks and I/O requests are provided. One method is a method of managing data blocks in a secure storage appliance. The method includes receiving a block of data associated with a volume, the volume associated with a plurality of shares stored on a plurality of physical storage devices, and storing the block of data in a buffer. The method also includes associating the block of data with a state from among a plurality of states, each of the states corresponding to a status of the block of data. The method further includes processing the block of data by performing at least one cryptographic operation on the block of data, and upon completion of processing the block of data, updating the state of the block of data. | 2010-07-01 |
| 20100169663 | Systems and Methods for Detecting Authorized Players - One embodiment includes method for determining whether a player application is authorized to play protected content. The method comprises reading a digital signature associated with the player application from a predetermined memory location using a protection interface associated with the player application, where the digital signature comprises one or more file designations. The embodiment further comprises mapping, by the protection interface, the one or more file designations to one or more files associated with the player application and transmitting mapping information from the protection interface to a verification application stored on a storage medium. The verification application is configured to determine whether the player application is authorized to play the protected content if the one or more file designations match the one or more files based on the mapping information. | 2010-07-01 |
| 20100169664 | SECURITY PROCESSOR AND RECORDING METHOD AND MEDIUM FOR CONFIGURING THE BEHAVIOUR OF THIS PROCESSOR - Security processor ( | 2010-07-01 |
| 20100169665 | METHOD FOR INDEXING ENCRYPTED COLUMN - The present invention relates to a method of creating indexes so that an index scan can be worked for columns in a database encrypted by means of secrete key cipher algorithm. The method of creating indexes according to the present invention comprises the steps of: re-encrypting to be able to maintain the sort ordering based on a plain text; creating new indexes based on the re-encrypted data; and configuring domain index architecture of encrypted columns so that the created index is used for the index scan in a query | 2010-07-01 |
| 20100169666 | METHODS AND SYSTEMS TO DIRECLTY RENDER AN IMAGE AND CORRELATE CORRESPONDING USER INPUT IN A SECUIRE MEMORY DOMAIN - Methods and systems to assign an application and a video frame buffer to a protected memory domain to render an image of a keyboard from the protected memory domain to a random position of the video frame buffer and correlate user input from a pointing device to the rendered keyboard image. The keyboard image may be randomly repositioned following a user input. The keyboard image may be rendered over a secure user image. An acknowledgment image may be rendered from the protected memory domain to a random position of the video frame buffer, and may be randomly repositioned in response to a user input that does not correlate to the acknowledgment image. User inputs that do not correlate to a randomly positioned image may be counted, and one or more processes may be aborted when the number of non-correlated user inputs exceeds a threshold. | 2010-07-01 |
