26th week of 2010 patent applcation highlights part 33 |
Patent application number | Title | Published |
20100165660 | BACKLIGHT AND DISPLAY SYSTEM USING SAME - A backlight that includes a front reflector and a back reflector that form a hollow light recycling cavity including an output surface is disclosed. The backlight further includes one or more light sources disposed to emit light into the light recycling cavity. The front reflector includes an on-axis average reflectivity of at least 90% for visible light polarized in a first plane, and an on-axis average reflectivity of at least 25% but less than 90% for visible light polarized in a second plane perpendicular to the first plane. | 2010-07-01 |
20100165661 | Lighting device - A lighting device includes: a light guide plate having a light incident part in an end face and a light radiation part in a flat plate surface; a light source part opposed to the light incident part; a light shield member with which an area near the light incident part on the flat plate surface of the light guide plate is covered; and a switch part including a switch main body, a switch knob and a pressing member connected to the switch knob to press the switch main body by pressing down the switch knob. An end part of the switch knob opposed to a center of the flat plate surface of the light guide plate is located on the light shield member, and the end face of the light guide plate is located between a first virtual line passing the end part of the switch knob and perpendicular to the flat plate surface of the light guide plate and a second virtual line passing the center of the switch main body and perpendicular to the flat plate surface of the light guide plate. | 2010-07-01 |
20100165662 | BACKLIGHT UNIT - A backlight unit that while attaining cost reduction, realizes inhibiting of a light quantity decrease in the vicinity of an end portion of light guide plate and achieving of an enhancement of light utilization efficiency. Backlight unit ( | 2010-07-01 |
20100165663 | Optical plate and backlight module using the same - An optical plate includes a first surface and a second surface opposite to the first surface. A plurality of elongated, arc-shaped depressions is defined in the first surface. A plurality of elongated, arc-shaped protrusions and a plurality of elongated, V-shaped protrusions protrude from the second surface. An extending direction of the elongated, arc-shaped protrusions intersects with an extending direction of the elongated, V-shaped protrusions. An extending direction of elongated, arc-shaped depressions is substantially parallel with the extending direction of the elongated, arc-shaped protrusions. | 2010-07-01 |
20100165664 | Gate driving circuit - A primary circuit turns on switching elements and generates energy from a direct-current power supply to a secondary circuit through a transformer. The secondary circuit charges a driven element using the energy obtained from the primary circuit through the transformer, turns on a switching element, discharges the energy accumulated in the driven element, and generates the energy in the primary circuit through the transformer. The primary circuit returns the energy obtained from the secondary circuit to the direct-current power supply. | 2010-07-01 |
20100165665 | Power supply control circuit and method for sensing voltage in the power supply control circuit - The present invention discloses a power supply control circuit, the power supply providing an output voltage to an output terminal from an input terminal through a transformer having a primary winding and a secondary winding, the power supply control circuit comprising: a power switch electrically connected with the primary winding; a switch control circuit controlling the power switch; and a sensing circuit supplying an output signal to the switch control circuit according to voltage signals obtained from two sides of the primary winding, wherein the sensing circuit includes a setting circuit for deciding the output voltage according to a reference signal. The present invention also relates to a voltage sensing method in the power supply control circuit. | 2010-07-01 |
20100165666 | PRIMARY-SIDE FEEDBACK CONTROL DEVICE AND RELATED METHOD FOR A POWER CONVERTER - A primary-side feedback control device for a power converter includes a control unit for generating a pulse signal according to a feedback signal for controlling on and off states of a switching transistor of the power converter, a comparator coupled to an auxiliary winding of a primary side of the power converter for generating at least one control signal according to a voltage on the auxiliary winding and a reference voltage, a sample-and-hold unit coupled to the auxiliary winding, the comparator, and the control unit for generating the feedback signal according to the voltage on the auxiliary winding and the at least one control signal, and a voltage generator coupled to the control unit, the comparator, and the sample-and-hold unit for generating the reference voltage according to the feedback signal. | 2010-07-01 |
20100165667 | Power System with Power Converters Having an Adaptive Controller - A power system having a power converter with an adaptive controller. The power system is coupled to a load and includes a power system controller that receives a signal indicating a system operational state of the load and selects a power converter operational state as a function thereof. The power system also includes a power converter with a power switch that conducts for a duty cycle to provide a regulated output characteristic at an output thereof. The power converter also includes a controller that receives a command from the power system controller to enter the power converter operational state and provides a signal to control the duty cycle of the power switch as a function of the output characteristic and in accordance with the command, thereby regulating an internal operating characteristic of the power converter to improve an operating efficiency thereof as a function of the system operational state. | 2010-07-01 |
20100165668 | HIGH EFFICIENCY UNIVERSAL INPUT SWITCHING POWER SUPPLY - A universal input switching power supply has the rectifier, a signal detecting unit detecting a voltage of an external AC power and outputting a detecting signal, a PFC circuit converts a first DC power from the rectifier to a second DC power with different voltage according to the detecting signal; and a parallel and serial type DC to DC converter converting the second DC power with different voltage to a constant voltage of the third DC power. The parallel and serial type DC to DC converter has a transformer having a primary and secondary coils and physically changes a turn ratio of the primary and secondary coils of a transformer thereof according to a voltage ratio of the second DC power and the third DC power. Accordingly, the universal input switching power supply has good transforming efficiency at different AC power source conditions. | 2010-07-01 |
20100165669 | SINGLE-STAGE ISOLATED HIGH POWER FACTOR AC/DC CONVERTER WITH LEAKAGE INDUCTOR ENERGY RECOVERY FUNCTION - A single-stage isolated high power factor AC/DC converter with a leakage inductor energy recovery function includes a buck-boost circuit, for step-down or step-down a power supply; a transformer, electrically connected to the buck-boost circuit, for transforming the stepped-down or stepped-up power supply; a switch, electrically connected to the buck-boost circuit; an input capacitor, electrically connected to the buck-boost circuit; and an output circuit, for outputting the power supply transformed by the transformer. When the switch is cut off, the buck-boost circuit provides an energy recovery path to return energy stored in a leakage inductor of the transformer to the input capacitor. The energy stored in the leakage inductor of the transformer in a flyback converter or a forward converter is returned to the input capacitor through the energy recovery path. The problem caused by the leakage inductor of the transformer is solved without using any additional element. | 2010-07-01 |
20100165670 | MULTI-OUTPUT SYNCHRONOUS FLYBACK CONVERTER - The present application concerns a multi-output synchronous Flyback converter. The Flyback converter comprises a primary controlled switch ( | 2010-07-01 |
20100165671 | Switched-mode Power Supplies - This disclosure relates to switched-mode power supplies, to transformers for such power supplies, and to methods of operating switched-mode power supplies. A switch mode power supply (SMPS), the switched-mode power supply having a power input, a switch, a transformer, and a power output; said transformer having a primary winding on a primary side of said power supply coupled to said power input via said switch, and a secondary winding on a secondary side of said switched-mode power supply coupled to said power output; wherein said transformer further includes first and second auxiliary windings, wherein said first auxiliary winding is more closely coupled to said primary winding than to said secondary winding and wherein said second auxiliary winding is more closely coupled to said secondary winding than to said primary winding. | 2010-07-01 |
20100165672 | VALLEY-MODE SWITCHING SCHEMES FOR SWITCHING POWER CONVERTERS - An improved valley-mode switching (VMS) scheme and circuitry for implementing the improved VMS switching scheme in a switch-mode power converter are disclosed. For a given switching cycle, a desired switch turn-on time is determined based on a pulse width modulation, pulse frequency modulation, or other suitable power converter control scheme. Also, one or more times corresponding to local minimums (valleys) are predicted for the voltage across a power switch of the switching power converter. The power switch is turned on at a valley immediately subsequent or otherwise subsequent to the desired switch time determined according to the power converter control scheme. Thus, the improved VMS scheme enables low-voltage switch operation to reduce switching loss and EMI noise without restricting the control scheme of the power converter. | 2010-07-01 |
20100165673 | Power supply having a two-way DC to DC converter - A power supply having a two-way DC to DC converter has an AC to DC converter and a two-way DC to DC converter. When an AC power is input to the AC to DC converter, the AC to DC converter transforms the AC power to a middle level DC power and the two-way DC to DC converter transforms the middle level DC power to a low level DC power. When the AC power is unavailable and the two-way DC to DC converter obtains an external DC power, the two-way DC to DC converter transforms the external DC power to the middle level DC power. Therefore, if the power supply obtains the external DC power, the power supply can still output the middle level DC power even the AC power is unavailable. | 2010-07-01 |
20100165674 | POWER CONVERSION SYSTEMS AND METHODS FOR CONTROLLING HARMONIC DISTORTION - Control systems, methods and power conversion systems are presented for controlling harmonic distortion, in which multi-sampling space vector modulation (SVM) is employed for controlling power converter switching devices, with a reference vector being sampled two or more times during each SVM period to update the SVM dwell times more than once during each SVM cycle. | 2010-07-01 |
20100165675 | SYSTEM AND METHOD FOR CONTROLLING VARIATIONS OF SWITCHING FREQUENCY - System and method for providing frequency control to a power converter. The system includes a pseudorandom signal generator configured to generate a digital signal. The digital signal is associated with at least an N-bit datum, and N is a positive integer. Additionally, the system includes a digital-to-analog converter configured to receive the digital signal and generate a first control signal, an output signal generator configured to receive the first control signal and generate at least a first output signal associated with a frequency, and a pulse-width-modulation generator configured to receive at least the first output signal. The N-bit datum represents a pseudorandom number. | 2010-07-01 |
20100165676 | SYSTEM AND METHOD PROVIDING OVER CURRENT AND OVER POWER PROTECTION FOR POWER CONVERTER - System and method for protecting a power converter. A system includes a threshold generator configured to generate a threshold signal, and a first comparator configured to receive the threshold signal and a first signal and to generate a comparison signal. The first signal is associated with an input current for a power converter. Additionally, the system includes a pulse-width-modulation generator configured to receive the comparison signal and generate a modulation signal in response to the comparison signal, and a switch configured to receive the modulation signal and adjust the input current for the power converter. The threshold signal is associated with a threshold magnitude as a function of time. The threshold magnitude increases with time at a first slope during a first period, and the threshold magnitude increases with time at a second slope during a second period. The first slope and the second slope are different. | 2010-07-01 |
20100165677 | Electronic device having a circuit protection unit - An electronic device includes a circuit protection unit providing over-current protection to a main circuit and including a series connection of first and second current limiting circuits, and a normally-open branch circuit coupled in parallel to the first current limiting circuit and operable to conduct when a voltage across the first current limiting circuit reaches a first predetermined threshold voltage not greater than an endure voltage of the first current limiting circuit. Prior to conduction of the branch circuit, the first current limiting circuit maintains a current flowing therethrough at a first limit value when a current flowing through the main circuit reaches the first limit value. Upon conduction of the branch circuit, the second current limiting circuit maintains a current flowing therethrough at a second limit value greater than the first limit value when the current flowing through the main circuit reaches the second limit value. | 2010-07-01 |
20100165678 | SYSTEM FOR CONVERTING AT LEAST ONE ELECTRICAL INPUT DIRECT CURRENT INTO AN ELECTRICAL POLYPHASE OUTPUT ALTERNATING CURRENT - A system for converting at least one electrical input direct current into an electrical output alternating current comprising M phases and supplied to M output terminals includes N polyphase inverters, connected in parallel, each converting the input direct current into an intermediate alternating current comprising M phases and supplied to M intermediate terminals; N×M first electromagnetic coupling coils, each being connected to a respective intermediate terminal; N×M magnetic cores, each first coil being wound around a respective core. | 2010-07-01 |
20100165679 | High efficiency universal input switching power supply - A universal input switching power supply has a signal detecting unit, two DC converting units and a physical wiring and controlling unit. The DC converting units are respectively adapted to couple to an AC power source to convert the AC power source to two first DC power sources and changes a voltage of each of the first power sources according to different voltage of the AC power source. The physical wiring and controlling unit is connected to the outputs of the DC converting units and the signal detecting unit and automatically connects the outputs of the PFC circuits in parallel if a high line voltage range of the AC power source is coupled to the full bridge rectifier. On the contrary, the physical wiring and controlling unit automatically connects the outputs of the PFC circuits in serial. Accordingly, the universal input switching power supply has good transmitting efficiency at different AC power source conditions. | 2010-07-01 |
20100165680 | POWER CONVERSION APPARATUS - An inverter module has a first inverter driving a first electric load and a second inverter driving a second electric load, mounted on a common insulation substrate. In the first inverter, the arms of the U, V and W phases are arranged on the insulation substrate such that arms adjacent in the horizontal direction in the drawing are located displaced from each other in the vertical direction in the drawing. In the second inverter, the arms of the U, V and W phases are arranged on the insulation substrate such that arms adjacent in the horizontal direction in the drawing are displaced from each other in the vertical direction in the drawing. Moreover, the arm of the first inverter and the arm of the second inverter are arranged to be adjacent along the horizontal direction in the drawing. By such an arrangement, the in-plane temperature distribution can be rendered uniform without having to increase the area occupied by the insulation substrate. | 2010-07-01 |
20100165681 | SEMICONDUCTOR DEVICE AND POWER CONVERTER USING THE SAME - In a driving circuit, for controlling the turning on and off of a main semiconductor switching device of an insulated gate type, in an insulated gate semiconductor switching device for electric power conversion, bipolar semiconductor devices of an insulated gate control type, particularly insulated gate bipolar transistors (IGBTs) are used at the output stage of a circuit that controls the gate voltage of the main semiconductor switching device. | 2010-07-01 |
20100165682 | CURRENT CONTROLLED POWER CONVERTER - A power module that converts a dc voltage into a three-phase ac voltage, current sensors that detect the ac side current of the power module, a shunt resistor and an amplifier that detect a dc side current of the power module, and a control section that controls the power module by pulse-width modulation using a spatial vector modulation method on the basis of the ac side current detected by the current sensors and the dc side current detected by the shunt resistor and the amplifier are provided. The control section corrects the amplitude and the offset of the ac side current detected by the current sensors on the basis of current components, corresponding to current components of prescribed phases of the ac side current, of the dc side current detected by the shunt resistor and the amplifier. | 2010-07-01 |
20100165683 | Switching power supply circuit - A switching power supply circuit that obtains a predetermined DC voltage output from an input AC power supply includes a full-wave rectifier and a boost circuit connected to the rectifier. The boost circuit generates a DC output having a predetermined voltage value from the rectifier output. A power factor improving circuit controls an ON-period of an output transistor of the boost circuit, based on feedback of the DC voltage output, and a dynamic over-voltage-protection circuit controls the ON-period of the output transistor as it performs a switching operation. The switching power supply circuit facilitates an over-voltage-protection function that prevents inductor buzzing with an integrated circuit having a small number of pins. | 2010-07-01 |
20100165684 | POWER ADAPTER - A power adapter to receive at least one AC input power and transform to DC primary output power includes a power factor correction circuit to receive the AC input power and modulate to become a modulated power, an isolation voltage step-down circuit connecting to the power factor correction circuit to modulate the modulated power to a modulated lower voltage power, a switch voltage regulation circuit connecting to the isolation voltage step-down circuit to receive the modulated lower voltage power, and a voltage stabilization circuit connecting to the switch voltage regulation circuit. The switch voltage regulation circuit sets a determined output level and regulates the modulated lower voltage power to become a determined power at the determined output level. The voltage stabilization circuit modulates the determined power to become the primary output power and supplies the primary output power to a primary output end. | 2010-07-01 |
20100165685 | POWER TRANSISTOR CHIP WITH BUILT-IN JUNCTION FIELD EFFECT TRANSISTOR AND APPLICATION CIRCUIT THEREOF - A power transistor chip and an application circuit thereof has a junction field effect transistor to act as a start-up circuit of an AC/DC voltage converter. The start-up circuit can be turned off after the PWM circuit of the AC/DC voltage converter operates normally to conserve the consumption of the power. Besides, the junction field effect transistor is built in the power transistor chip. Because the junction field effect transistor is fabricated with the same manufacturing process as the power transistor, it is capable of simplifying the entire process and lowering the production cost due to no additional mask and manufacturing process. | 2010-07-01 |
20100165686 | RECTIFIER CIRCUIT - A rectifier circuit for use in an energy harvesting application in which mechanical energy is converted into electrical energy by using an AC generator using an active rectifier bridge with a pair of input terminals adapted to be connected to an output of the AC generator and a pair of output terminals, an inductor connected across the output terminals of the active rectifier bridge and a storage capacitor. A pair of output switches selectively connects the storage capacitor across the inductor. A controller controls the active rectifier bridge and the pair of output switches such that in successive switching cycles within any half wave of AC input voltage from the output of the AC generator the inductor is first loaded by current from the output of the AC generator and then discharged into the storage capacitor. An energy harvesting system which uses an AC generator for generating electrical energy out of mechanical energy, a rectifier circuit which is connected with the input to the output of the AC generator and a low power wireless system as application unit. A method of rectifying an AC output voltage of an AC generator for use in an energy harvesting application. | 2010-07-01 |
20100165687 | OUTPUT INVERTER FOR SINGLE PHASE AND OUTPUT CURRENT DETECTING METHOD THEREOF - There are provided an output inverter for single phase which can detect a current with high precision through a smaller number of components, and an output current detecting method thereof. A first current detector ( | 2010-07-01 |
20100165688 | CASCADED FLYING CAPACITOR MODULAR HIGH VOLTAGE INVERTERS - A high voltage inverter is provided which includes a plurality of k-level flying capacitor H bridge modules, k being greater than 2, each having a positive dc terminal, a negative dc terminal, and two ac terminals, a connecting unit for connecting said ac terminals of said plurality of k-level flying capacitor H bridge modules in series to form a cascading set of modules, and a dc source connected to an ac source and having a transformer, a rectifier rectifying an output voltage of said transformer, and a capacitor connected between the positive and negative dc terminals. | 2010-07-01 |
20100165689 | REJUVENATION OF ANALOG MEMORY CELLS - A method for data storage in a memory that includes multiple analog memory cells fabricated using respective physical media, includes identifying a group of the memory cells whose physical media have deteriorated over time below a given storage quality level. A rejuvenation process, which causes the physical media of the memory cells in the group to meet the given storage quality level, is applied to the identified group. Data is stored in the rejuvenated group of the memory cells. | 2010-07-01 |
20100165690 | SEGMENTED TERNARY CONTENT ADDRESSABLE MEMORY SEARCH ARCHITECTURE - A segmented ternary content addressable memory (TCAM) search architecture is disclosed. In one embodiment, a TCAM device with a row of TCAM cells includes a first segment of the TCAM cells for determining a match of corresponding search bits of a search string with a first portion of a stored string in the first segment of the TCAM cells, an evaluation module for generating a search enable signal if the match of the corresponding search bits with the first portion of the stored string is determined, and a second segment of the TCAM cells for determining a match of remaining search bits of the search string with a remaining portion of the stored string in response to the search enable signal. | 2010-07-01 |
20100165691 | CONTENT ADDRESSABLE MEMORY - An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. | 2010-07-01 |
20100165692 | VARIABLE MEMORY REFRESH DEVICES AND METHODS - Memory devices and methods are described such as those that monitor and adjust characteristics for various different portions of a given memory device. Examples of different portions include tiles, or arrays, or dies. One memory device and method described includes monitoring and adjusting characteristics of different portions of a 3D stack of memory dies. One characteristic that can be adjusted at multiple selected portions includes refresh rate. | 2010-07-01 |
20100165693 | SEMICONDUCTOR MEMORY DEVICE HAVING OPEN BIT LINE STRUCTURE - A semiconductor memory device has an array structure of an open bit line structure and comprises a plurality of normal memory mats, two dummy mats and a plurality of rows of sense amplifiers. The normal memory mat includes a plurality of memory cells and arranged in a bit line extending direction, while the dummy mat includes a plurality of dummy cells and arranged in a bit line extending direction at both ends of the plurality of normal memory mats. The rows of sense amplifiers are arranged between the normal memory mats and between each of the normal memory mats and each of the dummy mats. A first predetermined number of the dummy cells, the number of which is smaller than a number of the memory cells arranged along each bit line of the normal memory mats, are arranged along each bit line of the dummy mats. | 2010-07-01 |
20100165694 | Memory Cell Array - Disclosed is a memory cell array including: word lines and first and second bit lines respectively connected to memory cells, wherein each memory cell includes a MOS transistor and a switching element formed inside a contact hole, the switching element includes first and second conductive layers and a gap in which a resistance value is changed by applying a predetermined voltage, each word line is connected to a gate electrode, each first bit line is connected to a second electrode, each second bit line is connected to the second conductive layer, and data is written by supplying a write voltage to the first bit line connected to the selected memory cell and specifying the word line connected to the memory cell, and data is read by supplying a read voltage to the first bit lines connected to the memory cell and specifying the word line connected to the memory cells. | 2010-07-01 |
20100165695 | Memory Cell Array - Disclosed is a memory cell array including word and first bit lines and second bit lines respectively connected to memory cells, wherein each memory cell includes a MOS transistor and switching element having first and second conductive layers and a gap in which a resistance value changes by applying a predetermined voltage, and data is written by specifying the first bit line to connect it to a ground, specifying the word line and supplying a write voltage to the second bit lines, and read by specifying the first bit line to connect it to the sense amplifier, specifying the word line and supplying a read voltage lower than the write voltage to the second bit lines, and the word line is specified when the word line voltage becomes a gate threshold value voltage or more and a sum of a drive voltage and the gate threshold value voltage or less. | 2010-07-01 |
20100165696 | Memory Cell Array - Disclosed is a memory cell array including word and first bit lines and second bit lines respectively connected to memory cells, wherein each memory cell includes a MOS transistor and switching element having first and second conductive layers and a gap in which a resistance value changes by applying a predetermined voltage, and data is written by specifying the first bit line to connect it to a ground, specifying the word line and supplying a write voltage to the second bit lines, and read by specifying the word line, and specifying the first bit line to supply a read voltage lower than the write voltage to the second bit lines, and the word line is specified when the voltage of the word line becomes a gate threshold value voltage or more and a sum of a drive voltage and the gate threshold value voltage or less. | 2010-07-01 |
20100165697 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes: a memory cell array including a plurality of first wirings, a plurality of second wirings intersecting with the first wirings, and a plurality of memory cells respectively arranged at intersections of the first and second wirings; a plurality of drivers that drive the first wirings; a dummy wiring continuously extending in a direction of the first wirings and in a direction of the second wirings, a part of the dummy wiring extending in the direction of the second wirings being connected to the plurality of drivers; a plurality of switch circuits connected to respective connection portions of the plurality of drivers and the dummy wiring; and a replica line extending in the direction of the second wirings and connected to the dummy wiring through the plurality of switch circuits. | 2010-07-01 |
20100165698 | NON-VOLATILE ONE-TIME - PROGRAMMABLE AND MULTIPLE-TIME PROGRAMMABLE MEMORY CONFIGURATION CIRCUIT - A programmable non-volatile configuration circuit uses a pair of non-volatile memory devices arranged in a pull-up and pull-down arrangement. The non-volatile memory devices have floating gates that overlaps a variable portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. The invention can be used in environments to store configuration data for programmable logic devices, field programmable arrays, and many other applications. | 2010-07-01 |
20100165699 | ANTIFUSE PROGRAMMABLE MEMORY ARRAY - Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, such as PROM, OTPROM, and other such programmable non-volatile memories. The circuitry employs an antifuse scheme that includes an array of memory bitcells, each containing a program device and an antifuse element configured with current path isolation well and for storing the memory cell state. The bitcell configuration, which can be used in conjunction with column/row select circuitry, power selector circuitry, and/or readout circuitry, allows for high-density memory array circuit designs and layouts. | 2010-07-01 |
20100165700 | ONE TIME PROGRAMMABLE MEMORY DEVICE AND MANUFACTURING METHOD OF ONE TIME PROGRAMMABLE MEMORY DEVICE - Embodiments relate to a manufacturing method of a one time programmable (OTP) memory device including: forming a common source in a linear configuration on a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate at both sides of the source; forming a gate over the gate dielectric layer; forming a spacer between the gates and at both side walls of the gate; and forming a drain on the semiconductor substrate at both sides of the spacer. With embodiments, the OTP memory device can be formed together with the logic part using the logic process and can increase the storage capacity of the OTP memory device by improving density of memory arrays. | 2010-07-01 |
20100165701 | RESISTIVE MEMORY - A resistive memory includes a plurality of memory cells, a plurality of reference cells having mutually different resistance values, at least one sense amplifier having a first input terminal connected to one selected memory cell which is selected from the plurality of memory cells at a time of read, and a second input terminal connected to one selected reference cell which is selected from the plurality of reference cells at the time of read, and one latch circuit which holds offset information of the at least one sense amplifier. The resistive memory further includes a decoder which selects, in accordance with the offset information, the one selected reference cell from the plurality of reference cells, and connects the one selected reference cell to the second input terminal of the at least one sense amplifier. | 2010-07-01 |
20100165702 | THREE DIMENSIONAL PROGRAMMABLE RESISTANCE MEMORY DEVICE WITH A READ/WRITE CIRCUIT STACKED UNDER A MEMORY CELL ARRAY - A programmable resistance memory device includes a semiconductor substrate, at least one cell array, in which memory cells are arranged formed above the semiconductor substrate. Each of the memory cells has a stack structure of a programmable resistance element and an access element, the programmable resistance element storing a high resistance state or a low resistance state determined due to the polarity of voltage application in a non-volatile manner. The access element has such a resistance value in an off-state in a certain voltage range that is ten time or more as high as that in a select state. A read/write circuit is formed on a semiconductor substrate as underlying the cell array for data reading and data writing in communication with the cell array. | 2010-07-01 |
20100165703 | SEMICONDUCTOR DEVICE FOR SUPPLYING STABLE VOLTAGE TO CONTROL ELECTRODE OF TRANSISTOR - A semiconductor device comprises an internal voltage generator circuit which includes a first transistor having a first and a second main electrode and a control electrode, a control circuit controlling a voltage between the second main electrode and the control electrode of the first transistor such that a voltage at the first main electrode of the first transistor remains at a predetermined voltage, and a second transistor having a first and a second main electrode and a control electrode. A voltage between the second main electrode and the control electrode of the first transistor is applied between the second main electrode and the control electrode of the second transistor. | 2010-07-01 |
20100165704 | Circuit and Method for a High Speed Memory Cell - A memory cell is disclosed, including a write access transistor coupled between a storage node and a write bit line, and active during a write cycle responsive to a voltage on a write word line; a read access transistor coupled between a read word line and a read bit line, and active during a read cycle responsive to a voltage at the storage node; and a storage capacitor coupled between the read word line and the storage node. Methods for operating the memory cell are also disclosed. | 2010-07-01 |
20100165705 | SEMICONDUCTOR INTEGRATED CIRCUIT - In a semiconductor integrated circuit having a register file of a multiport configuration, a first holding circuit | 2010-07-01 |
20100165706 | STATIC MEMORY CELL HAVING INDEPENDENT DATA HOLDING VOLTAGE - A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the memory cell. To permit the voltage difference between two data storage nodes in the inactivated memory cell to exceed the voltage difference between the two nodes when write data is applied from a data line pair DL and /DL to the two nodes in the activated memory cell, the power supply line voltage control transistors are turned on to apply a high voltage VCH to the power supply lines after the word line voltage is turned off. The data holding voltage in the memory cell can be activated to a high voltage independent of the data line voltage, and the data holding voltage can be dynamically set so that read and write operations can be performed at high speed with low power consumption. | 2010-07-01 |
20100165707 | Read/Write Margin Improvement in SRAM Design Using Dual-Gate Transistors - An integrated circuit structure includes a static random access memory (SRAM) cell. The SRAM cell includes a pull-up transistor and a pull-down transistor forming an inverter with the pull-up transistor. The pull-down transistor includes a front gate connected to a gate of the pull-up transistor, and a back-gate decoupled from the front gate. | 2010-07-01 |
20100165708 | MEMORY CONTROLLER AND DECODER - A memory controller and a decoder are provided. The decoder is adapted to the memory controller. The decoder includes a first transistor to a fourth transistor. Gates of the first to the fourth transistor are coupled to a first to a fourth control signal respectively. A first terminal and a second terminal of the first transistor are coupled to a first voltage and a first terminal of the second transistor respectively. First terminals and second terminals of the third transistor and the fourth transistor are coupled to a second terminal of the second transistor and a second voltage respectively. When the first transistor and the second transistor are turned off, a voltage of the second control signal is lower than a voltage of the first control signal. Thereby, a gate-induced drain leakage (GIDL) current of the transistors is reduced. | 2010-07-01 |
20100165709 | ROBUST SRAM MEMORY CELL CAPACITOR PLATE VOLTAGE GENERATOR - An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies. | 2010-07-01 |
20100165710 | Random access memory architecture including midpoint reference - A random access memory architecture includes a first series connected pair of memory elements ( | 2010-07-01 |
20100165711 | SET ALGORITHM FOR PHASE CHANGE MEMORY CELL - Memory devices and methods for operating such devices are described herein. A method is described herein for operating a memory cell comprising phase change material and programmable to a plurality of resistance states including a high resistance state and a lower resistance state. The method comprises applying a first bias arrangement to the memory cell to establish the lower resistance state, the first bias arrangement comprising a first voltage pulse. The method further comprises determining whether the memory cell is in the lower resistance state, and if the memory cell is not in the lower resistance state then applying a second bias arrangement to the memory cell. The second bias arrangement comprises a second voltage pulse having a pulse height greater than that of the first voltage pulse. | 2010-07-01 |
20100165712 | METHOD FOR LOW-STRESS MULTILEVEL READING OF PHASE CHANGE MEMORY CELLS AND MULTILEVEL PHASE CHANGE MEMORY - According to a method for multilevel reading of a phase change memory cell a bit line ( | 2010-07-01 |
20100165713 | METHOD FOR LOW POWER ACCESSING A PHASE CHANGE MEMORY DEVICE - A method for accessing a phase change memory device, wherein a first sub-plurality of bitlines is grouped in a first group and a second sub-plurality of bitlines is grouped in a second group. At least a bitline in the first and second groups are selected; currents are supplied to the selected bitlines; and a selected wordline is biased. The bitlines are selected by selecting a first bitline in the first group and, while the first bitline is selected, selecting a second bitline in the second group which is arranged on the selected wordline symmetrically to the first bitline in the first group. | 2010-07-01 |
20100165714 | METHOD OF STORING AN INDICATION OF WHETHER A MEMORY LOCATION IN PHASE CHANGE MEMORY NEEDS PROGRAMMING - A phase change memory includes a float buffer which stores the result of a comparison between the current state of data in the phase change memory cells and an intended next state of each of those cells. The float buffer indicates which cells need to be programmed in order to achieve the new states and which cells happen to already be in the new states. Then, after programming of the cells, the float buffer indicates which cells still need to be programmed. Thus, a control stage uses the information in the float buffer to program only those cells whose states need to be changed. | 2010-07-01 |
20100165715 | PROTECTION REGISTER FOR A PHASE-CHANGE MEMORY - A memory device including a memory array comprising a set of phase change memory cells configured to store data. The memory device further includes a protection register including a set of protection cells configured to store protection information of the memory cells. The protection cells of the protection register are memory cells of the memory array. | 2010-07-01 |
20100165716 | NONVOLATILE MEMORY WITH OVONIC THRESHOLD SWITCHES - A memory device including a plurality of memory cells being arranged in a matrix having a plurality of rows and a plurality of columns. Each memory cell includes a storage element and a selector for selecting the corresponding storage element during a reading operation or a programming operation. The memory device further including a plurality of row lines each one for selecting the memory cells of a corresponding row and a plurality of column lines each one for selecting the memory cells of a corresponding column. The memory device further includes for each line among the row lines and/or the column lines a respective set of local lines each one for selecting a group of memory cells of the corresponding line, and a respective set of selection elements each one for selecting a corresponding local line of the set in response to the selection of the respective line. | 2010-07-01 |
20100165717 | WRITE DRIVER CIRCUIT OF PRAM - A phase change random access memory (PRAM) has a function of evaluating the lifetime and reliability of a cell in a write driver circuit. The write driver circuit of the PRAM includes a normal driver configured to provide a write current for set or reset of a phase change cell connected to a bit line, a test driver configured to share a node with the normal driver, and provide an additional current for a test to the write current through the shared node in response to a test mode control signal, and a mode control unit configured to control an operation according to the test mode by providing the test mode control signal to the test driver. | 2010-07-01 |
20100165718 | APPARATUS AND METHOD FOR SENSING MULTI-LEVEL CELL DATA - A multi-level sensing apparatus of the non-volatile memory includes a first sense amplifier configured to compare a first reference voltage with a read data of a bit line and amplify a comparison result to generate a first output; a reference voltage selector configured to select one of a second reference voltage and a third reference voltage as a fourth reference voltage according to a logic level of the first output; a second sense amplifier configured to compare the fourth reference voltage with the read data of the bit line and amplify a comparison result to generate a second output; and a decoder configured to decode the first and second outputs to output a sensing data. | 2010-07-01 |
20100165719 | PHASE CHANGE MEMORY DEVICE - A phase change memory device with memory cells ( | 2010-07-01 |
20100165720 | VERIFICATION CIRCUITS AND METHODS FOR PHASE CHANGE MEMORY ARRAY - A verification circuit for a phase change memory array is provided. A sensing unit senses a sensing voltage from a memory cell of the phase change memory array according to an enable signal. A comparator generates a comparing signal according to the sensing voltage and a reference voltage, so as to indicate whether the memory cell is in a reset state. A control unit generates a control signal according to the enable signal. An operating unit generates a first signal according to the control signal, so as to indicate whether the comparator is active. An adjustment unit provides a writing current to the cell, and increases the writing current according to the control signal until the comparing signal indicates that the memory cell is in a reset state | 2010-07-01 |
20100165721 | INTERNAL VOLTAGE GENERATING CIRCUIT OF PHASE CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD THEREOF - An internal voltage generating circuit includes a divided voltage generator configured to generate a divided voltage by dividing a feedback internal voltage level at a division ratio corresponding to an operation mode control signal, a voltage detector configured to detect a level of the divided voltage based on a reference voltage level, an internal voltage generator configured to receive a supply voltage as power source and generate the internal voltage in response to an output signal of the voltage detector, and an under-driving unit configured to under-drive an internal voltage terminal to a supply voltage in an under-driving operation region that is determined in response to the operation mode control signal. | 2010-07-01 |
20100165722 | Phase Change Memory - A phase change memory (PCM) in which the phase change storage element is crystallized by a gradually increasing/decreasing operating current. The PCM comprises a switching circuit, the phase change storage element, a bit select switch, a pulse generating module, and a counting module. The switching circuit comprises a plurality of switches, selectively providing branch paths to an output terminal of a current source. The bit select switch controls the conduction between the phase change storage element and the output terminal of the current source. The pulse generating module outputs a pulse signal oscillating between high and low voltage levels. When enabled, the counting module counts the oscillations of the pulse signal, and outputs the count result by a set of digital data. The set of digital data are coupled to the switching circuit to control the switches therein. | 2010-07-01 |
20100165723 | PHASE CHANGE MEMORY - A phase change memory with an operating current that can be gradually increased or gradually decreased. The phase change memory has a phase change storage element, a transistor, and a control circuit. The transistor is operable to adjust the operating current flowing through the phase change storage element. The transistor has a first terminal coupled to a voltage source, a second terminal coupled to the phase change storage element, and a control terminal receiving a control signal from the control circuit. The control circuit is specially designed to limit the transistor in a linear region. | 2010-07-01 |
20100165724 | WORD-LINE DRIVER INCLUDING PULL-UP RESISTOR AND PULL-DOWN TRANSISTOR - Embodiments include but are not limited to apparatuses and systems including a plurality of memory cells, each memory cell including a selector and a storage element coupled to the selector. A word-line may be coupled to the memory cells and may have a word-line driver including a pull-up resistor coupled to the selectors for the memory cells to access respective storage elements of the memory cells. Other embodiments may be described and claimed. | 2010-07-01 |
20100165725 | RELIABLE SET OPERATION FOR PHASE-CHANGE MEMORY CELL - A Phase-Change Memory (PCM) device and a method of writing data to the PCM device are described. The PCM device includes a multi-phase data storage cell having at least a Set state and a Reset state that may be established using a heater configured to heat the data storage cell. A memory interface may be coupled with the heater configured to write data to the data storage cell, the data being represented by the Set or the Reset states. A write Reset pulse is used to place the data storage cell in the Reset state corresponding to a read value that is less than a read threshold. A write Set pulse that is a predetermined function of the write Reset pulse is used to place the data storage cell in the Set state. The PCM device may include additional intermediate states that enable each data storage cell to store two or more bits of information. Other embodiments may be described and claimed. | 2010-07-01 |
20100165726 | DISCHARGE PHASE CHANGE MATERIAL MEMORY - An information storage array includes a programmable material at a storage location and a capacitor set. A switching network charges the capacitor set to a first voltage and discharges the capacitor set at a second voltage. The second voltage is greater than the first voltage and it or a waveform derived therefrom is applied to the storage location to thereby change a state of the programmable material. | 2010-07-01 |
20100165727 | PHASE CHANGE MATERIAL MEMORY HAVING NO ERASE CYCLE - An information storage array includes a programmable material at one or more storage locations and pulse generation circuitry for generating at least two pulses—in particular, a write pulse that writes a value into the programmable material an erase pulse that erases a value from the programmable material. In general, the erase pulse is greater in duration than the write pulse. Either the write pulse or the erase pulse is selected based at least in part on a state of a data bit to be stored in the programmable material. | 2010-07-01 |
20100165728 | PHASE CHANGE DEVICE HAVING TWO OR MORE SUBSTANTIAL AMORPHOUS REGIONS IN HIGH RESISTANCE STATE - Memory devices are described herein along with method for operating the memory device. A memory cell as described herein includes a first electrode and a second electrode. The memory cell also comprises phase change material having first and second active regions arranged in series along an inter-electrode current path between the first and second electrode. | 2010-07-01 |
20100165729 | NONVOLATILE MEMORY DEVICE AND RELATED METHODS OF OPERATION - In a nonvolatile memory device, a program operation is performed on a plurality of nonvolatile memory cells by programming data having a first logic state in a first group among a plurality of selected memory cells selected from the plurality of nonvolatile memory cells during a first program interval of the program operation, and thereafter, programming data having a second logic state different from the first logic state in a second group among the selected memory cells during a second program interval of the program operation after the first program interval. | 2010-07-01 |
20100165730 | READING MEMORY CELLS USING MULTIPLE THRESHOLDS - A method for operating a memory ( | 2010-07-01 |
20100165731 | MEMORY DEVICE AND OPERATING METHOD - A method of operating a memory device includes; defining a plurality of read levels, using the plurality of read levels to determine electrical property differences between first and second memory cells adjacent dispose along a common word line, and determining read data stored in the first and second memory cells in relation to the determination of electrical property differences between the first and second memory cells. | 2010-07-01 |
20100165732 | FLASH MEMORY APPARATUS AND READ OPERATION CONTROL METHOD THEREFOR - A flash memory apparatus of an embodiment is configured to include a flash memory including a plurality of blocks and a read operation control circuit determining whether to replace a block in accordance with the number of times a read process is performed for each block of the plurality of blocks. | 2010-07-01 |
20100165733 | NAND NONVOLATILE SEMICONDUCTOR MEMORY - A NAND nonvolatile semiconductor memory includes a plurality of series-connected memory cells each includes a charge storage layer and control gate electrode, a plurality of word lines respectively connected to control gate electrodes of the memory cells, a first selection transistor connected between one end of the memory cells and a source line, a second selection transistor connected between the other end of the memory cells and a bit line, and a driver configured to control voltages applied to the word lines. The driver applies a first voltage to a first word line connected to a selected memory cell, and applies a cutoff voltage that cuts off a channel of a memory cell to second word lines of a number not less than three arranged side by side on the source line side with respect to the first word line during a write operation. | 2010-07-01 |
20100165734 | SYSTEM AND METHOD FOR DATA RECOVERY IN A DISABLED INTEGRATED CIRCUIT - Systems and methods for providing memory access circuitry in application specific integrated circuits, and in certain configurations for recovering data from non-volatile memory registers in a partially disabled application specific integrated circuit as provided. In one configuration, a virtual partial dual-port non-volatile memory is provided having a secondary partial read only port. In another configuration, a physical partial dual-port non-volatile memory is provided having a secondary partial read only port. | 2010-07-01 |
20100165735 | NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory of an aspect of the present invention comprises a voltage step-down circuit including a first and a second circuit to achieve a voltage drop and configured to decrease the first voltage to a second voltage less than the first voltage, a transfer transistor to transfer the second voltage to a word line, and a control circuit to generate the second voltage as a first write voltage in a first mode wherein the first write voltage less than or equal to a prescribed magnitude is applied to the word line, and to generate the second voltage as a second write voltage in a second mode wherein the second write voltage greater than the prescribed magnitude is applied to the word line, wherein the difference between the first voltage and the second voltage is greater than or equal to the threshold voltage of the transfer transistor. | 2010-07-01 |
20100165736 | FLASH MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME - A flash memory device and a method for manufacturing the same are provided. The flash memory device can include first and second memory gates on a substrate, an oxide layer on sides of and on the substrate outside of the first and second memory gates, a source poly contact between the first and second memory gates, first and second select gates outside the first and second memory gates, a drain region outside the first and second select gates, and a metal contact on the drain region and the source poly contact. | 2010-07-01 |
20100165737 | ELECTROMECHANICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - In a memory device and a method of forming the same, in one embodiment, the memory device comprises a first word line structure on a substrate, the first word line structure extending in a first direction. A bit line is provided over the first word line structure and spaced apart from the first word line by a first gap, the bit line extending in a second direction transverse to the first direction. A second word line structure is provided over the bit line and spaced apart from the bit line by a second gap, the second word line structure extending in the first direction. The bit line is suspended between the first word line structure and the second word line structure such that the bit line deflects to be electrically coupled with a top portion of the first word line structure through the first gap in a first bent position and deflects to be electrically coupled with a bottom portion of the second word line structure through the second gap in a second bent position, and is isolated from the first word line structure and the second word line structure in a rest position. | 2010-07-01 |
20100165738 | Non-Volatile Memory And Method For Sensing With Pipelined Corrections For Neighboring Perturbations - A page of non-volatile multi-level storage elements on a word line WLn is sensed in parallel while compensating for perturbations from a neighboring page on an adjacent word line WLn+1. First, the programmed thresholds of storage elements on WLn+1 are sensed in the time domain and encoded as time markers. This is accomplished by a scanning sense voltage increasing with time. The time marker of a storage element indicates the time the storage element starts to conduct or equivalently when the scanning sense voltage has reached the threshold of the storage element. Secondly, the page on WLn is sensed while the same scanning voltage with an offset level is applied to WLn+1 as compensation. In particular, a storage element on WLn will be sensed at a time indicated by the time marker of an adjacent storage element on WLn+1, the time when the offset scanning voltage develops an appropriate compensating bias voltage on WLn+1. | 2010-07-01 |
20100165739 | NON-VOLATILE MULTILEVEL MEMORY CELL PROGRAMMING - Embodiments of the present disclosure provide methods, devices, modules, and systems for programming multilevel non-volatile multilevel memory cells. One method includes increasing a threshold voltage (Vt) for each of a number of memory cells until the Vt reaches a verify voltage (VFY) corresponding to a program state among a number of program states. The method includes determining whether the Vt of each of the cells has reached a pre-verify voltage (PVFY) associated with the program state, selectively biasing bit lines coupled to those cells whose Vt has reached the PVFY, adjusting the PVFY to a different level, and selectively biasing bit lines coupled to cells whose Vt has reached the adjusted PVFY, wherein the PVFY and the adjusted PVFY are less than the VFY. | 2010-07-01 |
20100165740 | NONVOLATILE SEMICONDUCTOR MEMORY CAPABLE OF TRIMMING AN INITIAL PROGRAM VOLTAGE FOR EACH WORD LINE - A nonvolatile semiconductor memory of the present invention includes a plurality of bit lines and word lines which are arranged to intersect each other; a memory cell array having a plurality of electrically-programmable memory cells arranged in a region in which the bit lines and the word lines intersect; a trimming circuit configured to obtain a parameter of an initial program voltage for each word line of the plurality of word lines; an initial Vpgm parameter register configured to receive the parameter of the initial program voltage from the trimming circuit and to store the parameter; and a control circuit configured to perform programming of data to the memory cell array based on the parameter of the initial program voltage stored in the initial Vpgm parameter register, the trimming circuit being arranged in a part of the control circuit. | 2010-07-01 |
20100165741 | DYNAMIC PASS VOLTAGE - The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying sensing voltages to selected access lines for sensing selected memory cells. The method also includes applying a dynamic pass voltage to unselected access lines while the sensing voltages are applied. | 2010-07-01 |
20100165742 | METHODS AND CIRCUITS FOR GENERATING A HIGH VOLTAGE AND RELATED SEMICONDUCTOR MEMORY DEVICES - Methods of generating a program voltage for programming a non-volatile memory device include generating an initial voltage and generating a first ramping voltage in response to the initial voltage. The first ramping voltage has a ramping speed slower than the ramping speed of the initial voltage. A second ramping voltage is generated in response to the first ramping voltage. The second ramping voltage has a lower ripple than the first ramping voltage. The second ramping voltage is output as a program voltage for programming a non-volatile memory device. A program voltage generating circuit includes a program voltage generating unit configured to generate an initial voltage, a ramping circuit configured to generate a first ramping voltage responsive to the initial voltage, and a voltage controlling unit configured to generate a second ramping voltage having relatively low ripple and to output the first ramping voltage or the second ramping voltage responsive to a voltage level of the first ramping voltage. Semiconductor memory devices including program voltage generating circuits are also disclosed. | 2010-07-01 |
20100165743 | Non-Volatile Memory And Method With Continuous Scanning Time-Domain Sensing - A page of non-volatile multi-level memory cells on a word line is sensed in parallel by sense amps via bit lines. A predetermined input sensing voltage as an increasing function of time applied to the word line allows scanning of the entire range of thresholds of the memory cell in one sweep. Sensing of the thresholds of individual cells is then reduced to a time-domain sensing by noting the times the individual cells become conducting. Each conducting time, adjusted for delays in the word line and the bit line, can be used to derive the sensing voltage level that developed at the word line local to the cell when the cell became conducting. The locally developed sensing voltage level yields the threshold of the cell. This time-domain sensing is relative insensitive to the number of levels of a multi-level memory and therefore resolve many levels rapidly in one sweep. | 2010-07-01 |
20100165744 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array and a sense amp circuit. The memory cell array includes bit lines connected to memory cells operative to store first logic data and second logic data smaller in cell current than the first logic. The sense amp circuit has a clamp transistor operative to clamp a bit line voltage. The sense amp circuit is operative to detect data in a selected memory cell via the clamp transistor and the bit line. The sense amp circuit is operative to read data from the selected memory cell in at least the two of first and second read cycles while a control voltage is applied to a gate of the clamp transistor. Different control voltages are applied to the gate of the clamp transistor in the first and second read cycles. | 2010-07-01 |
20100165745 | NON-VOLATILE MEMORY DEVICE AND DRIVING METHOD THEREOF - A non-volatile memory device and a driving method thereof. The non-volatile memory device includes a floating gate formed on and/or over a first type well, and transistors formed on and/or over a second type well and connected in series to the floating gate. One of the transistors is a first transistor for program and erase operations, and the other one is a second transistor for a reading operation. | 2010-07-01 |
20100165746 | SEMICONDUCTOR MEMORY CELL, METHOD FOR MANUFACTURING THE SAME AND METHOD FOR OPERATING THE SAME - A semiconductor memory cell, and method of manufacturing a semiconductor memory cell and an method of operating a semiconductor memory cell. A method of operating may include programming a semiconductor memory cell by applying a preset programming voltage to a common source and/or an N-well region, grounding and/or floating a control gate, and/or grounding a word line and/or a bit line. A method of operating may include erasing a semiconductor memory cell by floating and/or grounding a word line, applying a preset erase voltage to a control gate, and/or grounding an N-well, a bit line and/or a common source. A method of operating may include reading a semiconductor memory cell by grounding and/or floating a control gate, applying a preset read voltage to an N-well and/or a common source, grounding a word line, and/or applying a preset drain voltage to a bit line. | 2010-07-01 |
20100165747 | NON-VOLATILE MEMORY CELL HEALING - Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string. | 2010-07-01 |
20100165748 | ERASE COMPLETION RECOGNITION - Embodiments include but are not limited to apparatuses and systems including a main memory array, at least one erase status memory cell associated with the main memory array and configured to store a value indicative of an erase completion status of the main memory array, and a control module operatively coupled to the at least one erase status memory cell, the control module configured to perform operations on the main memory array based at least in part on the value stored in the at least one erase status memory cell. Other embodiments may be described and claimed. | 2010-07-01 |
20100165749 | Sense Amplifier Used in the Write Operations of SRAM - A static random access memory (SRAM) circuit includes a pair of complementary global bit-lines, and a pair of complementary local bit-lines. A global read/write circuit is coupled to, and configured to write a small-swing signal to, the pair of global bit-lines in a write operation. The SRAM circuit further includes a first multiplexer and a second multiplexer, each having a first input and a second input. The first input of the first multiplexer and the first input of the second multiplexer are coupled to different one of the pair of global bit-lines. A sense amplifier includes a first input coupled to an output of the first multiplexer, and a second input coupled to an output of the second multiplexer. The sense amplifier is configured to amplify the small-swing signal to a full-swing signal, and outputs the full-swing signal to the pair of local bit-lines in the write operation. | 2010-07-01 |
20100165750 | DATA INPUT DEVICE OF SEMICONDUCTOR MEMORY APPARTUS AND CONTROL METHOD THEREOF - A data input device of a semiconductor memory apparatus includes input means configured to input data; precharge means configured to supply a precharge voltage for converting inputted data to a differential signal; enable means configured to enable the input means and the precharge means to operate; and control means configured to control a current amount of the enable means in a standby mode. | 2010-07-01 |
20100165751 | DATA OUTPUT DEVICE FOR SEMICONDUCTOR MEMORY APPARATUS - A data output device of a semiconductor memory apparatus includes detection means configured to detect a specified operation frequency range; pre-driving means configured to be inputted with signals; driving means configured to receive outputs of the pre-driving means and drive an output of data; and adjustment means configured to adjust a slew rate of the driving means under the control of an output signal of the detection means. | 2010-07-01 |
20100165752 | LEVEL SHIFTER - A level shifter circuit includes first and second supply inputs for receiving a first supply voltage and a second supply voltage, respectively. The level shifter circuit further comprises a shifting circuit configured to receive an input voltage and output a selected one of the first supply voltage and the second supply voltage according to the value of the input voltage. The shifting circuit includes a circuit branch connected between the first supply input and the second supply input. The circuit branch includes a plurality of series-connected electronic devices and a voltage dropper device connected in series with the plurality of electronic devices for introducing a voltage drop. The level shifter circuit includes a bias generator configured to generate a bias voltage for the voltage dropper device according to values of the first supply voltage and the second supply voltage, said voltage drop depending on the bias voltage. | 2010-07-01 |
20100165753 | METHOD AND APPARATUS FOR REDUCING LEAKAGE IN BIT LINES OF A MEMORY DEVICE - A method and system to allow reduction of leakage in the bit lines of a memory device. In addition, minimal delay to the bit lines is introduced by the method and system. The memory device has a plurality of bit lines and a plurality of nodes to facilitate access of a respective one of the bit lines. A logic circuit that has a plurality of transistors and each transistor is coupled with the respective one of the bit lines and with a respective one of the nodes to reduce leakage of the bit lines when the transistors are deactivated. A just in time pre-charge method is also used to avoid the requirement of an additional pre-charge device to prevent excessive charge sharing while enabling the reduction of leakage of the bit lines. | 2010-07-01 |
20100165754 | SIGNAL SYNCHRONIZATION IN MULTI-VOLTAGE DOMAINS - A system and a method to improve signal synchronization in a plurality of signal paths traversing multiple voltage domains. According to an embodiment of the present disclosure a memory arrangement is preferred for signal synchronization. All read/write and clocks signals and other control signals are driven to periphery supply (Vp) levels, except wordline (WL[i]) signals which are driven at core supply (Vc) level. By doing so, lower average and peak current consumption associated with core supply (Vc) is achieved with constant delays and maintaining required signal synchronization in the signal paths traversing multiple voltage domains. | 2010-07-01 |
20100165755 | SINGLE-ENDED BIT LINE BASED STORAGE SYSTEM - A single-ended bit line based storage system. The storage system includes a first set of storage cells, a second set of storage cells, a first set of reference storage cells, a second set of reference storage cells, and a differential sensing block. The memory core is split vertically in half vertically to form the first set of storage cells and the second set of storage cells. The first set of reference storage cells provides a discharge rate lower than the discharge rate of said first set and second set of storage cells for storing data. The second set of reference storage cells provides a discharge rate lower than the discharge rate of said first set and second set of storage cells for storing data. The differential sensing block is coupled to the first set of storage cells and the second set of storage cells for generating an output data signal on receiving a control signal. | 2010-07-01 |
20100165756 | METHODS AND SYSTEMS TO IMPROVE WRITE RESPONSE TIMES OF MEMORY CELLS - Methods and systems to dynamically control state-retention strengths of a plurality of memory cells during a write operation to a subset of the memory cells. Dynamic control may include weakening state-retention strengths of the plurality of memory cells during a write operation to a subset of the memory cells, while preserving state-retention abilities of remaining ones of the plurality of memory cells. Weakening may include adjusting one or more resistances between one or more power supplies and the plurality of memory cells. Dynamic control may be selectively performed on portions of each of the memory cells in response to an input data logic state. Dynamic control may reduce a write contention within the subset of memory cells without disabling state-retention abilities of remaining ones of the plurality of memory cells, and may improve write response times of the memory cells. | 2010-07-01 |
20100165757 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a semiconductor layer; a source layer and a drain layer in the semiconductor layer; an electrically floating body region in the semiconductor layer between the source layer and the drain layer, accumulating or discharging charges for storing logical data; a gate dielectric film on the body region; and a first gate electrode and a second gate electrode on one body region via the gate dielectric film, the first and the second gate electrodes separated from each other in a channel length direction of a memory cell comprising the drain layer, the source layer, and the body region. | 2010-07-01 |
20100165758 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - The semiconductor memory device includes a data input/output unit configured to input data synchronously with a data clock and to output the data to a memory cell in response to an output strobe signal; and an output strobe signal generation unit configured to output the output strobe signal, wherein the output strobe signal is synchronized with a system clock in response to a write command regardless of whether the semiconductor memory device is in a write training mode. | 2010-07-01 |
20100165759 | Semiconductor Memory Device and Operation Method Thereof - A semiconductor memory device includes a strobe signal generator for receiving a write command and generating a write strobe signal that defines an activation period variably according to an operation frequency, and a data transfer unit for transferring data from an external device to an internal data line in response to the write strobe signal. | 2010-07-01 |