26th week of 2010 patent applcation highlights part 15 |
Patent application number | Title | Published |
20100163860 | SEMICONDUCTOR THIN FILM, METHOD FOR MANUFACTURING THE SAME, THIN FILM TRANSISTOR, AND ACTIVE-MATRIX-DRIVEN DISPLAY PANEL - Disclosed is a semiconductor thin film which can be formed at a relatively low temperature even on a flexible resin substrate. Since the semiconductor thin film is stable to visible light and has high device characteristics such as transistor characteristics, in the case where the semiconductor thin film is used as a switching device for driving a display, even when overlapped with a pixel part, the luminance of a display panel does not deteriorate. Specifically, a transparent semiconductor thin film | 2010-07-01 |
20100163861 | METHOD AND APPARATUS FOR OPTICALLY TRANSPARENT TRANSISTOR - A method and apparatus for an optically transparent field effect transistor on a substrate. The gate electrode, the dielectric, the semiconducting layer, the source electrode, and the drain electrode are optically transparent layers of nanoparticles that are formed using one or more graphic arts printing processes. The dielectric layer is in contact with the gate electrode, the semiconducting layer is in contact with the dielectric layer, and the source and drain electrodes are in contact with the semiconducting layer. | 2010-07-01 |
20100163862 | THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME - A method of fabricating a thin film transistor array substrate is presented. The method entails forming a gate interconnection line on an insulating substrate, forming a gate insulating layer on the gate interconnection line, forming a semiconductor layer and a data interconnection line on the semiconductor layer, sequentially forming multiple passivation layers, etching the passivation layers down to a drain electrode that is an extension of the data interconnection line. The portion of the drain electrode that is exposed at this stage is a part of the drain electrode-pixel electrode contact portion. A pixel electrode is formed connected to the drain electrode. Two of the passivation layers have the same composition but are processed at different temperatures. A thin film transistor prepared in the above manner is also presented. | 2010-07-01 |
20100163863 | THIN FILM FIELD EFFECT TRANSISTOR AND DISPLAY - A thin film field effect transistor includes at least: a substrate; and a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode, and a protective layer provided on the substrate in this order from the substrate side. The active layer is a layer containing an amorphous oxide containing at least one metal selected from the group consisting of In, Sn, Zn and Cd. The thin film field effect transistor further includes, between the active layer and at least one of the source electrode or the drain electrode, an electric resistance layer containing an oxide or nitride containing at least one metal selected from the group consisting of Ga, Al, Mg, Ca and Si. | 2010-07-01 |
20100163864 | SEMICONDUCTOR DEVICE - An object of the present invention is to increase the light emission efficiency of a ZnO-based optical semiconductor device. An optical semiconductor device B has a structure which includes n-type Zn | 2010-07-01 |
20100163865 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A display device includes a first wiring functioning as a gate electrode formed over a substrate, a gate insulating film formed over the first wiring, a second wiring and an electrode layer provided over the gate insulating film, and a high-resistance oxide semiconductor layer formed between the second wiring and the electrode layer are included. In the structure, the second wiring is formed using a stack of a low-resistance oxide semiconductor layer and a conductive layer over the low-resistance oxide semiconductor layer, and the electrode layer is formed using a stack of the low-resistance oxide semiconductor layer and the conductive layer which is stacked so that a region functioning as a pixel electrode of the low-resistance oxide semiconductor layer is exposed. | 2010-07-01 |
20100163866 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - One of factors that increase the contact resistance at the interface between a first semiconductor layer where a channel is formed and source and drain electrode layers is a film with high electric resistance formed by dust or impurity contamination of a surface of a metal material serving as the source and drain electrode layers. As a solution, a first protective layer and a second protective layer including a second semiconductor having a conductivity that is less than or equal to that of the first semiconductor layer is stacked successively over source and drain electrode layers without exposed to air, the stack of films is used for the source and drain electrode layers. | 2010-07-01 |
20100163867 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC DEVICE HAVING THE SAME - In a thin film transistor including an oxide semiconductor, an oxide cluster having higher electrical conductance than the oxide semiconductor layer is formed between the oxide semiconductor layer and a gate insulating layer, whereby field effect mobility of the thin film transistor can be increased and increase of off current can be suppressed. | 2010-07-01 |
20100163868 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device which includes a thin film transistor having an oxide semiconductor layer and excellent electrical characteristics is provided. Further, a method for manufacturing a semiconductor device in which plural kinds of thin film transistors of different structures are formed over one substrate to form plural kinds of circuits and in which the number of steps is not greatly increased is provided. After a metal thin film is formed over an insulating surface, an oxide semiconductor layer is formed thereover. Then, oxidation treatment such as heat treatment is performed to oxidize the metal thin film partly or entirely. Further, structures of thin film transistors are different between a circuit in which emphasis is placed on the speed of operation, such as a logic circuit, and a matrix circuit. | 2010-07-01 |
20100163869 | BONDING INSPECTION STRUCTURE - A bonding inspection structure is provided. The bonding inspection structure includes at least a elastic bump located on a substrate. At least an opening is formed in the top portion of the elastic bump. An inspection area of the top portion of the elastic bump is larger than an area of the opening. | 2010-07-01 |
20100163870 | Structure and Method for Testing MEMS Devices - A method for determining the presence of a sacrificial layer under a structure. The method includes providing at least one structure arranged above a substrate having a major surface lying in a plane, the at least one structure being clamped at at least one side. The method further includes exerting a force, such as a mechanical force, on the at least one structure. The force may have a predetermined amplitude and a component perpendicular to the substrate. Still further, the method includes determining the deflection of the at least one structure perpendicular to the plane of the substrate, and correlating the deflection of the at least one structure to the presence of a sacrificial layer between the substrate and the structure. | 2010-07-01 |
20100163871 | METHOD FOR INDEXING DIES COMPRISING INTEGRATED CIRCUITS - An embodiment of a method for indexing a plurality of die obtainable from a material wafer comprising a plurality of stacked material layers is disclosed. Each die is obtained in a respective position of the wafer; the plurality of dies is obtained by means of a manufacturing process performed in at least one manufacturing stage using at least one lithographic mask for treating a surface of the material wafer trough an exposition to a proper radiation. Said at least one manufacturing stage comprises at least two steps for treating a respective superficial portion of the material wafer that corresponds to a subset of said plurality of dies using the at least one lithographic mask through the exposition to the proper radiation in temporal succession. The method may include providing a die index on each die which is indicative of the position of the respective die by forming an external index indicative of the position of the superficial portion of the material wafer corresponding to the subset of the plurality of dies including said die. Said forming the external index may comprise forming in a set of material layers of the die a first reference structure adapted to define a mapping of the superficial portions of the wafer; said first reference structure may comprise a plurality of electronic components electrically coupled to each other by means of a respective common control line. The method may further comprise interrupting the control line in a position based on the position of the superficial portion corresponding to the subset of the plurality of dies including the die. | 2010-07-01 |
20100163872 | Bipolar Junction Transistor and Method of Manufacturing the Same - A bipolar junction transistor and a method of manufacturing a bipolar junction transistor are disclosed. An exemplary bipolar junction transistor includes a second conductivity type base region in a first conductivity type substrate, step-shaped recesses in the base region, a polysilicon layer doped with a first conductivity type impurity in the step-shaped recesses, and a step-shaped emitter region between the polysilicon layer and the base region. | 2010-07-01 |
20100163873 | PHOTO-VOLTAIC CELL DEVICE AND DISPLAY PANEL - A photo-voltaic cell device includes a first electrode, an N-type doped silicon-rich dielectric layer, a P-type doped silicon-rich dielectric layer, and a second electrode. The N-type doped silicon-rich dielectric layer is disposed on the first electrode, and the N-type doped silicon-rich dielectric layer is doped with an N-type dopant. The P-type doped silicon-rich dielectric layer is disposed on the N-type doped silicon-rich dielectric layer, and the P-type doped silicon-rich dielectric layer is doped with a P-type dopant. The second electrode is disposed on the P-type doped silicon-rich dielectric layer. A display panel including the photo-voltaic cell device is also provided. | 2010-07-01 |
20100163874 | DRIVER CIRCUIT AND SEMICONDUCTOR DEVICE - The silicon nitride layer | 2010-07-01 |
20100163875 | PIXEL PERFORMANCE IMPROVEMENT BY USE OF A FIELD SHIELD - A pixel cell ( | 2010-07-01 |
20100163876 | REFLECTIVE TFT SUBSTRATE AND METHOD FOR MANUFACTURING REFLECTIVE TFT SUBSTRATE - A reflective TFT substrate which can be operated for a prolonged period of time due to the presence of a protective insulating film, is free from occurrence of crosstalk, and is capable of significantly reducing manufacturing cost by decreasing the production steps in the production process. A reflective TFT substrate | 2010-07-01 |
20100163877 | DISPLAY DEVICE - A display has a glass substrate provided with a transparent conducting film, thin-film transistors, and an aluminum alloy wiring film electrically connecting the thin-film transistors to the transparent conducting film. The aluminum alloy wiring film is a layered structure having a first layer (X) of an aluminum alloy comprising at least one element selected from the specific element group Q including Ni and Ag, and at least one element selected from the specific element group R including rare-earth elements and Mg in a content in the specific range, and a second layer (Y) of an aluminum alloy containing having a resistivity lower than that of the first layer (X). The first layer (X) is in direct contact with the transparent conducting film. | 2010-07-01 |
20100163878 | ACTIVE MATRIX DISPLAYS AND OTHER ELECTRONIC DEVICES HAVING PLASTIC SUBSTRATES - A method of manufacturing a thin film electronic device comprises applying a plastic coating to a rigid carrier substrate using a wet casting process, the plastic coating forming a plastic substrate and comprising a transparent plastic material and a UV absorbing additive. Thin film electronic elements are formed over the plastic substrate, and the rigid carrier substrate is released from the plastic substrate. This invention provides a method of making transparent substrate materials suitable for a laser release process, through doping of the plastic material of the substrate with a UV absorber. This UV absorber absorbs in the wavelength the lift-off laser (for example 308-351 nm, or 355 nm) with a very high absorption. | 2010-07-01 |
20100163879 | Array substrate for liquid crystal display device and method of fabricating the same - A method of fabricating a liquid crystal display device includes: a first step of attaching a polarizing plate to an outer surface of a liquid crystal panel; a second step of attaching a tape carrier package (TCP) to the liquid crystal panel; a third step of coating a resin onto a rear surface of the TCP and a connection portion of the liquid crystal panel and the TCP; a fourth step of inspecting the TCP and the liquid crystal display panel; a fifth step of inserting the liquid crystal panel into a transferring means; a sixth step of transferring the transferring means; a seventh step of extracting the liquid crystal panel from the transferring means; a eighth step of attaching the TCP to a printed circuit board (PCB); a ninth step of inspecting the PCB, the TCP and the liquid crystal panel; and a tenth step of assembling the liquid crystal panel and a backlight unit with a plurality of frames. | 2010-07-01 |
20100163880 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor array panel comprises a repair line disposed in a peripheral area of a display area and being configured to repair when at least one of a gate line and a data line are disconnected, and a detour line disposed in the peripheral area and comprising at least one resistor having higher resistance than a remaining portion of the detour line, wherein both ends of the detour line are connected to the repair line to protect the array panel. | 2010-07-01 |
20100163881 | ARRAY SUBSTRATE FOR ELECTROPHORESIS TYPE DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME, METHOD OF REPAIRING A LINE OF THE SAME - An array substrate for an electrophoresis type display device includes a plurality of gate lines on a substrate; a gate insulating layer on the plurality of gate lines; a plurality of data lines on the gate insulating layer and crossing the plurality of gate lines to define a plurality of pixel regions; a thin film transistor corresponding to each pixel region, the thin film transistor including a gate electrode, a semiconductor layer, and source and drain electrodes; a first passivation layer on the plurality of data lines; a second passivation layer on the first passivation layer, wherein the second passivation layer includes a first hole over the data line, and/or a second hole over the gate line with at least the gate insulating layer therebetween; and a pixel electrode on the second passivation layer and connected to the drain electrode, wherein a portion of the pixel electrode covers the first hole, and another portion of the pixel electrode covers the second hole. A method of manufacturing the same, and a method of repairing a line of the same is also disclosed. | 2010-07-01 |
20100163882 | THIN FILM TRANSISTOR ARRAY SUBSTRATE FOR AN X-RAY DETECTOR AND METHOD OF FABRICATING THE SAME - A thin film transistor (TFT) array substrate for an X-ray detector and a method of fabricating the same are provided. The TFT array substrate includes a substrate, a gate line formed on the substrate, a data line crossing the gate line, a thin film transistor including a gate electrode, a source electrode, and a drain electrode, a first electrode connected to the drain electrode, a passivation layer formed over the gate line, the data line, the thin film transistor and the first electrode, a photoconductor formed over the passivation layer and connected to the first electrode, and a second electrode formed on the photoconductor. | 2010-07-01 |
20100163883 | MANUFACTURING METHOD OF ELECTRO LINE FOR LIQUID CRYSTAL DISPLAY DEVICE - A manufacturing method of an electro line for a liquid crystal display device includes depositing a barrier layer made of a conducting material on a substrate, depositing a copper layer (Cu) on the barrier layer, wet-etching the Cu layer using a first etchant, and dry-etching the barrier layer using a second etchant using the wet-etched Cu layer as an etch mask. | 2010-07-01 |
20100163884 | SWITCHING DEVICE STRUCTURE OF ACTIVE MATRIX DISPLAY - A switching device structure of active matrix display is provided. The switching device structure includes a substrate, a plurality of switching-device gate connection lines disposed on the substrate along a first direction and a plurality of switching devices disposed on the substrate along the first direction. Each switching device includes a gate electrode electrically connected to the any two adjacent switching-device gate connection lines, and the gate electrode protrudes from at least one side of the switching-device gate connection line along a second direction. | 2010-07-01 |
20100163885 | THIN FILM TRANSISTOR, METHOD OF FABRICATING THE SAME, AND ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE INCLUDING THE THIN FILM TRANSISTOR - A thin film transistor (TFT) includes a substrate, a semiconductor layer disposed on the substrate and including source and drain regions, each having a first metal catalyst crystallization region and a second metal catalyst crystallization region, and a channel region having the second metal catalyst crystallization region, a gate electrode disposed in a position corresponding to the channel region of the semiconductor layer, a gate insulating layer interposed between the semiconductor layer and the gate electrode to electrically insulate the semiconductor layer from the gate electrode, and source and drain electrodes electrically insulated from the gate electrode and electrically connected to the source and drain regions, respectively. An OLED display device includes the thin film transistor and a first electrode, an organic layer, and a second electrode electrically connected to the source and drain electrodes. | 2010-07-01 |
20100163886 | GALLIUM NITRIDE COMPOUND SEMICONDUCTOR LIGHT-EMITTING DEVICE, METHOD OF MANUFACTURING THE SAME, AND LAMP INCLUDING THE SAME - The present invention provides a gallium nitride compound semiconductor light-emitting device that prevents an increase in the specific resistance of a p-type semiconductor layer due to hydrogen annealing and reduces the specific resistance of a translucent conductive oxide film to lower a driving voltage Vf, a method of manufacturing the same, and a lamp including the same. The method of manufacturing the gallium nitride compound semiconductor light-emitting device includes: forming a positive electrode | 2010-07-01 |
20100163887 | LIGHT EMITTING DEVICE HAVING A PLURALITY OF NON-POLAR LIGHT EMITTING CELLS AND A METHOD OF FABRICATING THE SAME - The present invention relates to a light emitting device having a plurality of non-polar light emitting cells and a method of fabricating the same. Nitride semiconductor layers are disposed on a Gallium Nitride substrate having an upper surface. The upper surface is a non-polar or semi-polar crystal and forms an intersection angle with respect to a c-plane. The nitride semiconductor layers may be patterned to form light emitting cells separated from one another. When patterning the light emitting cells, the substrate may be partially removed in separation regions between the light emitting cells to form recess regions. The recess regions are filled with an insulating layer, and the substrate is at least partially removed by using the insulating layer. | 2010-07-01 |
20100163888 | MANUFACTURING PROCESS OF A POWER ELECTRONIC DEVICE INTEGRATED IN A SEMICONDUCTOR SUBSTRATE WITH WIDE BAND GAP AND ELECTRONIC DEVICE THUS OBTAINED - An embodiment of a process for manufacturing an electronic device on a semiconductor body of a material with wide forbidden bandgap having a first conductivity type. The process comprises the steps of: forming, on the semiconductor body, a first mask having a first window and a second window above a first surface portion and a second surface portion of the semiconductor body; forming, within the first and second surface portions of the semiconductor body underneath the first and second windows, at least one first conductive region and one second conductive region having a second conductivity type, the first conductive region and the second conductive region facing one another; forming a second mask on the semiconductor body, the second mask having a plurality of windows above surface portions of the first conductive region and the second conductive region; forming, within the first conductive region and the second conductive region and underneath the plurality of windows, a plurality of third conductive regions having the first conductivity type; removing completely the first and second masks; performing an activation thermal process of the first, second, and third conductive regions at a high temperature; and forming body and source regions. | 2010-07-01 |
20100163889 | OPTICAL MODULATOR WITH PIXELIZATION PATTERNS - Provided is an optical modulator having pixelization patterns. The optical modulator includes an optical-electric (O-E) conversion element converting input optical images to current signals using the photoelectric effect, and an electric-optical (E-O) conversion element that emits light using the current signals transferred from the O-E conversion element. Trenches are formed from at least a surface of the optical modulator to a predetermined depth in the optical modulator so as to block or reduce electrical interference between pixels when the electric signals are transferred from the O-E conversion element to the E-O conversion element. | 2010-07-01 |
20100163890 | LED LIGHTING DEVICE - An LED lighting device comprising an integral body comprising a dielectric thermally conductive polymer has an electrically conductive material directly attached to, or at least in part is molded within the body and forms a circuit pattern. Two or more LED die each having at least a portion thereof being attached directly either to one of a portion of the first body for direct thermal conduction or a portion of the electrically conductive material for direct electrical and thermal conduction or both. The integral body is optionally molded to have integral cooling surfaces such as fins. The integral body also may take a shape conforming to a mounting structure of a lighting fixture and may also include thereon additional electrical components for assisting the LED die in producing light, in other words drive components. Terminals may be integrally molded or formed in the body upon which a portion of the conductive material resides for electrical connection to another device such as a power source. | 2010-07-01 |
20100163891 | LIGHT EMITTING DIODE - An LED includes a substrate, two LED dies mounted on the substrate, an encapsulant molded on the substrate and sealing the two LED dies, and two phosphors contained within the encapsulant and surrounding the two LED dies, respectively. The two phosphors are distributed on the two LED dies in same density and different thicknesses, whereby the mixed light from one LED die and one phosphor has a color temperature different from that mixed from another LED die and another phosphor. | 2010-07-01 |
20100163892 | LED DEVICE AND METHOD OF PACKAGING THE SAME - A light emitting diode (LED) device including a transparent substrate, a plurality of LED chips, a circuit, and a transparent encapsulant is provided. The LED chips are fixed on the transparent substrate, and utilized for radiating at least a light beam. The circuit is disposed on the transparent substrate and electrically connected to the LED chips. The transparent encapsulant is utilized for packaging the LED chips. The light beam of the LED chips can propagate from two opposite sides of the transparent substrate. Blue LED chips and the circuit of the transparent substrate can be directly soldered, and the phosphors are arranged to convert the wavelength of blue light, so a dual-side white light emitting device can therefore be provided. | 2010-07-01 |
20100163893 | SEMICONDUCTOR LIGHT EMITTING DEVICE - Provided is a semiconductor light emitting device. | 2010-07-01 |
20100163894 | Group III nitride-based compound semiconductor light-emitting device - In the Group III nitride-based compound semiconductor light-emitting device of the invention, an non-light-emitting area is formed in a light-emitting layer. In a light-emitting diode where light is extracted on the side of an n-layer, an outer wiring trace portion and an inner wiring trace portion of an n-contact electrode impedes light emission from the light-emitting layer. Therefore, there are provided, at the interface between a p-layer and a p-contact electrode, high-resistance faces having a width wider than the orthogonal projections of contact areas between the outer and inner wiring trace portions and the n-layer on the interface between the p-contact electrode and the p-layer. Through this configuration, current flow is limited, and portions having a total area equivalent to that of the high-resistance faces of the light-emitting layer serve as non-light-emitting areas. Thus, current can be supplied preferentially to an area of the light-emitting area where the outer wiring trace portion and the inner wiring trace portion are difficult to shade light, whereby light extraction efficiency with respect to supplied current can be enhanced. | 2010-07-01 |
20100163895 | LIGHT EMITTING DEVICE - Provided is a compound light emitting device which facilitates easy connection of power supply lines, and has a high emission intensity in-plane uniformity. The light emitting device includes a first-conduction-type cladding layer, active layer structure, and second-conduction-type cladding layer each containing a III-V compound semiconductor. The first-conduction-type cladding layer and second-conduction-type cladding layer sandwich the active layer structure. The light emitting device includes a first-conduction-type-side electrode ( | 2010-07-01 |
20100163896 | Nitride Red Phosphors and White Light Emitting Diode Using Rare-Earth-Co-Doped Nitride Red Phosphors - Disclosed are nitride red phosphors and white light emitting diodes using the same. More particularly, the present invention provides a nitride red phosphor with easily controlled composition of phosphor fraction and improved uniformity and color gamut thereof, a method for preparation thereof, a white light emitting diode with excellent color rendition and high light emitting efficiency, and a white light emitting diode package using the same. | 2010-07-01 |
20100163897 | FLEXIBLE LIGHT SOURCE DEVICE AND FABRICATION METHOD THEREOF - A flexible light source device including a substrate, a light emitting device, a molding compound, a dielectric layer, and a metal line is provided. The substrate has a first surface, a second surface opposite to the first surface, and a first opening. The light emitting device is disposed on the first surface of the substrate and covers the first opening. The molding compound is located above the first surface and covers the light emitting device. The dielectric layer is disposed on the second surface and covers a sidewall of the first opening. The dielectric layer has a second opening which exposes part of the light emitting device. The metal line is disposed on the dielectric layer, wherein the metal line is electrically connected to the light emitting device via the second opening in the dielectric layer. Additionally, a fabrication method of the flexible light source device is also provided. | 2010-07-01 |
20100163898 | LIGHT EMITTING DIODE APPARATUS - A light emitting diode apparatus comprises a substrate having a circuit pattern, a reflection layer disposed on the substrate, at least one light emitting element disposed on the reflection layer, a reflector disposed around the at least one light emitting element, a sealing material formed over the at least one light emitting element and a phosphor layer disposed over the sealing material. The light emitting element comprises a conductive portion electrically coupled to the circuit pattern. In one embodiment, a plurality of light emitting elements are linearly arrayed, and a spacer is disposed between every two adjacent light emitting elements. | 2010-07-01 |
20100163899 | WHITE LIGHT EMITTING DEVICE - A white light emitting device is disclosed. The white light emitting device includes a blue light emitting diode (LED) including a plurality of active layers generating different peak wavelengths, and phosphors emitting yellow light when excited by light emitted from the blue LED. The white light emitting device ensures enhanced excitation efficiency of the phosphors, and high luminance. | 2010-07-01 |
20100163900 | LIGHT EMITTING DEVICE HAVING PLURALITY OF NON-POLAR LIGHT EMITTING CELLS AND METHOD OF FABRICATING THE SAME - Disclosed are a light emitting device having a plurality of non-polar light emitting cells and a method of fabricating the same. This method comprises preparing a first substrate of sapphire or silicon carbide having an upper surface with an r-plane, an a-plane or an m-plane. The first substrate has stripe-shaped anti-growth patterns on the upper surface thereof, and recess regions having sidewalls of a c-plane between the anti-growth patterns. Nitride semiconductor layers are grown on the substrate having the recess regions, and the nitride semiconductor layers are patterned to form the light emitting cells separated from one another. Accordingly, there is provided a light emitting device having non-polar light emitting cells with excellent crystal quality. | 2010-07-01 |
20100163901 | NITRIDE SEMICONDUCTOR LIGHT EMITTING ELEMENT - In a nitride semiconductor light emitting element, a light transmitting substrate has an upper surface on which a nitride semiconductor layer including at least a light emitting layer is formed. On the upper surface of the light transmitting substrate, recess regions and rise regions are formed. One of each of the recess regions and each of the rise regions is formed by a polygon having at least one apex having an interior angle of 180° or greater when viewed in a planar view. The other of each of the recess regions and each of the rise regions is formed not to be connected to one another in a straight line when viewed in a planar view. A nitride semiconductor light emitting element having such a configuration has excellent light extraction efficiency and can be manufactured at a moderate cost. | 2010-07-01 |
20100163902 | LIGHT EMITTING DEVICE - Disclosed is a light emitting device. The light emitting device includes a light emitting structure comprising an active layer to generate first light, a first conductive semiconductor layer on the active layer, and a second conductive semiconductor layer on the active layer so that the active layer is disposed between the first and second conductive semiconductor layers, wherein a portion of the light emitting structure is implanted with at least one element which generates second light from the first light. | 2010-07-01 |
20100163903 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device is provided. The semiconductor light emitting device comprises a plurality of compound semiconductor layers including a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer, and a layer of the plurality of compound semiconductor layers comprising a roughness comprising a sapphire material. | 2010-07-01 |
20100163904 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND LIGHT-EMITTING DEVICE PACKAGE HAVING THE SAME - Provided are a semiconductor light-emitting device and a light-emitting device package having the same. The semiconductor light-emitting device comprises a light-emitting structure, a first electrode unit, and a second electrode layer. The light-emitting structure comprises a plurality of compound semiconductor layers having a rounded side surface at an outer edge. The first electrode unit is disposed on the light-emitting structure. The second electrode layer is disposed under the light-emitting structure. | 2010-07-01 |
20100163905 | LIGHT EMITTING DEVICE PACKAGE - A light emitting device package and a method for manufacturing the same are provided. The light emitting device package comprises a package body including a cavity disposed at an upper portion. The light emitting device package includes an insulating layer disposed on a surface of the package body. The light emitting device package includes a plurality of metal layers disposed on the insulating layer. The light emitting device package includes a light emitting device disposed in the cavity. The light emitting device package includes a first metal plate disposed at a rear surface of the package body at a location corresponding to the light emitting device. | 2010-07-01 |
20100163906 | Light Emitting Device with Air Bars and Method of Manufacturing the Same - Disclosed are a light emitting device having at least one air bar capable of improving light extracting efficiency and a method of manufacturing the same. With the present invention, there is provided a method of manufacturing a light emitting device including a semiconductor layer(s) having an air-bar layer(s) with a plurality of air bars. The method includes at least one process cycle for forming the semiconductor layer(s). The process cycle includes: forming a patterning thin-film layer on a substrate or a thin-film layer; forming on the patterning thin-film layer an etching guide pattern and an air-bar pattern connected to the etching guide pattern; forming a semiconductor layer(s) on the patterns and exposing the etching guide pattern; wet-etch the exposed etching guide pattern by using a wet-etching solution; and etch the air-bar pattern connected to the etching guide pattern. | 2010-07-01 |
20100163907 | CHIP LEVEL PACKAGE OF LIGHT-EMITTING DIODE - The application discloses a light-emitting diode chip level package structure including: a permanent substrate having a first surface and a second surface; a first electrode on the first surface; a second electrode on the second surface; an adhesive layer on where the first surface of the permanent substrate is not covered by the first electrode; a growth substrate on the adhesive layer; a patterned semiconductor structure on the growth substrate; a third electrode and a fourth electrode on the patterned semiconductor structure and electrically connect with the patterned semiconductor structure; an electrical connecting structure on the sidewall of the patterned semiconductor structure electrically connecting the third electrode and the fourth electrode with the first electrode; and an insulation layer located on the side wall of the patterned semiconductor structure and between the electrical connecting structure for electrically insulating the patterned semiconductor structure. | 2010-07-01 |
20100163908 | Light emitting device having vertical structrue and method for manufacturing the same - A light emitting device having a vertical structure and a method for manufacturing the same, which are capable of damping impact generated during a substrate separation process and achieving an improvement in mass productivity, are disclosed. The light emitting device includes a semiconductor layer having a multilayer structure, a first electrode arranged at one surface of the semiconductor layer, a metal support arranged on the first electrode, and an impact damping layer arranged between the first electrode and the metal support, and made of a metal having a ductility higher than a ductility of a metal for the metal support. | 2010-07-01 |
20100163909 | MANUFACTURING METHOD AND STRUCTURE OF LIGHT-EMITTING DIODE WITH MULTILAYERED OPTICAL LENS - A manufacturing method and a structure of a light-emitting diode (LED) with a multilayered optical lens are provided. The manufacturing method includes the steps of: providing an LED chip; forming at least one inner protective layer covering the LED chip and its wire connecting points; and forming an outer protective layer covering the inner protective layer. Both the inner and outer protective layers are optical resin layers while the inner protective layer is harder than the outer protective layer. The structure of the LED includes: an LED chip; at least one inner protective layer covering the LED chip and its wire connecting points; and an outer protective layer covering the said inner protective layer. The relatively hard said inner protective layer can resist external force transmitted by the outer protective layer and protect the LED chip and its wire connecting points from damage by the external force. | 2010-07-01 |
20100163910 | LIGHT EMITTING DIODE - An LED chip ( | 2010-07-01 |
20100163911 | ELECTRODE STRUCTURES FOR LEDS WITH INCREASED ACTIVE AREA - An electrode structure is disclosed for enhancing the brightness and/or efficiency of an LED. The electrode structure can have a metal electrode and an optically transmissive thick dielectric material formed intermediate the electrode and a light emitting semiconductor material. The electrode and the thick dielectric cooperate to reflect light from the semiconductor material back into the semiconductor so as to enhance the likelihood of the light ultimately being transmitted from the semiconductor material. Such LED can have enhanced utility and can be suitable for uses such as general illumination. The semiconductor material can have a cutout formed therein and a portion of the electrode can be formed outside of the cutout and a portion of the electrode can be formed inside of the cutout. The portion of the electrode outside the cutout can be electrically isolated from the semiconductor material by the dielectric material. | 2010-07-01 |
20100163912 | NITRIDE-BASED SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A nitride-based semiconductor light emitting device having an improved structure in which light extraction efficiency is improved and a method of manufacturing the same are provided. The nitride-based semiconductor light emitting device comprises an n-clad layer, an active layer, and a p-clad layer, which are sequentially stacked on a substrate, wherein the n-clad layer comprises a first clad layer, a second clad layer, and a light extraction layer interposed between the first clad layer and the second clad layer and composed of an array of a plurality of nano-posts, the light extraction layer diffracting or/and scattering light generated in the active layer. | 2010-07-01 |
20100163913 | LAMP AND METHOD OF PRODUCING A LAMP - A method of producing a lamp, including: mounting light emitting junctions in respective receptacles; mounting the receptacles on a curved support structure so as to form a three-dimensional array; and placing the light emitting junctions in electrical connection with the support structure. | 2010-07-01 |
20100163914 | LIGHT EMITTING DEVICE - A light emitting device, in which an encapsulation resin is disposed at a space confined between an optical member and a mounting substrate. This encapsulation resin is possibly made free from a void-generation therein. In this light emitting device, the optical member can be precisely positioned. An electrode disposed outside a color conversion member is possibly free from an improper solder connection. A ring gate is formed on the top surface of the mounting substrate outside of the optical member, and acts to position the color conversion member. The ring gate acts to prevent an overflowing liquid encapsulation resin from flowing to the electrode provided. The ring gate is provided with a plurality of centering projections which are spaced circumferentially along its inner circumference to position the color conversion member. | 2010-07-01 |
20100163915 | Thin-Film Semiconductor Component and Component Assembly - A thin-film semiconductor component having a carrier layer and a layer stack which is arranged on the carrier layer, the layer stack containing a semiconductor material and being provided for emitting radiation, wherein a heat dissipating layer provided for cooling the semiconductor component is applied on the carrier layer. A component assembly is also disclosed. | 2010-07-01 |
20100163916 | FULL-COVER LIGHT-EMITTING DIODE LIGHT BAR AND METHOD FOR MANUFACTURING THE SAME - In a full-cover light-emitting diode light bar that can withstand a large bending deformation, a first lead and a second lead are juxtaposed with a distance. An insulating layer having a slot is formed on the first lead and the second lead via a hot pressing process. A crystal-receiving section of the first lead is displayed in the slot, and a connecting section of the second lead is displayed in the slot. A light-emitting diode crystal has a first electrode and a second electrode. Then, the light-emitting diode crystal is disposed in the slot with the first electrode being electrically fixed to the crystal-receiving section. The second electrode of the light-emitting diode crystal is electrically connected to the connecting section via a metallic lead. A light-transmitting body is used to seal the slot. Via the above process, a full-cover light-emitting diode light bar is formed. | 2010-07-01 |
20100163917 | LIGHT-EMITTING DIODE LIGHT BAR AND METHOD FOR MANUFACTURING THE SAME - In a light-emitting diode light bar of a light-emitting device, a first lead and a second lead are juxtaposed with a distance. A light-emitting diode crystal has a first electrode and a second electrode. Then, the first electrode is electrically fixed to the first lead. The second electrode is electrically connected to the second lead via a metallic lead. A light-transmitting body is used to package the light-emitting diode crystal and the metallic lead. Finally, via a hot pressing process, an insulating layer covers the first lead and the second lead. In this way, a light-emitting diode light bar is formed. | 2010-07-01 |
20100163918 | LED PACKAGE - The present invention relates to an LED package including a lead frame including a chip attaching portion with at least one LED chip attached thereto and a plurality of terminal portions each having a width narrower than the chip attaching portion, and a housing for supporting the lead frame. The plurality of terminal portions include at least one first terminal portion extending from a portion of a width of the chip attaching portion, and a plurality of second terminal portions spaced apart from the chip attaching portion. | 2010-07-01 |
20100163919 | Lighting device - Provided is a lighting device which includes a lead frame embedded in a glass material and has high reliability. The lighting device has a structure in which a light emitting element is mounted in a recess portion formed on a surface of a glass substrate and a sealing material is provided to cover the light emitting element. The lead frame is embedded in the glass substrate so as to be exposed on a side surface of the glass substrate and a bottom surface of the recess portion. A portion of the lead frame which is exposed in the recess portion is electrically connected with the light emitting element. With the structure as described above, the durability of the lighting device is improved. | 2010-07-01 |
20100163920 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device (A) includes a resin package ( | 2010-07-01 |
20100163921 | SEMICONDUCTOR CHIP ASSEMBLY WITH ALUMINUM POST/BASE HEAT SPREADER AND SILVER/COPPER CONDUCTIVE TRACE - A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The semiconductor device is electrically connected to the conductive trace and thermally connected to the heat spreader. The heat spreader is aluminum and includes a post and a base. The post extends upwardly from the base into an opening in the adhesive, and the base extends laterally from the post. The adhesive extends between the post and the conductive trace and between the base and the conductive trace. The conductive trace includes a silver coating and a copper core and provides signal routing between a pad and a terminal. | 2010-07-01 |
20100163922 | INSULATED GATE SEMICONDUCTOR DEVICE - By integrating a diode and a resistor connected in parallel into the same chip as an IGBT and connecting a cathode of the diode to a gate of the IGBT, the value of dv/dt can be limited to a predetermined range inside the chip of the IGBT without a deterioration in turn-on characteristics. Since the chip includes a resistor having such a resistance that a dv/dt breakdown of the IGBT can be prevented, the IGBT can be prevented from being broken by an increase in dv/dt at a site (user site) to which the chip is supplied. | 2010-07-01 |
20100163923 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device may include a semiconductor substrate having a first deep N well and/or a second deep N well, a first isolation layer over a first deep N well, and/or a first P well over a first deep N well. A semiconductor device may include an NMOS transistor over a first P well and/or a PMOS transistor over a first deep N well at an opposite side of a first isolation layer. A semiconductor device may include a second P well over a second deep N well, a second isolation layer interposed between a second deep N well and a second P well, and/or an emitter including first type impurities over a second deep N well. A semiconductor device may include a third isolation layer over a second P well, a collector including first type impurities over a second P well, and/or a base formed over a second P well and/or having a bottom surface to make contact with an emitter. | 2010-07-01 |
20100163924 | LATERAL SILICON CONTROLLED RECTIFIER STRUCTURE - A lateral silicon controlled rectifier structure includes a P-type substrate; an N-well region in the P-type substrate; a first P | 2010-07-01 |
20100163925 | AVALANCHE PHOTODIODE - In an electron-injection type APD, it is necessary to prevent a dark current increase and to secure the life time of the device. It is demanded to improve reliability of the APD with a lower production cost. With the InP buffer layer having an n-type doping region on the inside of a region defined by an optical absorption layer, a predetermined doping profile is achieved by ion implantation. Thus, electric field concentration in the avalanche multiplication layer is relaxed. Furthermore, a low-concentration second optical absorption layer is provided between the optical absorption layer and the avalanche multiplication layer. Responsivity of the optical absorption layer is maximized, and depletion of the lateral surface of the optical absorption layer is prevented; thus, electric field concentration is prevented. Preventing edge breakdown, the device improves its reliability. | 2010-07-01 |
20100163926 | MODULATION-DOPED MULTI-GATE DEVICES - Modulation-doped multi-gate devices are generally described. In one example, an apparatus includes a semiconductor substrate having a surface, one or more buffer films coupled to the surface of the semiconductor substrate, a first barrier film coupled to the one or more buffer films, a multi-gate fin coupled to the first barrier film, the multi-gate fin comprising a source region, a drain region, and a channel region of a multi-gate device wherein the channel region is disposed between the source region and the drain region, a spacer film coupled to the multi-gate fin, and a doped film coupled to the spacer film. | 2010-07-01 |
20100163927 | Apparatus and methods for forming a modulation doped non-planar transistor - Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed. | 2010-07-01 |
20100163928 | COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - An i-GaN layer (electron transit layer), an n-GaN layer (compound semiconductor layer) formed over the i-GaN layer (electron transit layer), and a source electrode, a drain electrode and a gate electrode formed over the n-GaN layer (compound semiconductor layer) are provided. A recess portion is formed inside an area between the source electrode and the drain electrode of the n-GaN layer (compound semiconductor layer) and at a portion separating from the gate electrode. | 2010-07-01 |
20100163929 | COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A compound semiconductor device includes a carrier transit layer formed over a substrate; a carrier supply layer formed over the carrier transit layer; a first metal film and a second metal film formed over the carrier supply layer; a first Al comprising film formed over the first metal film; a second Al comprising film formed over the second metal film; a first Au comprising film formed over the first metal film and is free of direct contact with the first Al comprising film; a second Au comprising film formed over the second metal film and free of direct contact with the second Al comprising film; and a gate electrode that is located over the carrier supply layer between the first metal film and the second metal film. | 2010-07-01 |
20100163930 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - An object of the present invention is to reduce on-state resistance and increases reliability in a semiconductor device having an electrode formed in a recessed structure. | 2010-07-01 |
20100163931 | GROUP III-V NITRIDE LAYER AND METHOD FOR PRODUCING THE SAME - There is disclosed a hexagonal Group III-V nitride layer exhibiting high quality crystallinity capable of improving the properties of a semiconductor device such as a light emitting element. This nitride layer is a Group III-V nitride layer belonging to hexagonal crystal formed by growth on a substrate having a different lattice constant, which has a growth-plane orientation of {1-100} and in which a full width at half maximum b | 2010-07-01 |
20100163932 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THEREOF - An image sensor may include a readout circuit formed over a first substrate made of InSb, the first substrate including a pixel part and a periphery part. A wiring and interlayer dielectric layer may be formed over the first substrate including the readout circuit. A photodiode may be formed over the interlayer dielectric layer and over the pixel part of the first substrate, and an upper electrode layer may be connected with the photodiode. | 2010-07-01 |
20100163933 | ANTIBLOOMING IMAGING APPARATUS, SYSTEMS, AND METHODS - Apparatus, systems, and methods are described to assist in reducing dark current in an active pixel sensor. In various embodiments, a potential barrier arrangement is configured to block the flow of charge carriers generated outside a photosensitive region. In various embodiments, a potential well-potential barrier arrangement is formed to direct charge carriers away from the photosensitive region during an integration time. | 2010-07-01 |
20100163934 | METHOD FOR FABRICATING A JUNCTION FIELD EFFECT TRANSISTOR AND THE JUNCTION FIELD EFFECT TRANSISTOR ITSELF - A method for fabricating a junction field effect transistor includes the steps of the type I semiconductor at the base thereof being doped with the type II semiconductor to form a type II well with a hole; then, a drive-in process of the type II semiconductor is performed to allow the implant dosage of the type II well getting less gradually from the surroundings of the hole toward the center of the hole; and finally, the gate, the source and the drain of the junction field effect transistor being formed successively on the type II well. The implant dosage at the hole, which is acted as a channel, is determined in accordance with the preset size of the hole during the type II well being formed such that it is capable being compatible with the output voltages of different junction field effect transistors to achieve the purpose of the adjustment of the pinch-off voltage of the junction field effect transistor without the need of the mask and the manufacturing process. | 2010-07-01 |
20100163935 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a junction FET of a normally-off type, a technique capable of achieving both of improvement of a blocking voltage and reduction of an ON resistance is provided. In a junction FET using silicon carbide as a substrate material, impurities are doped to a vicinity of a p-n junction between a gate region and a channel-formed region, the impurities having a conductive type which is reverse to that of impurities doped in the gate region and same as that of impurities doped in the channel-formed region. In this manner, an impurity profile of the p-n junction becomes abrupt, and further, an impurity concentration of a junction region forming the p-n junction with the gate region in the channel-formed region is higher than those of a center region in the channel-formed region and of an epitaxial layer. | 2010-07-01 |
20100163936 | Structure and Method for Fabrication of Field Effect Transistor Gates With or Without Field Plates - A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate. | 2010-07-01 |
20100163937 | METHODS OF FORMING NICKEL SULFIDE FILM ON A SEMICONDUCTOR DEVICE - Embodiments of the present invention describe a method of forming nickel sulfide layer on a semiconductor device. A nickel sulfide layer is formed on a substrate by alternatingly exposing the substrate to a nickel-containing precursor and a sulfur-containing precursor. | 2010-07-01 |
20100163938 | METHOD FOR FORMING SILICIDE IN SEMICONDUCTOR DEVICE - A method of forming a silicide in a semiconductor device includes: forming a poly gate on and/or over the upper portion of a silicon substrate having an active area and an STI formed therein; forming a spacer wall on and/or over both sidewalls of the poly gate; forming source/drain by performing high-concentration ion implantation; forming a silicide blocking pattern on and/or over both sidewalls of the spacer wall and on the STI; forming a multilayer silicide material on and/or over substantially the entire surface of the silicon substrate having the silicide blocking pattern formed thereover; and performing an RTA process on the multilayer silicide material to form a silicide by reaction between the poly gate and the source/drain electrode. | 2010-07-01 |
20100163939 | TRANSISTOR DEVICE COMPRISING AN EMBEDDED SEMICONDUCTOR ALLOY HAVING AN ASYMMETRIC CONFIGURATION - In sophisticated semiconductor devices, an asymmetric transistor configuration may be obtained on the basis of a strain-inducing semiconductor alloy. To this end, strain relaxation implantation processes may be performed at the drain side according to some illustrative embodiments, while, in other cases, the deposition of the strain-inducing alloy may be performed in an asymmetric manner with respect to the drain side and the source side of the transistor. | 2010-07-01 |
20100163940 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - Provided are an image sensor and a method for manufacturing the same. The image sensor comprises a photodiode, a floating diffusion region, a reset transistor, and a drive transistor. The photodiode generates photocharges. The floating diffusion region accumulates the photocharges. The reset transistor has a source connected to the floating diffusion region, and has a gate and a drain connected to each other to perform a reset function. The drive transistor receives the photocharges and serves as a source follower buffer amplifier. | 2010-07-01 |
20100163941 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - An image sensor and a method for manufacturing the same that includes readout circuitry, an electrical junction region, an interconnection, an image sensing device, and an infrared filter. The readout circuitry and the electrical junction region are formed in a first substrate and are electrically connected to each other. The interconnection is formed over the electrical junction region and the image sensing device is formed over the interconnection. The infrared filter is formed on the image sensing device and includes a plurality of thin films. | 2010-07-01 |
20100163942 | CMOS IMAGE SENSOR HAVING DOUBLE GATE INSULATOR THEREIN AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a CMOS image sensor includes: preparing a semiconductor substrate incorporating therein a p-type epitaxial layer by epitaxially growing up an upper portion of the semiconductor substrate; forming a pixel array in one predetermined location of the semiconductor substrate, the pixel array having a plurality of transistors and a photodiode therein, wherein each transistor employs a gate insulator with a thickness ranging from 40 Å to 90 Å; and forming a logic circuit in the other predetermined location of the semiconductor substrate, the logic circuit having at least one transistor, wherein the transistor employs a gate insulator with a thickness ranging from 5 Å to 40 Å. | 2010-07-01 |
20100163943 | SEMICONDUCTOR MEMORY DEVICE - A memory includes a first interlayer on transistors; a first and second plugs connected to the transistor; ferroelectric capacitors; a second interlayer covering a side surface of the capacitor; a local interconnection connecting the second plug to the upper electrode, wherein two upper electrodes adjacent to each other on the second plug are connected to the second plug, the lower electrodes adjacent to each other on the first plug are connected to the first plug, cell blocks comprising the connected capacitors are arranged, cell blocks adjacent to each other are arranged to be shifted by a half pitch of the local interconnection, a first gap between two capacitors adjacent to each other on the second plug is larger than twice a thickness of the second interlayer, and a second gap between the cell blocks adjacent to each other is smaller than twice the thickness of the second interlayer. | 2010-07-01 |
20100163944 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor memory device includes a switching transistor provided on a semiconductor substrate; an interlayer dielectric film on the switching transistor; a contact plug in the interlayer dielectric film; a ferroelectric capacitor above the contact plug and the interlayer dielectric film, the ferroelectric capacitor comprising a lower electrode, a ferroelectric film and an upper electrode; a diffusion layer in the semiconductor substrate, the diffusion layer electrically connecting the contact plug to the switching transistor; a hydrogen barrier film on a side surface of the ferroelectric capacitor; and an interconnection comprising a TiN film or a TiAl | 2010-07-01 |
20100163945 | Embedded memory cell and method of manufacturing same - An embedded memory cell includes a semiconducting substrate ( | 2010-07-01 |
20100163946 | SEMICONDCUTOR DEVICE HAVING VERTICAL GATE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming buried bit lines separated from each other by a trench in a substrate, forming a plurality of first pillar holes that expose a top surface of the substrate, forming first active pillars buried in the first pillar holes, forming a gate conductive layer over entire surface of a resultant structure including the first active pillars, forming a gate electrode by etching the gate conducting layer to cover the first active pillars, forming a plurality of second pillar holes that expose the first active pillars by partially etching the gate electrode, and forming second active pillars buried in the second pillar holes and connected to the first active pillars. | 2010-07-01 |
20100163947 | METHOD FOR FABRICATING PIP CAPACITOR - A PIP capacitor and methods thereof. A method of fabricating a PIP capacitor may include forming a field oxide film over a silicon substrate to define a device isolating region and/or an active region. A method of fabricating a PIP capacitor may include forming a lower polysilicon electrode having doped impurities on and/or over an field oxide film. A method of fabricating a PIP capacitor may include performing an oxidizing step to form a first oxide film over a polysilicon and/or a second oxide film on and/or over an active region. A method of fabricating a PIP capacitor may include forming an upper polysilicon electrode on and/or over a region of a first oxide film and forming a gate electrode on and/or over a second oxide film at substantially the same time. A method of fabricating a PIP capacitor may include forming a polysilicon resistor. A PIP capacitor is disclosed. | 2010-07-01 |
20100163948 | Integrated Circuit Having Efficiently Packed Decoupling Capacitors - An integrated circuit includes a substrate having a semiconducting surface ( | 2010-07-01 |
20100163949 | VERTICAL METAL-INSULATOR-METAL (MIM) CAPACITOR USING GATE STACK, GATE SPACER AND CONTACT VIA - A semiconductor structure including a vertical metal-insulator-metal capacitor, and a method for fabricating the semiconductor structure including the vertical metal-insulator-metal capacitor, each use structural components from a dummy metal oxide semiconductor field effect transistor located and formed over an isolation region located over a semiconductor substrate. The dummy metal oxide field effect transistor may be formed simultaneously with a metal oxide semiconductor field effect transistor located over a semiconductor substrate that includes the isolation region. The metal-insulator-metal capacitor uses a gate as a capacitor plate, a uniform thickness gate spacer as a gate dielectric and a contact via as another capacitor plate. The uniform thickness gate spacer may include a conductor layer for enhanced capacitance. A mirrored metal-insulator-metal capacitor structure that uses a single contact via may also be used for enhanced capacitance. | 2010-07-01 |
20100163950 | Power Device with Monolithically Integrated RC Snubber - A semiconductor structure includes a power transistor monolithically integrated with a RC snubber in a die. The power transistor includes body regions extending in a silicon region, gate electrodes insulated from the body region by a gate dielectric, source regions extending in the body regions, the source and the body regions being of opposite conductivity type, and a source interconnect contacting the source regions. The RC snubber comprises including snubber electrodes insulated from the silicon region by a snubber dielectric such that the snubber electrodes and the silicon region form a snubber capacitor having a predetermined value. The snubber electrodes are connected to the source interconnect in a manner so as to form a snubber resistor of a predetermined value between the snubber capacitor and the source interconnect. The snubber capacitor and the snubber resistor are configured to substantially dampen output ringing when the power transistor switches states. | 2010-07-01 |
20100163951 | FLASH MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME - A flash memory device is disclosed including: a device isolation layer and an active area formed on a semiconductor substrate in which a source plate and a bit line area are defined; a memory gate formed over the active area of the bit line area; a control gate formed on the semiconductor substrate including the memory gate; a common source area and a drain area disposed on both sides of the control gate; and a common source line contact formed over the common source area of the semiconductor substrate at the active area of the source plate, wherein the active area of the source plate is formed having the same interval with the active area of the bit line area, and the control gate is formed to cross the source plate and the bit line area disposed at both sides of the source plate. | 2010-07-01 |
20100163952 | Flash Cell with Integrated High-K Dielectric and Metal-Based Control Gate - A semiconductor device is described having an integrated high-k dielectric layer and metal control gate. A method of fabricating the same is described. Embodiments of the semiconductor device include a high-k dielectric layer disposed on a floating gate. The high-k dielectric layer defines a recess. A metal control gate is formed in the recess. | 2010-07-01 |
20100163953 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first polysilicon pattern formed on a semiconductor substrate, a second polysilicon pattern formed at a lateral side of the first polysilicon pattern such that the second polysilicon pattern extends to a height higher than the first polysilicon pattern, a third polysilicon pattern formed in a region restricted by a top surface of the first polysilicon pattern and a lateral side of the second polysilicon pattern, and a contact electrically connected with the second polysilicon pattern and the third polysilicon pattern. | 2010-07-01 |
20100163954 | FLASH MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed are a dual bit type NROM flash memory device and a method for manufacturing the same using a self-aligned scheme. The flash memory device includes a plurality of bit lines buried in a substrate in one direction while being spaced apart from each other at a regular interval; floating gates aligned at both sides of each of the bit lines on the substrate; and a plurality of word lines spaced apart from each other at a regular interval while crossing the bit lines. In the flash memory device of an embodiment, polysilicon is used for a trapping layer, so the programming and erasing operations can be performed at a higher speed, a threshold voltage (Vt) window is widened, and retention characteristics are improved. | 2010-07-01 |
20100163955 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is provided including: a spacer shaped floating gate formed on a semiconductor substrate; a dielectric layer spacer formed at one side wall of the floating gate; a third oxide layer formed over the floating gate and the dielectric layer; and a control gate formed over the third oxide layer. According to an embodiment, the structure of the floating gate in a plate shape whose center is concave is improved to the spacer structure, making it possible to minimize the size of the semiconductor memory device and to improve density. Moreover, a LOCOS process can be excluded while forming the floating gate, making it possible to more efficiently fabricate the device. | 2010-07-01 |
20100163956 | EEPROM DEVICE AND METHOD OF MANUFACTURING THE SAME - An EEPROM device may have, at the region where the control gate is formed, a gate oxide layer having a relatively smaller thickness than the gate oxide layer of the tunneling region by removing the gate oxide layer, at a predetermined thickness, at the region where the control gate is formed. Thus, integration of an EEPROM device may be maximized as a result of minimizing the area of the control gate. | 2010-07-01 |
20100163957 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING MEMORY CELLS FORMED TO HAVE DOUBLE-LAYERED GATE ELECTRODES - A nonvolatile semiconductor memory device includes a plurality of floating gate electrodes respectively formed above a semiconductor substrate with first insulating films disposed therebetween, and a control gate electrode formed above the plurality of floating gate electrodes with a second insulating film disposed therebetween. In each of the plurality of floating gate electrodes is formed to have a width of an upper portion thereof in a channel width direction which is smaller than a width of a lower portion thereof in the channel width direction and one of contact surfaces thereof on at least opposed sides which contact the second insulating film is formed to have one surface, and the second insulating film has a maximum film thickness in a vertical direction, the maximum film thickness being set smaller than a distance from a lowest surface to a highest surface of the second insulating film in the vertical direction. | 2010-07-01 |
20100163958 | SINGLE-POLY EEPROM CELL AND METHOD FOR FABRICATING THE SAME - A single-poly EEPROM cell and a method for fabricating the same include a single floating gate formed in a single body; first and second read transistors sharing the single floating gate; and a control gate spaced apart from the first and second read transistors and overlapped with the floating gate. In the single-poly EEPROM structure, as a tunneling region is removed and a read PTR is additionally formed, a read margin can be enhanced without increase of overall area. | 2010-07-01 |
20100163959 | Etch Stop Structures For Floating Gate Devices - Etch stop structures for floating gate devices are generally described. In one example, a floating gate device includes a semiconductor substrate having a surface on which one or more floating gate devices are formed, a tunnel dielectric coupled with the surface of the semiconductor substrate, a floating gate structure coupled with the tunnel dielectric, the floating gate structure having a first surface, a second surface, and a third surface, wherein the third surface is substantially parallel with the surface of the semiconductor substrate and wherein the first surface is substantially parallel with the second surface and substantially perpendicular with the third surface, an etch stop film coupled with the third surface of the floating gate structure, and an inter-gate dielectric coupled with the first surface and the second surface of the floating gate structure wherein the inter-gate dielectric comprises a material that is less resistant to an etchant that removes material of a control gate structure than the etch stop film. | 2010-07-01 |