26th week of 2022 patent applcation highlights part 67 |
Patent application number | Title | Published |
20220208527 | Cooled Shield for ICP Source - Provided is a plasma processing apparatus or system including a plasma chamber and an inductively coupled plasma source. A shielding device is disposed between the plasma chamber the inductively coupled plasma source. The shielding device includes a top annular portion, a bottom annular portion, and a plurality of thermal pads coupled to top annular portion and/or bottom annular portion with one or more retaining members. The one or more retaining members provide a compressive force to secure the one or more thermal pads against the outer surface of the dielectric wall. The plurality of thermal pads are configured to modulate a heat flux from the dielectric wall into the respective thermal pad. Methods of processing workpieces are also disclosed. | 2022-06-30 |
20220208528 | DEVICE FOR ADJUSTING PLASMA EDGE IN PROCESSING CHAMBER AND CONTROL METHOD THEREOF - The present invention relates to a device for adjusting a plasma curve. The device includes a metal adjusting ring having an inner side surface, an inclined surface and a top surface. The inclined surface extends downwards from the top surface to the inner side surface. The inclined surface and the top surface define an included angle, which is within a range of 150 degrees to 120 degrees. | 2022-06-30 |
20220208529 | Configurable Faraday Shield - A configurable Faraday shield is provided. The configurable Faraday shield includes a plurality of ribs. Each of the ribs can be spaced apart from one another along a circumferential direction. Furthermore, at least a portion of the configurable Faraday shield is movable between at least a first position and a second position to selectively couple the configurable Faraday shield to a radio frequency ground plane. When the at least a portion of the configurable Faraday shield is in the first position, the configurable Faraday shield can be decoupled from the radio frequency ground plane such that the configurable Faraday shield is electrically floating. Conversely, when the at least a portion of the configurable Faraday shield is in the second position, the configurable Faraday shield can be coupled to the radio frequency ground plane such that the configurable Faraday shield is electrically grounded. | 2022-06-30 |
20220208530 | SUBSTRATE PROCESSING APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM - There is provided technic that includes: a processing chamber having a film formation processing area and a modification processing area adjacent to the film formation processing area; a film former configured to perform film formation processing on a substrate in the film formation processing area; a modifier configured to perform modification processing different from the film formation processing on the substrate in the modification processing area; a substrate mounter configured to support the substrate; and a controller configured to control the substrate mounter such that a speed of moving the substrate is different between the film formation processing area and the modification processing area when the substrate moves in each of the film formation processing area and the modification processing area. | 2022-06-30 |
20220208531 | VERTICALLY ADJUSTABLE PLASMA SOURCE - The disclosure describes a plasma source assemblies comprising a differential screw assembly, an RF hot electrode, a top cover, an upper housing and a lower housing. The differential screw assembly is configured to provide force to align the plasma source assembly vertically matching planarity of a susceptor. More particularly, the differential screw assembly increases a distance between the top cover and the upper housing to align the gap with the susceptor. The disclosure also provides a better thermal management by cooling fins. A temperature capacity of the plasma source assemblies is extended by using titanium electrode. The disclosure provides a cladding material covering a portion of a first surface of RF hot electrode, a second surface of RF hot electrode, a bottom surface of RF hot electrode, a portion of a surface of the showerhead and a portion of lower housing surface. | 2022-06-30 |
20220208532 | METHOD OF PLASMA PROCESSING A SUBSTRATE IN A PLASMA CHAMBER AND PLASMA PROCESSING SYSTEM - A method of plasma processing a substrate in a plasma chamber is provided. The method includes the steps of supplying a power supply signal to electrodes arranged within the plasma chamber in order to form a plasma in the plasma chamber, monitoring at least one parameter related to the plasma processing, determining a feature related to the at least one monitored parameter, and adjusting the power supply signal during the plasma processing to modify, in particular reduce, the feature. The modification of the feature eliminates or mitigates formation of crazing on the substrate. | 2022-06-30 |
20220208533 | SURFACE PROCESSING EQUIPMENT AND SURFACE PROCESSING METHOD - A surface processing equipment using energy beam including a multi-axis platform, a surface profile measuring device, an energy beam generator and a computing device is provided. The multi-axis platform is configured to carry a workpiece and move the workpiece to the first position or the second position. The surface profile measuring device has a working area, and the first position is located on the working area. The surface profile measuring device is configured to measure the workpiece to obtain surface profile. The energy beam generator is configured to provide an energy beam to the workpiece for processing, and the second position is located on a transmission path of the energy beam. The computing device is connected to the surface profile measuring device and the energy beam generator. The computing device adjusts the energy beam generator according to the error profile. | 2022-06-30 |
20220208534 | SPUTTERING APPARATUS AND METHOD OF CONTROLLING SPUTTERING APPARATUS - There is provided a sputtering apparatus comprising: a target from which sputtered particles are emitted; a substrate support configured to support a substrate; a substrate moving mechanism configured to move the substrate in one direction; and a shielding member disposed between the target and the substrate support and having an opening through which the sputtered particles pass. The shielding member includes a first shielding member and a second shielding member disposed in a vertical direction. | 2022-06-30 |
20220208535 | SYSTEMS AND METHODS FOR PERFORMING TANDEM MASS SPECTROMETRY - A method of performing tandem mass spectrometry includes supplying a sample to a chromatography column, directing components included in the sample and eluting from the chromatography column to a mass spectrometer, acquiring a series of mass spectra including intensity values of ions produced from the components as a function of m/z of the ions, extracting, from the series of mass spectra, a plurality of detection points representing intensity as a function of time for a selected m/z, estimating, based on the plurality of detection points extracted from the series of mass spectra, a relative position of a selected detection point included in the plurality of detection points, and performing, at the mass spectrometer and based on the estimated relative position, a dependent acquisition for the selected m/z. The relative position of the selected detection point represents a position of the selected detection point relative to an expected reference point. | 2022-06-30 |
20220208536 | System and Method for High Throughput Mass Spectrometry Analysis - A high throughput mass spectrometry system that includes one or more sample preparation devices located at one or more of first locations configured to prepare samples for mass spectrometry analysis; one or more ionization sources configured to produce ions from the prepared samples at the one or more of the first locations; one or more mass spectrometers located at one or more of second locations configured to analyze the produced ions from the prepared samples based on mass to charge ratio of the produced ions; and one or more ion transfer devices configured to transfer the produced ions from the one or more of the first locations to the one or more of the second locations. | 2022-06-30 |
20220208537 | APERTURE PLATE ASSEMBLY - An aperture plate assembly for an analytical instrument comprises a first sub-assembly comprising an aperture plate and a second sub-assembly comprising a guide. The first sub-assembly is configured to be attached to the second sub-assembly such that the aperture plate is positioned in a first position relative to the second sub-assembly. The first sub-assembly and the second sub-assembly are configured such that when the first sub-assembly is engaged by the guide, the aperture plate can be moved into the first position and the first sub-assembly can be attached to the second sub-assembly. | 2022-06-30 |
20220208538 | INTEGRATED MICROFLUIDIC PROBE (IMFP) AND METHODS OF USE THEREOF - The invention generally relates to mass spectral analysis. In certain embodiments, methods of the invention involve a probe for nano spray desorption electro spray ionization (nano-DESI) with fixed positioning of the channels therein for consistent and stable formation of a liquid bridge for nano-DESI and mass spectrometry imaging (MSI). Probes may incorporate a shear force probe for sensing and maintaining a desired distance between the probe and the sample surface being analyzed. | 2022-06-30 |
20220208539 | METHOD AND APPARATUS FOR MASS SPECTROMETRY - Disclosed herein are methods and systems for ionizing organic compounds by exposing head space vapors to corona discharge. The methods and systems are suitable for high throughput screening of samples, including biofluids. The methods and systems are suitable for rapid evaluation of chemical reactions, permitting discovery of novel organic reaction pathways. | 2022-06-30 |
20220208540 | System for Identifying Structures of Molecular Compounds from Mass Spectrometry Data - A method and system is for searching a database to identify structures of molecular compounds from mass spectrometry data. Operations of the method and system include receiving a query for a target molecular structure in the database, the query representing a query spectrum; accessing a machine learning model trained with molecule-spectrum pairs; inputting the query spectrum into the machine learning model; generating, from the machine learning model, a score for each of one or more molecular structures, each score representing a probability that a molecular structure corresponds to the query spectrum; selecting, based on each of the scores, a small molecule; and outputting, on a user interface, a representation of the small molecule. | 2022-06-30 |
20220208541 | APPARATUS AND METHOD FOR MANUFACTURING A WAFER - Various embodiments provide an apparatus and method for fabricating a wafer, such as a SiC wafer. The apparatus includes a support having a plurality of arms for supporting a substrate. The arms allows for physical contact between the support and the substrate to be minimized. As a result, when the substrate is melted, surface tension between the arms and molten material is reduced, and the molten material will be less likely to cling to the support. | 2022-06-30 |
20220208542 | SELECTIVE PASSIVATION AND SELECTIVE DEPOSITION - Methods for selective deposition are provided. Material is selectively deposited on a first surface of a substrate relative to a second surface of a different material composition. An inhibitor, such as a polyimide layer, is selectively formed from vapor phase reactants on the first surface relative to the second surface. A layer of interest is selectively deposited from vapor phase reactants on the second surface relative to the first surface. The first surface can be metallic while the second surface is dielectric. Accordingly, material, such as a dielectric transition metal oxides and nitrides, can be selectively deposited on metallic surfaces relative dielectric surfaces using techniques described herein. | 2022-06-30 |
20220208543 | MODULATED ATOMIC LAYER DEPOSITION - Methods and apparatuses for depositing thin films using long and short conversion times during alternating cycles of atomic layer deposition (ALD) are provided herein. Embodiments involve alternating conversion duration of an ALD cycle in one or more cycles of a multi-cycle ALD process. Some embodiments involve modulation of dose, purge, pressure, plasma power or plasma energy in two or more ALD cycles. | 2022-06-30 |
20220208544 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING METHOD, NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM AND SUBSTRATE PROCESSING APPARATUS - According to one aspect of a technique of the present disclosure, there is provided a method of manufacturing a semiconductor device, including: (A) forming a film containing a predetermined element and nitrogen on a substrate by performing a cycle a predetermined number of times, wherein the cycle includes: (a) forming a first layer by supplying a source gas containing the predetermined element and a halogen element to the substrate heated to a first temperature; (b) forming a second layer by modifying the first layer by supplying a plasma-excited first modification gas containing hydrogen free of nitrogen; and (c) forming a third layer by modifying the second layer by supplying a plasma-excited second modification gas containing nitrogen and hydrogen. A supply time T | 2022-06-30 |
20220208545 | SUBSTRATE TREATMENT APPARATUS AND SUBSTRATE TREATMENT METHOD - A substrate treatment method includes a rinsing step of performing treatment of a substrate with a rinse liquid, an immersing step of immersing the substrate in a diluted isopropyl alcohol (dIPA) stored in a treatment tank after the rinsing step, a first isopropyl alcohol treatment step of performing treatment of the substrate with an isopropyl alcohol after the immersing step, and a water-repellent treatment step of performing water-repellent treatment of the substrate after the first isopropyl alcohol treatment step. | 2022-06-30 |
20220208546 | SEMICONDUCTOR STRUCTRE AND METHOD - This disclosure relates to a semiconductor structure ( | 2022-06-30 |
20220208547 | METHOD FOR FORMING INSULATING FILM, APPARATUS FOR PROCESSING SUBSTRATE, AND SYSTEM FOR PROCESSING SUBSTRATE - There is provided a technique of forming an insulating film containing silicon oxide. A coating solution containing polysilazane is applied onto a wafer W, the solvent of the coating solution is volatilized, and the coating film is irradiated with ultraviolet rays in nitrogen atmosphere before performing a curing process. Dangling bonds are generated in silicon which is a pre-hydrolyzed site in polysilazane. Therefore, the energy for hydrolysis is reduced, and unhydrolyzed sites are reduced even when the temperature of the curing process is 350° C. Since efficient dehydration condensation occurs, the crosslinking rate is improved, and a dense (good-quality) insulation film is formed. By forming a protective film on the surface of the coating film to which ultraviolet rays irradiated, the reaction of dangling bonds prior to the curing process is suppressed. | 2022-06-30 |
20220208548 | VERTICAL NANOWIRE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A vertical nanowire semiconductor device manufactured by a method of manufacturing a vertical nanowire semiconductor device is provided. The vertical nanowire semiconductor device includes a substrate, a first conductive layer in a source or drain area formed above the substrate, a semiconductor nanowire of a channel area vertically upright with respect to the substrate on the first conductive layer, wherein a crystal structure thereof is grown in <111> orientation, a second conductive layer of a drain or source area provided on the top of the semiconductor nanowire, a metal layer on the second conductive layer, a NiSi | 2022-06-30 |
20220208549 | INDIUM PHOSPHIDE SUBSTRATE - Provided is an indium phosphide substrate which has suppressed sharpness of a wafer edge when polishing is carried out from the back surface of the wafer by a method such as back lapping. An indium phosphide substrate, wherein when planes A each parallel to a main surface are taken in a wafer, the phosphide substrate has an angle θ on the main surface side of 0°<θ≤110° for all of the planes A where a distance from the main surface is 100 μm or more and 200 μm or less, wherein the angle θ is formed by a plane B, the plane B including an intersection line of an wafer edge with each of the planes A and being tangent to the wafer edge, and an plane of each of the planes A extending in a wafer outside direction, and wherein in a cross section orthogonal to the wafer edge, the indium phosphide substrate has an edge round at least on the main surface side, and the edge round on the main surface side has a radius of curvature R | 2022-06-30 |
20220208550 | Method and Apparatus for Plasma Etching - Plasma etching a compound semiconductor substrate includes providing a substrate that includes a compound semiconductor material on a substrate support within a chamber. An etchant gas or gas mixture is introduced into the chamber. A plasma of the etchant gas or gas mixture is sustained within the chamber to plasma etch the compound semiconductor material. A pulsed electrical bias power is applied to the substrate support whilst the plasma is being sustained. The pulsed electrical bias power has a pulse frequency of less than or equal to about 160 Hz and a duty cycle of less than or equal to about 50%. | 2022-06-30 |
20220208551 | ALTERNATING ETCH AND PASSIVATION PROCESS - Tin oxide films are used as spacers and hardmasks in semiconductor device manufacturing. In one method, tin oxide layer (e.g., spacer footing) needs to be selectively etched in a presence of an exposed silicon-containing layer, such as SiOC, SiON, SiONC, amorphous silicon, SiC, or SiN. In order to reduce damage to the silicon-containing layer the process involves passivating the silicon-containing layer towards a tin oxide etch chemistry, etching the tin oxide, and repeating passivation and etch in an alternating fashion. For example, passivation and etch can be each performed between 2-50 times. In one implementation, passivation is performed by treating the substrate with an oxygen-containing reactant, activated in a plasma, and the tin oxide etching is performed by a chlorine-based chemistry, such as using a mixture of Cl | 2022-06-30 |
20220208552 | SEMICONDUCTOR PROCESS POLISHING COMPOSITION AND POLISHING METHOD OF SUBSTRATE APPLIED WITH POLISHING COMPOSITION - A semiconductor process polishing composition, and a polishing method of a substrate applied with a polishing composition are provided. The process provides a polishing composition improved in the polishing rate, selectivity and dispersibility, and provides a manufacturing method of a substrate that is polished by applying such a polishing composition for a semiconductor process. | 2022-06-30 |
20220208553 | SELECTIVE REMOVAL OF METAL OXIDE HARD MASKS - Compositions useful for the selective etching, i.e., removal, of metal oxide hard masks such as zirconium oxide and hafnium oxide, often used as hard masks in microelectronic devices, in the presence of other materials such as polysilicon, silicon dioxide, silicon nitride, and tungsten are provided. | 2022-06-30 |
20220208554 | ETCHING APPARATUS AND ETCHING METHOD - Provided is an etching apparatus for etching a silicon oxide film using a processing gas containing hydrogen fluoride and ammonia, including: a chamber; a gas supply unit; a water vapor supply unit; and a control unit. The chamber is configured such that a substrate having the silicon oxide film on a surface thereof can be disposed therein. The gas supply unit is configured to be capable of supplying one of the processing gas and a precursor gas of the processing gas to the chamber. The water vapor supply unit is capable of supplying water vapor to the chamber. The control unit controls the gas supply unit and the water vapor supply unit to supply the water vapor and one of the processing gas and the precursor gas to the chamber during etching processing. | 2022-06-30 |
20220208555 | DEPOSITION OF SELF ASSEMBLED MONOLAYER FOR ENABLING SELECTIVE DEPOSITION AND ETCH - A method for selectively etching a first region of a structure with respect to a second region of the structure is provided. The method comprises at least one cycle. Each cycle comprises selectively depositing an inhibitor layer on the first region of the structure, providing an atomic layer deposition over the structure, wherein the atomic layer deposition selectively deposits a mask on the second region of the structure with respect to the inhibitor layer, and selectively etching the first region of the structure with respect to the mask. The selectively depositing an inhibitor layer on the first region of the structure comprises providing an inhibitor layer gas and forming the inhibitor layer gas into inhibitor layer radicals, wherein the inhibitor layer radicals selectively deposit on the first region of the structure with respect to the second region of the structure. | 2022-06-30 |
20220208556 | METHOD OF MAKING A THREE-DIMENSIONAL MEMORY DEVICE USING COMPOSITE HARD MASKS FOR FORMATION OF DEEP VIA OPENINGS - An alternating stack of first material layers and second material layers can be formed over a semiconductor material layer. A patterning film is formed over the alternating stack, and openings are formed through the patterning film. Via openings are formed through the alternating stack at least to a top surface of the semiconductor material layer by performing a first anisotropic etch process that transfers a pattern of the openings in the patterning film. A cladding liner can be formed on a top surface of the patterning film and sidewalls of the openings in the pattering film. The via openings can be vertically extended through the semiconductor material layer at least to a bottom surface of the semiconductor material layer by performing a second anisotropic etch process employing the cladding liner as an etch mask. | 2022-06-30 |
20220208557 | METHOD OF PROCESSING SUBSTRATE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, RECORDING MEDIUM, AND SUBSTRATE PROCESSING APPARATUS - A film having film continuity can be formed. | 2022-06-30 |
20220208558 | SUBSTRATE PROCESSING METHOD, MICROPATTERN FORMING METHOD, AND SUBSTRATE PROCESSING APPARATUS - A substrate processing method includes providing a surface tension reducing agent as a gas onto a substrate, the substrate having an exposed photoresist layer and layer of developer on the exposed photoresist layer, and causing a bulk flow of the developer in order to remove the developer from the substrate. | 2022-06-30 |
20220208559 | METHOD AND APPARATUS FOR CHIP MANUFACTURING - Chip manufacturing, including: assembling at least two chips on a layer; and applying mold compound on the at least two chips to the sides and bottom including flowing around interconnects, thereby leaving the top of each of the at least two chips exposed. | 2022-06-30 |
20220208560 | APPARATUS FOR TREATING SUBSTRATE AND METHOD FOR TREATING SUBSTRATE - Provided is an apparatus for treating a substrate. In the exemplary embodiment, the apparatus for treating the substrate includes a support member configured to support a substrate and provided rotatably; a treating liquid nozzle configured to supply selectively a high-temperature first treating liquid and a high-temperature second treating liquid onto the substrate; and a controller configured to control the treating liquid nozzle so that the treating liquid nozzle first supplies the first treating liquid onto the substrate and then supplies the second treating liquid onto the substrate. | 2022-06-30 |
20220208561 | SUPPORTING DEVICE AND APPARATUS FOR PROCESSING A SUBSTRATE INCLUDING A SUPPORTING DEVICE - An apparatus for processing a substrate may include a process chamber providing a processing space in which a predetermined process may be performed on the substrate, and a supporting device contacting the process chamber and supporting the process chamber. The supporting device may include a supporting chamber providing a supporting space for supporting components of the process chamber and a supply member supplying a fluid into the supporting space. | 2022-06-30 |
20220208562 | PRESSURE ADJUSTMENT APPARATUS FOR CONTROLLING PRESSURE IN CHAMBER AND SUBSTRATE PROCESSING APPARATUS INCLUDING THE SAME - A pressure adjustment apparatus includes a storage tank storing a gas for the chamber with an outlet, a first supply line supplying the gas from an external line to the storage tank, a second supply line supplying the gas from the storage tank to the chamber, a discharge line discharging the gas from the chamber using the outlet of the chamber, and a controller controlling valves at the first, second, and discharge lines. The discharge line includes first and second valves connected to each other in parallel at an end portion of the outlet of the chamber, and a third valve connected to the end portion of the outlet of the chamber. The controller opens the first and second valves to discharge the gas from the chamber, and opens the third valve after a predetermined amount of time after the opening of the first and second valves. | 2022-06-30 |
20220208563 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - A substrate processing apparatus includes a spin chuck that holds a substrate, and a fluid nozzle disposed to face a principal surface of the substrate which is held by the spin chuck. The fluid nozzle includes a gas discharge port from which a gas is discharged radially from the center side of the principal surface of the substrate to the peripheral edge side, and a gas flow passage through which the gas is supplied to the gas discharge port, the gas flow passage having a tubular shape along an intersecting direction with respect to the principal surface of the substrate. The gas flow passage has a gas retaining portion whose flow passage cross-sectional area is larger than other portions of the gas flow passage, and a rectifying structure provided in a portion of the gas flow passage different from the gas retaining portion, the rectifying structure that rectifies a flow of the gas in the gas flow passage. | 2022-06-30 |
20220208564 | APPARATUS AND METHOD FOR TREATING SUBSTRATE - A substrate treating device includes a liquid treating chamber for liquid-treating a substrate therein, a drying chamber for dry-treating the liquid-treated substrate, a transfer device for transferring the substrate between the liquid treating chamber and the drying chamber, and a controller for controlling the liquid treating chamber and the transfer device. The transfer device includes a transfer robot having a hand for placing the substrate thereon, and a heating member for heating the substrate. The controller controls the transfer device such that the heating member of the transfer device heats a liquid on the substrate to a first temperature before the transfer device transfers the substrate taken out from the liquid treating chamber to the drying chamber. | 2022-06-30 |
20220208565 | APPARATUS AND METHOD FOR PROCESSING SUBSTRATE - A substrate processing apparatus includes a substrate cleaning unit cleaning a substrate, a substrate drying unit drying the substrate, and a transfer robot transferring the substrate between the substrate cleaning unit and the substrate drying unit. The substrate drying unit includes a substrate processing container having a substrate processing space accommodating the substrate, and the transfer robot includes a surface temperature measurement sensor measuring a surface temperature of the substrate processing container. | 2022-06-30 |
20220208566 | SUBSTRATE DRYING METHOD AND SUBSTRATE DRYING APPARATUS - A substrate processing method includes: a pressure increasing process of increasing an internal pressure of a process container to a processing pressure by supplying a process fluid into the process container; and after the pressure increasing process, a circulating process of supplying the process fluid from a second discharge part into the process container and discharging the process fluid in the process container from a fluid discharge part, while maintaining the internal pressure at the processing pressure, wherein the pressure increasing process includes: a first pressure increasing stage of increasing the internal pressure to a switching pressure by supplying the process fluid from a first discharge part into the process container; and after the first pressure increasing stage, a second pressure increasing stage of increasing the internal pressure from the switching pressure to the processing pressure by supplying the process fluid from the second discharge part into the process container. | 2022-06-30 |
20220208567 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - A substrate processing apparatus includes a processing vessel; and a processing fluid supply configured to supply a processing fluid in a supercritical state into the processing vessel. The processing fluid supply includes a fluid supply line; a cooling device provided in the fluid supply line, and configured to cool the processing fluid in a gas state to produce the processing fluid in a liquid state; a pump positioned downstream of the cooling device; a heating device positioned downstream of the pump, and configured to heat the processing fluid in the liquid state to generate the processing fluid in the supercritical state; a first flow rate adjuster positioned between the pump and the heating device, and configured to adjust a supply flow rate of the processing fluid supplied to the processing vessel; and a controller configured to control the first flow rate adjuster. | 2022-06-30 |
20220208568 | APPARATUS AND METHOD FOR SUPPLYING LIQUID - A liquid supply unit includes a tank having an inner space for storing the liquid, an inlet line for supplying the liquid from the liquid supply source to the inner space and having an inlet valve installed thereon, an outlet line for supplying the liquid from the tank to a nozzle or for recollecting the liquid to the tank and having an outlet valve installed thereon, a gas supply line for supplying a gas to the inner space and having a gas control valve installed thereon, an exhaust line for exhausting the inner space and having an exhaust valve installed thereon, a circulation line for circulating the liquid stored in the inner space, and a controller controlling the liquid supply unit so that the circulation line is pressurized while the liquid is supplied to the inner space. | 2022-06-30 |
20220208569 | APPARATUS FOR TREATING SUBSTRATE AND METHOD FOR TREATING SUBSTRATE - The inventive concept provides a substrate treating apparatus. According to the inventive concept, the substrate treating apparatus treats the substrate by supplying a treating liquid on a rotating substrate. The exhaust unit exhausting an atmosphere of an inner space comprises: a first exhaust port introducing the atmosphere of the inner space, a first exhaust line provided to exhaust an atmosphere introduced through the first exhaust port in a first direction and a second exhaust port introducing the atmosphere of the inner space, and a second exhaust line provided to exhaust an atmosphere introduced through the second exhaust port in a second direction. The controller controls the support unit so an exhaust direction inside of the first exhaust line and the second exhaust line become a forward direction with respect to a rotation direction of the substrate. | 2022-06-30 |
20220208570 | MULTIPLE SEMICONDUCTOR DIE CONTAINER LOAD PORT - A multiple die container load port may include a housing with an opening, and an elevator to accommodate a plurality of different sized die containers. The multiple die container load port may include a stage supported by the housing and moveable within the opening of the housing by the elevator. The stage may include one or more positioning mechanisms to facilitate positioning of the plurality of different sized die containers on the stage, and may include different portions movable by the elevator to accommodate the plurality of different sized die containers. The multiple die container load port may include a position sensor to identify one of the plurality of different sized die containers positioned on the stage. | 2022-06-30 |
20220208571 | HYPERBARIC SAW FOR SAWING PACKAGED DEVICES - In a described example, an apparatus includes: a process chamber configured for a pressure greater than one atmosphere, having a device chuck configured to support electronic devices that are mounted on package substrates and partially covered in mold compound, the electronic devices spaced from one another by saw streets; and a saw in the process chamber configured to cut through the mold compound and package substrates in the saw streets to separate the molded electronic devices one from another. | 2022-06-30 |
20220208572 | Workpiece Processing Apparatus with Thermal Processing Systems - A processing apparatus for a thermal treatment of a workpiece is presented. The processing apparatus includes a processing chamber, a workpiece support disposed within the processing chamber, a gas delivery system configured to flow one or more process gases into the processing chamber from the a first side of the processing chamber, one or more radiative heating sources disposed on the second side of the processing chamber, one or more dielectric windows disposed between the workpiece support and the one or more radiative heating sources, a rotation system configured to rotate the one or more radiative heating sources, and a workpiece temperature measurement system configured at a temperature measurement wavelength range to obtain a measurement indicative of a temperature of a back side of the workpiece. | 2022-06-30 |
20220208573 | TAPE MOUNTER - A tape mounter includes a frame delivery mechanism for delivering a ring frame, a wafer delivery mechanism for delivering a wafer, a tape affixing mechanism for affixing a dicing tape to a ring frame and a wafer and integrally combining the ring frame and the wafer with each other to turn them into a frame set, a frame cassette stage for placing a frame cassette thereon, a robot capable of removing a ring frame from the frame cassette placed on the frame cassette stage or storing the frame set into the frame cassette placed on the frame cassette stage, and a controller. | 2022-06-30 |
20220208574 | TRANSFER APPARATUS - A transfer apparatus includes a first vacuum transfer module; a first transfer robot disposed in the first vacuum transfer module and at least one ring. In addition, a second vacuum transfer module is provided; and a second transfer robot is disposed in the second vacuum transfer module. A tubular connecting module is disposed between the first vacuum transfer module and the second vacuum transfer module. Further, the first vacuum transfer module, the second vacuum transfer module and the tubular connecting module are arranged along a first direction, with the tubular connecting module having a first length in the first direction, and the first length is smaller than the diameter of the wafer. A wafer support is rotatably attached to the tubular connecting module and at least three ring supporting members outwardly extend from the wafer support to support the at least one ring. | 2022-06-30 |
20220208575 | FORELINE ASSEMBLY FOR QUAD STATION PROCESS MODULE - A foreline assembly for a quad station process module (QSM) is provided. In some examples, a foreline assembly comprises four inlets each connectable to a chamber port of a process module of the QSM and an outlet connectable directly or indirectly to a vacuum source. A first foreline bifurcation is disposed proximate the outlet of the foreline assembly. Two second bifurcations are each disposed between the first foreline bifurcation and a respective pair of the inlets. The first and second bifurcations divide the foreline assembly into three sections. A respective diameter of a foreline in each section increases stepwise at a respective bifurcation in a direction of gas flow from at least one of the inlets to the outlet of the foreline assembly and is constant within a respective section of the foreline assembly. | 2022-06-30 |
20220208576 | SUBSTRATE PROCESSING APPARATUS - A substrate processing apparatus includes one or more substrate processing modules; a vacuum transfer module connected to the one or more substrate processing modules; | 2022-06-30 |
20220208577 | MANIPULATOR FINGER, MANIPULATOR, AND METHOD OF OPERATING THE SAME - This application relates to a manipulator finger, a manipulator, and a method of operating the same. In an embodiment of this application, the manipulator finger includes: a finger; and one or more temperature measuring elements disposed in the finger and respectively connected to one or more temperature measuring contact points on a surface of the finger. The manipulator finger may be configured to monitor a temperature of a wafer in real time during delivery of the wafer. | 2022-06-30 |
20220208578 | TEMPERATURE CONTROL UNIT - A temperature control unit has a temperature control unit body, a temperature control part provided inside the temperature control unit body, which raises and lowers a surface temperature of the temperature control unit body on a side where a temperature control object is located, and a thin coating temperature measuring resistance part composed of a thermal sprayed coating. The thin coating temperature measuring resistance part is formed over a certain range in a surface on the side where the temperature control object is located, and which is provided inside the temperature control unit body on a side closer to the temperature control object than the temperature control part. The thin coating temperature measuring resistance part can accurately measure an average temperature of a temperature control surface. | 2022-06-30 |
20220208579 | SYNCHRONOUS SUBSTRATE TRANSPORT AND ELECTRICAL PROBING - A system for glass substrate inspection, such as flat patterned media, includes an air table that holds the glass substrate. The air table includes chucklets that emit gas as air bearings. A camera is disposed over the air table and moves in a direction across a width of a top surface of the glass substrate. An assembly includes a gripper and a probe bar configured to be transported under the camera. The gripper is configured to grip a bottom surface of the glass substrate opposite the top surface. The probe bar delivers driving signals to the glass substrate through a plurality of probe pins. | 2022-06-30 |
20220208580 | WAFER INSPECTION METHOD - A wafer inspection method includes acquiring an inspection image from an edge region of a wafer, generating a color profile of the inspection image in a radial direction of the wafer, detecting a side surface of a layer formed on the wafer based on a change in the color profile in a first direction from a side surface of the wafer toward a center of the wafer, and calculating a distance between the side surface of the layer and the side surface of the wafer. | 2022-06-30 |
20220208581 | CONTAMINATION CONTROL IN SEMICONDUCTOR MANUFACTURING SYSTEMS - The present disclosure relates to a contamination controlled semiconductor processing system. The contamination controlled semiconductor processing system includes a processing chamber, a contamination detection system, and a contamination removal system. The processing chamber is configured to process a wafer. The contamination detection system is configured to determine whether a contamination level on a surface of the door is greater than a baseline level. The contamination removal system is configured to remove contaminants from the surface of the door in response to the contamination level being greater than the baseline level. | 2022-06-30 |
20220208582 | REMOTE OPTIMIZATION OF PURGE FLOW RATES IN A CONTAINER - Optimizing purge flow parameters in a substrate container, includes streaming a purge working fluid into an interior of the substrate container, discharging the purge working fluid from the interior of the substrate container, and varying purge flow parameters of the purge working fluid for a predetermined period of time, detecting at least one environmental condition in the interior of the substrate container during the predetermined period of time, determining optimized purge flow parameters based on the varied purge flow parameters and the at least one detected environmental condition during the predetermined period of time, and adjusting the streaming and the discharging in accordance with the optimized purge flow parameters. The substrate container may include, for example, a front opening unified pod or a reticle pod. | 2022-06-30 |
20220208583 | Article Transport Vehicle - An article transport vehicle includes a travel body; a holding device that holds an article; and a lift device that is on the travel body, and that raises and lowers the holding device with respect to the travel body. The holding device includes: a connection portion connected to the lift device and an article support portion that supports the article; an elastic support mechanism that is between the article support portion and the connection portion, and that supports the article support portion against the connection portion while being elastic in a vertical direction, and a guide mechanism that guides the article support portion in the vertical direction with respect to the connection portion. The guide mechanism allows the article support portion to move parallel with the vertical direction with respect to the connection portion and restricts swinging of the article support portion with respect to the connection portion. | 2022-06-30 |
20220208584 | WAFER TRANSFER METHOD AND MECHANICAL ARM - This application relates to a wafer transfer method and a mechanical arm. The method includes: providing a first wafer to a finger portion front end of a mechanical arm; extending the mechanical arm to a first length to move the finger portion front end of the mechanical arm to a first processing position in a first processing chamber; placing the first wafer at the first processing position; contracting the mechanical arm to move the finger portion front end of the mechanical arm out of the first processing chamber; providing a second wafer to the finger portion front end of the mechanical arm; extending the mechanical arm to a second length to move the finger portion front end of the mechanical arm to a second processing position in the first processing chamber, wherein the second length is different from the first length; and placing the second wafer at the second processing position. | 2022-06-30 |
20220208585 | X-Y Stage - This invention provides an x-y stage includes linear motors, linkages coupled to the linear motors respectively, a decoupling member coupling to the linkages movable in x-y directions freely, and a table fastened to the decoupling member. Coils or armatures of the linear motors can be fastened to the wall of vacuum chamber, such that heats generated in the coils can be conducted outside the vacuum chamber directly through the wall of the chamber. Cables for the coils or armatures are also fastened to the wall of chamber, and particle issue generated by the movable cable in the vacuum chamber can be removed. | 2022-06-30 |
20220208586 | SUBSTRATE STORING AND ALIGNING APPARATUS IN SUBSTRATE BONDING EQUIPMENT FOR BONDING SUBSTRATES TO EACH OTHER - A substrate storing and aligning apparatus is proposed. The substrate storing and aligning apparatus is capable of efficiently using space in substrate bonding equipment. The substrate storing and aligning apparatus in the substrate bonding equipment for bonding substrates includes a front end buffer including a front end storing slot configured to temporarily store a substrate, and a front end opening configured such that a transfer robot is movable therethrough to transfer the substrate from the front end storing slot, and a front end aligner provided to be stacked on an upper portion of the front end buffer, and configured to rotate the substrate so as to align the substrate. | 2022-06-30 |
20220208587 | SUBSTRATE COOLING UNIT, SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM - A substrate cooling unit includes a substrate holding mechanism holding a substrate horizontally, a driver that raises and lowers the substrate holding mechanism, a cooling plate having a surface facing a surface of the substrate, a laser emitter disposed at one lateral end of a space in which the substrate is raised and lowered and that emits a laser beam distributed with a width in a direction in which the substrate holding mechanism is raised and lowered and parallel to the surface of the substrate. A laser receiver disposed at the other lateral end of the space and that acquires light receiving position specifying information indicating a position at which the laser beam is received in the direction in which the substrate holding mechanism is raised and lowered. A calculator that calculates a distance between the cooling plate and the substrate based on the light receiving position specifying information. | 2022-06-30 |
20220208588 | WAFER TRANSFER APPARATUS - A wafer transfer apparatus includes a holding plate having a holding surface adapted to be opposed to one side of a wafer, a suction holding portion provided so as to be exposed to the holding surface for holding the wafer under suction in a noncontact fashion, three or more restricting members for restricting the movement of the wafer in a direction parallel to the one side of the wafer, each restricting member having a roller portion rotatable about its axis, the roller portion being adapted to come into contacted with the peripheral edge of the wafer held under suction by the suction holding portion, and a moving unit connected to the holding plate for moving the holding plate to thereby transfer the wafer. At least one of the restricting members functions as a rotational drive portion for rotating the roller portion about its axis to thereby rotate the wafer. | 2022-06-30 |
20220208589 | SUBSTRATE GRIPPING APPARATUS AND LIQUID PROCESSING APPARATUS, AND SUBSTRATE PROCESSING EQUIPMENT INCLUDING SAME - An apparatus and a method of reducing the replacement cycle due to abrasion of chuck pins that support a lateral surface of a substrate are proposed. A substrate gripping apparatus for gripping the substrate in substrate processing equipment includes a chuck, a gear box configured to be movable with respect to the chuck, a rotation gear provided inside the gear box, chuck pins configured to be rotatable while being coupled to the rotation gear and to be brought into contact with a lateral surface of the substrate. According to the embodiment of the present disclosure, the substrate is configured such that the lateral surface thereof is supported by various positions of each of the chuck pins. Therefore, the life of the chuck pins can be improved and maintenance costs can be reduced. | 2022-06-30 |
20220208590 | SEMICONDUCTOR PROCESSING APPARATUS AND METHOD - This application relates to a semiconductor processing apparatus and method. In an embodiment of this application, the semiconductor processing apparatus includes: a wafer pocket provided with a lower electrode, where the lower electrode is coupled to a direct-current power supply; and an upper electrode disposed opposite to the wafer pocket, where the upper electrode is coupled to a radio frequency generator through a matching circuit, and is grounded through a low-pass filter. | 2022-06-30 |
20220208591 | Electrostatic Chuck Assembly for Plasma Processing Apparatus - An electrostatic chuck including a workpiece support surface, clamping layer, heating layer, thermal control system, and sealing band is disclosed. The sealing band surrounds an outer perimeter of the electrostatic chuck including at least a portion of the workpiece surface. The sealing band has a width greater than about 3 millimeters (mm) up to about 10 mm. Plasma processing apparatuses and systems incorporating the electrostatic chuck are also provided. | 2022-06-30 |
20220208592 | ELECTROSTATIC CHUCK PREPARED BY ADDITIVE MANUFACTURING, AND RELATED METHODS AND STRUCTURES - Described are electrostatic chucks that are useful to support a workpiece during a step of processing the workpiece, and electrostatic chuck base components prepared by an additive manufacturing technique. | 2022-06-30 |
20220208593 | ELECTROSTATIC CHUCK AND SUBSTRATE FIXING DEVICE - An electrostatic chuck includes a base body having a placement surface on which a suction target object is placed, a thermal diffusion layer directly formed on a surface of the base body opposite to the placement surface, an insulation layer arranged to be in contact with the thermal diffusion, on a side of the thermal diffusion layer opposite to the base body, and a heat generating body embedded in the insulation layer, The thermal diffusion layer is formed of a material having a thermal conductivity higher than the insulation layer. | 2022-06-30 |
20220208594 | VARIOUS 3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH MEMORY CELLS - A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one first metal layer disposed above the plurality of first transistors; a second metal layer disposed above the at least one first metal layer; a plurality of second transistors disposed atop the second metal layer; a plurality of third transistors disposed atop the plurality of second transistors; a plurality of fourth transistors disposed atop the plurality of third transistors; a third metal layer disposed above the plurality of fourth transistors; a fourth metal layer disposed above the third metal layer; and a plurality of connecting metal paths from the fourth metal layer or the third metal layer to the second metal layer, where the device includes an array of memory cells, and where at least one of the memory cells includes one of the plurality of third transistors. | 2022-06-30 |
20220208595 | WAFER SUPPORT PIN LIFTING DEVICE - A wafer support pin lifting device includes a support plate, a slide block and a lifting pole. The support plate is for supporting multiple support pins. The slide block is slidably connected to an inner wall of a cavity so that the slide block slides relative to the cavity. The lifting pole has a first end, a second end and a third end. The first end is connected to the support plate, the second end is pivotally connected to the slide block, and the third end is connected to an actuator. With the pivotal connection between the second end of the lifting pole and the slide block, the lifting pole approaching the high position causes the support plate to be approximately horizontal, and the lifting pole approaching the low position causes the support plate to be tilted. | 2022-06-30 |
20220208596 | CHUCK PIN ASSEMBLY, AND SUBSTRATE HOLDING APPARATUS AND LIQUID PROCESSING APPARATUS INCLUDING SAME - A chuck pin assembly includes a body member provided on a circumferential portion of a chuck supporting a substrate and configured to be movable with respect to the chuck, a grip member gripping a lateral portion of the substrate, and a rotational connection member rotatably coupling the grip member to the body member. As the grip member is rotatable, it is possible to prevent the chuck pin from being worn at a specific portion which contacts the substrate, and to improve the life of the chuck pin. | 2022-06-30 |
20220208597 | SEMICONDUCTOR HEAT TREATMENT MEMBER AND MANUFACTURING METHOD THEREOF - The present invention relates to a semiconductor heat treatment member for holding a semiconductor wafer, including a base member a surface of which is covered with an oxide film, the base member including a silicon carbide, in which a surface of a wafer holding portion to be in contact with a semiconductor wafer has an arithmetic average roughness Ra of smaller than or equal to 0.3 μm and an element average length RSm of shorter than or equal to 40 μm. | 2022-06-30 |
20220208598 | PROTECTION MECHANISM AND METHOD FOR PROTECTING WAFER AND PIN - This application provides a protection mechanism and a method for protecting a wafer and a pin. The protection mechanism includes: a drive; a linear unit, connected to the drive, so as to cause a pin to eject a wafer under the action of the drive; a torsion meter, configured to measure a torque of the protection mechanism in a process of ejecting the wafer by the pin; and a control module, configured to receive the torque measured by the torsion meter, and compare the torque with a predetermined value. The torsion meter is disposed between the drive and the linear unit. The to protection mechanism can effectively measure, in real time, a torque generated in a process of ejecting the wafer, and can determine, according to the torque, whether an abnormality occurs in the ejection process, so that an accident such as wafer fragmentation or pin fracturing can be effectively prevented. | 2022-06-30 |
20220208599 | BULK WAFER SWITCH ISOLATION - The present disclosure relates to semiconductor structures and, more particularly, to bulk wafer switch isolation structures and methods of manufacture. The structure includes: a bulk substrate material; an active region on the bulk substrate material; an inactive region adjacent to the active region; and an amorphous material covering the bulk substrate material in the inactive region, which is adjacent to the active region. | 2022-06-30 |
20220208600 | METHOD OF MAKING A THREE-DIMENSIONAL MEMORY DEVICE USING COMPOSITE HARD MASKS FOR FORMATION OF DEEP VIA OPENINGS - A source-level semiconductor layer and an alternating stack of first material layers and second material layers is formed above a substrate. A hard mask layer is formed over the alternating stack, and is subsequently patterned to provide a pattern of cavities therethrough. Via openings are formed through the alternating stack by performing an anisotropic etch process. A cladding liner is formed on sidewalls of the cavities in the hard mask layer and on a top surface of the hard mask layer. The via openings are vertically extended at least through the source-level semiconductor layer by performing a second anisotropic etch process employing a combination of the cladding liner and the hard mask layer as an etch mask. | 2022-06-30 |
20220208601 | TRENCH SHIELD ISOLATION LAYER - A semiconductor device has a semiconductor material in a substrate. The semiconductor device has an MOS transistor. A trench in the substrate extends from a top surface of the substrate) into the semiconductor material. A shield is disposed in the trench. The shield has a contact portion which extends toward a top surface of the trench. A gate of the MOS transistor is disposed in the trench over the shield. The gate is electrically isolated from the shield. The gate is electrically isolated from the contact portion of the shield by a shield isolation layer which covers an angled surface of the contact portion extending toward the top of the trench. Methods of forming the semiconductor device are disclosed. | 2022-06-30 |
20220208602 | ARCHITECTURE OF THREE-DIMENSIONAL MEMORY DEVICE AND METHODS REGARDING THE SAME - Architectures of 3D memory arrays, systems, and methods regarding the same are described. An array may include a substrate arranged with conductive contacts in a geometric pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. After etching material, a sacrificial layer may be deposited in a trench that forms a serpentine shape. Portions of the sacrificial layer may be removed to form openings, into which cell material is deposited. An insulative material may be formed in contact with the sacrificial layer. The conductive pillars extend substantially perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. A chalcogenide material may be formed in the recesses partially around the conductive pillars. | 2022-06-30 |
20220208603 | METHOD FOR FORMING SEMICONDUCTOR DEVICE WITH MULTI-LAYER ETCH STOP STRUCTURE - A method for forming a semiconductor device structure is provided. The method includes successively forming a first multi-layer etch stop structure and an insulating layer over a first conductive feature. The insulating layer and the first multi-layer etch stop structure are successively etched to form an opening substantially aligned to the first conductive feature. A second conductive feature is formed in the opening. The formation of the first multi-layer etch stop structure and the second multi-layer etch stop structure includes forming a first metal-containing dielectric layer, forming a silicon-containing dielectric layer over the first metal-containing dielectric layer, and forming a second metal-containing dielectric layer over the silicon-containing dielectric layer. The second metal-containing dielectric layer has a material that is different from the material of the first metal-containing dielectric layer. | 2022-06-30 |
20220208604 | PROTECTION OF SEED LAYERS DURING ELECTRODEPOSITION OF METALS IN SEMICONDUCTOR DEVICE MANUFACTURING - A protective layer is formed over a copper seed layer on a semiconductor substrate prior to electroplating. The protective layer is capable of protecting the copper seed layer from oxidation and from dissolution in an electrolyte during initial phases of electroplating. The protective layer, in some embodiments, prevents the copper seed layer from contacting atmosphere, and from being oxidized by atmospheric oxygen and/or moisture. The protective layer contains a metal that is less noble than copper (e.g., cobalt), where the metal can be in an oxidized form that is readily soluble in a plating liquid. In one embodiment a protective cobalt layer is formed by depositing cobalt metal by chemical vapor deposition over copper seed layer without exposing the copper seed layer to atmosphere, followed by subsequent oxidation of cobalt to cobalt oxide that occurs after the substrate is exposed to atmosphere. The resulting protective layer is dissolved during electroplating. | 2022-06-30 |
20220208605 | METHOD OF FORMING A CONTACT PLUG IN A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In a method of forming a contact plug in a semiconductor integrated circuit device, the contact plug may be formed in a process chamber of a substrate-processing apparatus. The process chamber may have a process space. The process chamber may include a substrate supporter placed in a lower region of the process space to support a semiconductor substrate, and a gas injector placed in an upper region of the process space to inject a gas to the semiconductor substrate. An insulating interlayer having a contact hole may be formed on the semiconductor substrate loaded into the process space. A nucleation layer may be formed on an inner surface of the contact hole and an upper surface of the insulating interlayer. A semi-bulk layer may be formed on the nucleation layer in a lower region of the contact hole. An inhibiting layer may be formed on the semi-bulk layer and the exposed nucleation layer. A main-bulk layer may be formed on the semi-bulk layer to fill the contact hole with the main-bulk layer. | 2022-06-30 |
20220208606 | METHODS FOR FORMING CONDUCTIVE VIAS, AND ASSOCIATED DEVICES AND SYSTEMS - Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion. | 2022-06-30 |
20220208607 | 3D Integrated Circuit and Methods of Forming the Same - An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer. | 2022-06-30 |
20220208608 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Provided is a semiconductor device that includes a cylindrical insulating film, a front surface side pad, a conductor layer, and a back surface side pad. The cylindrical insulating film is configured in a cylindrical shape penetrating a semiconductor substrate. The front surface side pad is formed adjacent to a front surface of the semiconductor substrate inside the cylindrical insulating film. The conductor layer is arranged adjacent to the front surface side pad and an inner side of the cylindrical insulating film after removing the semiconductor substrate inside the cylindrical insulating film adjacent to the front surface side pad. The back surface side pad is arranged on a back surface of the semiconductor substrate and is connected to the front surface side pad via the conductor layer. | 2022-06-30 |
20220208609 | SYSTEMS AND METHODS FOR MITIGATING CRACK PROPAGATION IN SEMICONDUCTOR DIE MANUFACTURING - A method for mitigating crack propagation during manufacture of semiconductor dies, and associated systems and methods are disclosed herein. The method includes forming holes into a first side of a wafer substrate opposite a second side. The wafer substrate has active components at the second side. Each hole extends from the first side towards the second side an extend to an intermediate depth within the wafer substrate such that a bottom of the holes is spaced vertically apart from the active components on the second side. The holes are configured to inhibit cracks in the wafer substrate from propagating longitudinally across the wafer substrate. The method also includes backgrinding the first side of the wafer substrate to thin the wafer substrate after forming the holes. The method also includes dicing the wafer substrate after backgrinding to separate individual semiconductor dies from each other. | 2022-06-30 |
20220208610 | SUBSTRATE DICING METHOD, METHOD OF FABRICATING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR CHIP FABRICATED BY THEM - According to an embodiment of inventive concepts, a substrate dicing method may include forming reformed patterns in a substrate using a laser beam, grinding a bottom surface of the substrate to thin the substrate, and expanding the substrate to divide the substrate into a plurality of semiconductor chips. The forming of the reformed patterns may include forming a first reformed pattern in the substrate and providing an edge focused beam to a region crossing the first reformed pattern to form a second reformed pattern in contact with the first reformed pattern. | 2022-06-30 |
20220208611 | Semiconductor Structure and Forming Method Thereof - The present application relates to a semiconductor structure and its forming method. The semiconductor structure comprises a substrate; a first transistor that includes a first channel disposed within the substrate, and a first end disposed at surface of the substrate, the first end being adapted to connect with a first-type storage cell; a second transistor that includes a second channel disposed within the substrate, and a second end disposed at surface of the substrate, the second end being adapted to connect with a second-type storage cell, the second channel having a length greater than length of the first channel. The present application enables fabrication techniques of the first transistor and the second transistor compatible. Moreover, the present application is conducive to enhancing integration density of the storage cells of the first transistor and/or the second transistor in the memory lays foundation for enlarging the fields of application of the memory. | 2022-06-30 |
20220208612 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - A method for forming a semiconductor device. A substrate having a first region and a second region surrounding the first region is provided. The first region includes a first active area and a first gate. A dummy pattern is disposed on the substrate within the second region around a perimeter of the first region. A resist pattern masks the second region and includes an opening that exposes the first region. An ion implantation process is performed to implant dopants through the opening into the first active area not covered by the first gate within the first region, thereby forming doped regions in the first active area. A resist stripping process is performed to remove the resist pattern by using a sulfuric acid-hydrogen peroxide mixture (SPM) solution at a temperature that is higher than or equal to 120˜190 degrees Celsius. The substrate is subjected to a cleaning process. | 2022-06-30 |
20220208613 | FinFETs With Epitaxy Regions Having Mixed Wavy and Non-Wavy Portions - A method includes forming a first fin-group having has a plurality of semiconductor fins, and a second fin-group. The plurality of semiconductor fins include a first semiconductor fin, which is farthest from the second fin-group among the first fin-group, a second semiconductor fin, and a third semiconductor fin, which is closest to the second fin-group among the first fin-group. The method further includes performing an epitaxy process to form an epitaxy region based on the plurality of semiconductor fins. The epitaxy region includes a first portion and a second portion. The first portion is in middle between the first semiconductor fin and the second semiconductor fin. The first portion has a first top surface. The second portion is in middle between the second semiconductor fin and the third semiconductor fin. The second portion has a second top surface lower than the first top surface. | 2022-06-30 |
20220208614 | Semiconductor Device and Method of Forming the Same - An embodiment method includes: forming a dielectric-containing substrate over a semiconductor substrate; forming a stack of first semiconductor layers and second semiconductor layers over the dielectric-containing substrate, wherein the first semiconductor layers and the second semiconductor layers have different material compositions and alternate with one another within the stack; patterning the first semiconductor layer and the second semiconductor layers into a fin structure such that the fin structure includes sacrificial layers including the second semiconductor layers and channel layers including the first semiconductor layers; forming source/drain features adjacent to the sacrificial layers and the channel layers; removing the sacrificial layers of the fin structure so that the channel layers of the fin structure are exposed; and forming a gate structure around the exposed channel layers, wherein the dielectric-containing substrate is interposed between the gate structure and the semiconductor substrate. | 2022-06-30 |
20220208615 | Dielectric Fins With Different Dielectric Constants and Sizes in Different Regions of a Semiconductor Device - A semiconductor device includes. A first epi-layer and a second epi-layer are each located in a first region of the semiconductor device. A first dielectric fin is located between the first epi-layer and the second epi-layer. The first dielectric fin has a first dielectric constant. A third epi-layer and a fourth epi-layer are each located in a second region of the semiconductor device. A second dielectric fin is located between the third epi-layer and the fourth epi-layer. The second dielectric fin has a second dielectric constant that is less than the first dielectric constant. | 2022-06-30 |
20220208616 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES BY ETCHING ACTIVE FINS USING ETCHING MASKS - In a method of manufacturing a semiconductor device, first to third active fins are formed on a substrate. Each of the first to third active fins extends in a first direction, and the second active fin, the first active fin, and the third active fin are disposed in this order in a second direction crossing the first direction. The second active fin is removed using a first etching mask covering the first and third active fins. The third active fin is removed using a second etching mask covering the first active fin and a portion of the substrate from which the second active fin is removed. A first gate structure is formed on the first active fin. A first source/drain layer is formed on a portion of the first active fin adjacent the first gate structure. | 2022-06-30 |
20220208617 | DETECTION METHOD OF METAL IMPURITY IN WAFER - The present application provides a detection method of metal impurity in wafer. The method comprises conducting a medium temperature thermal treatment for a first predicted time period to the wafer, cooling the wafer and conducting a low temperature thermal treatment for a second predicted time period, cooling the wafer to ambient temperature; providing a liquid of vapor phase decomposition on the wafer to collect metal impurities; atomizing the liquid containing the collected metal impurities, conducting an inductively coupled plasma mass spectrometry analysis and obtaining concentrations of the metal impurities. The present application applies the combination of various thermal treatment without an interrupt of cooling to ambient temperature to contemplate diffusions of various metal impurities to the wafer surface. Accordingly, the detection of metal impurities can be conducted with reduced time cost and enhanced efficiency. | 2022-06-30 |
20220208618 | OPTICAL INSPECTION APPARATUS IN SEMICONDUCTOR PROCESS SYSTEM - The present invention discloses an optical detection apparatus for defining a detection surface on a carrier unit for a wafer in a semiconductor manufacturing process so as to obtain a corresponding detection image, wherein a vertical movement path for another device to move is defined above the carrier unit. The optical detection apparatus includes a support, and an imaging device disposed on the support and configured to be non-interfering with the movement path. The imaging device includes a lens group, an image capturing portion and a moving base. With the moving base, the photosensitive element of the image capturing portion is allowed to move horizontally relative to the lens group, and the imaging position can be adjusted, preventing image deformation or a reduced resolution easily caused by capturing at an oblique angle. Thus, the optical detection apparatus resolves complications of additionally mounting an optical detection apparatus in an optical detection environment within a narrow space. | 2022-06-30 |
20220208619 | METHODS FOR IMPLANTING SEMICONDUCTOR SUBSTRATES - Systems for implanting semiconductor structures with ions are disclosed. The semiconductor structure is positioned on a heatsink and ions are implanted through a front surface of the semiconductor structure to form a damage region in the semiconductor structure. A parameter related to the coefficient of friction of the heatsink is measured. The parameter is compared to a baseline range. | 2022-06-30 |
20220208620 | SEMICONDUCTOR DEVICE MANUFACTURE WITH IN-LINE HOTSPOT DETECTION - Controlling semiconductor device manufacture by acquiring training scatterometric signatures collected at training locations on training semiconductor wafers and corresponding to locations within a predefined design of a training semiconductor device, the training signatures collected after predefined processing steps during manufacture of the device on the training wafers, acquiring manufacturing outcome data associated with the training locations, training a prediction model using the training signatures and the manufacturing outcome data, and applying the prediction model to a candidate scatterometric signature to predict a manufacturing outcome, the candidate signature collected at a candidate location on a candidate semiconductor wafer, the candidate location corresponding to a location within the same predefined design of a candidate semiconductor device, the candidate signature collected after any of the processing steps during manufacture of the candidate device on the candidate wafer. | 2022-06-30 |
20220208621 | Asymmetry Correction Via Oriented Wafer Loading - A method for chemical mechanical polishing includes receiving an angular removal profile for a carrier head and an angular thickness profile of a substrate. Prior to polishing the substrate, a desired angle of the carrier head relative to the substrate is selected for loading the substrate into the carrier head. Selecting the desired angle is performed based on a comparison of the angular removal profile for the carrier head and the angular thickness profile of the substrate to reduce angular non-uniformity in polishing. The carrier head is rotated to receive the substrate at the desired angle, the substrate is transferred to the carrier head and loaded in the carrier head with the carrier head at the desired angle relative to the substrate, and the substrate is polished. | 2022-06-30 |
20220208622 | SEMICONDUCTOR PACKAGE, RESIN MOLDED PRODUCT, AND METHOD OF MOLDING RESIN MOLDED PRODUCT - A semiconductor package includes a flat plate-shaped terminal integrally formed with a housing portion for a semiconductor chip and a rod-shaped terminal pin that penetrates through a through-hole of the plate-shaped terminal. On a surface of the plate-shaped terminal, a resin guide portion for guiding the terminal pin to the through-hole of the plate-shaped terminal is provided. The resin guide portion is a portion of the housing portion and has a through-hole that is continuous with the through-hole of the plate-shaped terminal. During assembly of the semiconductor package, the terminal pin is inserted into the through-hole of the plate-shaped terminal, via the through-hole of the resin guide portion. A sidewall of the through-hole of the resin guide portion and a sidewall of the through-hole of the plate-shaped terminal have a same slope and form a single continuous surface; a border between the through-hole of the resin guide portion and the through-hole of the plate-shaped terminal is free of any step. | 2022-06-30 |
20220208623 | SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel. | 2022-06-30 |
20220208624 | SEMICONDUCTOR PACKAGE INCLUDING DUAL STIFFENER - A semiconductor package includes; a dual stiffener including an upper stiffener and a lower stiffener, an upper package including an upper package substrate, a semiconductor chip centrally mounted on an upper surface of the upper package substrate, and the upper stiffener disposed along an outer edge of the upper package substrate, and a lower package substrate that centrally mounts the upper package and includes the lower stiffener disposed on an upper surface of the lower package substrate to surround the upper package substrate. | 2022-06-30 |
20220208625 | SEMICONDUCTOR ASSEMBLIES WITH FLOW CONTROLLER TO MITIGATE INGRESSION OF MOLD MATERIAL - Semiconductor devices having flow controllers configured to reduce mitigation of mold material between stacked layers, and associated systems and methods, are disclosed herein. In some embodiments, the semiconductor device includes a package substrate that has first and second surfaces. First and second die stacks are formed on the first surface and are adjacent to each other. A portion of the first surface extends between the first and second die stacks. A layer of material is adhered to top surfaces of the first and second die stacks and extends at a distance above the package substrate to form a tunnel between the layer of material, opposing sidewalls of the die stacks, and the package substrate. The semiconductor device further includes a flow controller that is adhered to at least a portion of the first surface inside the tunnel that reduces a cross-sectional surface area of at least a portion of the tunnel. | 2022-06-30 |
20220208626 | MODULE - A module includes a substrate, a first component, and a first sealing resin layer. The substrate includes a first principal surface. The first component is mounted on the first principal surface. The first sealing resin layer contains a filler containing an inorganic oxide as a main component. The first sealing resin layer is provided on the first principal surface. The first sealing resin layer seals the first component. A marking portion is provided on a surface of the first sealing resin layer on a side opposite to the substrate. In the first sealing resin layer, the content rate of the filler is smaller in a second portion on the side opposite to the substrate than in a first portion on the substrate. | 2022-06-30 |