26th week of 2022 patent applcation highlights part 49 |
Patent application number | Title | Published |
20220206724 | Printer - The printer ( | 2022-06-30 |
20220206725 | PROGRAMMABLE REDACTION FOR SECURE UI, REPORTS, SCANS, AND PRINTS - An exemplary apparatus includes a processor, a printing device, a user interface, and an input/output device. The printing device is in communication with the processor. The user interface is in communication with the processor. The input/output device is in communication with the processor and with a computerized network external to the apparatus. The processor is adapted to maintain a general lexicon of mask words. The processor is adapted to provide, through the user interface and the computerized network, options to change the mask words in the general lexicon to create a local lexicon. The processor is adapted to redact the mask words in the local lexicon from at least one of: printed items; items displayed on the user interface; and items provided to the computerized network through the input/output device. | 2022-06-30 |
20220206726 | OUTPUT SYSTEM, SYSTEM, AND OUTPUT METHOD - An output system, a system, and an output method. The output system communicates with an output apparatus and an information processing apparatus, and transmits, in response to a request from the output apparatus for electronic data including source identification information received from the information processing apparatus, electronic data associated with a user identified based on the source identification information to the output apparatus. | 2022-06-30 |
20220206727 | NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM, AND PRINTING SYSTEM - A supporting program causes a computer of an information processing device to display a setting screen for receiving an input operation of print settings, and acquire sheet information representing information of a sheet a printer uses for printing. Further, when there is a print instruction output from an application program and instructing a general-use printing program implemented, in advance, in an operating system, to perform printing of an image, the computer performs acquiring sheet information included in the print settings and determining suitability of a sheet by comparing the sheet information acquired from the printer with the sheet information of the print settings. The computer displays a warning message for a user when it is determined that the sheet is unsuitable. | 2022-06-30 |
20220206728 | MANAGING UNRESOLVED JOBS OF DEVICES WITH CLOUD SERVER - An example operation method includes receiving unresolved job information about a job, requested by user identification information, from a first device, storing the unresolved job information in user data of the user identification information, receiving the user identification information from a second device, from the second device, and providing the unresolved job information stored in the user data to the second device. | 2022-06-30 |
20220206729 | IMAGE PROCESSING APPARATUS, DISPLAY CONTROL METHOD, AND COMPUTER-READABLE STORAGE MEDIUM FOR STORING PROGRAM - An image processing apparatus comprising a display control unit configured to, in a case where there is an item in which a content has not been set in a plurality of items of job information, decide for each history data of a plurality of jobs an item to be used for displaying a list of execution histories of the plurality of jobs and, based on a content set for the decided item, control the display unit so as to display the list of execution histories of the plurality of jobs. | 2022-06-30 |
20220206730 | IMAGE PROCESSING APPARATUS, METHOD, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM FOR STORING PROGRAM - A first storage unit, in a case of starting an execution of a job, stores job information in a first non-volatile memory; and a second storage unit stores, in a second non-volatile memory that, a consumables usage amount that changes over a course of the execution of the job. When the execution of the job does not successfully end due to an error of the image processing apparatus, after recovering from the error, a job log including a job execution result up until an occurrence of the error is generated using the job information stored in the first non-volatile memory and the consumables usage amount stored in the second non-volatile memory. | 2022-06-30 |
20220206731 | PRINTER AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM STORING COMPUTER-READABLE INSTRUCTIONS FOR PRINTER - A printer may include a controller configured to: in a case where a predetermined instruction is obtained from a user under a situation where a service state of the printer for receiving a print job providing service from a server is a disabled state, shift the service state from the disabled state to an enabled state; in a case where a registration instruction to register printer information related to the printer in the server is obtained, send the printer information to the server; in a case where the registration instruction is obtained under the situation where the service state is the disabled state, shift the service state from the disabled state to the enabled state without obtaining the predetermined instruction from the user. | 2022-06-30 |
20220206732 | IMAGE PROCESSING DEVICE AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM STORING COMPUTER-READABLE INSTRUCTIONS FOR IMAGE PROCESSING DEVICE - An image processing device may include a controller configured to, in a case where a disabling instruction to cause a service state to shift to a disabled state is obtained under a situation where the service state is an enabled state, shift the service state from the enabled state to the disabled state, and in the case where the disabling instruction is obtained under the situation where the service state is the enabled state, send a first event deletion instruction to a server. The first event deletion instruction may be an instruction to delete, from an event which is to be notified to the image processing device, an acceptance of a job sending request by the server. | 2022-06-30 |
20220206733 | ELECTRONIC DEVICE - The disclosure provides an electronic device including a display and a processor circuit. The display device may include a first display region and a second display region. The processor circuit may include a first port and a second port. The processor circuit receives a data signal through the first port and generates a first image signal for display in the first display region. The processor circuit receives a second image signal through the second port and displays the second image signal in the second display region. | 2022-06-30 |
20220206734 | CONTROL AND DISPLAY DEVICE, IN PARTICULAR FOR A VEHICLE - A control and display device for a vehicle includes a control element and an associated display area. In the display area are superimposed: a first layer that is opaque except for a translucent complex pictogram, the complex pictogram combining two separate elementary pictograms; two separate filtering areas, each filtering area having the shape of a corresponding single elementary pictogram, each filtering area transmitting wavelengths within a respective range, the respective ranges of wavelengths being disjoint; and a light source suitable for emitting within the respective different ranges of wavelengths, concomitantly or alternately. The two filtering areas are positioned between the light source and the complex pictogram on the opaque layer. | 2022-06-30 |
20220206735 | Display Method for Side Area of Screen and Electronic Device - A display method for a side area of a screen and an electronic device, the device including a first display, wherein the first display comprises at least a main display area and at least one side display area, wherein the main display area and the at least one side display area are located on different planes, and wherein the main display area and the at least one side display area are configured to display an output of a first application, a processor, and a non-transitory computer readable medium storing a program for execution by the processor, the program including instructions to cause, in response to a first task of the first application being triggered, the at least one side display area to display at least one dynamic interface associated with the first task. | 2022-06-30 |
20220206736 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING SYSTEM, AND NON-TRANSITORY COMPUTER READABLE MEDIUM - An information processing apparatus includes: a display that displays a virtual screen superimposed on real space; and a processor configured to, instead of causing a content of a screen to be displayed on a display screen of an external apparatus, cause the content to be displayed as the virtual screen superimposed on the display screen. | 2022-06-30 |
20220206737 | METHOD AND APPARATUS FOR DISPLAYING MULTIPLE DEVICES ON SHARED SCREEN - A system and method is disclosed that allows multiple casting devices to work together to populate a large display screen according to the subject matter disclosed herein. The system includes a receiving device that includes two or more screen-cast receivers and a controller. Each screen-cast receiver receives from a corresponding casting device at least a portion of a frame of original content of the corresponding casting device generated in a native resolution of the corresponding casting device. The controller synchronizes each received portion of the frame of the original content of the corresponding casting device to form a video output signal that comprises a combination of each received portion, in addition to any internally generated content derived by the receiving display. A casting device may be a smartphone, a tablet, or a computing device, such as a laptop computer. | 2022-06-30 |
20220206738 | SELECTING AN AUDIO TRACK IN ASSOCIATION WITH MULTI-VIDEO CLIP CAPTURE - Aspects of the present disclosure involve a system comprising a computer-readable storage medium storing a program and method for providing audio with captured video clips. The program and method provide for displaying, by a messaging application, a capture user interface for capturing video; providing a camera mode selection element which is selectable to switch between a first camera mode for capturing a single video clip and a second camera mode for capturing multiple video clips, to generate a media content item; providing an audio selection element which is selectable to select an audio track for the media content item; receiving, via the camera mode selection element, first user input selecting the second camera mode; receiving, via the audio selection element, second user input selecting the audio track; and providing for capturing multiple video clips in association with the selected audio track for generating the media content item. | 2022-06-30 |
20220206739 | METHOD TO MUTE AND UNMUTE A MICROPHONE SIGNAL - A method for muting and unmuting a microphone is provided. The method includes providing a processor, receiving an input microphone signal, measuring the input microphone signal for a loudness level at a sampling rate, calculating a mute threshold level, checking if the loudness level is higher than or equal to the mute threshold level, and resetting a mute delay timer upon determining that the loudness level is higher than or equal to the mute threshold level and obtaining the input microphone signal, or checking if the mute delay timer is running upon determining that the loudness level is not higher than or equal to the mute threshold level and attenuating the input microphone signal if the mute delay timer is not running or obtaining the input microphone signal if the mute delay timer is still running, and writing the input microphone signal or attenuated input microphone signal to an output buffer. | 2022-06-30 |
20220206740 | ACOUSTIC DEVICE AND MUSIC PIECE REPRODUCTION PROGRAM - An acoustic device includes: a music player that is capable of simultaneously playing a plurality of music pieces of which music piece data includes specific playback positions set therefor; a playback speed adjusting section configured to adjust a playback speed of each of the music pieces; a music piece switching section configured to execute switching from a first music piece being played by the music player to a second music piece; and a playback position adjusting section configured to execute adjustment such that the specific playback position of the second music piece is aligned on a time axis with the specific playback position of the first music piece being played at a playback speed adjusted by the playback speed adjusting section. | 2022-06-30 |
20220206741 | VOLUME ADJUSTMENT METHOD AND ELECTRONIC DEVICE - A volume adjustment method and an electronic device are provided. The method is applied to an electronic device having a curved screen with the left side and the right side both being arc shaped. The method includes: receiving a first operation of a user in a first side area of the curved screen, where the first side area is on either the left side or the right side; displaying first prompt information at an operation position corresponding to the first operation; and increasing the volume in response to a second operation when the second operation of the user on the first prompt identifier is detected, or decreasing the volume in response to a third operation when the third operation of the user on the second prompt identifier is detected. | 2022-06-30 |
20220206742 | AGENT DISPLAY METHOD, NON-TRANSITORY COMPUTER READABLE MEDIUM, AND AGENT DISPLAY SYSTEM - The present disclosure provides an agent display method and the like that reduces the trouble of a user confirming an answer (or answers) while increasing the possibility of presenting an answer (or answers) of high value to the user without omission. An agent display method for simultaneously displaying a plurality of agents each configured to respond to a speech text of a user, the agent display method including: an answer selection step of selecting the answer text of each of the plurality of agents to the speech text of the user; and an agent display step of displaying a screen including the plurality of agents, in which the agent display step includes displaying the agent that the user should check first among the plurality of agents in a more emphasized form than those of the agents other than the agent that the user should check first. | 2022-06-30 |
20220206743 | INSTRUCTIONS TO CONVERT FROM FP16 TO BF8 - Techniques for converting FP16 to BF8 using bias are described. An exemplary embodiment utilizes decoder circuitry to decode a single instruction, the single instruction to include one or more fields to identify a first source operand, one or more fields to identify a second source operand, one or more fields to identify a source/destination operand, and one or more fields for an opcode, wherein the opcode is to indicate that execution circuitry is to convert packed half-precision data from the identified first and second sources to packed bfloat8 data using bias terms from the identified source/destination operand and store the packed bfloat8 data into corresponding data element positions of the identified source/destination operand; and execution circuitry to execute the decoded instruction according to the opcode to convert packed half-precision data from the identified first and second sources to packed bfloat8 data using bias terms from the identified source/destination operand and store the packed bfloat8 data into corresponding data element positions of the identified source/destination operand. | 2022-06-30 |
20220206744 | CONVERSION APPARATUS, CONVERSION METHOD AND PROGRAM - A conversion apparatus includes: a determination unit configured to, using a numeric value of an amount of a given type as input, determine a conversion method to be applied to the numeric value among multiple conversion methods based on the type of the amount and the size of the numeric value; a conversion unit configured to convert the numeric value into a relative value obtained based on a predetermined reference, using the conversion method determined by the determination unit; and an output unit configured to output a result of applying the value to a predetermined template, and thereby the conversion apparatus generates an expression that is easy to understand. | 2022-06-30 |
20220206745 | RELATIONSHIP ANALYSIS UTILIZING BIOFEEDBACK INFORMATION - Systems, methods, and computer software are disclosed for determining group dynamics. This can include receiving input data related to a particular group and determining, by a machine learning algorithm, a quantified group dynamic for the particular group. The machine learning algorithm can be trained with at least group information, user information, sensor data, and subjective evaluation data. A client device can generate an electronic indication of the quantified group dynamic. | 2022-06-30 |
20220206746 | SORTING DEVICE, SELECTING SYSTEM, SORTING METHOD, AND NONTRANSITORY COMPUTER READABLE MEDIUM - An object is to provide a sorting device, a selecting system, a sorting method, and a program capable of preventing a decrease in processing speed and an increase in the number of processing steps. The sorting device includes a rank computation device ( | 2022-06-30 |
20220206747 | Efficient Dual-path Floating-Point Arithmetic Operators - Systems and methods related to performing arithmetic operations on floating-point numbers. Floating-point arithmetic circuitry is configured to receive two floating-point numbers. The floating-point arithmetic circuitry includes a first path configured to perform a first operation on the two floating-point numbers based at least in part on a difference in size between the two floating-point numbers. The floating-point arithmetic circuitry includes a second path configured to perform a second operation on the two floating-point numbers based at least in part on the difference is size between the two floating-point numbers. The first path and the second path diverge from each other after receipt of the floating-point numbers in the floating-point arithmetic circuitry and converge on a shared adder that is used for the first operation and the second operation. | 2022-06-30 |
20220206748 | Novel fast adder - Disclosed is a novel fast adder, which belongs to the field of computer hardware processor design. By means of the novel fast adder, the number of gate circuit levels of a common adder can be reduced, such that the operating speed of a computer is increased. Two groups of recording modules are used for recording signals, and after the two groups of recording modules complete signal recording, a signal unit of one group of recording modules transfers the recorded signals to a signal-free unit of the other group of recording modules, and simplification of operation data is completed, and then a data addition operation is carried out, such that the operation time is shortened. | 2022-06-30 |
20220206749 | COMPUTING DEVICE AND METHOD FOR REUSING DATA - A computing device and a method for reusing data are provided. The computing device includes a general register and an arithmetic unit coupled to the general register. The arithmetic unit includes a data reuse unit, which is coupled to multiple dot product data units. The data reuse unit is configured to read from the general register and temporarily store a data set used for multiple convolution operations, and determine multiple data subsets from the data set to be respectively inputted into the multiple dot product data units. Two data subsets inputted into two adjacent dot product data unit include a portion of the same data. Each of the multiple dot product data units is configured to perform a dot product operation on the inputted data subset, so as to generate a dot product operation result. | 2022-06-30 |
20220206750 | PROGRAMMABLE ANALOG SIGNAL PROCESSING ARRAY FOR TIME-DISCRETE PROCESSING OF ANALOG SIGNALS - A programmable analog processing array for programmable time-discrete processing of analog input signals in accordance with a desired signal processing function comprises a network of mutually interconnectable and pre-configurable analog processing slices that form unit circuit cells of the network. Each processing slice comprises a set of cell circuit elements including: a switchable clock input port for receiving a clock signal, a delay element for receiving a respective analog slice input signal and for forwarding the received slice input signal with a pre-configurable time delay as a respective delayed slice input signal, an analog multiplier element receiving the delayed slice input signal for providing an analog multiplier output signal corresponding to a product of the delayed slice input signal with a pre-configurable multiplication factor, an analog adder element receiving a pre-configurable selection of at least two adder input signals including the multiplier output signal and for providing an analog adder output signal corresponding to a sum of the adder input signals, and including an analog resample element for receiving the adder output signal and for providing the received adder output with a pre-configurable time delay as an analog slice output signal. | 2022-06-30 |
20220206751 | TERNARY IN-MEMORY ACCELERATOR - A circuit of cells used as a memory array and capable of in-memory arithmetic is disclosed which includes a plurality of signed ternary processing, each signed ternary processing cell includes a first memory cell, adapted to hold a first digital value, a second memory cell, adapted to hold a second digital value, wherein a binary combination of the first digital value and the second digital value establishes a first signed ternary operand, a signed ternary input forming a second signed ternary operand, and a signed ternary output, wherein the signed ternary output represents a signed multiplication of the first signed ternary operand and the second signed ternary operand, a sense circuit adapted to output a subtraction result. | 2022-06-30 |
20220206752 | ELECTRONIC DEVICE, INPUT-DATA PROCESSING METHOD, AND STORAGE MEDIUM - An electronic device including a processor configured to execute a program stored in a memory, in which the processor executes input-screen display processing of causing a display to display an input screen, in order to accept input of data for a certain item, executes, when the input of the data for the certain item is accepted by a first method during display of the input screen, default-value setting processing of setting the data as a default value for the certain item, and executes data processing with the data, and executes, when the input of the data for the certain item is accepted by a second method during display of the input screen, default-value non-setting processing of not setting the data as the default value, and executes the data processing with the data. | 2022-06-30 |
20220206753 | Cascade Multiplier using Unit Element Analog Multiplier-Accumulator - A multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. The number of bits in the B input is a number of AND-groups and the number of bits in A is the number of AND gates in an AND-group. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges from the charge transfer lines, the charge coupled to an analog to digital converter which forms the dot product output. The charge transfer lines may span multiple unit elements. | 2022-06-30 |
20220206754 | Scaleable Analog Multiplier-Accumulator with Shared Result Bus - A plurality of unit elements share a charge transfer bus, each unit element accepts A and B digital inputs and generates a product P as an analog charge transferred to the charge transfer bus, each unit element comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates of each unit element are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges contributed by all unit elements to the charge transfer lines according to a bit weight and converted to a digital value output. | 2022-06-30 |
20220206755 | Differential Analog Multiplier for a Signed Binary Input - A differential multiplier-accumulator accepts A and B digital inputs plus a sign bit and generates a dot product P by applying the bits of the A input and the bits of the B inputs to respective positive and negative unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. One of the positive and negative unit element is enabled by the sign bit, the enabled unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each positive and negative unit element having the bits of A applied to each associated AND gate input of each unit element, which charge to charge transfer lines, and the charge transfer lines are coupled to binary weighted charge summing capacitors and to an analog to digital converter to generate a digital output product. | 2022-06-30 |
20220206756 | MAC OPERATING DEVICE AND METHOD FOR PROCESSING MACHINE LEARNING ALGORITHM - A MAC operating device comprising a plurality of operation circuits respectively including an operation capacitor and a plurality of switches; and a division capacitor, wherein one end of the operation capacitor is respectively connected to a first operation switch connected to an input terminal and a first reset switch connected to a ground terminal, and the other end of the operation capacitor is connected to both a second operation switch connected to a division capacitor and a second reset switch connected to the ground terminal is provided. | 2022-06-30 |
20220206757 | MULTIPLIER - A multiplier ( | 2022-06-30 |
20220206758 | ADDER CIRCUIT USING LOOKUP TABLES - A four-input lookup table (“LUT4”) is modified to operate in a first mode as an ordinary LUT4 and in a second mode as a 1-bit adder providing a sum output and a carry output. A six-input lookup table (“LUT6”) is modified to operate in a first mode as an ordinary LUT6 with a single output and in a second mode as a 2-bit adder providing a sum output and a carry output. Both possible results for the two different possible carry inputs can be determined and selected between when the carry input is available, implementing a 2-bit carry-select adder when in the second mode and retaining the ability to operate as an ordinary LUT6 in the first mode. Using the novel LUT6 design in a circuit chip fabric allows a 2-bit adder slice to be built that efficiently makes use of the LUT6 without requiring additional logic blocks. | 2022-06-30 |
20220206759 | PRODUCING IDIOMATIC SOFTWARE DOCUMENTATION FOR MANY PROGRAMMING LANGUAGES FROM A COMMON SPECIFICATION - Computer-implemented techniques solve a number of problems with producing idiomatic software documentation for many programming languages from a common specification written in a common specification programming language. The techniques may be employed by a documentation generator computer program that translates the common specification into software programming interface documentation for each of many different programming language targets. The techniques may also be employed by a source-to-source compiler that incorporates the techniques to generate documentation from the common specification for each of many different programming language targets in addition to compiling the common specification into the different target languages. | 2022-06-30 |
20220206760 | DESIGN ASSISTANCE TOOL - A design assistance tool, which assists a design of at least one process, defines a metamodel using at least one metaclass, performs a design of the at least one process using the metamodel, stores a content of the design in a database as a design content, displays the design content as a view on a display, and performs creation, modification, or deletion of at least one of the metamodel or a design result based on the metamodel using the view on the display. The view on the display includes multiple view types described in different formats. When the creation, modification, or deletion of at least one of the metamodel or the design result based on the metamodel is made using one view type, corresponding design information is stored in the database, and the creation, modification, or deletion is reflected in another view type based on the stored design information. | 2022-06-30 |
20220206761 | DESIGN ASSISTANCE TOOL - A design assistance tool, which assists a design of at least two processes includes a database and a display, and is configured to: define a metamodel using one or more metaclass in each of the at least two processes; and perform a design of each process using the corresponding metamodel. The metamodel in one process has a derivation relationship and a different relationship with the metamodel in another process, the database stores the metamodel in one process and the metamodel in another process in associated manner according to the derivation relationship and the different relationship. In the derivation relationship, which is used as trace information, the one or more metaclass in one process is defined based on content of the one or more metaclass in another process. A design result of the process and the derivation relationship used as trace information are displayed in a view of the display. | 2022-06-30 |
20220206762 | CODELESS DEVELOPMENT OF ENTERPRISE APPLICATION - The present invention provides a platform architecture, a development application framework and a method for codeless development of one or more Supply chain management (SCM) enterprise application. The invention includes a layered platform architecture for supporting and executing development of SCM applications. The platform and method provide interaction of an SCM application user, a citizen developer user and a platform developer user with one or more layers of the platform architecture for codeless development of the SCM applications. | 2022-06-30 |
20220206763 | INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING APPARATUS INFORMATION PROCESSING METHOD, AND PROGRAM - An information processing system, which provides services in cooperation with a cloud system, includes element accumulation means for accumulating an element included in a page for providing a service on the cloud system, page-data generating means for generating a page for a new service by using the element accumulated by the element accumulation means, and element-program execution means for executing a program associated with the element included in the page. | 2022-06-30 |
20220206764 | ATTESTATION OF OPERATIONS BY TOOL CHAINS - Attestation of operations by tool chains is described. An example of a storage medium includes instructions for receiving source code for processing of a secure workload of a tenant; selecting at least a first compute node to provide computation for the workload; processing the source code by an attestable tool chain to generate machine code for the first compute node, including performing one or more conversions of the source code by one or more convertors to generate converted code and generating an attestation associated with each code conversion, and receiving machine code for the first compute node and generating an attestation associated with the first compute node; and providing each of the attestations from the first stage and the second stage for verification. | 2022-06-30 |
20220206765 | INTERMEDIATE REPRESENTATION CONSTRUCTION METHOD, COMPILER, AND SERVER - An intermediate representation construction method is provided. The method includes: obtaining a first intermediate representation (IR), where the first IR includes a computing statement, the computing statement includes a tensor and an operator, an operation represented by the operator is performed by a computing unit, the computing unit is configured to perform an operation on data that is migrated through a first storage location and a second storage location sequentially, and the tensor is data that is used when the operation represented by the operator is performed; and generating a second IR based on the computing statement, where the second IR includes first data migration information and data segmentation information. | 2022-06-30 |
20220206766 | CONTROL AND RECONFIGURATION OF DATA FLOW GRAPHS ON HETEROGENEOUS COMPUTING PLATFORM - Embodiments herein use control application programming interfaces (APIs) to control the execution of a dataflow graph in a heterogeneous processing system. That is, embodiments herein describe a programming model along with associated APIs and methods that can control, interact, and at least partially reconfigure a user application (e.g., the dataflow graph) executing on the heterogeneous processing system through a local executing control program. Using the control APIs, users can manipulate such remotely executing graphs directly as local objects and perform control operations on them (e.g., for loading and initializing the graphs; dynamically adjusting parameters for adaptive control; monitoring application parameters, system states and events; scheduling operations to read and write data across the distributed memory boundary of the platform; controlling the execution life-cycle of a subsystem; and partially reconfiguring the computing resources for a new subsystem). | 2022-06-30 |
20220206767 | METHOD FOR COMPILING SOURCE CODE OF EMBEDDED PROCESSOR AND COMPILER THEREOF - A method and a compiler for compiling of a source code of a program of an embedded processor including: determining a target memory statement to access a memory region of the embedded processor from among memory statements included in the source code; inserting, in the vicinity of the target memory statement, an additional statement to detect a memory vulnerability error when the target memory statement accesses the memory region; changing the target memory statement into binary codes; and changing the additional statement into binary codes are provided. | 2022-06-30 |
20220206768 | COMPILER ADAPTED IN GRAPHICS PROCESSING UNIT AND NON-TRANSITORY COMPUTER-READABLE MEDIUM - A compiler includes a front-end module, an optimization module, and a back-end module. The front-end module pre-processes a source code to generate an intermediate code. The optimization module optimizes the intermediate code. The back-end module translates the optimized intermediate code to generate a machine code. Optimization includes translating a branch instruction in the intermediate code into performing the following operations: establishing a post dominator tree for the branch instruction to find an immediate post dominator of the branch instruction as a reconverge point of a first path and a second path of the branch instruction; inserting a specific instruction at the front end of the reconverge point, so as to jumping to execute the instructions of the second path on the condition that once the specific instruction on the first path is executed. | 2022-06-30 |
20220206769 | Framework For User-Directed Profile-Driven Optimizations - A method for using profiling to obtain application-specific, preferred parameter values for an application is disclosed. First, a parameter for which to obtain an application-specific value is identified. Code is then augmented for application-specific profiling of the parameter. The parameter is profiled and profile data is collected. The profile data is then analyzed to determine the application's preferred parameter value for the profile parameter. | 2022-06-30 |
20220206770 | USING ARTIFICIAL INTELLIGENCE TO OPTIMIZE SOFTWARE TO RUN ON HETEROGENEOUS COMPUTING RESOURCE - Systems and methods are described that implement a tool chain which receives original software source code, analyzes the code and divides the code into modules that run optimally on the available heterogeneous resources. For example, the toolchain system segments original source code into code segments, and determine the specialized processor resource, such as a digital signal processing (DSP) processor, Field Programming Gate Array (FPGA), Graphical Processing Unit (GPU), and the like, that most optimally performs computations of the particular code segment. A parsing engine determines the processor of the heterogenous resources, based on a set of rules and/or a trained classifier (e.g., a trained machine learning model). New code segments can be generated that can be executed on the determined type of processor. Further, the system enables application programming interfaces (APIs) that can interface the new code segment with other generated code segments and/or some portions of the original code. | 2022-06-30 |
20220206771 | TEMPLATE BASED APPROACH AUTOMATING THE LIFECYCLE OF API MANAGEMENT DEPLOYMENT - The present invention is directed towards a method | 2022-06-30 |
20220206772 | SCALABLE, ROBUST, AND SECURE MULTI-TENANT EDGE ARCHITECTURE FOR MISSION-CRITICAL APPLICATIONS - Aspects of the present disclosure provide systems, methods, and computer-readable storage media that support cross-server containerized application allocation, multi-tenant namespace management, and data layer deployment in an edge environment. To illustrate, containers associated with an application are deployed to edge servers based on a geographic characteristic of the edge server with respect to an edge device receiving services from the application. A common data layer is provided across the edge environment to manage communications between the different containers, and between the application and other applications of the edge environment. Managing the communication is based on namespaces and/or a modality (e.g., private or public) associated with the application. Authentication configuration of the application is used to determine edge resource access for the containers of the application. A common orchestration layer is provided across the edge environment to manage scaling and configuration updates of the application. | 2022-06-30 |
20220206773 | SYSTEMS AND METHODS FOR BUILDING AND DEPLOYING MACHINE LEARNING APPLICATIONS - According to some aspects, techniques are provided for building and deploying a machine learning application that do not require a user to have expert knowledge of machine learning or programming. These techniques may be executed by a system that provides a graphical user interface which allows a user to visually define a workflow for a machine learning application, without requiring the user to be an expert in machine learning. The system may automatically represent the workflow as a specification that may be used to build and deploy a machine learning application. The system may automatically execute the workflow in a series of stages while managing data flow and execution context between the stages. Such an execution process may provide flexibility in execution so that a user can build a complex machine learning application without it being necessary for the user to have detailed knowledge of how execution is managed. | 2022-06-30 |
20220206774 | SYSTEMS AND METHODS FOR BUILDING AND DEPLOYING MACHINE LEARNING APPLICATIONS - According to some aspects, techniques are provided for building and deploying a machine learning application that do not require a user to have expert knowledge of machine learning or programming. These techniques may be executed by a system that provides a graphical user interface which allows a user to visually define a workflow for a machine learning application, without requiring the user to be an expert in machine learning. The system may automatically represent the workflow as a specification that may be used to build and deploy a machine learning application. The system may automatically execute the workflow in a series of stages while managing data flow and execution context between the stages. Such an execution process may provide flexibility in execution so that a user can build a complex machine learning application without it being necessary for the user to have detailed knowledge of how execution is managed. | 2022-06-30 |
20220206775 | DYNAMIC INVOCATION OF PARTNER PRODUCT EXIT ROUTINE IN AN ACTIVE INFORMATION MANAGEMENT SYSTEM - A method in a mainframe computing system to invoke a partner product exit routine in an information management system while the information management system is in operation. The method includes scheduling an interrupt routine for execution, creating, by the interrupt routine, an information management system task, where the information management system task is a work unit that provides a logical service within the information management system, scheduling, by the interrupt routine, the information management system task for execution, invoking, by the information management system task, the partner product exit routine, and installing, by the partner product exit routine, a component of a software product that allows the software product to integrate with the information management system. | 2022-06-30 |
20220206776 | EDGE SYSTEM AND METHOD FOR CONTROLLING EDGE SYSTEM - An edge system configured by an edge terminal that implements a predetermined function by operating a container using a hardware resource logically allocated by an orchestration technique, wherein the edge terminal is configured to acquire a corresponding image from an image registry based on predetermined setting information, and perform a setting process of deploying to the edge terminal using the acquired image, the edge terminal further includes a device having a predetermined function, and the setting information includes information related to the device. | 2022-06-30 |
20220206777 | MOUSE CHIP EASILY UPDATING FIRMWARE AND OPERATING METHOD THEREOF - There is provided a control chip including a microcontroller unit (MCU), a bus arbiter, a first bus, a second bus, a void hardware, a cache controller, a flash controller and a flash memory, wherein the flash memory is recorded with a firmware. When the MCU does not receive an update instruction, the bus arbiter reads, according to a function command of the MCU, a function return value associated with the function command from the flash memory via the first bus, the cache controller and the flash controller. When the MCU receives the update instruction, the bus arbiter updates the firmware in the flash memory via the second bus and the flash controller, and the void hardware actively replies a void return value associated with the function command to the MCU to replace the function return value. | 2022-06-30 |
20220206778 | System and Method of Utilizing Data Binding to Propagate Data Changes - In one embodiment, one or more computing systems executes a computer program defining (1) a bound value that references a bound variable and (2) a terminating bound value that references computation instructions for deriving a runtime value from at least the bound value of the bound variable. A computation orchestration layer of a programming framework initializes, according to the computer program, a subscription tracker that tracks subscription relationships between the bound variable and the terminating bound value. The computation orchestration layer uses, in response to receiving an indication of an update to the bound value of the bound variable, the subscription tracker to determine that the terminating bound value subscribes to updates to the bound value of the bound variable. The computation orchestration layer sends an update stream associated with the update to a callback function associated with the terminating bound value. | 2022-06-30 |
20220206779 | CONTROL SYSTEM, MOVING OBJECT, CONTROL METHOD, AND COMPUTER-READABLE STORAGE MEDIUM - A control system comprises a first and second moving object control unit for controlling a moving object, an update control unit for controlling reception, from an external apparatus, of a first update program for updating the first moving object control unit and a second update program for updating the second moving object control unit to control updates of the first and second moving object control unit by the first and second update program, and an acquisition unit for acquiring update information indicating an amount of electric power needed to update the first moving object control unit by the first update program and an amount of electric power needed to update the second moving object control unit by the second update program, wherein the update control unit selects, based on the update information, a moving object control unit to be updated among the first and second moving object control unit. | 2022-06-30 |
20220206780 | ONLINE UPGRADING METHOD AND SYSTEM FOR MULTI-CORE EMBEDDED SYSTEM - The present disclosure provides an online upgrade method and system for a multi-core embedded system. The system includes a service system and a multi-core embedded system. The service system is used to provide upgrade firmware files. The multi-core embedded system includes: a system on chip, including a multi-core embedded processor system and a programmable logic module, the programmable logic module maps the memory of the multi-core embedded processor system to the service system; a communication module, establishing the communication connection between the system on chip and the service system, receiving and caches the upgraded firmware files from the service system; a DMA module, used for fast data transfer between the communication module and the memory of the multi-core embedded processor system; an interrupt controller, executing interrupt processing, so that the multi-core embedded processor system can obtain the upgraded firmware files through the memory. | 2022-06-30 |
20220206781 | VEHICLE AND NETWORK SYSTEM - A vehicle and a network system are capable of downloading and updating the latest software from a plurality of other vehicles that are not subject to distance restrictions during an update time in a parking or autonomous driving situation. The vehicle includes a controller and a communicator, which is configured to perform communication with a server and a plurality of other vehicles in a network. Based on a software update request of the vehicle, the controller is configured to perform a software update of the vehicle through the other vehicle in response to a determination that the number of the other vehicle having a processor corresponding to a processor included in the vehicle among the plurality of other vehicles and the other vehicle for which the software update included in a wireless network formed by the vehicle is completed is greater than or equal to a predetermined reference value. | 2022-06-30 |
20220206782 | UPGRADING A SEQUENCE OF MICROSERVICES IN A CLOUD COMPUTING ENVIRONMENT - Approaches presented herein enable hot upgrading a microservices sequence in a cloud computing environment. More specifically, a next microservice of microservice subsequence in a running sequence is obtained, in response to a message to invoke the microservice or subsequence. The running microservice sequence includes at least one unexecuted microservice or subsequence that is to be hot upgraded. The running microservice sequence is generated based on a sequence that is to be hot upgraded which comprises an ordered list of microservices and/or subsequences. The approach may include determining the status of a next microservice or subsequence. The approach may further include invoking the next microservice or subsequence in the running sequence, in response to the status of the next microservice or subsequence being upgrade-complete. | 2022-06-30 |
20220206783 | SYSTEMS AND METHODS FOR GRADUALLY UPDATING A SOFTWARE OBJECT ON A PLURALITY OF COMPUTER NODES - Disclosed herein are systems and method for gradually updating software object instances on a plurality of computer nodes. In an exemplary aspect, in response to receiving a notification from a software object instance, a system may register the software object instance at an update server. The system may store and deploy a plurality of links, wherein each deployed link uniquely corresponds to a registered software object instance. The system may then associate two or more subsets of the plurality of links with two or more update locations, in accordance with an update policy. The system may place an update to the software object instance at the two or more update locations in accordance with an update policy. In response to receiving an update request via a link from a computing node, the system may further redirect the update request to an update location associated with the link. | 2022-06-30 |
20220206784 | SELF-HEALING LEARNING SYSTEM FOR ONE OR MORE CONTROLLERS - Disclosed embodiments relate to automatically providing updates to at least one vehicle, Operations may include receiving, at a server remote from the at least one vehicle, Electronic Control Unit (ECU) activity data from the at least one vehicle, the ECU activity data corresponding to actual operation of the ECU in the at least one vehicle; determining, at the server and based on the ECU activity data, a software vulnerability affecting the at least one vehicle, the software vulnerability being determined based on a deviation between the received ECU activity data and expected ECU activity data; identifying, at the server, an ECU software update based on the determined software vulnerability; and sending, from the server, a delta file configured to update software on tree ECU with a software update corresponding to the identified ECU software update. | 2022-06-30 |
20220206785 | CONDITIONING AUTOREGRESSIVE LANGUAGE MODEL TO IMPROVE CODE MIGRATION - Implementations are described herein for using machine learning to perform various tasks related to migrating source code based on relatively few (“few shots”) demonstrations. In various implementations, an autoregressive language model may be conditioned based on demonstration tuple(s). In some implementations, a demonstration tuple may include a pre-migration version of a first source code snippet and a post-migration version of the first source code snippet. In other implementations, demonstration tuples may include other data, such as intermediate forms (e.g., natural language descriptions or pseudocode), input-output pairs demonstrating intended behavior, etc. The autoregressive language model may be trained on corpora of source code and natural language documentation on the subject of computer programming. A pre-migration version of a source code file may be processed based on the conditioned autoregressive language model, and a post-migration version may be generated based on output generated based on the conditioned autoregressive model. | 2022-06-30 |
20220206786 | CODE LIBRARY SELECTION MANAGEMENT - An embodiment includes executing a querying process that searches for candidate code libraries to replace a current library in a software application. The embodiment also includes receiving a search result from the querying process, wherein the search result includes a set of candidate code libraries. The embodiment also includes identifying a top candidate code library as a highest ranking code library of the set of candidate code libraries based on predetermined metrics. The embodiment also includes generating a revised software application from the original software application, the generating comprising replacing the current library in the original software application with the top candidate code library. | 2022-06-30 |
20220206787 | CROSS-PUBLISHING SOFTWARE LIBRARIES TO MODULE REPOSITORIES - Embodiments provide computer-implemented techniques for publishing multiple software libraries to multiple source code repositories using a set of repository agents each configured to execute one or more source code repository-specific pre-publication actions for different source code repositories. | 2022-06-30 |
20220206788 | VERSION CONTROL METHOD FOR PROGRAM PROJECT AND ASSOCIATED ELECTRIC DEVICE - The present application provides an electronic device and a version control method thereof for comparing program code files of a program project in different versions. The method includes: reading a first manifest file of a first version and a second manifest file of a second version of the program project; and performing an analyzing main program on the first manifest file and the second manifest file to generate a comparison result, and displaying the comparison result on a display device. | 2022-06-30 |
20220206789 | AUTOMATICALLY UPDATING DOCUMENTATION - A method comprises executing a code in a development environment for: documenting versions of source files of a software program in a plurality of source documentation objects, where at least one of the source documentation objects comprises a textual description comprising one or more text-extracts, each text-extract comprising at least one marked token extracted from one of the versions of the source files; accessing a new version of a source file; performing an identification of when at least one updated token in the new version is different from the marked token; and in response to the identification: classifying the updated token according to differences identified between the updated token and the marked token; and subject to the classification being a member of a set of updatable changes, generating an updated source documentation object by modifying the text-extract in the textual description according to the classification and the differences. | 2022-06-30 |
20220206790 | SCENE SWITCHING METHOD, DEVICE AND MEDIUM - This application discloses a scene switching method, device and medium. The method includes after having loaded a first Activity interface of an application development project, removing a first scene contained in the first Activity interface in response to an operation of loading a second Activity interface of the application development project loading the second Activity interface and loading the first scene in the second Activity interface, replacing the first scene with a second scene in the second Activity interface, the multiple scenes being provided by a scene development project imported into the application development project, and the first Activity interface and the second Activity interface being developed and obtained by the application development project. | 2022-06-30 |
20220206791 | METHODS, SYSTEMS, AND APPARATUSES TO OPTIMIZE CROSS-LANE PACKED DATA INSTRUCTION IMPLEMENTATION ON A PARTIAL WIDTH PROCESSOR WITH A MINIMAL NUMBER OF MICRO-OPERATIONS - Systems, methods, and apparatuses relating to circuitry to implement a cross-lane packed data instruction on a partial (e.g., half) width processor with a minimal number of micro-operations are described. In one embodiment, a hardware processor core includes a decoder circuit to decode a single packed data instruction into only a first micro-operation and a second micro-operation, a packed data execution circuit to execute the first micro-operation and the second micro-operation, and a reservation station circuit coupled between the decoder circuit and the packed data execution circuit, the reservation station circuit comprising a first reservation station entry for the first micro-operation to store a first set of fields that indicate three or more input sources and a first destination, and a second reservation station entry for the second micro-operation to store a second set of fields to indicate three or more input sources and a second destination. | 2022-06-30 |
20220206792 | METHODS, SYSTEMS, AND APPARATUSES TO OPTIMIZE PARTIAL FLAG UPDATING INSTRUCTIONS VIA DYNAMIC TWO-PASS EXECUTION IN A PROCESSOR - Systems, methods, and apparatuses relating to circuitry to implement dynamic two-pass execution of a partial flag updating instruction in a processor are described. In one embodiment, a hardware processor core includes a decoder circuit to decode instructions into a set of one or more micro-operations, an execution circuit to execute the micro-operations decoded for the instructions, a data register to store data, a flag register to store a plurality of flags, and a reservation station circuit coupled between the decoder circuit and the execution circuit, the reservation station circuit to, in response to an indicator bit set to a multiple pass mode for a single micro-operation in a reservation station entry, perform a first dispatch of the single micro-operation to the execution circuit, when a source data operand in the data register is ready for execution and a source flag operand in the flag register is not ready for execution, to generate a data resultant, and a second dispatch of the single micro-operation to the execution circuit when both the source data operand in the data register and the source flag operand in the flag register are ready for execution to generate a flag resultant based on one or more of the plurality of flags in the flag register. | 2022-06-30 |
20220206793 | METHODS, SYSTEMS, AND APPARATUSES FOR A SCALABLE RESERVATION STATION IMPLEMENTING A SINGLE UNIFIED SPECULATION STATE PROPAGATION AND EXECUTION WAKEUP MATRIX CIRCUIT IN A PROCESSOR - Systems, methods, and apparatuses relating to a scalable reservation station circuit implementing a single unified speculation state propagation and execution wakeup matrix in a processor are described. In one embodiment, a hardware processor core includes a decoder circuit to decode one or more instructions into a first micro-operation to load data from a data cache, a second micro-operation dependent on the first micro-operation, and a third micro-operation dependent on the second micro-operation; an execution circuit to execute the first micro-operation, the second micro-operation, and the third micro-operation; and a reservation station circuit comprising a load speculation tracker circuit and coupled between the decoder circuit and the execution circuit, the load speculation tracker circuit to, for a reservation station entry of the third micro-operation, track progress of the first micro-operation in the data cache to generate a cancellation indication for the third micro-operation in response to a miss of the data in the data cache for the first micro-operation, wherein the load speculation tracker circuit is to begin to track the progress of the first micro-operation in the data cache in response to a dispatch of the first micro-operation into the data cache. | 2022-06-30 |
20220206794 | SYSTEM FOR EXECUTING NEW INSTRUCTIONS AND METHOD FOR EXECUTING NEW INSTRUCTIONS - A method for executing new instructions includes the following steps. An instruction is received. A determination is made as to whether the received instruction is a new instruction. When the received instruction is the new instruction, a emulation flag is generated. The emulation flag is a first value. A system management interrupt is generated according to the emulation flag. In response to the system management interrupt, entering the system management mode and simulating the execution of the received instruction in the system management mode to generate a simulation execution result. The simulation execution result is stored in a system management memory. | 2022-06-30 |
20220206795 | SHARING REGISTER FILE USAGE BETWEEN FUSED PROCESSING RESOURCES - Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a shared local memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive an instruction to initiate a matrix multiplication operation, write a first set of matrix data into a first set of registers, and share the first set of matrix data between the first processing resource and the second processing resource for use in the matrix multiplication operation. Other embodiments may be described and claimed. | 2022-06-30 |
20220206796 | MULTI-FUNCTIONAL EXECUTION LANE FOR IMAGE PROCESSOR - An apparatus is described that includes an execution unit having a multiply add computation unit, a first ALU logic unit and a second ALU logic unit. The ALU unit is to perform first, second, third and fourth instructions. The first instruction is a multiply add instruction. The second instruction is to perform parallel ALU operations with the first and second ALU logic units operating simultaneously to produce different respective output resultants of the second instruction. The third instruction is to perform sequential ALU operations with one of the ALU logic units operating from an output of the other of the ALU logic units to determine an output resultant of the third instruction. The fourth instruction is to perform an iterative divide operation in which the first ALU logic unit and the second ALU logic unit operate during to determine first and second division resultant digit values. | 2022-06-30 |
20220206797 | MEMORY BANDWIDTH MONITORING EXTENSIBLE COUNTER - Embodiments of apparatuses and methods for memory bandwidth monitoring extensible counters are described. In embodiments, an apparatus includes memory bandwidth monitoring hardware to monitor an event, a shared cache to be shared by multiple cores. At least one of the cores is to execute multiple threads and includes at least three registers. The first register is programmable by software to store a thread identifier of one of threads and an event identifier of the event during execution of the thread. At least one value of the event identifier corresponds to a shared cache miss. The second register is to provide to the software a second value corresponding to a number of bits available to represent the count. The third register is to provide to the software a count of occurrences of the event and an indicator to indicate whether the count reached a maximum count representable by the number of bits. | 2022-06-30 |
20220206798 | SCHEDULER QUEUE ASSIGNMENT - Systems, apparatuses, and methods for implementing scheduler queue assignment logic are disclosed. A processor includes at least a decode unit, scheduler queue assignment logic, scheduler queues, pickers, and execution units. The assignment logic receives a plurality of operations from a decode unit in each clock cycle. The assignment logic includes a separate logical unit for each different type of operation which is executable by the different execution units of the processor. For each different type of operation, the assignment logic determines which of the possible assignment permutations are valid for assigning different numbers of operations to scheduler queues in a given clock cycle. The assignment logic receives an indication of how many operations to assign in the given clock cycle, and then the assignment logic selects one of the valid assignment permutations for the number of operations specified by the indication. | 2022-06-30 |
20220206799 | Apparatus for Processor with Hardware Fence and Associated Methods - An apparatus includes a pipelined processor. The pipelined processor includes a pipeline and a hardware fence. The hardware fence detects if a hazard condition exists by comparing an address for an input operation with an address for an output operation. | 2022-06-30 |
20220206800 | APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS FOR ALIGNING TILES OF A MATRIX OPERATIONS ACCELERATOR - Systems, methods, and apparatuses relating to one or more instructions for row or column aligning of a tile of a matrix operations accelerator are described. In one embodiment, a system includes a matrix operations accelerator circuit comprising a two-dimensional grid of processing elements, a first plurality of registers that represents a first two-dimensional matrix coupled to the two-dimensional grid of processing elements, and a second plurality of registers that represents a second two-dimensional matrix coupled to the two-dimensional grid of processing elements; and a hardware processor core coupled to the matrix operations accelerator circuit and comprising a decoder circuit to decode a single instruction into a decoded instruction, the single instruction including a first field that identifies the first two-dimensional matrix, a second field that identifies the second two-dimensional matrix, and an opcode that indicates an execution circuit of the hardware processor core is to cause a third two-dimensional matrix to be logically formed for input into the two-dimensional grid of processing elements from the first two-dimensional matrix and the second two-dimensional matrix without moving data elements within the first plurality of registers and the second plurality of registers, and the execution circuit of the hardware processor core to execute the decoded instruction according to the opcode. | 2022-06-30 |
20220206801 | APPARATUSES, METHODS, AND SYSTEMS FOR 8-BIT FLOATING-POINT MATRIX DOT PRODUCT INSTRUCTIONS - Systems, methods, and apparatuses relating to 8-bit floating-point matrix dot product instructions are described. A processor embodiment includes fetch circuitry to fetch an instruction having fields to specify an opcode and locations of a destination matrix having single-precision elements, a first source matrix, and a second source matrix, the source matrices having elements that each comprise a quadruple of 8-bit floating-point values, the opcode to indicate execution circuitry is to cause, for each element of the first source matrix and corresponding element of the second source matrix, a conversion of the 8-bit floating-point values to single-precision values, a multiplication of different pairs of converted single-precision values to generate plurality of results, and an accumulation of the results with previous contents of a corresponding element of the destination matrix, decode circuitry to decode the fetched instruction, and the execution circuitry to respond to the decoded instruction as specified by the opcode. | 2022-06-30 |
20220206802 | Method and Apparatus for Dual Multiplication Units in a Data Path - A processor is provided that includes a first multiplication unit in a first data path of the processor, the first multiplication unit configured to perform single issue multiply instructions, and a second multiplication unit in the first data path, the second multiplication unit configured to perform single issue multiply instructions, wherein the first multiplication unit and the second multiplication unit are configured to execute respective single issue multiply instructions in parallel. | 2022-06-30 |
20220206803 | OPTIMIZE BOUND INFORMATION ACCESSES IN BUFFER PROTECTION - A method, system and apparatus for providing bound information accesses in buffer protection, including providing one-to-one mapping between a general-purpose register and bound information in a BI (bound information) register, saving loaded bound information in the BI register for future use, providing integrity of the bound information in the BI register that is maintained along program execution, and providing a pro-active load of the bound information with one-bit extra control on load instruction of the BI register. | 2022-06-30 |
20220206804 | LOOP EXECUTION IN A RECONFIGURABLE COMPUTE FABRIC - Various examples are directed to systems and methods for executing a loop in a reconfigurable compute fabric. A first flow controller may initiate a first thread at a first synchronous flow to execute a first portion of a first iteration of the loop. A second flow controller may receive a first asynchronous message instructing the second flow controller to initiate a first thread at a second synchronous flow to execute a second portion of the first iteration. The second flow controller may determine that the first iteration of the loop is the last iteration of the loop to be executed and initiate the first thread at the second synchronous flow with a last iteration flag set. | 2022-06-30 |
20220206805 | INSTRUCTIONS TO CONVERT FROM FP16 TO BF8 - Techniques for converting FP16 data elements to BF8 data elements using a single instruction are described. An exemplary apparatus includes decoder circuitry to decode a single instruction, the single instruction to include a one or more fields to identify a source operand, one or more fields to identify a destination operand, and one or more fields for an opcode, the opcode to indicate that execution circuitry is to convert packed half-precision floating-point data from the identified source to packed bfloat8 data and store the packed bfloat8 data into corresponding data element positions of the identified destination operand; and execution circuitry to execute the decoded instruction according to the opcode to convert packed half-precision floating-point data from the identified source to packed bfloat8 data and store the packed bfloat8 data into corresponding data element positions. | 2022-06-30 |
20220206806 | INSTRUCTION SIMULATION DEVICE AND METHOD THEREOF - An instruction simulation device and a method thereof are provided. The simulation device includes a monitor, which is configured to determine whether a ready-for-execution instruction is an instruction under a new/extended instruction set sharing the same instruction set architecture as that of the processor. If the ready-for-execution instruction is an extended instruction, it is converted into a simulation program which consists of a compatible instruction sequence further composed of at least one native instruction of the processor or a compatible instruction recognizable/executable by the processor. An execution result of the extended instruction is simulated by executing the simulation program, thereby extending the service life of an electronic appliance embodied with the disclosed simulation device therein. | 2022-06-30 |
20220206807 | INSTRUCTION CONVERSION DEVICE, INSTRUCTION CONVERSION METHOD, INSTRUCTION CONVERSION SYSTEM, AND PROCESSOR - The disclosure relates to an instruction conversion device, an instruction conversion method, an instruction conversion system, and a processor. The instruction conversion device includes a monitor for determining whether a ready-for-execution instruction is an instruction that belongs to a new instruction set or an extended instruction set, wherein the new instruction set and the extended instruction set have the same type of the instruction set architecture as that of the processor. If the ready-for-execution instruction is determined as an extended instruction, this extended instruction is converted into a converted instruction sequence by means of the conversion system, this converted instruction sequence is then sent to the processor for executions, thereby extending the lifespans of the electronic devices embodied with old-version processors. | 2022-06-30 |
20220206808 | METHOD AND SYSTEM FOR EXECUTING NEW INSTRUCTIONS - A method for executing new instructions is provided. The method is used in a processor and includes: receiving an instruction; when the received instruction is an unknown instruction, executing a conversion program by an operating system, wherein the conversion program executes the following steps: determining whether the received instruction is a new instruction; converting the received instruction into at least one old instruction when the received instruction is a new instruction; and executing the at least one old instruction. | 2022-06-30 |
20220206809 | METHOD AND SYSTEM FOR EXECUTING NEW INSTRUCTIONS - A method for converting instructions is provided. The method is used in a processor and includes: receiving an instruction; generating an unknown instruction exception when the received instruction is an unknown instruction; in response to the unknown instruction exception, entering a system management mode; and in the system management mode, executing the following steps through a conversion program: determining whether the received instruction is a new instruction; and simulating the execution of the received instruction by executing at least one old instruction when the received instruction is a new instruction. | 2022-06-30 |
20220206810 | SYSTEM FOR EXECUTING NEW INSTRUCTIONS AND METHOD FOR EXECUTING NEW INSTRUCTIONS - A method for executing new instructions includes receiving an instruction, and determining whether the received instruction is a new instruction according to an operation code of the received instruction. When the received instruction is a new instruction, the basic decoding information of the received instruction is stored in a private register. And, the system for executing the new instructions enters a system management mode, and simulates the execution of the received instruction according to the basic decoding information stored in the private register in the system management mode; wherein the basic decoding information includes the operation code. | 2022-06-30 |
20220206811 | METHOD AND SYSTEM FOR EXECUTING NEW INSTRUCTIONS - A method for executing new instructions is provided. The method is used in a processor and includes: receiving an instruction; generating an unknown instruction exception when the received instruction is an unknown instruction; in response to the unknown instruction exception, executing the following steps through a conversion program: determining whether the received instruction is a new instruction; and converting the received instruction into at least one old instruction when the received instruction is a new instruction; and executing the at least one old instruction in the same execution mode as the received instruction. | 2022-06-30 |
20220206812 | METHOD AND SYSTEM FOR CONVERTING INSTRUCTIONS - A method for converting instructions is provided. The method is used in a processor and includes: receiving an instruction, wherein the instruction is an unknown instruction; determining whether the received instruction is a new instruction; and converting the received instruction into at least one old instruction when the received instruction is a new instruction. | 2022-06-30 |
20220206813 | METHOD AND SYSTEM FOR EXECUTING NEW INSTRUCTIONS - A method for executing new instructions is provided. The method is used in a processor and includes: receiving an instruction; when the received instruction is an unknown instruction, the processor executes the following steps through a conversion program: determining whether the received instruction is a new instruction; and converting the received instruction into at least one old instruction when the received instruction is a new instruction; and simulating the execution of the received instruction by executing the at least one old instruction. | 2022-06-30 |
20220206814 | CRYPTOGRAPHIC ENFORCEMENT OF BORROW CHECKING - Techniques for borrow checking in hardware are described. The technology includes allocating an object in a memory and setting an ownership identifier (ID) in the allocated object, the allocated object being associated with a first variable in a program and setting a matching ownership ID in a pointer to the allocated object. When the allocated object is accessed during execution of the program by a processor, an exception is generated when the ownership ID in the allocated object does not match the ownership ID in the pointer, and execution of the program is continued when the ownership ID in the allocated object does match the ownership ID in the pointer. | 2022-06-30 |
20220206815 | SYSTEM FOR EXECUTING NEW INSTRUCTIONS AND METHOD FOR EXECUTING NEW INSTRUCTIONS - A method for executing new instructions includes the following steps: receiving an instruction and determining whether the received instruction is a new instruction. When the received instruction is the new instruction, entering a system management mode, and simulating the execution of the received instruction by executing at least one old instruction in the system management mode. | 2022-06-30 |
20220206816 | APPARATUS AND METHOD FOR HARDWARE-BASED MEMOIZATION OF FUNCTION CALLS TO REDUCE INSTRUCTION EXECUTION - Apparatus and method for memoizing repeat function calls are described herein. An apparatus embodiment includes: uop buffer circuitry to identify a function for memoization based on retiring micro-operations (uops) from a processing pipeline; memoization retirement circuitry to generate a signature of the function which includes input and output data of the function; a memoization data structure to store the signature; and predictor circuitry to detect an instance of the function to be executed by the processing pipeline and to responsively exclude a first subset of uops associated with the instance from execution when a confidence level associated with the function is above a threshold. One or more instructions that are data-dependent on execution of the instance is then provided with the output data of the function from the memoization data structure. | 2022-06-30 |
20220206817 | PRESERVING MEMORY ORDERING BETWEEN OFFLOADED INSTRUCTIONS AND NON-OFFLOADED INSTRUCTIONS - Preserving memory ordering between offloaded instructions and non-offloaded instructions is disclosed. An offload instruction for an operation to be offloaded is processed and a lock is placed on a memory address associated with the offload instruction. In response to completing a cache operation targeting the memory address, the lock on the memory address is removed. For multithreaded applications, upon determining that a plurality of processor cores have each begun executing a sequence of offload instructions, the execution of non-offload instructions that are younger than any of the offload instructions is restricted. In response to determining that each processor core has completed executing its sequence of offload instructions, the restriction is removed. The remote device may be, for example, a processing-in-memory device or an accelerator coupled to a memory. | 2022-06-30 |
20220206818 | HARDENING EXECUTION HARDWARE AGAINST SPECULATION VULNERABILITIES - Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and execution circuitry coupled to the decode circuitry. The decode circuitry is to decode a single instruction to mitigate vulnerability to a speculative execution attack. The execution circuitry is to be hardened in response to the single instruction. | 2022-06-30 |
20220206819 | DYNAMIC DETECTION OF SPECULATION VULNERABILITIES - Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes speculation vulnerability mitigation hardware and speculation vulnerability detection hardware. The speculation vulnerability mitigation hardware is to implement one or more of a plurality of speculation vulnerability mitigation mechanisms. The speculation vulnerability detection hardware to detect vulnerability to a speculative execution attack and to provide to software an indication of speculative execution attack vulnerability. | 2022-06-30 |
20220206820 | DYNAMIC INSIGHTS EXTRACTION AND TREND PREDICTION - Techniques for process execution trend prediction and visualization are disclosed. The disclosed system receives a process execution request to be executed on a set of targets. The request may include request characteristics, such as a request type and computations to be performed during execution. The system analyzes the request characteristics to determine the computations to execute and for initiates request execution on the targets. Based on the analysis, the system generates predictions regarding the execution, including an estimated completion time. During execution, the system displays various attributes of the execution in a dynamically updating visualization. The system also provides real-time recommendations on how the process can be optimized, such as to reduce execution time and errors. | 2022-06-30 |
20220206821 | DETERMINATION OF POWER-OFF DURATION OF NVME SSD - An SSD includes a controller having a first non-volatile memory in which a power-off timestamp is stored, and a hardware register accessible by a host. The SSD also includes a second non-volatile memory coupled to the controller, the second non-volatile memory storing instructions for at least one boot-up mode of the SSD. Upon power up of the controller and prior to the controller executing the instructions for at least one boot-up mode of the SSD, the controller receives, in the hardware register, a power-on timestamp from the host and determines, based on the power-on timestamp and the stored power-off timestamp, a boot-up mode of the SSD. | 2022-06-30 |
20220206822 | INFORMATION PROCESSING METHOD AND DEVICE, APPARATUS, AND STORAGE MEDIUM - An information processing method includes obtaining version information of an operating system to be installed at a computer apparatus; determining whether the operating system to be installed is supported by the computer apparatus according to the version information; and in response to determining that the operating system to be installed is not supported by the computer apparatus, displaying a prompt message on a current interface of the computer apparatus before an installation path of the operating system is determined, the prompt message being configured to prompt a user that the computer apparatus does not support the operating system to be installed. | 2022-06-30 |
20220206823 | INFORMATION PROCESSING METHOD AND ELECTRONIC APPARATUS - An information processing method includes performing a first boot operation, determining an execution time of the first boot operation and an execution time of a second boot operation before the first boot operation, in response to determining that an interval between the execution time of the first boot operation and the execution time of the second boot operation does not reach a first threshold, determining whether a call number of a first mirror image file before performing the first boot operation has reached a second threshold, and in response to determining that the call number of the first mirror image file before performing the first boot operation has not reached the second threshold, calling the first mirror image file. | 2022-06-30 |