26th week of 2016 patent applcation highlights part 69 |
Patent application number | Title | Published |
20160190258 | LIGHT EMITTING DEVICE HAVING VERTICAL STRUCTURE AND PACKAGE THEREOF - A light emitting device having a vertical structure and a package thereof, which are capable of damping impact generated in a substrate separation process, and achieving an improvement in mass productivity. The device and package include a sub-mount, a first-type electrode, a second-type electrode, a light emitting device, a zener diode, and a lens on the sub-mount. | 2016-06-30 |
20160190259 | EPITAXIAL STRUCTURE AND GROWTH THEREOF - The invention provides an epitaxial growth structure and a growth method thereof. The epitaxial growth structure comprises a substrate, a plurality of seeds, a plurality of nanorods and a film. The seeds arranged in an array are disposed on a surface of the substrate. The nanorods are disposed longitudinally on the seeds, respectively. The film covers horizontally on upper surfaces of the nanorods to form a substantial plane. | 2016-06-30 |
20160190260 | DOPED ZINC OXIDE AS N+ LAYER FOR SEMICONDUCTOR DEVICES - A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. An n-type layer is formed on or in the p-doped layer. The n-type layer includes ZnO on the p-doped layer to form an electronic device. | 2016-06-30 |
20160190261 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device capable of effectively increasing a threshold voltage and a method for manufacturing the silicon carbide semiconductor device. The silicon carbide semiconductor device includes a gate insulating film formed on part of surfaces of the well regions and the source region; and a gate electrode formed on a surface of the gate insulating film so as to be opposite to an end portion of the source region and the well regions. Furthermore, the gate insulating film has, in an interface region between the well regions and the gate insulating film, defects that each form a first trap having an energy level deeper than a conduction band end of silicon carbide and that include a bond between silicon and hydrogen. | 2016-06-30 |
20160190262 | CONFINED EARLY EPITAXY WITH LOCAL INTERCONNECT CAPABILITY - A non-planar semiconductor structure includes a semiconductor substrate, multiple raised semiconductor structures coupled to the substrate and surrounded at a lower portion thereof by a layer of isolation material, gate structure(s) and confined epitaxial material above active regions of the raised structures, the confined epitaxial material having recessed portion(s) therein. Dummy gate structures surrounding a portion of each of the raised structures are initially used, and the confined epitaxial material is created before replacing the dummy gate structures with final gate structures. The structure further includes silicide on upper surfaces of a top portion of the confined epitaxial material, and contacts above the silicide, the contacts including separate contacts electrically coupled to only one area of confined epitaxial material and common contact(s) electrically coupling two adjacent areas of the confined epitaxial material. | 2016-06-30 |
20160190263 | DEVICES FORMED BY PERFORMING A COMMON ETCH PATTERNING PROCESS TO FORM GATE AND SOURCE/DRAIN CONTACT OPENINGS - A device includes an isolation region that defines an active region in a semiconducting substrate and a gate structure, wherein the gate structure has an axial length in a long axis direction thereof such that a first portion of the gate structure is positioned above the active region and a second portion of the gate structure is positioned above the isolation region. Additionally, a gate cap layer is positioned above the gate structure, wherein a first portion of the gate cap layer that is positioned above the first portion of the gate structure is thicker than a second portion of the gate cap layer that is positioned above the second portion of the gate structure. | 2016-06-30 |
20160190264 | TRENCH POWER MOSFET AND MANUFACTURING METHOD THEREOF - A trench power MOSFET and a manufacturing method thereof are provided. The gate of the trench power MOSFET includes an upper doped region, a lower doped region and a middle region interposed therebetween. The upper has a conductive type reverse to that of the lower doped region, and the middle region is an intrinsic or lightly-doped region to form a PIN, P | 2016-06-30 |
20160190265 | SPLIT-GATE TRENCH POWER MOSFET WITH PROTECTED SHIELD OXIDE - A plurality of gate trenches is formed into a semiconductor substrate in an active cell region. One or more other trenches are formed in a different region. Each gate trench has a first conductive material in lower portions and a second conductive material in upper portions. In the gate trenches, a first insulating layer separates the first conductive material from the substrate, a second insulating layer separates the second conductive material from the substrate and a third insulating material separates the first and second conductive materials. The other trenches contain part of the first conductive material in a half-U shape in lower portions and part of the second conductive material in upper portions. In the other trenches, the third insulating layer separates the first and second conductive materials. The first insulating layer is thicker than the third insulating layer, and the third insulating layer is thicker than the second. | 2016-06-30 |
20160190266 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a first capacitive insulating film, a semiconductor region, a gate insulating film, and a gate electrode. The semiconductor region has a groove. The gate insulating film covers a surface of the groove. The gate electrode is in the groove. The gate electrode includes first and second conductive films. The first conductive film is in contact with the gate insulating film. The first conductive film has an upper surface which is higher than a close portion of the second conductive film. The close portion is closer to the upper surface of the first conductive film. | 2016-06-30 |
20160190267 | ALL AROUND CONTACT DEVICE AND METHOD OF MAKING THE SAME - A device is provided that comprises a first pillar disposed in a first region and overlying a base structure, and a second pillar disposed in a second region and overlying the base structure and being spaced apart from the first pillar by a device region. A bridge is disposed in the device region with a first end connected to the first pillar and a second end connected to the second pillar. The bridge includes a top, sides, and a bottom. The bridge is formed from one or more heterostructures with an undercut opening extending from the bottom to an underlying structure. A four-sided conductive contact wraps around and substantially surrounds the bridge around its top, its sides, and its bottom along at least a portion of its length between the first and second end. | 2016-06-30 |
20160190268 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure also includes a first isolation structure partially embedded in the substrate. The first isolation structure has a first upper surface with a first recess. The semiconductor device structure further includes a second isolation structure partially embedded in the substrate. In addition, the semiconductor device structure includes a first gate over the substrate and between the first isolation structure and the second isolation structure. The first gate extends onto the first upper surface to cover the first recess. The semiconductor device structure includes a second gate over the first gate. | 2016-06-30 |
20160190269 | TAPERED GATE OXIDE IN LDMOS DEVICES - Approaches for LDMOS devices are provided. A method of forming a semiconductor structure includes forming a gate dielectric including a first portion having a first uniform thickness, a second portion having a second uniform thickness different than the first uniform thickness, and a transition portion having tapered surface extending from the first portion to the second portion. The gate dielectric is formed on a planar upper surface of a substrate. The tapered surface is at an acute angle relative to the upper surface of the substrate. | 2016-06-30 |
20160190270 | ACTIVE DEVICE AND HIGH VOLTAGE-SEMICONDUCTOR DEVICE WITH THE SAME - A high voltage (HV) semiconductor device is provided, comprising a substrate, a first well having a first conductive type and extending down from a surface of the substrate; a plurality of active devices respectively formed on the substrate, and the adjacent active devices electrically separated from each other by an insulation. One of the active devices comprises a diffusion region doped with impurity of the first conductive type and extending down from a surface of the first well, a ring gate formed in the diffusion region, and a light doping region having a second conductive type and extending down from a surface of the diffusion region. The light doping region is offset from an edge of the insulation. | 2016-06-30 |
20160190271 | SEMICONDUCTOR DEVICE HAVING FILLER AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing a semiconductor device, the device including an active fin protruding from a substrate and extending in a first direction, a first device isolation region disposed at a sidewall of the active fin and extending in a second direction, the second direction crossing the first direction, a normal gate electrode crossing the active fin, a first dummy gate electrode having an undercut portion on the first device isolation region, the first dummy gate electrode extending in the second direction, and a first filler filling the undercut portion on the first device isolation region, wherein the undercut portion is disposed at a lower portion of the first dummy gate electrode. | 2016-06-30 |
20160190272 | METHOD OF FORMING HORIZONTAL GATE ALL AROUND STRUCTURE - This disclosure provides a horizontal structure by using a double STI recess method. The double STI recess method includes: forming a plurality of fins on the substrate; forming shallow trench isolation between the fins; performing first etch-back on the shallow trench isolation; forming source and drain regions adjacent to channels of the fins; and performing second etch-back on the shallow trench isolations to expose a lower portion of the fins as a larger process window for forming gates of the fins. | 2016-06-30 |
20160190273 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The reliability of a semiconductor device is increased by suppression of a variation in electric characteristics of a transistor as much as possible. As a cause of a variation in electric characteristics of a transistor including an oxide semiconductor, the concentration of hydrogen in the oxide semiconductor, the density of oxygen vacancies in the oxide semiconductor, or the like can be given. A source electrode and a drain electrode are formed using a conductive material which is easily bonded to oxygen. A channel formation region is formed using an oxide layer formed by a sputtering method or the like under an atmosphere containing oxygen. Thus, the concentration of hydrogen in a stack, in particular, the concentration of hydrogen in a channel formation region can be reduced. | 2016-06-30 |
20160190274 | METHODS OF FORMING CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES - A device includes a first epi semiconductor material positioned in a source/drain region of the device, the first epi semiconductor material having a first lateral width at an upper surface thereof. An extended-height epi contact structure having an upper surface and first and second side surfaces is positioned on the first epi semiconductor material, the upper surface and the first and second side surfaces collectively defining a contact length of the extended-height epi contact structure that is greater than the first lateral width. A metal silicide region is positioned on the upper surface and the first and second side surfaces of the extended-height epi contact structure. | 2016-06-30 |
20160190275 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: forming an amorphous silicon layer on an insulating layer; introducing oxygen into the amorphous silicon layer; and forming a silicon oxynitride layer by nitriding the amorphous silicon layer having oxygen introduced thereinto. | 2016-06-30 |
20160190276 | METHOD AND SYSTEM FOR IN-SITU ETCH AND REGROWTH IN GALLIUM NITRIDE BASED DEVICES - A method of regrowing material includes providing a III-nitride structure including a masking layer and patterning the masking layer to form an etch mask. The method also includes removing, using an in-situ etch, a portion of the III-nitride structure to expose a regrowth region and regrowing a III-nitride material in the regrowth region. | 2016-06-30 |
20160190277 | BIPOLAR TRANSISTOR STRUCTURE AND A METHOD OF MANUFACTURING A BIPOLAR TRANSISTOR STRUCTURE - According to various embodiments, a bipolar transistor structure may include: a substrate; a collector region in the substrate; a base region disposed over the collector region, an emitter region disposed over the base region; a base terminal laterally electrically contacting the base region, wherein the base terminal includes polysilicon. | 2016-06-30 |
20160190278 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A compound semiconductor device includes: an electron transit layer; an electron supply layer formed over the electron transit layer; and a GaN cap layer formed over the electron supply layer, wherein the electron supply layer includes a first layer made of i-type Al | 2016-06-30 |
20160190279 | Unknown - A SOI substrate is covered by a semiconductor material pattern which comprises a dividing pattern made from electrically insulating material. The dividing pattern is coated by one or more semiconductor materials. The semiconductor material pattern is covered by a gate electrode which faces the dividing pattern. The semiconductor material pattern and the gate pattern are covered by a covering layer. The substrate is eliminated to access the source/drain regions. A second covering layer is deposited and access vias are formed to access the source/drain regions and gate electrode. | 2016-06-30 |
20160190280 | STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE WITH GATE STACK - Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate electrode over the semiconductor substrate. The semiconductor device structure also includes a source/drain structure adjacent to the gate electrode. The semiconductor device structure further includes a spacer element over a sidewall of the gate electrode, and the spacer element has an upper portion having a first exterior surface and a lower portion having a second exterior surface. Lateral distances between the first exterior surface and the sidewall of the gate electrode are substantially the same. Lateral distances between the second exterior surface and the sidewall of the gate electrode increase along a direction from a top of the lower portion towards the semiconductor substrate. | 2016-06-30 |
20160190281 | EXTENDED-DRAIN TRANSISTOR USING INNER SPACER - An MOS device with increased drain-source voltage (Vds) includes a source region and a drain region deposited on a substrate. A gate region includes an inner spacer that extends the drain region. The inner spacer is formed attached to an isolation spacer that isolates the drain region from the gate region. The inner spacer is configured to extend the drain region to modify an electric field in a portion of a conductive band of the MOS device. | 2016-06-30 |
20160190282 | VERTICAL TRANSISTOR DEVICES FOR EMBEDDED MEMORY AND LOGIC TECHNOLOGIES - Vertical transistor devices are described. For example, in one embodiment, a vertical transistor device includes an epitaxial source semiconductor region disposed on a substrate, an epitaxial channel semiconductor region disposed on the source semiconductor region, an epitaxial drain semiconductor region disposed on the channel semiconductor region, and a gate electrode region surrounding sidewalls of the semiconductor channel region. A composition of at least one of the semiconductor regions varies along a longitudinal axis that is perpendicular with respect to a surface of the substrate. | 2016-06-30 |
20160190283 | FABRICATION OF MOSFET DEVICE WITH REDUCED BREAKDOWN VOLTAGE - Fabricating a semiconductor device comprises: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body in the epitaxial layer; forming a source embedded in the body; forming a contact trench that extends through the source and at least part of the body; disposing an implant at least along a contact trench wall; and disposing an epitaxial enhancement portion below the contact trench and in contact with the implant. | 2016-06-30 |
20160190284 | METHOD FOR FABRICATING LIGHTLY DOPED DRAIN AREA, THIN FILM TRANSISTOR AND ARRAY SUBSTRATE - Embodiments of the disclosure provide a method for fabricating a lightly doped drain area, a thin film transistor, and a thin film transistor array substrate. In an embodiment of the disclosure, a poly-silicon layer, a gate insulation layer, and a gate metal layer are formed in sequence on a substrate; the gate metal layer is patterned to form a gate electrode; the gate insulation layer is etched to form a stepped structure, wherein a width of the gate electrode is smaller than a width of the stepped structure, and an edge of the stepped structure is not covered by the gate electrode; and the poly-silicon layer is doped by an ion doping process using the gate electrode and the gate insulation layer with the stepped structure as a mask to form both a lightly doped area and a heavily doped area. | 2016-06-30 |
20160190285 | ENRICHED, HIGH MOBILITY STRAINED FIN HAVING BOTTOM DIELECTRIC ISOLATION - Embodiments are directed to a method of enriching and electrically isolating a fin of a FinFET. The method includes forming at least one fin. The method further includes forming under a first set of conditions an enriched upper portion of the at least one fin. The method further includes forming under a second set of conditions an electrically isolated region from a lower portion of the at least one fin, wherein forming under the first set of conditions is spaced in time from forming under the second set of conditions. The method further includes controlling the first set of conditions separately from the second set of conditions. | 2016-06-30 |
20160190286 | SURFACE PASSIVATION FOR GERMANIUM-BASED SEMICONDUCTOR STRUCTURE - The present disclosure provides a method forming a semiconductor device in accordance with some embodiments. The method includes receiving a substrate having a fin protruding through the substrate, wherein the fin is formed of a first semiconductor material, exposing the substrate in an environment including hydrogen radicals, thereby passivating the protruded fin using the hydrogen radicals, and epitaxially growing a cap layer of a second semiconductor material to cover the protruded fin. | 2016-06-30 |
20160190287 | METHOD FOR FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes following steps. Firstly, a substrate having a transistor is provided, where the transistor includes a source/drain region. A dielectric layer is formed on the substrate, and a contact plug is formed in the dielectric layer to electrically connect the source/drain region. Next, a mask layer is formed on the dielectric layer, where the mask layer includes a first layer and a second layer stacked thereon. After this a slot-cut pattern is formed on the second layer of the mask layer, and a contact slot pattern is formed on the first layer of the mask layer. Finally, the second layer is removed and a contact opening is formed by using the contact slot pattern on the first layer. | 2016-06-30 |
20160190288 | ENRICHED, HIGH MOBILITY STRAINED FIN HAVING BOTTOM DIELECTRIC ISOLATION - Embodiments are directed to a method of enriching and electrically isolating a fin of a FinFET. The method includes forming at least one fin. The method further includes forming under a first set of conditions an enriched upper portion of the at least one fin. The method further includes forming under a second set of conditions an electrically isolated region from a lower portion of the at least one fin, wherein forming under the first set of conditions is spaced in time from forming under the second set of conditions. The method further includes controlling the first set of conditions separately from the second set of conditions. | 2016-06-30 |
20160190289 | METHODS OF FORMING TRANSISTOR STRUCTURES - Methods for fabricating transistor structures are provided, the methods including: forming a fin structure with an upper fin portion and a lower fin portion, the upper fin portion including a sacrificial material; forming a gate structure over the fin; selectively removing the upper fin portion to form a tunnel between the gate structure and lower fin portion; and providing a channel material in the tunnel to define the channel region of the gate structure. The sacrificial material may be a material that can be selectively etched without etching the material of the lower fin portion. The channel material may further be provided to form source and drain regions of the transistor structure, which may result in a junctionless FinFET structure. | 2016-06-30 |
20160190290 | ATOMIC LAYER DEPOSITION OF P-TYPE OXIDE SEMICONDUCTOR THIN FILMS - Provided herein are methods of depositing p-type metal oxide thin films by atomic layer deposition (ALD). Also provided are p-type metal oxide thin films and TFTs including p-type metal oxide channels. In some implementations, the p-type metal oxide thin films have a metal and oxygen vacancy defect density of less than 10 | 2016-06-30 |
20160190291 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A transistor with superior electric characteristics is manufactured. An oxide insulating film is formed over a substrate, an oxide semiconductor film is formed over the oxide insulating film, heat treatment is then conducted at a temperature at which hydrogen contained in the oxide semiconductor film is desorbed and part of oxygen contained in the oxide insulating film is desorbed, then the heated oxide semiconductor film is etched into a predetermined shape to form an island-shaped oxide semiconductor film, a pair of electrodes is formed over the island-shaped oxide semiconductor film, a gate insulating film is formed over the pair of electrodes and the island-shaped oxide semiconductor film, and a gate electrode is formed over the gate insulating film. | 2016-06-30 |
20160190292 | BIPOLAR TRANSISTOR WITH EXTRINSIC BASE REGION AND METHODS OF FABRICATION - The present disclosure relates to integrated circuit (IC) structures and methods of forming the same. An IC structure according to the present disclosure can include: a doped substrate region adjacent to an insulating region; a crystalline base structure including: an intrinsic base region located on and contacting the doped substrate region, the intrinsic base region having a first thickness; an extrinsic base region adjacent to the insulating region, wherein the extrinsic base region has a second thickness greater than the first thickness; a semiconductor layer located on the intrinsic base region of the crystalline base structure; and a doped semiconductor layer located on the semiconductor layer. | 2016-06-30 |
20160190293 | A Transistor and Method of Making - A SiGe HBT has an inverted heterojunction structure, where the emitter layer is formed prior to the base layer and the collector layer. The frequency performance of the SiGe HBT is significantly improved through a better thermal process budget for the base profile, essential for higher cut-off frequency (f | 2016-06-30 |
20160190294 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In order to improve the characteristics of a semiconductor device including: a channel layer and a barrier layer formed above a substrate; and a gate electrode arranged over the barrier layer via a gate insulating film, the semiconductor device is configured as follows. A silicon nitride film is provided over the barrier layer between a source electrode and the gate electrode, and is also provided over the barrier layer between a drain electrode and the gate electrode GE. The surface potential of the barrier layer is reduced by the silicon nitride film, thereby allowing two-dimensional electron gas to be formed. Thus, by selectively forming two-dimensional electron gas only in a region where the silicon nitride film is formed, a normally-off operation can be performed even if a trench gate structure is not adopted. | 2016-06-30 |
20160190295 | FIELD EFFECT TRANSISTOR - A field effect transistor includes a substrate; a first semiconductor layer, disposed over the substrate; a second semiconductor layer, disposed over the first semiconductor layer, wherein an interface between the first semiconductor layer and the second semiconductor layer has a two-dimensional electron gas; a p+ III-V semiconductor layer, disposed over the second semiconductor layer; and a depolarization layer, disposed between the second semiconductor layer and the p+ III-V semiconductor layer, wherein the depolarization layer includes a metal oxide layer. | 2016-06-30 |
20160190296 | GALLIUM NITRIDE BASED HIGH ELECTRON MOBILITY TRANSISTOR INCLUDING AN ALUMINUM GALLIUM NITRIDE BARRIER LAYER - A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a III-nitride epitaxial layer of the first conductivity type coupled to the first surface of the III-nitride substrate, and a first metallic structure electrically coupled to the second surface of the III-nitride substrate. The semiconductor structure further includes an AlGaN epitaxial layer coupled to the III-nitride epitaxial layer of the first conductivity type, and a III-nitride epitaxial structure of a second conductivity type coupled to the AlGaN epitaxial layer. The III-nitride epitaxial structure comprises at least one edge termination structure. | 2016-06-30 |
20160190297 | HIGH-ELECTRON-MOBILITY TRANSISTORS - High-electron-mobility transistors that include field plates are described. In a first implementation, a HEMT includes a first and a second semiconductor material disposed to form a heterojunction at which a two-dimensional electron gas arises and source, a drain, and gate electrodes. The gate electrode is disposed to regulate conduction in the heterojunction between the source electrode and the drain electrode. The gate has a drain-side edge. A gate-connected field plate is disposed above a drain-side edge of the gate electrode and extends laterally toward the drain. A second field plate is disposed above a drain-side edge of the gate-connected field plate and extends laterally toward the drain. | 2016-06-30 |
20160190298 | FORMING ENHANCEMENT MODE III-NITRIDE DEVICES - A method of fabricating a III-N device includes forming a III-N channel layer on a substrate, a III-N barrier layer on the channel layer, an insulator layer on the barrier layer, and a trench in a first portion of the device. Forming the trench comprises removing the insulator layer and a part of the barrier layer in the first portion of the device, such that a remaining portion of the barrier layer in the first portion of the device has a thickness away from a top surface of the channel layer, the thickness being within a predetermined thickness range, annealing the III-N device in a gas ambient including oxygen at an elevated temperature to oxidize the remaining portion of the barrier layer in the first portion of the device, and removing the oxidized remaining portion of the barrier layer in the first portion of the device. | 2016-06-30 |
20160190299 | SEMICONDUCTOR DEVICE HAVING VIA HOLE COATED IN SIDE SURFACES WITH HEAT TREATED NITRIDE METAL AND METHOD TO FORM THE SAME - A semiconductor device having a via hole whose side surface is covered with nitride metals is disclosed. The via hole is formed within an insulating region that surrounds a conductive region, where both regions are made of nitride semiconductor materials. The via hole is filled with a back metal and in side surfaces thereof is covered with a nitride metal which is heat treated at a preset temperature for a preset period. Nitrogen atoms in the nitride metal diffuse into the nitride semiconductor materials in the insulating regions and compensate nitride vacancies therein. The interface between the nitride metal and the nitride semiconductor material is converted into an altered region that shows high resistivity enough to suppress currents leaking from the via hole metal to the conductive region of the nitride semiconductor material. | 2016-06-30 |
20160190300 | SILICON CARBIDE (SiC) DEVICE WITH IMPROVED GATE DIELECTRIC SHIELDING - In one general aspect, an apparatus can include a silicon carbide (SiC) device can include a gate dielectric, a first doped region having a first conductivity type, a body region of the first conductivity type, and a second doped region having a second conductivity type. The second doped region has a first portion disposed between the first doped region and the body region, and the second doped region has a second portion disposed between the first doped region and the gate dielectric. | 2016-06-30 |
20160190301 | Semiconductor Device with Stripe-Shaped Trench Gate Structures, Transistor Mesas and Diode Mesas - A semiconductor device includes stripe-shaped trench gate structures that extend in a semiconductor body along a first horizontal direction. Transistor mesas between neighboring trench gate structures include body regions and source zones, wherein the body regions form first pn junctions with a drift structure and second pn junctions with the source zones. The source zones directly adjoin two neighboring trench gate structures, respectively. Diode mesas that include at least portions of diode regions form third pn junctions with the drift structure. The diode mesas directly adjoin two neighboring trench gate structures, respectively. The transistor mesas and the diode mesas alternate at least along the first horizontal direction. | 2016-06-30 |
20160190302 | SOI BASED FINFET WITH STRAINED SOURCE-DRAIN REGIONS - A method of fabricating a semiconductor device where: (i) the fins are formed over a porous semiconductor material layer (for example, a silicon layer); and (ii) the porous semiconductor layer is then oxidized to form an insulator layer (for example, a SiO | 2016-06-30 |
20160190303 | SILICON GERMANIUM-ON-INSULATOR FINFET - A method of making a structurally stable SiGe-on-insulator FinFET employs a silicon nitride liner to prevent de-stabilizing oxidation at the base of a SiGe fin. The silicon nitride liner blocks access of oxygen to the lower corners of the fin to facilitate fabrication of a high-concentration SiGe fin. The silicon nitride liner is effective as an oxide barrier even if its thickness is less than about 5 nm. Use of the SiN liner provides structural stability for fins that have higher germanium content, in the range of 25-55% germanium concentration. | 2016-06-30 |
20160190304 | DEFECT-FREE STRAIN RELAXED BUFFER LAYER - A modified silicon substrate having a substantially defect-free strain relaxed buffer layer of SiGe is suitable for use as a foundation on which to construct a high performance CMOS FinFET device. The substantially defect-free SiGe strain-relaxed buffer layer can be formed by making cuts in, or segmenting, a strained epitaxial film, causing edges of the film segments to experience an elastic strain relaxation. When the segments are small enough, the overall film is relaxed so that the film is substantially without dislocation defects. Once the substantially defect-free strain-relaxed buffer layer is formed, strained channel layers can be grown epitaxially from the relaxed SRB layer. The strained channel layers are then patterned to create fins for a FinFET device. In one embodiment, dual strained channel layers are formed—a tensilely strained layer for NFET devices, and a compressively strained layer for PFET devices. | 2016-06-30 |
20160190305 | Structure and Method for 3D FinFET Metal Gate - The present disclosure provides a semiconductor structure in accordance with some embodiments. The semiconductor structure includes a semiconductor substrate; and a gate stack disposed on the semiconductor substrate; wherein the gate stack includes a high k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer, wherein the gate stack has a convex top surface. | 2016-06-30 |
20160190306 | FINFET DEVICE WITH A SUBSTANTIALLY SELF-ALIGNED ISOLATION REGION POSITIONED UNDER THE CHANNEL REGION - One illustrative device disclosed herein includes, among other things, a semiconductor substrate, a fin structure, a gate structure positioned around a portion of the fin structure in the channel region of the device, spaced-apart portions of a second semiconductor material positioned vertically between the fin structure and the substrate, wherein the second semiconductor material is a different semiconductor material than that of the fin, and a local channel isolation material positioned laterally between the spaced-apart portions of the second semiconductor material and vertically below the fin structure and the gate structure, wherein the local channel isolation material is positioned under at least a portion of the channel region of the device. | 2016-06-30 |
20160190307 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SAME - A silicon carbide semiconductor device includes a drift layer of a first conductivity type, a source region of the first conductivity type, an active trench formed in penetration through the source region, a base region, a termination trench formed around the active trench, a gate insulating film formed on a bottom surface, a side surface of the active trench, a gate electrode embedded and formed in the active trench with the gate insulating film interposed therebetween, a protective diffusion layer of a second conductivity type formed in a lower portion of the active trench and a part of a lower portion of the termination trench and having a first impurity concentration, and a termination diffusion layer of the second conductivity type formed on an outside of the protective diffusion layer in the lower portion of the termination trench and having a second impurity concentration lower than the first impurity concentration. | 2016-06-30 |
20160190308 | SILICON-CARBIDE TRENCH GATE MOSFETS - In a general aspect, an apparatus can include a semiconductor substrate, a drift region disposed in the semiconductor substrate; a body region disposed in the drift region and a source region disposed in the body region. The apparatus can also include a gate trench disposed in the semiconductor substrate. The apparatus can further include a gate dielectric disposed on a sidewall and a bottom surface of the gate trench, the gate dielectric on the sidewall defining a first interface with the body region and the gate dielectric on the bottom surface defining a second interface with the body region. The apparatus can still further include a gate electrode disposed on the gate dielectric and a lateral channel region disposed in the body region, the lateral channel region being defined along the second interface. | 2016-06-30 |
20160190309 | NANO MOSFET WITH TRENCH BOTTOM OXIDE SHIELDED AND THIRD DIMENSIONAL P-BODY CONTACT - A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device may include a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each of the trenches has a depth in a first dimension, a width in a second dimension and a length in a third dimension. The body region is of opposite conductivity type to the lightly and heavily doped layers. The source region is formed proximate the upper surface. One or more deep contacts are formed at one or more locations along the third dimension proximate one or more of the trenches. The contacts extend in the first direction from the upper surface into the lightly doped layer and are in electrical contact with the source region. | 2016-06-30 |
20160190310 | RADIO FREQUENCY LDMOS DEVICE AND A FABRICATION METHOD THEREFOR - A radio frequency LDMOS device, wherein the drift region includes a first injection region and a second injection region; the first injection region situated between a second lateral surface of a polysilicon gate and a second lateral surface of a first Faraday shielding layer; the second injection region situated between the second lateral surface of the first Faraday shielding layer and the drain region and encloses the drain region; the second lateral surface of the second Faraday shielding layer is a surface of a side near the drain region, the maximum electric field strength of the drift region on the bottom of the second lateral surface of the second Faraday shielding layer is regulated via regulation of the doping concentration of the second injection region; the doping concentration of the first injection region is higher than the second injection region. | 2016-06-30 |
20160190311 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes: an insulating layer; a semiconductor layer of a first conductive type laminated on the insulating layer; an annular deep trench having a thickness reaching the insulating layer from a top surface of the semiconductor layer; a body region of a second conductive type formed across an entire thickness of the semiconductor layer along a side surface of the deep trench in an element forming region surrounded by the deep trench; a drift region of the first conductive type constituted of a remainder region besides the body region in the element forming region; a source region of the first conductive type formed in a top layer portion of the body region; a drain region of the first conductive type formed in a top layer portion of the drift region; and a first conductive type region formed in the drift region, having a deepest portion reaching a position deeper than the drain region, and having a first conductive type impurity concentration higher than the first conductive type impurity concentration of the semiconductor layer and lower than the first conductive type impurity concentration of the drain region. | 2016-06-30 |
20160190312 | VERTICAL GATE ALL-AROUND TRANSISTOR - Vertical GAA FET structures are disclosed in which a current-carrying nanowire is oriented substantially perpendicular to the surface of a silicon substrate. The vertical GAA FET is intended to meet design and performance criteria for the 7 nm technology generation. In some embodiments, electrical contacts to the drain and gate terminals of the vertically oriented GAA FET can be made via the backside of the substrate. Examples are disclosed in which various n-type and p-type transistor designs have different contact configurations. In one example, a backside gate contact extends through the isolation region between adjacent devices. Other embodiments feature dual gate contacts for circuit design flexibility. The different contact configurations can be used to adjust metal pattern density. | 2016-06-30 |
20160190313 | LOCAL BURIED CHANNEL DIELECTRIC FOR VERTICAL NAND PERFORMANCE ENHANCEMENT AND VERTICAL SCALING - A non-volatile memory device and a method for forming the non-volatile memory device are disclosed. The memory device utilizes a local buried channel dielectric in a NAND string that reduces bulk channel leakage at the edge of the NAND string where the electric field gradient along the direction of the string pillar is at or near a maximum during programming operations. The memory device comprises a channel that is coupled at one end to a bitline and at the other end to a source. A select gate is formed at the end of the channel coupled to the bitline to selectively control conduction between the bitline and the channel. At least one non-volatile memory cell is formed along the length of the channel between the select gate and the second end of the channel. A local dielectric region is formed within the channel at the first end of the channel. | 2016-06-30 |
20160190314 | VERTICAL SLIT TRANSISTOR WITH OPTIMIZED AC PERFORMANCE - A vertical slit transistor includes raised source, drain, and channel regions in a semiconductor substrate. Two gate electrodes are positioned adjacent respective sidewalls of the semiconductor substrate. A dielectric material separates the gate electrodes from the source and drain regions. | 2016-06-30 |
20160190315 | METHOD AND STRUCTURE OF MAKING ENHANCED UTBB FDSOI DEVICES - An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material. A gate dielectric is positioned on a top surface and on the exposed side surface of the second layer of semiconductor material. A gate electrode is positioned on the top surface and the exposed side surface of the second layer of semiconductor material. | 2016-06-30 |
20160190316 | CHARGE CARRIER TRANSPORT FACILITATED BY STRAIN - A semiconductor structure and formation thereof. The semiconductor structure has a first semiconductor layer with a first lattice structure and a second epitaxial semiconductor layer that is lattice-matched with the first semiconductor layer. At least two source/drain regions, which have a second lattice structure, penetrate the second semiconductor layer and contact the first semiconductor layer. A portion of the second semiconductor layer is between the source/drain regions and has a degree of uniaxial strain that is based, at least in part, on a difference between the first lattice structure and the second lattice structure. | 2016-06-30 |
20160190317 | HETERO-CHANNEL FINFET - A hetero-channel FinFET device provides enhanced switching performance over a FinFET device having a silicon channel, and is easier to integrate into a fabrication process than is a FinFET device having a germanium channel. A FinFET device featuring the heterogeneous Si/SiGe channel includes a fin having a central region made of silicon and sidewall regions made of SiGe. A hetero-channel pFET device in particular has higher carrier mobility and less gate-induced drain leakage current than either a silicon device or a SiGe device. The hetero-channel FinFET permits the SiGe portion of the channel to have a Ge concentration in the range of about 25-40% and permits the fin height to exceed 40 nm while remaining stable. | 2016-06-30 |
20160190318 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a substrate, first strain-inducing source and drain structures, a first gate structure, a first channel region, second strain-inducing source and drain structures, a second gate structure, and a second channel region. At least one of the first strain-inducing source and drain structures has a first proximity to the first channel region. At least one of the second strain-inducing source and drain structures has a second proximity to the second channel region. The second proximity is different from the first proximity. | 2016-06-30 |
20160190319 | Non-Planar Semiconductor Devices having Multi-Layered Compliant Substrates - Non-planar semiconductor devices having multi-layered compliant substrates and methods of fabricating such non-planar semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a lower portion composed of a first semiconductor material with a first lattice constant (L1), and has an upper portion composed of a second semiconductor material with a second lattice constant (L2). A cladding layer is disposed on the upper portion, but not on the lower portion, of the semiconductor fin. The cladding layer is composed of a third semiconductor material with a third lattice constant (L3), wherein L3>L2>L1. A gate stack is disposed on a channel region of the cladding layer. Source/drain regions are disposed on either side of the channel region. | 2016-06-30 |
20160190320 | SURFACE TENSION MODIFICATION USING SILANE WITH HYDROPHOBIC FUNCTIONAL GROUP FOR THIN FILM DEPOSITION - A semiconductor structure that includes crystalline surfaces and amorphous hydrophilic surfaces is provided. The hydrophilic surfaces are treated with silane that includes a hydrophobic functional group, converting the hydrophilic surfaces to hydrophobic surfaces. Chemical vapor deposition or other suitable deposition methods are used to simultaneously deposit a material on both surfaces and due to the surface treatment, the deposited material exhibits superior adherence qualities on both surfaces. In one embodiment, the structure is an opening formed in a semiconductor substrate and bounded by at least one portion of a crystalline silicon surface and at least one portion of an amorphous silicon oxide structure. | 2016-06-30 |
20160190321 | FinFET Low Resistivity Contact Formation Method - The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate, and wherein a surface of the strained material has received a passivation treatment; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a dielectric layer coating the sidewalls and bottom of the opening, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; a metal barrier coating an opening of the dielectric layer; and a metal layer filling a coated opening of the dielectric layer. | 2016-06-30 |
20160190322 | LARGE AREA CONTACTS FOR SMALL TRANSISTORS - A large area electrical contact for use in integrated circuits features a non-planar, sloped bottom profile. The sloped bottom profile provides a larger electrical contact area, thus reducing the contact resistance, while maintaining a small contact footprint. The sloped bottom profile can be formed by recessing an underlying layer, wherein the bottom profile can be crafted to have a V-shape, U-shape, crescent shape, or other profile shape that includes at least a substantially sloped portion in the vertical direction. In one embodiment, the underlying layer is an epitaxial fin of a FinFET. A method of fabricating the low-resistance electrical contact employs a thin etch stop liner for use as a hard mask. The etch stop liner, e.g., HfO | 2016-06-30 |
20160190323 | FINFET DEVICE INCLUDING A UNIFORM SILICON ALLOY FIN - A method includes forming at least one fin on a semiconductor substrate. A silicon alloy material is formed on the fin and on exposed surface portions of the substrate. A thermal process is performed to define a silicon alloy fin from the silicon alloy material and the fin and to define silicon alloy surface portions from the silicon alloy material and the exposed surface portions of the substrate. A semiconductor device includes a substrate, a fin defined on the substrate, the fin comprising a silicon alloy and having a substantially vertical sidewall, and silicon alloy surface portions on the substrate adjacent the fin. | 2016-06-30 |
20160190324 | CONFORMAL NITRIDATION OF ONE OR MORE FIN-TYPE TRANSISTOR LAYERS - Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface. | 2016-06-30 |
20160190325 | HIGH-RELIABILITY, LOW-RESISTANCE CONTACTS FOR NANOSCALE TRANSISTORS - Tapered source and drain contacts for use in an epitaxial FinFET prevent short circuits and damage to parts of the FinFET during contact processing, thus improving device reliability. The inventive contacts feature tapered sidewalls and a pedestal where electrical contact is made to fins in the source and drain regions. The pedestal also provides greater contact area to the fins, which are augmented by extensions. Raised isolation regions define a valley around the fins. During source/drain contact formation, the valley is lined with a conformal barrier that also covers the fins themselves. The barrier protects underlying local oxide and adjacent isolation regions against gouging while forming the contact. The valley is filled with an amorphous silicon layer that protects the epitaxial fin material from damage during contact formation. A simple tapered structure is used for the gate contact. | 2016-06-30 |
20160190326 | SELF-ALIGNED METAL OXIDE THIN FILM TRANSISTOR AND METHOD OF MAKING SAME - A method for forming a TFT includes providing a substrate, a gate electrode on the substrate, an electrically insulating layer on the substrate to totally cover the gate electrode, a channel layer on the electrically insulating layer, a first photoresist pattern on the channel layer, a metal layer on the electrically insulating layer, the channel layer and the first photoresist layer, and a second photoresist pattern on the metal layer. A middle portion of the metal layer is then removed to form a source electrode and a drain electrode and to expose the first photoresist pattern and a portion of the channel layer between the first and second photoresist patterns. The exposed portion of the channel layer is then processed to have its electrical conductivity be lowered to thereby reduce a hot-carrier effect of the channel layer. | 2016-06-30 |
20160190327 | THIN FILM TRANSISTOR SUBSTRATE, MANUFACTURING METHOD THEREOF, AND LIQUID CRYSTAL DISPLAY PANEL USING SAME - A thin film transistor (TFT) includes a substrate, a TFT formed on the substrate, and a passivation layer formed on the TFT. The TFT includes a gate, a source, a drain, and a channel layer. The source and the drain are respectively located at opposite sides of the channel layer. The channel layer includes oxygen ions which are implanted into the channel layer by an oxygen implanting process performed in an environment having an air pressure greater than a standard atmospheric pressure. | 2016-06-30 |
20160190328 | THIN FILM TRANSISTOR AND DISPLAY DEVICE INCLUDING THE SAME - A thin film transistor including a gate electrode disposed on a substrate, a channel overlapping the gate electrode, a source electrode electrically connected to the channel, and a drain electrode electrically connected to the channel and spaced apart from the source electrode. The channel includes a first channel layer contacting the source electrode and the drain electrode, and a second channel layer disposed on the first channel layer and spaced apart from the source electrode and the drain electrode. | 2016-06-30 |
20160190329 | FIELD-EFFECT TRANSISTOR AND METHOD FOR PRODUCING FIELD-EFFECT TRANSISTOR - To provide a field-effect transistor, containing: a gate electrode configured to apply gate voltage; a source electrode and a drain electrode, both of which are configured to take out electric current; an active layer formed of a n-type oxide semiconductor, provided in contact with the source electrode and the drain electrode; and a gate insulating layer provided between the gate electrode and the active layer, wherein work function of the source electrode and drain electrode is 4.90 eV or greater, and wherein an electron carrier density of the n-type oxide semiconductor is 4.0×10 | 2016-06-30 |
20160190330 | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE INCLUDING THE SEMICONDUCTOR DEVICE - The field-effect mobility of a semiconductor device is improved, and the on-state current thereof is increased, so that stable electrical characteristics are obtained. The semiconductor device includes a first oxide insulator, an oxide semiconductor, and a second oxide insulator which are stacked. The first oxide insulator includes In, Zn, and M (M represents Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf), and the content of In is lower than the content of M, and the content of In is lower than the content of Zn. The oxide semiconductor includes In and M (M represents Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf), and the content of In is higher than the content of M The second oxide insulator includes In, Zn, and M (M represents Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf). | 2016-06-30 |
20160190331 | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE HAVING SEMICONDUCTOR DEVICE - Luminance variation due to change of current through a light-emitting element caused by change in environmental temperature is suppressed. Current through a first light-emitting element in a pixel portion is controlled by a monitor circuit. The monitor circuit includes a second light-emitting element, a transistor, a resistor, and an amplifier circuit. An anode of the second light-emitting element is connected to a source of the transistor. A cathode of the second light-emitting element is connected to the resistor and a first input terminal of the amplifier circuit. A second input terminal of the amplifier circuit is connected to a second power supply line. An output terminal of the amplifier circuit is connected to a gate of the transistor. The drain of the transistor is connected to a third power supply line. The transistor and the resistor each include an oxide semiconductor film. | 2016-06-30 |
20160190332 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An oxide semiconductor film is formed over a substrate, a film of a semiconductor other than an oxide semiconductor is formed over the oxide semiconductor film, and then an oxygen atom in the oxide semiconductor film and an atom in the film of a semiconductor are bonded to each other at an interface between the oxide semiconductor film and the film of a semiconductor. Accordingly, the interface can be made continuous. Further, oxygen released from the oxide semiconductor film is diffused into the film of a semiconductor, so that the film of a semiconductor can be oxidized to form an insulating film. The use of the gate insulating film thus formed leads to a reduction in interface scattering of electrons at the interface between the oxide semiconductor film and the gate insulating film; so that a transistor with excellent electric characteristics can be manufactured. | 2016-06-30 |
20160190333 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - One object of the present invention is to provide a structure of a transistor including an oxide semiconductor in a channel formation region in which the threshold voltage of electric characteristics of the transistor can be positive, which is a so-called normally-off switching element, and a manufacturing method thereof. A second oxide semiconductor layer which has greater electron affinity and a smaller energy gap than a first oxide semiconductor layer is formed over the first oxide semiconductor layer. Further, a third oxide semiconductor layer is formed to cover side surfaces and a top surface of the second oxide semiconductor layer, that is, the third oxide semiconductor layer covers the second oxide semiconductor layer. | 2016-06-30 |
20160190334 | MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a memory device including a substrate, a plurality of tunneling dielectric layers, a plurality of isolation structures, and a plurality of cap layers. The tunneling dielectric layers are located on the substrate. Each isolation structure has an upper portion and a lower portion. The lower portions of the isolation structures are located in the substrate and arranged alternately with the tunneling dielectric layers along a first direction. The upper portions of the isolation structures are located on the lower portions. The cap layers are located on the upper portions. A top surface of the cap layer is a planar surface. | 2016-06-30 |
20160190335 | Split-Gate Flash Memory Having Mirror Structure and Method for Forming the Same - Split-gate flash memory and forming method thereof are provided. The method includes: forming a first dielectric layer on a semiconductor substrate; forming a floating gate layer on the first dielectric layer; forming a mask layer on the floating gate layer; etching the mask layer until first groove exposing the floating gate layer is formed; forming a protective sidewall on sidewall of the first groove; forming a gate dielectric layer on bottom and the sidewall of the first groove; forming two control gates on the gate dielectric layer, the remained first groove serving as second groove; etching the gate dielectric layer and the floating gate layer at bottom of the second groove until third groove exposing the first dielectric layer is formed; forming a source in the semiconductor substrate under the third groove; and forming a second dielectric layer in the third groove. Reliability and durability of the memory are improved. | 2016-06-30 |
20160190336 | COMPLEMENTARY HIGH MOBILITY NANOWIRE NEURON DEVICE - A method for forming a semiconductor device includes providing a substrate structure, which includes a nanowire structure supported by two isolation regions on a substrate. The nanowire structure includes a first nanowire and a second nanowire having different high mobility semiconductor materials and conductivity types. A multi-layer film structure is formed surrounding the nanowire structure and includes a conductive material layer sandwiched between two dielectric layers. A plurality of first electrodes are formed surrounding the multi-layer film structure surrounding a channel region of the first nanowire, and a plurality of second electrodes are formed surrounding the multi-layer film structure surrounding a channel region of the second nanowire. A third electrode is formed to contact one end of the nanowire structure, and a fourth electrode is formed to contact the other end of the nanowire structure. A fifth electrode is formed and coupled to a center portion of the nanowire structure. | 2016-06-30 |
20160190337 | Photopatternable Materials and Related Electronic Devices and Methods - The present polymeric materials can be patterned with relatively low photo-exposure energies and are thermally stable, mechanically robust, resist water penetration, and show good adhesion to metal oxides, metals, metal alloys, as well as organic materials. In addition, these polymeric materials can be solution-processed (e.g., by spin-coating), and can exhibit good chemical (e.g., solvent and etchant) resistance in the cured form. | 2016-06-30 |
20160190338 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To provide a semiconductor device suitable for high reliability and high-speed operation. The semiconductor device includes a first conductor, a first insulator, a second insulator, a semiconductor, and an electron trap layer. The semiconductor includes a channel formation region. The first conductor includes a region overlapping with the channel formation region with the first insulator provided therebetween. The second insulator is placed to include a region in contact with a side surface of the first conductor. The electron trap layer is placed to face the first conductor with the second insulator provided therebetween. | 2016-06-30 |
20160190339 | SEMICONDUCTOR DEVICES WITH CONDUCTIVE CONTACT STRUCTURES HAVING A LARGER METAL SILICIDE CONTACT AREA - A semiconductor device includes a source/drain region, a gate structure, a gate cap layer positioned above the gate structure and a sidewall spacer positioned adjacent to opposite sides of the gate structure. A first epi semiconductor material is positioned in the source/drain region, the first epi semiconductor material having a first lateral width at an upper surface thereof. A second epi semiconductor material is positioned on the first epi semiconductor material, the second epi semiconductor material extending laterally over and covering at least a portion of an uppermost end of the sidewall spacer and having a second lateral width at an upper surface thereof that is greater than the first lateral width. A metal silicide region is positioned on the upper surface of the second epi semiconductor material. | 2016-06-30 |
20160190340 | LATERAL GATE ELECTRODE TFT SWITCH AND LIQUID CRYSTAL DISPLAY DEVICE - A lateral gate electrode TFT switch and a liquid crystal display device are disclosed. The lateral TFT switch has a substrate, a source-drain area, a gate insulation layer and a gate electrode. The source-drain area is disposed on the substrate and has a source electrode, a drain electrode and a semiconductor layer. The semiconductor layer is disposed between the source electrode and the drain electrode. The source electrode and the drain electrode are vertically disposed on the substrate. The gate insulation layer is disposed adjacent to the source-drain area. The gate electrode is disposed adjacent to the gate insulation layer. The gate insulation layer is used to separate the source-drain area from the gate electrode. | 2016-06-30 |
20160190341 | THIN FILM TRANSISTOR AND THIN FILM TRANSISTOR SUBSTRATE - A thin film transistor includes a first gate electrode located on a base, a second gate electrode located on the base, an insulating layer, a source electrode, a drain electrode, and a channel layer. The insulating layer covers the base, the first gate electrode, and the second gate electrode. The second gate electrode is insulated from the first gate electrode. The channel layer includes a first portion and a second portion sandwiched between the first portion and the insulating layer. A conductivity of the second portion is larger than a conductivity of the first portion. The first portion includes a first region facing the first gate electrode and a second region facing the second gate electrode. The source electrode is electrically connected to the first region, and the drain electrode is electrically connected to the second region. | 2016-06-30 |
20160190342 | ACTIVE ELEMENT AND FABRICATING METHOD THEREOF - An active element and a fabricating method thereof are provided. The active element includes a gate, a gate insulating layer, a channel, a source and a drain. The gate is disposed on a substrate. The gate insulating layer is disposed on the substrate and covers the gate. The gate insulating layer is divided into a first region having uniform thickness and a second region having uniform thickness. The thickness of the gate insulating layer in the first region is different from the thickness of the gate insulating layer in the second region. The channel is disposed on the gate insulating layer. The source and the drain are disposed on the gate insulating layer and separated from each other. The distribution region of the source and the drain is identical to the distribution region of the first region. The channel contacts with the source and the drain. | 2016-06-30 |
20160190343 | A FET DEVICE HAVING A VERTICAL CHANNEL IN A 2D MATERIAL LAYER - Semiconductor devices and methods of forming the same are provided. A source/drain electrode stack is formed over a substrate, wherein the source/drain electrode stack comprises a first source/drain electrode and a second source/drain electrode. A source/channel/drain layer is formed on a sidewall of the source/drain electrode stack, wherein the source/channel/drain layer comprises a 2D material. A gate stack is formed on the source/channel/drain layer. | 2016-06-30 |
20160190344 | SEMICONDUCTOR DEVICES WITH GRAPHENE NANORIBBONS - Semiconductor devices with graphene nanoribbons and methods of manufacture are disclosed. The method includes forming at least one layer of Si material on a substrate. The method further includes forming at least one layer of carbon based material adjacent to the at least one layer of Si. The method further includes patterning at least one of the at least one layer of Si material and the at least one layer of carbon based material. The method further includes forming graphene on the patterned carbon based material. | 2016-06-30 |
20160190345 | STRAIN COMPENSATION IN TRANSISTORS - Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires. | 2016-06-30 |
20160190346 | Semiconductor Device, Display Device, Display Module, Electronic Device, Oxide, and Manufacturing Method of Oxide - The semiconductor device includes a first insulator over a substrate, a first oxide semiconductor over the first insulator, a second oxide semiconductor over the first oxide semiconductor, a first conductor and a second conductor in contact with the second oxide semiconductor, a third oxide semiconductor on the second oxide semiconductor and the first and second conductors, a second insulator over the third oxide semiconductor, and a third conductor over the second insulator. At least one of the first oxide semiconductor, the second oxide semiconductor, and the third oxide semiconductor has a crystallinity peak that corresponds to a (hkl) plane (h=0, k=0, l is a natural number) observed by X-ray diffraction using a Cu K-alpha radiation as a radiation source. The peak appears at a diffraction angle 2 theta greater than or equal to 31.3 degrees and less than 33.5 degrees. | 2016-06-30 |
20160190347 | SEMICONDUCTOR DEVICE - A semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes an insulating layer, a semiconductor layer over the insulating layer, a source electrode layer and a drain electrode layer electrically connected to the semiconductor layer, a gate insulating film over the semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer overlapping with part of the semiconductor layer, part of the source electrode layer, and part of the drain electrode layer with the gate insulating film therebetween. A cross section of the semiconductor layer in the channel width direction is substantially triangular or substantially trapezoidal. The effective channel width is shorter than that for a rectangular cross section. | 2016-06-30 |
20160190348 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a semiconductor device including a transistor including a gate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, a first oxide insulating film covering the transistor, and a second oxide insulating film formed over the first oxide insulating film, the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the oxide semiconductor film has an amorphous structure or a microcrystalline structure, the first oxide insulating film is an oxide insulating film through which oxygen is permeated, and the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition. | 2016-06-30 |
20160190349 | e-Flash Si Dot Nitrogen Passivation for Trap Reduction - The present disclosure relates to a structure and method for reducing dangling bonds around quantum dots in a memory cell. In some embodiments, the structure has a semiconductor substrate having a tunnel dielectric layer disposed over it and a plurality of quantum dots disposed over the tunnel dielectric layer. A passivation layer is formed conformally over outer surfaces of the quantum dots and a top dielectric layer is disposed conformally around the passivation layer. The passivation layer can be formed prior to forming the top dielectric layer over the quantum dots or after forming the top dielectric layer. The passivation layer reduces the dangling bonds at an interface between the quantum dots and the top dielectric layer, thereby preventing trap sites that may hinder operations of the memory cell. | 2016-06-30 |
20160190350 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a power feeding region of a memory cell (MC) in which a sidewall-shaped memory gate electrode (MG) of a memory nMIS (Qnm) is provided by self alignment on a side surface of a selection gate electrode (CG) of a selection nMIS (Qnc) via an insulating film, a plug (PM) which supplies a voltage to the memory gate electrode (MG) is embedded in a contact hole (CM) formed in an interlayer insulating film ( | 2016-06-30 |
20160190351 | METHOD AND SYSTEM FOR GAN VERTICAL JFET UTILIZING A REGROWN GATE - A vertical field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction. | 2016-06-30 |
20160190352 | OPTICAL SENSOR DEVICE - A package for an optical sensor device has a double-molded structure in which a first resin molded portion and a second resin molded portion are integrated. The first resin molded portion has a structure in which peripheries of a die pad portion on which an optical sensor element is mounted and a part of leads are molded with a resin so as to be integrated. The second resin molded portion has a structure in which the periphery of the first resin molded portion is molded with a resin so as to form an outer shape of the package. A glass substrate having a filter function is bonded to an upper surface of the resin molded portions to form a cavity in which is mounted the optical sensor element. | 2016-06-30 |
20160190353 | PHOTOSENSITIVE MODULE AND METHOD FOR FORMING THE SAME - A method for forming a photosensitive module is provided. The method includes providing a substrate having a first surface and a second surface opposite thereto. A conducting pad is located on the first surface. A cover plate is provided on the first surface of the substrate. An opening is formed. The opening penetrates the substrate and exposes the conducting pad. A redistribution layer is formed in the first opening to electrically connect to the conducting pad. The cover plate is removed and a dicing process is performed to form a sensing device. The sensing device is bonded to a circuit board. An optical component is mounted on the circuit board and corresponds to the sensing device. A photosensitive module formed by the method is also provided. | 2016-06-30 |
20160190354 | BARRIER-LESS METAL SEED STACK AND CONTACT - Approaches for forming barrier-less seed stacks and contacts are described. In an example, a solar cell includes a substrate and a conductive contact disposed on the substrate. The conductive contact includes a copper layer directly contacting the substrate. In another example, a solar cell includes a substrate and a seed layer disposed directly on the substrate. The seed layer consists essentially of one or more non-diffusion-barrier metal layers. A conductive contact includes a copper layer disposed directly on the seed layer. An exemplary method of fabricating a solar cell involves providing a substrate, and forming a seed layer over the substrate. The seed layer includes one or more non-diffusion-barrier metal layers. The method further involves forming a conductive contact for the solar cell from the seed layer. | 2016-06-30 |
20160190355 | Auto-Adjusting Device and Method for Adjusting Drive Voltage Light Receiver - An auto-adjusting device for adjusting a drive voltage of a light receiver includes an amplifier, an analog-to-digital converter, a determination control circuit and a boost circuit. The amplifier is configured to amplify an analog signal generated by the light receiver. The analog-to-digital converter is configured to convert the amplified analog signal to a digital signal. The determination control circuit is configured to process and determine the digital signal, and output a control signal when the processed digital signal satisfies a predetermined condition. The boost circuit is configured to receive the control signal and adjust the drive voltage of the light receiver. | 2016-06-30 |
20160190356 | SOLAR CELL MODULE AND SOLAR CELL MODULE MANUFACTURING METHOD - A solar cell module manufacturing method is provided. This method includes: preparing a solar cell element that has a surface whose outer periphery is surrounded by a plurality of sides, an encapsulant that seals the solar cell elements, and a coating that has light diffusivity; applying the coating in an outer peripheral area of the surface via a printing plate that has a pattern corresponding to the outer peripheral area and in which a protection member is provided at a position that corresponds to a corner portion located between two sides of the plurality of sides, the two sides extending in directions that intersect with each other; and sealing, with the encapsulant, the solar cell element on which the coating is printed. | 2016-06-30 |
20160190357 | ANTI-GLARE FILM FOR SOLAR CELL MODULE, SOLAR CELL MODULE PROVIDED WITH ANTI-GLARE FILM, AND METHOD FOR MANUFACTURING SAME - An anti-glare film includes a first inorganic layer and a second inorganic layer in this order has form a substrate side. The first inorganic layer contains transparent spherical inorganic fine particles in an inorganic binder. The inorganic binder in the first inorganic layer mainly includes a silicon oxide containing Si—O bonds obtained by hydrolysis of a Si—H bond and a Si—N bond. The second inorganic layer contains an inorganic binder. Preferably, an average thickness of the first inorganic layer is 500 to 2000 nm, an average thickness of the second inorganic layer is 50 to 1000 nm, and a ratio is 0.025 to 0.5. The second inorganic layer may furthermore contain fine particles. The anti-glare film can be used as an anti-glare film for a solar cell module. | 2016-06-30 |