26th week of 2017 patent applcation highlights part 54 |
Patent application number | Title | Published |
20170186678 | FAN-OUT CHIP PACKAGE AND ITS FABRICATING METHOD | 2017-06-29 |
20170186679 | Semiconductor Device Package and Manufacturing Method Thereof | 2017-06-29 |
20170186680 | WIRING SUBSTRATE | 2017-06-29 |
20170186681 | Packaging Device Having Plural Microstructures Disposed Proximate to Die Mounting Region | 2017-06-29 |
20170186682 | SELF-ALIGNED VIA FORMING TO CONDUCTIVE LINE AND RELATED WIRING STRUCTURE | 2017-06-29 |
20170186683 | Method and Structure for Interconnection | 2017-06-29 |
20170186684 | WIRING SUBSTRATE | 2017-06-29 |
20170186685 | Method of Forming Metal Interconnection | 2017-06-29 |
20170186686 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | 2017-06-29 |
20170186687 | METHOD FOR SELECTIVE RE-ROUTING OF SELECTED AREAS IN A TARGET LAYER AND IN ADJACENT INTERCONNECTING LAYERS OF AN IC DEVICE | 2017-06-29 |
20170186688 | METHODS AND DEVICES FOR METAL FILLING PROCESSES | 2017-06-29 |
20170186689 | SENSOR DEVICE | 2017-06-29 |
20170186690 | Semiconductor Device and Method of Forming Inductor Over Insulating Material Filled Trench in Substrate | 2017-06-29 |
20170186691 | TECHNIQUES BASED ON ELECTROMIGRATION CHARACTERISTICS OF CELL INTERCONNECT | 2017-06-29 |
20170186692 | METAL GATE TRANSISTOR AND FABRICATION METHOD THEREOF | 2017-06-29 |
20170186693 | SOI WAFERS WITH BURIED DIELECTRIC LAYERS TO PREVENT CU DIFFUSION | 2017-06-29 |
20170186694 | DEVICES AND METHODS RELATED TO A SPUTTERED TITANIUM TUNGSTEN LAYER FORMED OVER A COPPER INTERCONNECT STACK STRUCTURE | 2017-06-29 |
20170186695 | Method of Manufacturing a Semiconductor Device with Epitaxial Layers and an Alignment Mark | 2017-06-29 |
20170186696 | METHOD OF MARKING A SEMICONDUCTOR PACKAGE | 2017-06-29 |
20170186697 | Electromagnetically shielded electronic devices and related systems and methods | 2017-06-29 |
20170186698 | ELECTRONIC PACKAGE HAVING ELECTROMAGNETIC INTERFERENCE SHIELDING AND ASSOCIATED METHOD | 2017-06-29 |
20170186699 | Electromagnetic interference shielding for system-in-package technology | 2017-06-29 |
20170186700 | SEMICONDUCTOR PACKAGE STRUCTURE BASED ON CASCADE CIRCUITS | 2017-06-29 |
20170186701 | CRACK RESISTANT ELECTRONIC DEVICE PACKAGE SUBSTRATES | 2017-06-29 |
20170186702 | PACKAGING SUBSTRATE AND ELECTRONIC PACKAGE HAVING THE SAME | 2017-06-29 |
20170186703 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE | 2017-06-29 |
20170186704 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING MOISTURE-RESISTANT RINGS BEING FORMED IN A PERIPHERAL REGION | 2017-06-29 |
20170186705 | Non-Rectangular Electronic Device Components | 2017-06-29 |
20170186706 | SYSTEM AND METHOD FOR PROTECTING AN INTEGRATED CIRCUIT (IC) DEVICE | 2017-06-29 |
20170186707 | STRUCTURES TO MITIGATE CONTAMINATION ON A BACK SIDE OF A SEMICONDUCTOR SUBSTRATE | 2017-06-29 |
20170186708 | Electronic device packages with conformal emi shielding and related methos | 2017-06-29 |
20170186709 | MANUFACTURING METHOD OF CHIP PACKAGE AND PACKAGE SUBSTRATE | 2017-06-29 |
20170186710 | GLASS INTERPOSER INTEGRATED HIGH QUALITY ELECTRONIC COMPONENTS AND SYSTEMS | 2017-06-29 |
20170186711 | STRUCTURE AND METHOD OF FAN-OUT STACKED PACKAGES | 2017-06-29 |
20170186712 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME | 2017-06-29 |
20170186713 | SYSTEM AND METHOD FOR AN IMPROVED INTERCONNECT STRUCTURE | 2017-06-29 |
20170186714 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD | 2017-06-29 |
20170186715 | Bond Structures and the Methods of Forming the Same | 2017-06-29 |
20170186716 | CHIP WITH I/O PADS ON PERIPHERIES AND METHOD MAKING THE SAME | 2017-06-29 |
20170186717 | METHOD AND STRUCTURE FOR WAFER-LEVEL PACKAGING | 2017-06-29 |
20170186718 | ELECTRONIC DEVICE, ELECTRONIC DEVICE FABRICATION METHOD, AND ELECTRONIC APPARATUS | 2017-06-29 |
20170186719 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SAME, AND ELECTRONIC APPARATUS | 2017-06-29 |
20170186720 | ADHESIVE BONDING COMPOSITION AND ELECTRONIC COMPONENTS PREPARED FROM THE SAME | 2017-06-29 |
20170186721 | SEMICONDUCTOR MOUNTING APPARATUS, HEAD THEREOF, AND METHOD FOR MANUFACTURING LAMINATED CHIP | 2017-06-29 |
20170186722 | SYSTEMS AND PROCESSES FOR MEASURING THICKNESS VALUES OF SEMICONDUCTOR SUBSTRATES | 2017-06-29 |
20170186723 | Trace Design for Bump-on-Trace (BOT) Assembly | 2017-06-29 |
20170186724 | SYSTEMS AND METHODS FOR BONDING SEMICONDUCTOR ELEMENTS | 2017-06-29 |
20170186725 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR WAFER | 2017-06-29 |
20170186726 | Packaged Semiconductor Devices and Packaging Methods | 2017-06-29 |
20170186727 | DISCRETE FLEXIBLE INTERCONNECTS FOR MODULES OF INTEGRATED CIRCUITS | 2017-06-29 |
20170186728 | CHIP STACK COOLING STRUCTURE | 2017-06-29 |
20170186729 | STACKED SEMICONDUCTOR DIES WITH SELECTIVE CAPILLARY UNDER FILL | 2017-06-29 |
20170186730 | SYSTEM AND METHOD FOR PROVIDING 3D WAFER ASSEMBLY WITH KNOWN-GOOD-DIES | 2017-06-29 |
20170186731 | SOLID STATE DRIVE OPTIMIZED FOR WAFERS | 2017-06-29 |
20170186732 | SEAL-RING STRUCTURE FOR STACKING INTEGRATED CIRCUITS | 2017-06-29 |
20170186733 | Method for Aligning Micro-Electronic Components | 2017-06-29 |
20170186734 | SEMICONDUCTOR PACKAGE | 2017-06-29 |
20170186735 | LED MODULE | 2017-06-29 |
20170186736 | Structure and Formation Method for Chip Package | 2017-06-29 |
20170186737 | THIN FAN-OUT MULTI-CHIP STACKED PACKAGES AND THE METHOD FOR MANUFACTURING THE SAME | 2017-06-29 |
20170186738 | SEMICONDUCTOR MODULE | 2017-06-29 |
20170186739 | PACKAGING OPTOELECTRONIC COMPONENTS AND CMOS CIRCUITRY USING SILICON-ON-INSULATOR SUBSTRATES FOR PHOTONICS APPLICATIONS | 2017-06-29 |
20170186740 | MATRIX-ADDRESSED DEVICE REPAIR | 2017-06-29 |
20170186741 | INTEGRATED CIRCUITS USING GUARD RINGS FOR ESD SYSTEMS, AND METHODS FOR FORMING THE INTEGRATED CIRCUITS | 2017-06-29 |
20170186742 | IMPLEMENTATION OF LONG-CHANNEL THICK-OXIDE DEVICES IN VERTICAL TRANSISTOR FLOW | 2017-06-29 |
20170186743 | SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME | 2017-06-29 |
20170186744 | SEMICONDUCTOR DEVICE HAVING CONTACT PLUG AND METHOD OF FORMING THE SAME | 2017-06-29 |
20170186745 | Resistance Mitigation in Physical Design | 2017-06-29 |
20170186746 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME | 2017-06-29 |
20170186747 | STRUCTURE AND METHOD FOR SiGe FIN FORMATION IN A SEMICONDUCTOR DEVICE | 2017-06-29 |
20170186748 | FinFET Device Having Flat-Top Epitaxial Features and Method of Making the Same | 2017-06-29 |
20170186749 | SEMICONDUCTOR DEVICE | 2017-06-29 |
20170186750 | MEMORY DEVICE WITH REDUCED-RESISTANCE INTERCONNECT | 2017-06-29 |
20170186751 | Semiconductor Device and Memory Device Including the Semiconductor Device | 2017-06-29 |
20170186752 | SEMICONDUCTOR DEVICES INCLUDING CAPACITORS AND METHODS OF MANUFACTURING THE SAME | 2017-06-29 |
20170186753 | SEMICONDUCTOR DEVICE HAVING BURIED GATE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME, MEMORY CELL HAVING THE SAME AND ELECTRONIC DEVICE HAVING THE SAME | 2017-06-29 |
20170186754 | ATOMIC LAYER DEPOSITION OF III-V COMPOUNDS TO FORM V-NAND DEVICES | 2017-06-29 |
20170186755 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME | 2017-06-29 |
20170186756 | ANTI-FUSE TYPE NONVOLATILE MEMORY CELLS, ARRAYS THEREOF, AND METHODS OF OPERATING THE SAME | 2017-06-29 |
20170186757 | METHODS OF FORMING A FERROELECTRIC MEMORY CELL | 2017-06-29 |
20170186758 | 3-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF | 2017-06-29 |
20170186759 | INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME | 2017-06-29 |
20170186760 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE | 2017-06-29 |
20170186761 | SEMICONDUCTOR MEMORY DEVICE | 2017-06-29 |
20170186762 | METHOD TO FABRICATE UNIFORM TUNNELING DIELECTRIC OF EMBEDDED FLASH MEMORY CELL | 2017-06-29 |
20170186763 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | 2017-06-29 |
20170186764 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | 2017-06-29 |
20170186765 | Vertical memory having varying storage cell design through the storage cell stack | 2017-06-29 |
20170186766 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE | 2017-06-29 |
20170186767 | MEMORY DEVICES | 2017-06-29 |
20170186768 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE | 2017-06-29 |
20170186769 | SEMICONDUCTOR DEVICE INCLUDING A STACK HAVING A SIDEWALL WITH RECESSED AND PROTRUDING PORTIONS | 2017-06-29 |
20170186770 | 3D SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE | 2017-06-29 |
20170186771 | Semiconductor Chip and Method for Manufacturing the Same | 2017-06-29 |
20170186772 | Semiconductor Chip Including Integrated Circuit Defined Within Dynamic Array Section | 2017-06-29 |
20170186773 | TOUCH DRIVE CIRCUIT AND DRIVING METHOD THEREFOR, ARRAY SUBSTRATE AND TOUCH DISPLAY APPARATUS | 2017-06-29 |
20170186774 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | 2017-06-29 |
20170186775 | FINFET WITH STACKED FACETED S/D EPITAXY FOR IMPROVED CONTACT RESISTANCE | 2017-06-29 |
20170186776 | ACTIVE LAYER, THIN-FILM TRANSISTOR ARRAY SUBSTRATE COMPRISING THE SAME, AND DISPLAY DEVICE COMPRISING THE SAME | 2017-06-29 |
20170186777 | DISPLAY DEVICE, DISPLAY MODULE, AND ELECTRONIC DEVICE | 2017-06-29 |