| 26th week of 2012 patent applcation highlights part 72 |
| Patent application number | Title | Published |
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| 20120166796 | SYSTEM AND METHOD OF PROVISIONING OR MANAGING DEVICE CERTIFICATES IN A COMMUNICATION NETWORK - A certificate manager transmits a certificate service advertisement to a plurality of certificate clients. The certificate service advertisement identifies the certificate manager and includes segregation data. The segregation data indicates a set of services offered or a set of clients for which the certificate manager offers service. Responsive to the transmitting of the certificate service advertisement, the certificate manager receives a certificate service request from at least one certificate client of the plurality of certificate clients. The certificate manager verifies that the at least one certificate client is associated with the set of clients for which the certificate manager offers service, and the certificate manager fulfills the certificate service request. | 2012-06-28 |
| 20120166797 | Systems and Methods for Controlling Access to Encrypted Data Stored on a Mobile Device - Encrypted data on mobile devices is protected by remotely storing a decryption key. In order to decrypt the encrypted data on the mobile device, the mobile device obtains the decryption key from an access control system that is remote from the mobile device. The access control system can control access to the encrypted data by controlling access to the decryption key. For example, the access control system can implement user authentication as a condition for providing the decryption key. Access to the encrypted data can also be controlled by withholding the decryption key where, for instance, a mobile device has been reported to be lost or stolen, or once an individual's access privilege has been revoked, or at certain times of the day. | 2012-06-28 |
| 20120166798 | METHOD AND SYSTEM FOR USING NEIGHBOR DISCOVERY UNSPECIFIED SOLICITATION TO OBTAIN LINK LOCAL ADDRESS - A system that facilitates enhancing security for a computer device by obtaining a link layer address of an IPv6 IPsec address. The system including a computer device having a software module, which performs the following steps: capturing multicast addresses and solicited multicast addresses for one or more IPv6 IPsec addresses; calculating the computer device identifier from the one or more multicast addresses and solicited multicast addresses; storing the computer device identifier for the one or more multicast addresses and solicited multicast addresses; sending a neighbor solicitation to one or more of the IPv6 IPsec addresses as a tentative target address simulating double address detection; capturing the neighbor advertisement response from the one or more IPv6 IPsec addresses and calculating a link-layer identifier; generating a neighbor cache with the link-layer identifier; and enabling IPv6 IPsec communication with the one or more IPv6 IPsec addresses using the link-layer identifier. | 2012-06-28 |
| 20120166799 | SYSTEM AND METHOD FOR SECURELY MOVING CONTENT - A domain controller is provided for use with a content source and a media device. The content source can provide encrypted content and rights data corresponding to the encrypted content. The media device can provide a request for the encrypted content and the rights data. The domain controller includes a communication portion, a digital rights management portion and a memory portion. The communication portion can engage in a first bi-directional communication with the content source and can engage in a second bi-directional communication with the media device. The digital rights management portion can receive the rights data. The memory portion can store the encrypted content. The second bi-directional communication includes an authorization and authentication communication between the communication portion and the media device, a secure move message exchange between the communication portion and the media device and a content download from the communication portion to the media device. | 2012-06-28 |
| 20120166800 | PROCESS AND DEVICE FOR AUTHENTICATION - The authentication process comprises:
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| 20120166801 | MUTUAL AUTHENTICATION SYSTEM AND METHOD FOR MOBILE TERMINALS - Provided is a technique for mutual authentication between different kinds of objects (devices, apparatuses, users, etc.) by expanding the kinds of objects that are subject to authentication, such as authentication between users, authentication between users and an apparatuses (devices, equipment, terminals, etc.), and authentication between apparatuses (devices, equipment, terminals, etc.). | 2012-06-28 |
| 20120166802 | METHOD AND APPARATUS FOR ESTABLISHING A SECURITY ASSOCIATION - A method for establishing a security association between a client and a service node for the purpose of pushing information from the service node to the client, where the client and a key server share a base secret. The method comprises sending a request for generation and provision of a service key from the service node to a key server, the request identifying the client and the service node, generating a service key at the key server using the identities of the client and the service node, the base secret, and additional information, and sending the service key to the service node together with said additional information, forwarding said additional information from the service node to the client, and at the client, generating said service key using the received additional information and the base key. A similar approach may be used to provide p2p key management. | 2012-06-28 |
| 20120166803 | VERIFICATION METHOD, APPARATUS, AND SYSTEM FOR RESOURCE ACCESS CONTROL - A verification method includes obtaining a Uniform Resource Locator (URL) link from a user terminal. The URL link is generated by a portal server according to obtained user terminal information and includes the user terminal information. The method further includes obtaining the user terminal information included in the URL link and performing a validity check according to user terminal information stored on a network side and the user terminal information included in the URL link. The validity check can be performed on the URL link according to the user terminal information, which prevents different users from accessing a resource through the same correct URL link and avoids occurrence of link theft. | 2012-06-28 |
| 20120166804 | VLAN Tunneling - According to one embodiment of the invention, a method is described that is directed to sending, by a network device, information over a first tunnel associated with a first virtual local area network. Also, a second tunnel associated with the second virtual local area network is created by the network device if the information is determined to be received from a network device that is a member of the second virtual local area network differing from the first virtual local area network. Herein, the first tunnel and the second tunnel each encapsulates at least data link traffic. | 2012-06-28 |
| 20120166805 | METHOD AND SYSTEM FOR EXCHANGE MULTIFUNCTION JOB SECURITY USING IPV6 NEIGHBOR DISCOVERY OPTIONS - A method that facilitates exchange multifunction job security using IPv6 Neighbor Discovery, which includes generating a job on a first node, the first node having a software module, which creates at least one security option for the job; sending a neighbor solicitation request with the at least one security option to a second node; receiving the neighbor solicitation request on the second node, the second node having a software module for processing the neighbor solicitation request with the at least one security option; sending a neighbor advertisement to the first node; receiving the neighbor advertisement from the second node to obtain a job identifier for the job; and if the job identifier for the job is obtained, processing the job on the first node. | 2012-06-28 |
| 20120166806 | Method and Apparatus to Use Identify Information for Digital Signing and Encrypting Content Integrity and Authenticity in Content Oriented Networks - A content router comprising storage configured to cache, in a content oriented network (CON), a content object with a signature signed by a publisher based on a known identity to a subscriber; and a transmitter coupled to the storage and configured to forward the content object with the signature upon request to the subscriber, wherein the subscriber uses the signature to verify one of the content object's integrity and the content object's authenticity based on the known identity without verifying a trust of a publisher key for the publisher, and wherein the known identity is trusted by the publisher and does not require verifying trust from the publisher. | 2012-06-28 |
| 20120166807 | Systems and Methods Using Cryptography to Protect Secure Computing Environments - Secure computation environments are protected from bogus or rogue load modules, executables and other data elements through use of digital signatures, seals and certificates issued by a verifying authority. A verifying authority—which may be a trusted independent third party—tests the load modules or other executables to verify that their corresponding specifications are accurate and complete, and then digitally signs the load module or other executable based on tamper resistance work factor classification. Secure computation environments with different tamper resistance work factors use different verification digital signature authentication techniques (e.g., different signature algorithms and/or signature verification keys)—allowing one tamper resistance work factor environment to protect itself against load modules from another, different tamper resistance work factor environment. Several dissimilar digital signature algorithms may be used to reduce vulnerability from algorithm compromise, and subsets of multiple digital signatures may be used to reduce the scope of any specific compromise. | 2012-06-28 |
| 20120166808 | LATTICE-BASED RING SIGNATURE METHOD - A lattice-based ring signature method includes generating a dimension, a bound, a length of a hashed message, a Gaussian parameter and an open parameter, which are parameters necessary for a ring signature. Further, the lattice-based ring signature method includes generating a signature key and a verifying key for a user who construct a ring by using the parameter necessary for the ring signature. Furthermore, the lattice-based ring signature method generating a signature for a message and the ring by using the signature key and the verifying key. | 2012-06-28 |
| 20120166809 | SYSTEM AND METHOD FOR CRYPTOGRAPHIC KEY EXCHANGE USING MATRICES - Two parties can establish a cryptographic key using a matrix based key exchange protocol, for secure communications without any prior distribution of secret keys or other secret data, and without revealing said key to any third party who may have access to all of the transmissions between them. A common matrix M, shared in advance, is multiplied by a random matrix K on the sending side, and a different random matrix N on the receiving side. The matrix product KM is sent from the sending side to the receiving side, and the matrix product MN is sent from the receiving side to the sending side. Both sides produce the common matrix product KMN, and use it for producing a symmetric key for encrypted communications. | 2012-06-28 |
| 20120166810 | Biometrically Securing and Transmitting Data - The disclosed technology combines biometric authentication and data transmission technologies to provide for secure storing of private information and wireless transmission of the private information in order to perform predefined tasks. A user may securely store his private information in an electronic database. To access the private information stored securely, the user provides his biometric data. Upon successful biometric authentication of the user, authorization is granted to the user to access the private information stored in the electronic database. Upon successful biometric authentication, the private information can be transmitted via short range wireless communication. Optionally, upon successful biometric authentication, the private information can be transmitted via wireless communication over a computer network. | 2012-06-28 |
| 20120166811 | System and Method for Efficiently Detecting Additions and Alterations to Individual Application Elements for Multiple Releases of Applications in the Environments where the Applications can be Altered - Systems, methods and computer readable media for detecting customization of an application running on a customer's environment are described. An application's original source can maintain a master hash registry for an application. The master hash registry includes valid and invalid hash codes for all objects in the application across all versions of the application. This master hash registry may be provided to the customer. A customization detection system loads a master hash registry to memory. The customization detection system may then retrieve an application object from the application, generate hash values for the object and compare these values with the object's master hash registry values to determine whether the application object is new or whether it has been customized in a supportable or unsupportable manner. The customization detection system may then set the object's customization status based on the results of the comparison. | 2012-06-28 |
| 20120166812 | METHOD, APPARATUS AND SYSTEM FOR SECURE COMMUNICATION OF RADIO FRONT END TEST/CALIBRATION INSTRUCTIONS - Techniques for a programmable engine to provide security mechanisms protecting information which is in support of testing and/or calibration a radio front end. In an embodiment, test/calibration information is to be communicated to, from or within the programmable engine for processing by a particular resource of the programmable engine. In another embodiment, test/calibration is exchanged along a dedicated hardware data path between a security module of the programmable engine and an execution module of the programmable engine, wherein any data exchanged in the dedicated hardware data path is only accessible from the dedicated hardware data path via one or both of the security module and the execution module. | 2012-06-28 |
| 20120166813 | REPRODUCING DATA FROM OBFUSCATED DATA RETRIEVED FROM A DISPERSED STORAGE NETWORK - A method begins by a processing module processing a data retrieval request that identifies data, wherein the data is stored as a plurality of sets of encoded data slices, wherein one or more encoded data slices of the plurality of sets of encoded data slices has been replaced with one or more encoded secret slices of secret data. The method continues with the processing module receiving at least a threshold number of the plurality of sets of encoded data slices and determining whether a secret data extraction process is initiated. The method continues with the processing module obtaining an inter-dispersing function to extract the one or more encoded secret slices to produce extracted encoded secret slices and decoding the extracted encoded secret slices in accordance with secret dispersed storage error encoding parameters to reproduce the secret data when the secret data extraction process is initiated. | 2012-06-28 |
| 20120166814 | MEMORY CARD, HOST DEVICE, CERTIFICATION ISSUING DEVICE, MEMORY CONTROLLER, MEMORY CHIP, METHOD OF PRODUCING MEMORY CARD, AND DATA READING AND WRITING METHOD - A memory card includes one or more memory chips that store memory quality data including a storage volume value; and a certification storing unit that stores a storage volume certification including a sum storage volume value of one or more memory chips. | 2012-06-28 |
| 20120166815 | SECURE DATA PARSER METHOD AND SYSTEM - A secure data parser is provided that may be integrated into any suitable system for securely storing and communicating data. The secure data parser parses data and then splits the data into multiple portions that are stored or communicated distinctly. Encryption of the original data, the portions of data, or both may be employed for additional security. The secure data parser may be used to protect data in motion by splitting original data into portions of data, that may be communicated using multiple communications paths. | 2012-06-28 |
| 20120166816 | Auxiliary Functionality for Pixel Data - The various methods and systems described herein are directed to supplying a secure channel for software executing on a host computer. The methods and systems address and provide solutions for an attack model in which rogue software executing on the host computer attempts to inappropriately obtain or otherwise manipulate data. Some embodiments can provide pixel data that can be kept confidential (in that untrusted software applications cannot read the data off of the display screen). In addition, other embodiments can preserve the integrity of the pixel data by detecting whether the pixel data has been inappropriately manipulated. Various embodiments are based on a decryption engine that is located on a video card very late in the video processing chain such that programmatic access to decrypted pixel data is denied. | 2012-06-28 |
| 20120166817 | Secured Data Display Method, Data Storage Device and Encryption Chip Card - The present invention discloses secured data display method capable of non-intrusively and non-destructively displaying secured data in a secured data storage device of an encryption system. The secured data display method includes steps of receiving and storing a secured data transmitted via a first encryption mechanism according to a first communication protocol, and receiving an output data transmitted by a data access device of the encryption system according to a second communication protocol. The secured data and the output data comprise a same content. | 2012-06-28 |
| 20120166818 | SYSTEMS AND METHODS FOR SECURE MULTI-TENANT DATA STORAGE - Systems and methods are provided for transmitting data for secure storage. For each of two or more data sets, a plurality of shares are generated containing a distribution of data from an encrypted version of the data set. The shares are then stored in a shared memory device, wherein a data set may be reconstructed from a threshold number of the associated plurality of shares using an associated key. Also provided are systems and methods for providing access to secured data. A plurality of shares containing a distribution of data from an encrypted version of a data set are stored in a memory device. A client is provided with a virtual machine that indicates the plurality of shares, and the capability to reconstruct the data set from the plurality of shares using an associated key. | 2012-06-28 |
| 20120166819 | Power Management of Optical Access Networks - Power management is performed in an optical access network to reduce energy consumption. Service information is determined about traffic at the first node. Power management is controlled based on the determined service information. The first node can control power management at the first node and/or the second node. The first node can categorize traffic according to service and determine traffic activity per service. Service information can include service type of the traffic, traffic class of the traffic, and/or quality of service requirements of the traffic. | 2012-06-28 |
| 20120166820 | RESTART CIRCUIT OF SERVER - A restart circuit includes a voltage input terminal, a diode, an electronic switch, a restart signal output terminal, and a timing chip. The voltage input terminal is connected to an anode of the diode. A cathode of the diode is connected to a power pin and a reset pin of the chip and connected to a trigger pin of the chip through a resistor. A trigger pin of the chip is grounded through a capacitor. A count pin of the chip is grounded through a capacitor. A discharge pin and a threshold pin of the chip are connected and grounded through a resistor and a capacitor in that order. An output pin of the chip is connected to a control terminal of the switch. A first terminal of the switch is grounded. A second terminal of the switch is connected to the restart signal output terminal. | 2012-06-28 |
| 20120166821 | START-UP CONTROL APPARATUS AND METHOD - A start-up control apparatus includes a switch, an advanced configuration and power interface (ACPI) controller, a power supply, and a control chip. The switch creates a trigger signal. The trigger signal includes a first falling-edge and a first rising-edge. The control chip includes a control module and a monitoring module. | 2012-06-28 |
| 20120166822 | MECHANISMS FOR ENABLING POWER MANAGEMENT OF EMBEDDED DYNAMIC RANDOM ACCESS MEMORY ON A SEMICONDUCTOR INTEGRATED CIRCUIT PACKAGE - Power management of an embedded dynamic random access memory (eDRAM) by receiving an eDRAM power state transition event and determining both the current power state of the eDRAM and the next power state of the eDRAM from the power states of: a power-on state, a power-off state, and a self-refresh state. Using the current power state and the next power state to determine whether a power state transition is required, and, in the case that a power state transition is required, transition the eDRAM to the next power state. Power management is achieved because transitioning to a power-off state or self-refresh state reduces the amount of power consumed by the eDRAM as compared to the power-on state. | 2012-06-28 |
| 20120166823 | MECHANISMS FOR UTILIZING EFFICIENCY METRICS TO CONTROL EMBEDDED DYNAMIC RANDOM ACCESS MEMORY POWER STATES ON A SEMICONDUCTOR INTEGRATED CIRCUIT PACKAGE - Power management of an embedded dynamic random access memory (eDRAM) using collected performance counter statistics to generating a set of one or more eDRAM effectiveness predictions. Using a set of one or more eDRAM effectiveness thresholds, each corresponding to one of the set of eDRAM effectiveness predictions, to determine whether at least one eDRAM effectiveness prediction has crossed over threshold. In the case that at least one eDRAM effectiveness prediction has crossed over its threshold, transitioning the eDRAM to a new power state. Power management is achieved by transitioning to a power-off state or self-refresh state and reducing the amount of power consumed by the eDRAM as compared to a power-on state. | 2012-06-28 |
| 20120166824 | POWER CONTROLLER IN INFORMATION PROCESSOR - A power controller ( | 2012-06-28 |
| 20120166825 | Controlling the Power Consumption of Computers - A system comprising a group of computers including a group power controller is provided. Each computer of the group has a performance monitor for monitoring a measure of performance of the computer. The measure of performance is the value of at least one performance metric of the computer excluding contributions to the activity metric(s) of one or more predetermined activities. The group power controller is configured to allocate to the computers of the group shares of a maximum power consumption of the group. The shares are allocated in dependence on the monitored measures of performance. Each computer of the group has an individual power controller configured to limit the power consumption of the computer to the share allocated by the group power controller. | 2012-06-28 |
| 20120166826 | BUS-HANDLING - A processor, comprising a processing unit having an active state and a sleep state in which at least one of its sub-sections is inactive and a communication port adapted to receive signals from external units over a bus, which is configured to be not fully operative when the processor is in the sleep state. The processor additionally includes a bus monitoring unit configured to stall the bus responsive to identifying transmissions on the bus directed to the communication port, while the processing unit is in the sleep state and to indicate to the communication port that a transmission started while it was in the sleep state. | 2012-06-28 |
| 20120166827 | Method and Apparatus for Reducing Dynamic Power within System-on-a-Chip Routing Resources - A method for saving power in transmission of data across buses. By knowing the power characteristics of a bus and characteristics of data to be transmitted across the bus, the data can be encoded in such a fashion as to conserve system power over transmitting the same data in an unencoded format across the bus. The encoding method may be selected before transmission of the data across the bus, and may change depending on the data to be transmitted across the bus. | 2012-06-28 |
| 20120166828 | METHOD AND SYSTEM FOR POWER CONTROL TO MINIMIZE POWER CONSUMPTION - The embodiments provide a system and method for device power control. In particular, the embodiments enable a device, such as a direct attached storage device coupled to a host, to enter into a mode that consumes less power. In one embodiment, the mode is self-initiated and triggered based on a preset timeout of non-use or other condition. Alternatively, this reduced power mode may be initiated based on a request by the host. During the reduced power mode of operation, the device may continue to appear active or on-line to its host. However, if its non-use persists, the device may employ a progression of power saving actions. If needed by the host, the direct attached storage device is configured to respond as if it were on-line and reverse one or more of the progression of power saving actions. | 2012-06-28 |
| 20120166829 | METHOD AND SYSTEM FOR MANAGING A STORAGE NETWORK TO REDUCE POWER CONSUMPTION - Methods, computer systems, and computer program products are provided for managing a storage network system is provided. The storage network system includes a plurality of zones. Each of the plurality of zones includes at least one storage network device. A link-down event associated with one of the storage network devices is detected. One of the plurality of zones is identified is identified as being unused if the zone is not accessed by another of the storage network devices in another of the plurality of zones and if the zone does not access another of the storage network devices in another of the plurality of zones. | 2012-06-28 |
| 20120166830 | OFFLINE SETUP RECORDING DEVICE AND METHOD AND ELECTRONIC APPARATUS USING THE SAME - An offline setup recording device used in an electronic apparatus is illustrated. When the electronic apparatus is power on, the total energy storage unit is charged by a power supply through the unidirectional conduction unit, such that a total voltage is stored therein. When the electronic apparatus is power off, a user operates the automatically recovering switch to be conducted, such that the state energy storage unit is charged by the total energy storage through the automatically recovering switch, and a storage voltage signal is stored therein. When the electronic apparatus is power on again, the reading unit receives the power, reads out the storage voltage signal, and outputs a read voltage signal accordingly. | 2012-06-28 |
| 20120166831 | SYSTEM FOR CONTROLLING POWER CONSUMPTION OF SEMICONDUCTOR INTEGRATED CIRCUIT - According to one embodiment, a semiconductor integrated circuit has peripheral devices and a clock supply control circuit which controls supply of clock signals to the devices. An operating system for controlling execution of tasks includes a task information registration unit, a dispatcher, a semaphore managing unit, and a power consumption managing unit. The task information registration unit registers peripheral device use information as task information. The dispatcher controls start of any one of the tasks when an execution request of the task is received and to control switching task execution. The semaphore managing unit to manage state of acquisition and store semaphores. The power consumption managing unit refers to the peripheral device use information and the semaphores, and issues a request to the clock supply control circuit so as to supply or stop the clock signal, in accordance with execution states of the tasks and acquisition state of the semaphores. | 2012-06-28 |
| 20120166832 | DISTRIBUTED MANAGEMENT OF A SHARED POWER SOURCE TO A MULTI-CORE MICROPROCESSOR - Microprocessors are provided with decentralized logic and associated methods for indicating power related operating states, such as desired voltages and frequency ratios, to shared microprocessor power resources such as a voltage regulator module (VRM) and phase locked loops (PLLs). Each core is configured to generate a value to indicate a desired operating state of the core. Each core is also configured to receive a corresponding value from each other core sharing the applicable resource, and to calculate a composite value compatible with the minimal needs of each core sharing the applicable resource. Each core is further configured to conditionally drive the composite value off core to the applicable resource based on whether the core is designated as a master core for purposes of controlling or coordinating the applicable resource. The composite value is supplied to the applicable shared resource without using any active logic outside the plurality of cores. | 2012-06-28 |
| 20120166833 | INFORMATION PROCESSING DEVICE, CONTROL METHOD AND CONTROL PROGRAM - An information processing device ( | 2012-06-28 |
| 20120166834 | COMPUTING LOAD MANAGEMENT METHOD AND SYSTEM - A load management method and system. The method includes detecting and monitoring by a computing system, a frequency signal associated with an input voltage signal used for powering computing apparatuses at a specified location. The computing system compares the frequency signal to a predetermined frequency value. The computing system determines that the frequency signal comprises a first value that is not equal to the predetermined frequency value. The computing system calculates a difference value between the first value and the predetermined frequency value. The computing system compares the difference value to a second value and analyzes a power demand profile. The computing system enables a load adjustment modification process associated with the plurality of power consumption devices based on the difference value and the power demand profile. The computing system generates and stores a report associated with the load adjustment modification process. | 2012-06-28 |
| 20120166835 | ENERGY LOAD MANAGEMENT METHOD AND SYSTEM - A modification method and system. The method includes detecting and monitoring by a computing system, a frequency signal associated with an input voltage signal used for powering a plurality of power consumption devices at a specified location. The computing system compares the frequency signal to a predetermined frequency value. The computing system determines that the frequency signal comprises a first value that is not equal to the predetermined frequency value. The computing system calculates a difference value between the first value and the predetermined frequency value. The computing system compares the difference value to a second value. The computing system enables a load adjustment modification process associated with the plurality of power consumption devices. The computing system generates and stores a report associated with the load adjustment modification process. | 2012-06-28 |
| 20120166836 | SYSTEM FOR CONSERVING BATTERY LIFE IN A BATTERY OPERATED DEVICE - A battery operated device includes a receiver for receiving a transmission that includes a postamble. A sensor, in a tire, measures a parameter of the tire and outputs data indicative of the parameter. A microprocessor is coupled to the receiver and the sensor. The microprocessor is configured to periodically partially awaken to determine whether the transmission is likely a forward link packet (FLP) by examining the postamble, and to transmit the data in a reverse link packet (RLP) in response to confirming that the transmission is a FLP. | 2012-06-28 |
| 20120166837 | DECENTRALIZED POWER MANAGEMENT DISTRIBUTED AMONG MULTIPLE PROCESSOR CORES - A multi-core processor provides a configurable resource shared by two or more cores, wherein configurations of the resource affect the power, speed, or efficiency with which the cores sharing the resource are able to operate. Internal core power state management logic configures each core to participate in a de-centralized inter-core power state discovery process to discover a composite target power state for the shared resource that is a most restrictive or power-conserving state that will not interfere with any of the corresponding target power states of each core sharing the resource. The internal core power state management logic determines whether the core is a master core authorized to configure the resource, and if so, configures that resource in the discovered composite power state. The de-centralized power state discovery process is carried out between the cores on sideband, non-system bus wires, without the assistance of centralized non-core logic. | 2012-06-28 |
| 20120166838 | METHOD AND SYSTEMS FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING ON-OFF KEYING FOR POWER CONTROL - Systems and a method for controlling power of a device with power management software are described. In one embodiment, a computer implemented method initiates power control having ON-OFF keying to control power consumption of a device for energy efficiency and energy conservation. An ON-OFF period of the ON-OFF keying for the device is computed. The method sets a target frequency, a target supply voltage, and a power gate control for the device based on the ON-OFF keying. | 2012-06-28 |
| 20120166839 | METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING ENERGY EFFICIENT PROCESSOR THERMAL THROTTLING USING DEEP POWER DOWN MODE - Embodiments of the invention relate to energy efficient and conserving thermal throttling of electronic device processors using a zero voltage processor state. For example, a processor die may include a power control unit (PCU), and an execution unit having power gates and a thermal sensor. The PCU is attached to the thermal sensor to determine if a temperature of the execution unit has increased to greater than an upper threshold, such as while the execution unit is processing data in an active processor power state. The PCU is also attached to the power gates so that upon such detection, it can change the active processor power state to a zero processor power state to reduce the temperature of the execution unit. When the sensor detects that the temperature has decreased to less than a lower threshold, the PCU can change the processor power state back to the active state. | 2012-06-28 |
| 20120166840 | METHOD AND APPARATUS FOR IMPROVING THE RESUME TIME OF A PLATFORM - A method and apparatus for improving the resume time of a platform. In one embodiment of the invention, the context of the platform is saved prior to entering an inactive state of the platform. When the platform is switched back to an active state, it reads the saved context and restores the platform to its original state prior to entering the inactive state. In one embodiment of the invention, the platform determines whether it should compress the saved context before storing it in a non-volatile memory based on the operating condition of the platform. This allows the platform to select the optimum method to allow faster resume time of the platform. | 2012-06-28 |
| 20120166841 | EVENT SYSTEM AND TIMEKEEPING FOR BATTERY MANAGEMENT AND PROTECTION SYSTEM - Operating a battery management and protection system includes generating a set of events each of which has a respective frequency F/n | 2012-06-28 |
| 20120166842 | THERMALLY DOWNWARD SCALABLE SYSTEM - An apparatus may comprise a power management system. Other embodiments are described and claimed. | 2012-06-28 |
| 20120166843 | METHOD, APPARATUS AND SYSTEM TO TRANSITION SYSTEM POWER STATE OF A COMPUTER PLATFORM - Techniques to tie a processor power state transition on a platform to another power state transition on the platform. In an embodiment, processor governor functionality of an operating system detects an idle condition of a processor executing the operating system. Based on the processor idle condition and one or more indicated conditions of other platform devices, tying logic may determine a system power state to transition the platform to. For example, the tying logic may select from one of a plurality of idle standby system power states. | 2012-06-28 |
| 20120166844 | POWER MANAGEMENT IN ELECTRONIC SYSTEMS - In one embodiment, an electronic apparatus comprises at least one processor and a computer readable medium coupled to the processor and comprising logic instructions encoded in the computer readable medium, wherein the instructions, when executed in a processing system, cause the processing system to perform operations comprising initializing a direct memory access profiler in an electronic system, wherein the direct memory access is coupled to a policy manager in the electronic system, measuring at least one memory consumption characteristic of the electronic system, communicating the at least one memory consumption characteristic to a policy manager of the electronic system, and using the at least one memory consumption characteristic to adjust a power state of the electronic system. | 2012-06-28 |
| 20120166845 | POWER STATE SYNCHRONIZATION IN A MULTI-CORE PROCESSOR - A multi-core processor includes microcode distributed in each core enabling each core to participate in a de-centralized inter-core state discovery process. In a related microcode-implemented method, states of a multi-core processor are discovered by at least two cores participating in a de-centralized inter-core state discovery process. The inter-core state discovery process is carried out through a combination of microcode executing on each participating core and signals exchanged between the cores through sideband non-system-bus communication wires. The discovery process is unmediated by any centralized non-core logic. Applicable discoverable states include target and composite power states, whether and how many cores are enabled, the availability and distribution of various resources, and hierarchical structures and coordination systems for the cores. The inter-core state discovery process may be carried out in accordance with various hierarchical coordination systems involving chained inter-core communications. | 2012-06-28 |
| 20120166846 | USB SYSTEM AND POWER MANAGEMENT MODULE AND METHOD THEREOF - A power management module is configured to set up a power mode of a computer system. A peripheral device having a Universal Serial Bus (USB) is connected to the computer system. The power management module includes an Operating System (OS) and a filter driver. The OS is configured to set up the power mode of the computer system, and the filter driver is configured to change the power mode of the computer system according to a packet transmitting/receiving status of the peripheral device. | 2012-06-28 |
| 20120166847 | BATTERIES FOR ELECTRIC TOOLS - A battery for an electric tool includes at least one battery cell, a peripheral device operable to detect a battery condition of the at least one battery cell, and a microcomputer communicating with the peripheral device. The microcomputer periodically operates the peripheral device for detecting the battery condition during the time when the battery is not electrically connected to the electric tool. | 2012-06-28 |
| 20120166848 | ADAPTIVE NETWORK AND METHOD - A plurality of modules interact to form an adaptive network in which each module transmits and receives data signals indicative of the proximity of objects. A central computer accumulates the data produced or received and relayed by each module. One of the modules is operable as a leaf node having a sleep mode to conserve energy and an interactive mode. The central computer can send a message to the leaf node commanding it to stay awake in order to receive subsequent communications. | 2012-06-28 |
| 20120166849 | SYSTEMS AND METHODS FOR CONTROL OF INTEGRATED CIRCUITS COMPRISING BODY BIASING SYSTEMS - Systems and methods for control of integrated circuits comprising body-biasing systems. In accordance with a first embodiment of the present invention, a desirable power condition of a computer system comprising a microprocessor is determined. Body biasing voltage information corresponding to the power condition is accessed. A voltage supply coupled to a body terminal of the microprocessor is commanded to generate a voltage corresponding to the body biasing voltage information corresponding to the power condition. | 2012-06-28 |
| 20120166850 | INFORMATION PROCESSING APPARATUS AND METHOD FOR CONTROLLING INFORMATION PROCESSING APPARATUS - An information processing apparatus includes a storage unit configured to store data, a supply unit configured to supply electric power to the storage unit, a determination unit configured to determine whether to cause the information processing apparatus to operate in a power saving mode, a measuring unit configured to measure an elapsed time after a power source of the information processing apparatus is turned on and until the determination unit determines to cause the information processing apparatus to operate in a power saving mode, and a control unit configured to control the supply unit to decrease electric power supplied from the supply unit to the storage unit at a timing determined based on the elapsed time and a predetermined reference time, in case that the determination unit determines to cause the information processing apparatus to operate in a power saving mode. | 2012-06-28 |
| 20120166851 | SYSTEMS AND METHODS FOR SHARING A WIRELESS ANTENNA IN A HYBRID ENVIRONMENT - Embodiments operating shared peripherals in a hybrid computing system are described. Embodiments control a shared wireless antenna variously between a primary system and a secondary system, where the secondary system is detachable from the primary system and operates as an independent computing device in the disconnected state, while operating as a display device in the connected state. | 2012-06-28 |
| 20120166852 | METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING IMPROVED PROCESSOR CORE DEEP POWER DOWN EXIT LATENCY BY USING REGISTER SECONDARY UNINTERRUPTED POWER SUPPLY - Embodiments of the invention relate to improving exit latency from computing device processor core deep power down. Processor state data may be maintained during deep power down mode by providing a secondary uninterrupted voltage supply to always on keeper circuits that reside within critical state registers of the processor. When these registers receive a control signal indicating that the processor power state is going to be reduced from an active processor power state to a zero processor power state, they write critical state data from the critical state register latches to the keeper circuits that are supplied with the uninterrupted power. Then, when a register receives a control signal indicating that a processor power state of the processor is going to be increased back to an active processor power state, the critical state data stored in the keeper circuits is written back to the critical state register latches. | 2012-06-28 |
| 20120166853 | POWER SUPPLY SYSTEM CAPABLE OF AUTOMATICALLY ADJUSTING OPERATING VOLTAGE OF CPU - An exemplary power supply system for a CPU, includes a power managing module and a computer system module. The power managing module supplies a current operating voltage to the CPU. The computer system module electrically communicates with the power managing module and the CPU, obtains a next operating voltage required in a next program carried out by the CPU, and controls the power managing module to adjust the current operating voltage to be the next operating voltage before the next program is carried out. | 2012-06-28 |
| 20120166854 | Controlling Current Transients In A Processor - In one embodiment, a processor includes a core with a front end unit, at least one execution unit, and a back end unit. Multiple voltage drop detectors can be located within the core each to output a voltage drop signal when a detected voltage falls below a threshold voltage. In turn, a current transient logic coupled to receive the voltage drop signals can control a micro-architectural parameter of at least one of the front end unit, execution unit and back end unit responsive to receipt of a voltage drop signal. Other embodiments are described and claimed. | 2012-06-28 |
| 20120166855 | EVENT SYSTEM AND TIMEKEEPING FOR BATTERY MANAGEMENT AND PROTECTION SYSTEM - Operating a battery management and protection system includes generating a set of events each of which has a respective frequency F/n | 2012-06-28 |
| 20120166856 | SIGNAL SYNCHRONIZING SYSTEMS AND METHODS - Signal synchronizing systems and methods are disclosed. A signal synchronizing system includes a sequential logic circuit to receive an input signal and to generate a plurality of intermediate signals from the input signal based on a clock signal. A logic circuit combines the intermediate signals to generate an output signal. A signal receiver includes a microcontroller and a signal synchronizer coupled to the microcontroller. The signal synchronizer includes a sequential logic circuit to receive an input signal from a transmitter and to generate a plurality of intermediate signals from the received input signal based on a clock signal. A logic circuit combines the intermediate signals to generate an output signal. | 2012-06-28 |
| 20120166857 | INTERFACE CIRCUIT, INVERTER DEVICE, INVERTER SYSTEM, AND TRANSMITTING AND RECEIVING METHOD - An interface circuit includes a general-purpose CPU configured to transmit a clock to a serial encoder with which bidirectional serial communication of clock synchronization type is to be performed, the CPU being configured to transmit and receive data to and from the serial encoder; and an additional circuit configured to detect a start bit of reception data transmitted from the serial encoder. The general-purpose CPU starts counting the number of bits of the reception data in response to a detection signal from the additional circuit, the detection signal indicating the detection of the start bit. The CPU stops transmitting the clock to the serial encoder upon completion of counting a predetermined number of bits of the reception data. | 2012-06-28 |
| 20120166858 | Apparatus and Method for Processing Wirelessly Communicated Data and Clock Information Within an Electronic Device - An electronic device ( | 2012-06-28 |
| 20120166859 | METHOD AND APPARATUS FOR GENERATING A SYSTEM CLOCK SIGNAL - An apparatus includes a processor, a clock recovery circuit and a frequency locked loop. The processor receives a system clock signal to clock operations of the processor; and the clock recovery circuit recovers a clock signal from data communication occurring over a bus. The frequency locked loop receives the clock signal from the clock recovery circuit as a reference clock signal, and the frequency locked loop is adapted to lock onto the clock signal provided by the clock recovery circuit to provide the system clock signal. | 2012-06-28 |
| 20120166860 | SEQUENTIAL ON-CHIP CLOCK CONTROLLER WITH DYNAMIC BYPASS FOR MULTI-CLOCK DOMAIN TESTING - A controller includes a clock control unit configured to provide a first output to test circuitry and a bypass unit configured to provide a second output to a further controller. The controller is configured to cause the bypass unit to output the second output and to optionally cause the clock control unit to output the first output. | 2012-06-28 |
| 20120166861 | METHOD FOR ADJUSTING CLOCK FREQUENCY OF A PROCESSING UNIT OF A COMPUTER SYSTEM AND RELATED DEVICE - A method for adjusting clock frequency of a processing unit of a computer system includes calculating a busyness ratio of the processing unit according to a status signal provided by the processing unit, determining whether the busyness ratio is in a busyness ratio range, when the busyness ratio is not in the busyness ratio range, determining whether a calculation result generated according to a clock frequency of the processing unit and a frequency difference is in a frequency range, and when the calculation result is in the frequency range, adjusting the clock frequency of the processing unit according to the calculation result and outputting the adjusted clock frequency to a clock generator, wherein the busyness ratio range, the frequency range and the frequency difference are decided according to an operation state of a peripheral unit of the computer system. | 2012-06-28 |
| 20120166862 | METHOD FOR MEASURING A TEMPERATURE IN AN ELECTRONIC DEVICE HAVING A BATTERY AND A MEMORY DEVICE - A temperature sensing device can be embedded in a memory module or system in order to sense the temperature of the memory module or system. One oscillator generates a temperature variable signal that increases frequency as the temperature of the oscillator increases and decreases frequency when the temperature of the oscillator decreases. A temperature invariant oscillator generates a fixed width signal that is controlled by an oscillator read logic and indicates a temperature sense cycle. An n-bit counter is clocked by the temperature variable signal while the fixed width signal enables/inhibits the counter. The faster the counter counts, the larger the count value at the end of the sense cycle indicated by the fixed width signal. A larger count value indicates a warmer temperature. A smaller count value indicates a colder temperature. | 2012-06-28 |
| 20120166863 | Methods And Apparatus For Synchronizing Communication With A Memory Controller - A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals. | 2012-06-28 |
| 20120166864 | SYSTEM AND METHOD FOR DETECTING ERRORS OCCURRING IN COMPUTING DEVICE - A system and method detects errors occurring in a computing device. The computing device includes a central processing unit (CPU) and a memory. The method sets an interruption tag for the computing device and initializes the interruption tag as zero, and detects a general purpose input output (GPIO) signal output from the CPU through a GPIO interface. The method further determines whether the GPIO signal is in a first voltage level at every time interval, and adds one to the interruption tag when the GPIO signal is switched from the first voltage level to a second voltage level. In addition, the method determines that inter errors occur in the CPU if the interruption tag is equal to one, and determines that multi-bit errors occur in the memory if the interruption tag is greater than one. | 2012-06-28 |
| 20120166865 | Method, Device for Running Internet Protocol Television Service System, and Internet Protocol Television Service System - The present invention discloses a method, apparatus and system for operating an internet protocol television service system. The present invention relates to communication field, and solves the problem of poor quality of service caused by using a cold backup electronic programmer guide (EPG) server or transferring a user to other EPG server. The method includes: a backup electronic programmer guide (EPG) server receiving an obtaining instruction message sent by a service control manager, wherein the obtaining instruction message instructs the backup EPG server to obtain service information of a failed present network EPG server; the backup EPG server obtaining the service information of the failed present network EPG server according to the obtaining instruction message, and sending an obtaining response message to the service control manager after finishing obtaining the service information. | 2012-06-28 |
| 20120166866 | Fault-Tolerance And Fault-Containment Models For Zoning Clustered Application Silos Into Continuous Availability And High Availability Zones In Clustered Systems During Recovery And Maintenance - A cluster recovery and maintenance technique for a server cluster having plural nodes implementing a server tier in a client-server computing architecture. A first group of N active nodes each run a software stack comprising a cluster management tier and a cluster application tier that actively provides services on behalf of one or more client applications running in a client application tier on the clients. A second group of M spare nodes each run a software stack comprising a cluster management tier and a cluster application tier that does not actively provide client application services. First and second zones in the cluster are determined in response to an active node membership change involving one or more active nodes departing from or being added to the first group as a result of an active node failing or becoming unreachable or as a result of a maintenance operation involving an active node. | 2012-06-28 |
| 20120166867 | STORING DIRECTORY METADATA IN A DISPERSED STORAGE NETWORK - A method begins by a processing module dispersed storage error encoding data to produce encoded data slices and updating directory metadata regarding storing the data in a dispersed storage network (DSN) memory to produce updated directory metadata. The method continues with the processing module dispersed storage error encoding the updated directory metadata to produce encoded directory metadata slices and transmitting one or more data slice write requests to the DSN that each include a first transaction number. The method continues with the processing module transmitting one or more directory metadata write requests to the DSN memory, wherein the one or more directory metadata write requests includes a second transaction number, and when a favorable write response condition exists, transmitting a commit request to the DSN memory to commit storage of at least one of: the encoded data slices and the encoded directory metadata slices. | 2012-06-28 |
| 20120166868 | SEGMENTING DATA FOR STORAGE IN A DISPERSED STORAGE NETWORK - A method begins by a processing module receiving data of a file for storage in a dispersed storage network (DSN) memory and determining a segmentation scheme for storing the data. The method continues with the processing module determining how to store the data in accordance with the segmentation scheme to produce information for storing the data and generating an entry within a segment allocation table associated with the file, wherein the entry includes the information for storing the data and the segmentation scheme. The method continues with the processing module facilitating storage of the segment allocation table in the DSN memory. The method continues with the processing module segmenting the data in accordance with the segmentation scheme to produce a plurality of data segments and facilitating storage of the plurality of data segments in the DSN memory in accordance with the information for storing the data. | 2012-06-28 |
| 20120166869 | PREDICTING, DIAGNOSING, AND RECOVERING FROM APPLICATION FAILURES BASED ON RESOURCE ACCESS PATTERNS - Technologies are described herein for differentiating normal operation of an application program from error conditions to predict, diagnose, and recover from application failures. Access to resources by the application program is monitored, and resource access events are logged. Resource access patterns are established from the logged resource access events utilizing computer pattern recognition techniques. If subsequent access to resources by the application program deviates from the established patterns, then a user and/or administrator of the application program is notified of a potential error condition based on the detected deviation. In addition, sequences of resource access events that deviate from the established resources access patterns are correlated with an error condition based on a temporal proximity to the time of occurrence of the error to provide diagnostic information regarding the error. | 2012-06-28 |
| 20120166870 | METHOD AND APPARATUS FOR RECOVERING ERRORS IN A STORAGE SYSTEM - Apparatus and method for recovering errors from erroneous files in a storage system. In order to recover the errors from the erroneous files, each of at least three erroneous files stored in the storage system may be divided in half to form three sets of divided files. Three corresponding, portions from each of the three sets of divided files may be compared. A determination may be made as to whether at least two portions among the three corresponding portions are substantially identical. Based on the determination, substantially identical portions are determined to be non-erroneous portions. Then, a non-matched portion that is not substantially identical to the two substantially identical portions may be replaced with one of the non-erroneous portions. | 2012-06-28 |
| 20120166871 | Methods and Systems for Providing Fault Recovery to Side Effects Occurring During Data Processing - Embodiments may recover from faults by forming a new set of rows by removing rows associated with faulting save operations and repeating the saving and forming operations using the new set of rows until a set of rows that can be saved from the known start state without fault is determined. When the subset of successful rows is found, embodiments are able to provide assurance that no side effects (i.e., code or operations triggered by saving of a data to a particular location) have been executed on behalf of any of the failed rows (side effects from custom PL/SOQL code included) by deferring execution of triggers until an entire set of rows can be saved and committed. | 2012-06-28 |
| 20120166872 | CONDENSED FOTA BACKUP - A method and apparatus update an image stored in a memory of a device. A next block writing index n for updating a first target memory block of the memory is determined. Backup data is written to a backup block of the memory when n is an even number. The first target memory block is updated with the new data. The backup data is calculated based on a binary operation between new data corresponding to n and old data stored in a second target memory block corresponding to n+1, and the binary operation has reversibility. If n is the last block writing index, then the binary operation is not used and the backup data is the same as the new data. | 2012-06-28 |
| 20120166873 | SYSTEM AND METHOD FOR HANDLING SYSTEM FAILURE - A system and a method for handling a system failure are disclosed. The method is adapted for an information handling system having a basic input and output system and a micro-controller. The method includes the following steps: sending, via the micro-controller, a signal; checking, via the micro-controller, whether an acknowledgement is received from the basic input and output system responsive to the signal; and scanning, via the micro-controller, a type of a system failure in response to the acknowledgement being not received. | 2012-06-28 |
| 20120166874 | Wireless Device Expert System - A wireless expert system connects to a plurality of diagnostic modules and is configured to receive a complaint from a user of a wireless device, the complaint comprising data and attributes. The expert system executes a two-phase process. In the first phase, the complaint is analyzed to determine which of the diagnostic modules should be run. In the second phase, the selected diagnostic modules are run, and the user is provided with a recommended corrective action. If the action is successful, the expert system is updated with the successful resolution, providing additional assurance for future analyses. | 2012-06-28 |
| 20120166875 | Conducting an application-aware test in a virtual environment - A system and method for service aware virtualization is disclosed. The system comprises a plurality of virtual instances operating on virtualization software and a plurality of service manager modules operating on the virtualization software. Each service manager module is coupled to a separate virtual instance and configured to interface with an operation of guest software operating within the virtual instance on the virtualization software. A management interface coupled to the service manager modules interfaces with the plurality of virtual instances. | 2012-06-28 |
| 20120166876 | APPLICATION INTEGRATION TESTING - Application testing is disclosed. A definition of a test to be performed on a subject application is received in a generic form not specific to the subject application. The test is performed by exchanging data with the subject application, as required to perform the test, using a test connector application associated with the subject application to do at least one of (1) convert an input data to be supplied to the subject application during the test from a generic data format not specific to the subject application into an application-specific data format associated with the subject application, if the application-specific data format is different than the generic data format and (2) normalize an output data received from the subject application in the application-specific data format into the generic data format not specific to the subject application, if the application-specific data format is different than the generic data format. | 2012-06-28 |
| 20120166877 | SYSTEM AND METHOD FOR GRAMMAR BASED TEST PLANNING - The present disclosure generally relates to the testing of a system that includes software or hardware components. In some embodiments, a testing framework generates a set of test cases for a system under test using a grammar. Each test case may perform an action, such as provide an input to the system under test, and result in an output from the system under test. The inputs and outputs are then compared to the expected results to determine whether the system under test is performing correctly. Prior to generating the set of test cases from the grammar, the testing framework processes the grammar to identify attributes of the test cases to be derived from the grammar and facilitates the modification of the grammar. | 2012-06-28 |
| 20120166878 | Methods and Systems for Diagnosing Hardware and Software Faults Using Time-Stamped Events - A transportation vehicle including a high-resolution clock, an electronic network including two or more tasks, including first and second tasks, and a memory including instructions causing a processor to classify faults in the electronic network using the clock. The steps include receiving a first fault code generated at the first task, receiving a second fault trouble code generated at the second task of the electronic system in response to a second fault, and identifying an execution cycle offset associated with the first and second tasks using an execution schedule, and considering whether the first cycle is separated from the second cycle by the execution cycle offset identified by the schedule. The instructions also cause the processor to identify causal relationships for a plurality of faults via a pair-wise repetition of the above-described analysis for at least one combination of tasks other than the first and second tasks. | 2012-06-28 |
| 20120166879 | Computer- readable recording medium, apparatus, and method for processing data - A method for processing data includes storing a type information of a configuration element of a first data process system in association with an identification information of the configuration element in a configuration information storage part, determining the type information corresponding to a message output from the first data process system, the message including the identification information, comparing a first message group including a plurality of first messages and a second message group including a plurality of second messages, the plural second messages being stored in association with the type information of a second data process system in a message group storage part, determining whether the plural first messages match the plural second messages, and determining whether the type information of the plural first messages match the type information of the plural second messages when the plural first messages do not match the plural second messages. | 2012-06-28 |
| 20120166880 | INDEPENDENTLY BASED DIAGNOSTIC MONITORING - An independently based diagnostic system tests the execution of a processor. The processor is arranged to provide a diagnostic output that provides a pre-determined time-variant signal. The independently based diagnostic system has an independent basis from which to evaluate the pre-determined time-variant signal. The independent basis can be, for example, an independent time base that is separately generated from the processor time base used to clock the processor and/or an independent voltage source that is separate from the processor power supply. The independently based diagnostic system provides progressive notifications of the results of successive evaluations of the pre-determined time-variant signal. | 2012-06-28 |
| 20120166881 | COMMUNICATION DEVICE, AND COMPUTER READABLE MEDIUM AND CONTROL METHOD FOR THE SAME - A communication device configured to be connected with a public network and an IP network is provided, the communication device including a communication controller that selectively performs one of a public line communication process via the public network and an IP communication process via the IP network. When determining that a redialing process to reattempt the IP communication process via the IP network is unlikely to be successfully performed, the communication controller performs a fallback process to attempt the public line communication process via the public network after switching from the IP communication process via the IP network to the public line communication process via the public network, in a situation where a setting for performing the fallback process is configured. When determining that the redialing process via the IP network is not unlikely to be successfully performed, the communication controller performs the redialing process. | 2012-06-28 |
| 20120166882 | METHODS AND TOOLS TO DEBUG COMPLEX MULTI-CORE, MULTI-SOCKET QPI BASED SYSTEM - Methods and apparatus relating to debugging complex multi-core and/or multi-socket systems are described. In one embodiment, a debug controller detects an event corresponding to a failure in a computing system and transmits data corresponding to the event to one of the other debug controllers in the system. Other embodiments are also disclosed and claimed. | 2012-06-28 |
| 20120166883 | SYSTEM, PROGRAM, AND METHOD FOR COLLECTING ERRORS WHICH OCCUR WHILE A USER USES A COMPUTER - A method, computer program product, and computer system for collecting errors which occur while a user uses a computer includes collecting log information on an operating environment including an operating procedure from a computing device associated with a user; accumulating the collected log information; identifying, from the log information, a second operating procedure similar to the operating procedure, wherein the second operating procedure had an error occur and no longer includes the error, in response to receiving the log information corresponding to the operating procedure in which the error occurs; and providing the user with the second operating procedure included in the searched log information. | 2012-06-28 |
| 20120166884 | LEVERAGING THE RELATIONSHIP BETWEEN OBJECT IDs AND FUNCTIONS IN DIAGNOSING SOFTWARE DEFECTS DURING THE POST-DEPLOYMENT PHASE - A hashing tool can be used to generate Object UIDs from a software application. The software application can be tested. A change and release management system can receive Object UIDs involved in a defect uncovered during the testing. The change and release management system can receive names of functions involved in the defect uncovered during the testing and defect fixing. A graphical representation of function names versus Object UIDs for which the defect occurred can be created. | 2012-06-28 |
| 20120166885 | SYSTEM AND METHOD FOR TESTING HARD DISK DRIVE OF COMPUTING DEVICE - A system and method test serial attached SCSI (SAS) hard disk drives (HDDs) of a computing device. The computing device includes a SAS backpanel, and the SAS backpanel includes one or more connectors that are respectively connected to the SAS HDDs. An identification (ID) of each of the connectors and an SCSI address of each of the SAS HDDs are obtained. A predefined file is created, and the obtained ID of each connector and the SCSI address of each SAS HDD are recorded into the predefined file. An SCSI address of a SAS HDD to be tested is obtained from the predefined file, and functions of the SAS HDD are tested. An ID of the connector connected to the SAS HDD is obtained from the predefined file, and is displayed on a display device if one or more of the functions are abnormal. | 2012-06-28 |
| 20120166886 | NON-DISRUPTIVE FAILOVER OF RDMA CONNECTION - A novel RDMA connection failover technique that minimizes disruption to upper subsystem modules (executed on a computer node), which create requests for data transfer. A new failover virtual layer performs failover of an RDMA connection in error so that the upper subsystem that created a request does not have knowledge of an error (which is recoverable in software and hardware), or of a failure on the RDMA connection due to the error. Since the upper subsystem does not have knowledge of a failure on the RDMA connection or of a performed failover of the RDMA connection, the upper subsystem continues providing requests to the failover virtual layer without interruption, thereby minimizing downtime of the data transfer activity. | 2012-06-28 |
| 20120166887 | Monitoring multiple data transfers - Trace circuitry for monitoring a behaviour of at least one processor and for generating items of trace data indicative of processing activities of said at least one processor executing a stream of instructions is disclosed. The stream of instructions comprises different types of instructions, each type specifying a different operation, at least one type of instruction comprising a multiple transfer instruction specifying a plurality of data transfers. The trace circuitry is responsive to detection of the at least one processor executing at least one of the multiple transfer instructions and to an indication that at least one of the plurality of data transfers is to be traced: to output for each of the data transfers to be traced a value indicative of a predetermined index value associated with the data transfer, the at least one multiple transfer instruction having predetermined index values associated with each of the plurality of data transfers, such that the predetermined index value provides individual identification of each of the data transfers. | 2012-06-28 |
| 20120166888 | METHOD AND SOFTWARE PROGRAM PRODUCT FOR DETERMINING THE QUALITY OF AN INFORMATION TECHNOLOGY SYSTEM - The present embodiments disclose a method and an associated computer program product for determining the quality of an information technology (IT) system including a plurality of hardware units and software modules. A total score value for the IT system is calculated from different score values ascertained independently of one another. The different score values are measures for deviations of the quality of the hardware units or the software modules from first predefinable target values. The total score value is a measure of a deviation of the quality of the IT system from a second predefinable target value. | 2012-06-28 |
| 20120166889 | METHOD AND A SYSTEM FOR PERFORMING A TWO-PHASE COMMIT PROTOCOL - The invention provides an enhanced two phase commit process to perform a transaction started by an application program and involving access to one or more resources managed by respective resource managers. The method comprises the steps of: enlisting the resource managers participating in the transaction, said enlisting step including associating a priority rank with each identified resource manager based on predefined priority rules; sending a prepare signal to said enlisted resource managers to begin the process of committing the transaction; and if a ready signal is received from all resource managers in response to the prepare signal, committing the resource managers in the order defined from the priority ranks associated with the resource managers. | 2012-06-28 |
| 20120166890 | ERROR DETECTION IN FIFO QUEUES USING SIGNATURE BITS - A first in, first out (FIFO) queue includes logic to provide detection of operational errors in the FIFO queue. The FIFO queue includes entries to store data written to the FIFO queue and signature bits, each signature bit corresponding to one of the entries. A test pattern and a read signature register includes a number of bits greater than a depth of the FIFO queue. A comparator compares the test pattern to the read signature register and output an error signal indicating whether the test pattern matches the read signature register. | 2012-06-28 |
| 20120166891 | TWO-LEVEL SYSTEM MAIN MEMORY - Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory. | 2012-06-28 |
| 20120166892 | ORPHAN OBJECT TRACKING FOR OBJECTS HAVING ACQUIRE-RELEASE SEMANTICS - A method for object tracking of resource objects with acquire and release semantics can include instrumenting both an acquisition method and a release method of a resource object to write a reference to the resource object to an open object set upon acquiring the resource object, and to remove the reference to the resource object in the open object set upon releasing the resource object. The method also can include determining whether the resource object both has been flagged for garbage collection in the virtual machine and also remains referenced in the open object set. Finally, the method can include generating an error record in the virtual machine responsive to determining the resource object to have been both flagged for garbage collection in the virtual machine and also remaining referenced in the open object set. | 2012-06-28 |
| 20120166893 | Recording and Preventing Crash in an Appliance - A computer implemented method for recording a crash in an appliance is provided. The method includes the following steps: running a core process to perform a transaction, which will make the core process undergo at least one state sequentially, wherein each state includes at least one call stack; executing a supervisor process to generate a state record, to sequentially record all undergone states of the core process in the transaction; in response to a crash of the core process in the transaction, generating a fault record to record all call stacks in a latest state of the core process; generating a crash report according to the state record and the fault record. | 2012-06-28 |
| 20120166894 | CIRCUIT AND METHOD FOR CORRECTING SKEW IN A PLURALITY OF COMMUNICATION CHANNELS FOR COMMUNICATING WITH A MEMORY DEVICE, MEMORY CONTROLLER, SYSTEM AND METHOD USING THE SAME, AND MEMORY TEST SYSTEM AND METHOD USING THE SAME - In a circuit, memory controller, memory system, and method for correcting skew among a plurality of communication channels used in communicating with a memory circuit, the circuit for correcting skew includes a transmitting circuit for transmitting a reference signal to input ends of the plurality of channels and through the plurality of channels, and a plurality of receiving circuits for receiving at the input ends of the plurality of channels a respective plurality of reflected signals, the reflected signals being reflected from respective output ends of the plurality of channels. A detection circuit receives the reflected signals and detects relative signal propagation time differences between the plurality of channels. A delay circuit coupled to at least one of the channels sets a signal propagation delay in the at least one of the channels based on the detected relative signal propagation time differences. | 2012-06-28 |
| 20120166895 | MULTICAST DIGITAL VIDEO LOST PACKET RECOVERY - An electronic communication network supports delivery of video program Internet protocol packets. A source device transmits both first and second video program Internet protocol packets. A first recipient device is assigned as positive acknowledgment leader by the source device and a second recipient device is assigned as negative acknowledgement leader by the source device. The first recipient device is operable to transmit to the source device a positive acknowledgment of receipt of the first video program Internet protocol packet. The second recipient device is operable to transmit to the source device a negative acknowledgment of non-receipt upon not receiving the first video program Internet protocol packet. The source device responds to the negative acknowledgement of non-receipt by the second recipient device by multicast resending the second video program Internet protocol packet to both the first and second recipient devices. | 2012-06-28 |
