26th week of 2013 patent applcation highlights part 17 |
Patent application number | Title | Published |
20130161777 | ANTI-REFLECTION STRUCTURES FOR CMOS IMAGE SENSORS - Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package. | 2013-06-27 |
20130161778 | ELECTRONICS DEVICE PACKAGE AND FABRICATION METHOD THEREOF - Embodiments provide a chip device package and a method for fabricating thereof. A semiconductor chip has a substrate. A supporting brick is separated from the substrate by a certain distance. A bonding pad having a surface is disposed across the substrate and the supporting brick. A bonding wire is electrically connected to the bonding pad. | 2013-06-27 |
20130161779 | SUPER TRENCH SCHOTTKY BARRIER SCHOTTKY DIODE - A Schottky diode includes an n | 2013-06-27 |
20130161780 | METHOD OF FABRICATING A GAN P-I-N DIODE USING IMPLANTATION - A III-nitride semiconductor device includes an active region for supporting current flow during forward-biased operation of the III-nitride semiconductor device. The active region includes a first III-nitride epitaxial material having a first conductivity type, and a second III-nitride epitaxial material having a second conductivity type. The III-nitride semiconductor device further includes an edge-termination region physically adjacent to the active region and including an implanted region comprising a portion of the first III-nitride epitaxial material. The implanted region of the first III-nitride epitaxial material has a reduced electrical conductivity in relation to portions of the first III-nitride epitaxial material adjacent to the implanted region | 2013-06-27 |
20130161781 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed, which can improve device characteristics by increasing a process margin between an active region and a storage node contact. The semiconductor device includes an active region, a device isolation film formed to have a lower height than the active region, and exposing an upper part of the active region, and a barrier pattern formed at a sidewall of the exposed active region of an upper part of the device isolation film. | 2013-06-27 |
20130161782 | Heterogeneous Chip Integration with Low Loss Interconnection through Adaptive Patterning - Integrating a semiconductor component with a substrate through a low loss interconnection formed through adaptive patterning includes forming a cavity in the substrate, placing the semiconductor component therein, filling a gap between the semiconductor component and substrate with a fill of same or similar dielectric constant as that of the substrate and adaptively patterning a low loss interconnection on the fill and extending between the contacts of the semiconductor component and the electrical traces on the substrate. The contacts and leads are located and adjoined using an adaptive patterning technique that places and forms a low loss radio frequency transmission line that compensates for any misalignment between the semiconductor component contacts and the substrate leads. | 2013-06-27 |
20130161783 | SEMICONDUCTOR DEVICE INCLUDING ISOLATION LAYER AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes an isolation trench formed in a semiconductor substrate; an isolation layer filling the isolation trench; and a first epitaxial layer interposed between the isolation layer and the semiconductor substrate, wherein a lattice structure of the semiconductor substrate has an angle difference from a lattice structure of the first epitaxial layer adjacent to the semiconductor substrate. | 2013-06-27 |
20130161784 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate; first and second pads that are disposed separate from each other on the substrate; and a solder resist that allows a portion of the substrate in a region between the first and second pads and to be exposed while covering a portion of the first and second pads in a region other than the region between the first and second pads. | 2013-06-27 |
20130161785 | ON CHIP INDUCTOR WITH FREQUENCY DEPENDENT INDUCTANCE - A set of metal line structures including a signal transmission metal line and a capacitively-grounded inductively-signal-coupled metal line is embedded in a dielectric material layer. A capacitor is serially connected between the capacitively-grounded inductively-signal-coupled metal line and a local electrical ground, which may be on the input side or on the output side. The set of metal line structures and the capacitor collective provide a frequency dependent inductor. The Q factor of the frequency dependent inductor has multiple peaks that enable the operation of the frequency dependent inductor at multiple frequencies. Multiple capacitively-grounded inductively-signal-coupled metal lines may be provided in the frequency-dependent inductor, each of which is connected to the local electrical ground through a capacitor. By selecting different capacitance values for the capacitors, multiple values of the Q-factor may be obtained in the frequency dependent inductor at different signal frequencies. | 2013-06-27 |
20130161786 | CAPACITOR ARRAY AND METHOD OF FABRICATING THE SAME - A capacitor array includes a plurality of capacitors and a support frame. Each capacitor includes an electrode. The support frame supports the plurality of electrodes and includes a plurality of support structures corresponding to the plurality of electrodes. Each support structure may surround the respective electrode. The support frame may include oxide of a doped oxidizable material. | 2013-06-27 |
20130161787 | SEMICONDUCTOR DEVICE HAVING CAPACITORS - A semiconductor device including at least one first capacitor and at least one second capacitor. The at least one first capacitor includes a first storage node having a cylindrical shape. The at least one second capacitor includes a lower second storage node having a hollow pillar shape including a hollow portion, and an upper second storage node having a cylindrical shape and extending upward from the lower second storage node. | 2013-06-27 |
20130161788 | Semiconductor Package Including Stacked Semiconductor Chips and a Redistribution Layer - Semiconductor packages including stacked semiconductor chips are provided. The semiconductor packages may include first semiconductor chips and a second semiconductor chip that are stacked sequentially on a board. The semiconductor packages may also include a wiring layer on the memory chips and the wiring layer may include redistribution patterns and redistribution pads. Each of the memory chips may include a data pad. The data pads of the first semiconductor chips may be electrically connected to the board via the second semiconductor chip, some of redistribution patterns, and some of redistribution pads. | 2013-06-27 |
20130161789 | Method for Fabricating a DRAM Capacitor - A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal. A dielectric layer is formed over the first electrode. The dielectric layer is subjected to a milliseconds anneal process that serves to crystallize the dielectric material and decrease the concentration of oxygen vacancies. | 2013-06-27 |
20130161790 | METHOD OF MANUFACTURING A FeRAM DEVICE - A lower electrode film, a ferroelectric film, and an upper electrode film are formed on an insulation film covering a transistor formed on a semiconductor substrate. Furthermore, a Pt film is formed as a cap layer on the upper electrode film. Then, a hard mask (a TiN film and an SiO | 2013-06-27 |
20130161791 | 3D VIA CAPACITOR WITH A FLOATING CONDUCTIVE PLATE FOR IMPROVED RELIABILITY - The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode overlies the sidewalls and at least a portion of the bottom of the via. A first high-k dielectric material layer overlies the first electrode. A first conductive plate is over the first high-k dielectric material layer. A second high-k dielectric material layer overlies the first conductive plate and leaves a remaining portion of the via unfilled. A second electrode is formed in the remaining portion of the via. The first conductive plate is substantially parallel to the first electrode and is not in contact with the first and second electrodes. An array of such 3D via capacitors is also provided. | 2013-06-27 |
20130161792 | SEMICONDUCTOR DEVICE HAVING TRENCH CAPACITOR STRUCTURE INTEGRATED THEREIN - Semiconductor devices are described that include a capacitor integrated therein. In an implementation, the semiconductor devices include a substrate. The substrate includes multiple capacitor regions, such as a first capacitor region and a second capacitor region that are adjacent to one another. Each capacitor region includes trenches that are formed within the substrate. A metal-insulator-metal capacitor is formed within the trenches and at least partially over the substrate. The trenches disposed within the first capacitor region are at least substantially perpendicular to the trenches disposed within the second capacitor region. | 2013-06-27 |
20130161793 | Silicon Single Crystal Substrate and Method Of Manufacturing The Same - Silicon single crystal substrates having uniform resistance, few BMDs in a surface layer and a moderate number of BMDs in a center of thickness of the substrate are formed from Czochralski silicon single crystals. The substrates have a resistivity in the center of a first main surface not lower than 50 Ω·cm and a rate of change in resistivity in the first main surface not higher than 3%, an average density of bulk micro defects in a region between the first main surface and a plane at a depth of 50 μm of less than 1×10 | 2013-06-27 |
20130161794 | INTERNALLY REFORMED SUBSTRATE FOR EPITAXIAL GROWTH, INTERNALLY REFORMED SUBSTRATE WITH MULTILAYER FILM, SEMICONDUCTOR DEVICE, BULK SEMICONDUCTOR SUBSTRATE, AND MANUFACTURING METHODS THEREFOR - Provided are an internally reformed substrate for epitaxial growth having an arbitrary warpage shape and/or an arbitrary warpage amount, an internally reformed substrate with a multilayer film using the internally reformed substrate for epitaxial growth, a semiconductor device, a bulk semiconductor substrate, and manufacturing methods therefor. The internally reformed substrate for epitaxial growth includes: a single crystal substrate; and a heat-denatured layer formed in an internal portion of the single crystal substrate by laser irradiation to the single crystal substrate. | 2013-06-27 |
20130161795 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, PROCESSING METHOD OF SEMICONDUCTOR WAFER, SEMICONDUCTOR WAFER - A disclosed method of manufacturing a semiconductor device includes forming a groove on a first surface of a semiconductor wafer along an outer periphery of the semiconductor wafer, forming a semiconductor device on the first surface, forming an adhesive layer on the first surface to cover the semiconductor device, bonding a support substrate to the first surface by the adhesive layer, grinding after the adhering of the support substrate a second surface of the semiconductor wafer opposite to the first surface, and dicing after the grinding the semiconductor wafer into individual semiconductor chips. | 2013-06-27 |
20130161796 | THROUGH SILICON VIA AND METHOD OF FORMING THE SAME - The present invention relates to a through silicon via (TSV). The TSV is disposed in a substrate including a via opening penetrating through a first surface and a second surface of the substrate. The TSV includes an insulation layer, a barrier layer, a buffer layer and a conductive electrode. The insulation layer is disposed on the surface of the via opening. The barrier layer is disposed on the surface of the insulation layer. The conductive electrode is disposed on the surface of the buffer layer and fills the via opening. The buffer layer further covers a surface of the conductive electrode at the side of the second surface. The present invention further discloses a method of forming the TSV. | 2013-06-27 |
20130161797 | SINGLE CRYSTAL SUBSTRATE, MANUFACTURING METHOD FOR SINGLE CRYSTAL SUBSTRATE, MANUFACTURING METHOD FOR SINGLE CRYSTAL SUBSTRATE WITH MULTILAYER FILM, AND ELEMENT MANUFACTURING METHOD - In order to correct warpage resulting from the formation of a multilayer film, provided are a single crystal substrate which includes a heat-denatured layer provided in one of two regions including a first region and a second region obtained by bisecting the single crystal substrate in a thickness direction thereof, and which is warped convexly toward a side of a surface of the region provided with the heat-denatured layer, a manufacturing method for the single crystal substrate, a manufacturing method for a single crystal substrate with a multilayer film using the single crystal substrate, and an element manufacturing method using the manufacturing method for a single crystal substrate with a multilayer film. | 2013-06-27 |
20130161798 | GRADED DENSITY LAYER FOR FORMATION OF INTERCONNECT STRUCTURES - Methods and structure are provided for utilizing a dielectric mask layer having a gradated density structure. The density of the dielectric mask layer is greatest at the interface of the dielectric mask layer and an underlying dielectric layer. The density of the dielectric mask layer is lowest at the interface of the dielectric mask layer and an overlaying hard mask. The lower density dielectric mask layer is more susceptible to removal than the higher density dielectric mask layer. The lower density dielectric mask layer is removed during at least one of an RIE etch or a post-RIE etch wet clean. Selective removal of the lower density dielectric mask layer creates a dielectric mask layer having a rounded profile. The dielectric mask layer comprises tetraethyl orthosilicate. | 2013-06-27 |
20130161799 | Patterned Semiconductor Bases, and Patterning Methods - Some embodiments include patterning methods. First and second masking features may be formed over first and second regions of a semiconductor base, respectively. A protective mask may be formed over the second masking features. First and second spacers may be formed along sidewall edges of the first masking features and along lateral edges of the protective mask, respectively. The protective mask and the first masking features may be removed without removing the second masking features, without removing the first spacers, and without removing the second spacers. The first spacers may be third masking features that are at a tighter pitch than the first masking features. Patterns of the second masking features and the third masking features may be transferred into the semiconductor base. Some embodiments include patterned semiconductor bases. | 2013-06-27 |
20130161800 | PCB FOR MUF AND MOLDING STRUCTURE OF THE PCB - A printed circuit board (PCB) for molded underfill (MUF) and a PCB molding structure that may expand a range of applying the PCB and may resolve a problem of generation of a void during manufacturing of a semiconductor package. The PCB includes: a molding area on which a plurality of semiconductor chips are mounted and that is sealed; and a peripheral area that is formed around the molding area, contacts a mold for molding during a molding process, and includes a first side adjacent to a portion into which a molding material is injected and a second side that faces the first side that is adjacent to a portion from which air may be discharged, wherein an active area where the semiconductor chips are disposed in the molding area is disposed nearer the first side than to the second side. | 2013-06-27 |
20130161801 | Module Including a Discrete Device Mounted on a DCB Substrate - A module includes a DCB substrate and a discrete device mounted on the DCB substrate, wherein the discrete device comprises a leadframe, a semiconductor chip mounted on the leadframe and an encapsulation material covering the semiconductor chip. | 2013-06-27 |
20130161802 | SEMICONDUCTOR PACKAGE HAVING ELECTRICAL CONNECTING STRUCTURES AND FABRICATION METHOD THEREOF - A semiconductor package having electrical connecting structures includes: a conductive layer having a die pad and traces surrounding the die pad; a chip; bonding wires; an encapsulant with a plurality of cavities having a depth greater than the thickness of the die pad and traces for embedding the die pad and the traces therein, and the cavities exposing the die pad and the traces; a solder mask layer formed in the cavities and having a plurality of openings for exposing the trace ends and a portion of the die pad; and solder balls formed in the openings and electrically connected to the trace ends. Engaging the solder mask layer with the encapsulant enhances adhesion strength of the solder mask layer so as to prolong the moisture permeation path and enhance package reliability. | 2013-06-27 |
20130161803 | Semiconductor Package with Conductive Heat Spreader - A semiconductor package that includes a semiconductor die and a heat spreader thermally coupled to the semiconductor and disposed at least partially within the molded housing of the package. | 2013-06-27 |
20130161804 | INTEGRATED CIRCUIT (IC) LEADFRAME DESIGN - Provided, in one embodiment, is an integrated circuit (IC) leadframe. In one example, the leadframe includes a paddle, wherein the paddle has a surface configured to accept an IC chip and has at least one edge. In this example, the leadframe may further include a plurality of lead fingers having ends extending toward the at least one edge, wherein the ends of ones of adjacent lead fingers are staggered proximate and distal the at least one edge. | 2013-06-27 |
20130161805 | INTEGRATED CIRCUIT (IC) LEADFRAME DESIGN - Provided, in one embodiment, is an integrated circuit (IC) leadframe. In one example, the leadframe includes a paddle, wherein the paddle has a surface configured to accept an IC chip and has at least one edge, the at least one edge having one or more slots located therein. In this example, the leadframe may further include a plurality of lead fingers having ends extending toward the at least one edge, wherein the ends of ones of pairs of adjacent lead fingers extend into corresponding slots in the paddle. | 2013-06-27 |
20130161806 | WINDOW CLAMP TOP PLATE FOR INTEGRATED CIRCUIT PACKAGING - A device and method for minimizing the forces that may compromise a lead frame mount to a support structure in an integrated circuit die package during various packaging method steps. When a window clamp is used to provide pressure during a lead frame bonding step or during a wire bonding step during packaging, the vertical force applied by the window clamp may be transferred in lateral direction by the physical contour of the top plate of the support structure. By changing the physical contour of the top plate of the support structure, such as by disposing a specific kind of contoured protrusion, one may minimize or eliminate the lateral forces that act against achieving a solid bond of the lead frame to the support structure. Further, during wire bonding, the same minimization or elimination of lateral forces lead to improved wire bonding. | 2013-06-27 |
20130161807 | METHOD FOR JOINTING METAL MEMBER AND RESIN AND JOINTED BODY THEREOF - Reliability is improved by improving adhesiveness, crack resistance, and moisture resistance of a metal member-resin jointed body by enhancing adhesiveness between the metal member and the resin. | 2013-06-27 |
20130161808 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - Disclosed herein are a semiconductor package and a method of manufacturing the same. According to a preferred embodiment of the present invention, the semiconductor package includes: a first package having a first semiconductor element mounted on an upper portion thereof and at least one solder ball formed on a lower portion thereof; a second package stacked on the upper portion of the first package; and an interposer formed between the first package and the second package. | 2013-06-27 |
20130161809 | SUBSTRATE STRUCTURE, SEMICONDUCTOR PACKAGE DEVICE, AND MANUFACTURING METHOD OF SUBSTRATE STRUCTURE - A substrate structure, a semiconductor package device and a manufacturing method of substrate structure are provided. The substrate structure comprises a conductive structure comprising a first metal layer, a second metal layer and a third metal layer. The second metal layer is disposed on the first metal layer. The third metal layer is disposed on the second metal layer. Each of the second metal layer and the third metal layer has a first surface and a second surface opposite to the first surface. The first surface of the third metal layer is connected to the second surface of the second metal layer. The surface area of the first surface of the third metal layer is larger than that of the second surface of the second metal layer. | 2013-06-27 |
20130161810 | SEMICONDUCTOR PACKAGE - The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A solder resistance layer is disposed on the substrate, having an extending portion covering a portion of the first conductive trace, wherein a width of the extending portion of the solder resistance layer is larger than that of the portion of the first conductive trace. A semiconductor die is disposed over the first conductive trace. | 2013-06-27 |
20130161811 | 3D IC CONFIGURATION WITH CONTACTLESS COMMUNICATION - A package comprises a die stack having at least two stacked dies coupled for contactless communications with each other. At least one of the stacked dies has a substrate joined to its major face. The substrate has a plurality of conductive traces in or on the substrate for conducting power to the dies and for conducting heat from the dies. At least one conductive pillar is joined to at least one of the conductive traces on at least a first edge of the substrate, for conducting power to the at least one die and for conducting heat from the at least one die. | 2013-06-27 |
20130161812 | DIE PACKAGES AND SYSTEMS HAVING THE DIE PACKAGES - A die package may include a package substrate; an interposer; and/or at least one first die connected between the package substrate and the interposer. The die package may further include at least one second die mounted on the interposer and/or a processor. A system may include a system board and/or a die package mounted on the system board. The die package may include a package substrate; an interposer; and/or at least one first die connected between the package substrate and the interposer. The system may further include at least one second die mounted on the interposer and/or a processor. The processor may control data processing operations of the at least one first die and/or the at least one second die. | 2013-06-27 |
20130161813 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes a first surface, a second surface, and a through hole that extends through the semiconductor substrate from the first surface to the second surface. An insulating layer covers the first surface and includes an opening at a location facing the through hole. An insulating film covers an inner wall of the through hole and an inner wall of the opening. A through electrode is formed in the through hole and the opening that are covered by the insulating film. A first connecting terminal is formed integrally with the through electrode to cover one end of the through electrode exposed from the insulating layer. The first connecting terminal has a larger size than the through electrode as viewed from above. | 2013-06-27 |
20130161814 | SEMICONDUCTOR CHIP WITH OFFSET PADS - A semiconductor chip device includes a first semiconductor chip adapted to be stacked with a second semiconductor chip wherein the second semiconductor chip includes a side and first and second conductor structures projecting from the side. The first semiconductor chip includes a first edge, a first conductor pad, a first conductor pillar positioned on but laterally offset from the first conductor pad toward the first edge and that has a first lateral dimension and is adapted to couple to one of the first and second conductor structures, a second conductor pad positioned nearer the first edge than the first conductor pad, and a second conductor pillar positioned on but laterally offset from the second conductor pad and that has a second lateral dimension larger than the first lateral dimension and is adapted to couple to the other of the first and second conductor structures. | 2013-06-27 |
20130161815 | SEMICONDUCTOR DEVICE - The semiconductor device has the CSP structure, and may include a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps may be arranged in two rows along the periphery of the semiconductor device. The electrode pads may be arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring may be extended from an electrode pad, and may be connected to any one of the outermost solder bumps or any one of the inner solder bumps. | 2013-06-27 |
20130161816 | SEMICONDUCTOR PACKAGE - The present invention relates to a semiconductor package. The semiconductor package includes a substrate, at least one chip, a plurality of conductive elements, a plurality of first conductors and a molding compound. The substrate has a plurality of first pads and a solder mask. The first pads are exposed to a first surface of the substrate, and the material of the first pads is copper. The solder mask is disposed on the first surface, contacts the first pads directly, and has at least on opening so as to expose part of the first pads. The chip is mounted on the first surface of the substrate. The conductive elements electrically connect the chip and the substrate. The first conductors are disposed on the first pads. The molding compound is disposed on the first surface of the substrate, and encapsulates the chip, the conductive elements and part of the first conductors. Whereby, the solder mask contacts the first pads directly, and thus results in higher bonding strength, so as to avoid the bridge between the first conductors caused by the first conductors permeating into the interface between the solder mask and the first pads. | 2013-06-27 |
20130161817 | TECHNIQUES FOR WAFER-LEVEL PROCESSING OF QFN PACKAGES - Semiconductor package device, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar. | 2013-06-27 |
20130161818 | 3-D NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A three-dimensional (3-D) nonvolatile memory device includes channel layers protruding perpendicular to a surface of a substrate, interlayer insulating layers and conductive layer patterns alternately formed to surround each of the channel layers, a slit formed between the channel layers, the slit penetrating the interlayer insulating layers and the conductive layer patterns, and an etch-stop layer formed on the surface of the substrate at the bottom of the slit. | 2013-06-27 |
20130161819 | SEMICONDUCTOR DEVICE STACKED STRUCTURE - A semiconductor device stacked structure is disclosed, which includes multiple semiconductor devices and at least one reinforcing structure. The semiconductor devices are stacked on one another. At least one semiconductor device has at least one through silicon via. Each reinforcing structure surrounds a corresponding one of the at least one through silicon via and is electrically insulated from the semiconductor devices. The at least one reinforcing structure includes multiple reinforcing elements and at least one connecting element. Each reinforcing element is disposed between the semiconductor devices. Vertical projections of the reinforcing elements on a plane define a close region, and a projection of the at least one through silicon via on the plane is located within the close region. The connecting element is located in an overlapping region of the vertical projections of the reinforcing elements on the plane, for connecting the reinforcing elements to form the reinforcing structure. | 2013-06-27 |
20130161820 | METHOD FOR BONDING TWO SILICON SUBSTRATES, AND A CORRESPONDEING SYSTEM OF TWO SILICON SUBSTRATES - A method for bonding two silicon substrates and a corresponding system of two silicon substrates. The method includes: providing first and second silicon substrates; depositing a first bonding layer of pure aluminum or of aluminum-copper having a copper component between 0.1 and 5% on a first bonding surface of the first silicon substrate; depositing a second bonding layer of germanium above the first bonding surface or above a second bonding surface of the second silicon substrate; subsequently joining the first and second silicon substrates, so that the first and the second bonding surfaces lie opposite each other; and implementing a thermal treatment step to form an eutectic bonding layer of aluminum-germanium or containing aluminum-germanium as the main component, between the first silicon substrate and the second silicon substrate, spikes which contain aluminum as a minimum and extend into the first silicon substrate, forming at least on the first bonding surface. | 2013-06-27 |
20130161821 | NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile memory device includes a substrate including a cell region, contact regions and dummy contact regions. The contact regions and the dummy contact regions alternately are disposed. A plurality of word lines stacked at the cell region of the substrate and contact groups stacked at the contact regions and the dummy contact regions of the substrate. The contact groups include a plurality of pad layers being coupled to the word lines, and each of the contact groups has stepped structure disposed at a corresponding contact region. | 2013-06-27 |
20130161822 | CONTROLLING DENSITY OF PARTICLES WITHIN UNDERFILL SURROUNDING SOLDER BUMP CONTACTS - A method forms an integrated circuit structure, using a manufacturing device, to have kerf regions and external contacts, and to have conductive structures in the kerf regions. The method also forms an underfill material on a surface of the integrated circuit structure, using the manufacturing device, that contacts the kerf regions and the external contacts. The underfill material comprises electrically attracted filler particles that affect the coefficient of thermal expansion and elastic modulus of the underfill material. When forming the underfill material, the method applies an electrical charge to the conductive structures and the external contacts. | 2013-06-27 |
20130161823 | Semiconductor Device and Method of Manufacturing the Same - A semiconductor device capable of realizing highly reliable three-dimensional mounting, and a method of manufacturing the same, are provided. A projected electrode | 2013-06-27 |
20130161824 | Semiconductor Device and Method of Forming Insulating Layer in Notches Around Conductive TSV for Stress Relief - A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A notch is formed in the semiconductor wafer around each of the conductive vias. The notch around the conductive vias can be formed by wet etching, dry etching, or LDA. A first insulating layer is formed over a surface of the semiconductor wafer and conductive vias and into the notch to provide stress relief between the conductive vias and semiconductor wafer. A portion of the first insulating layer is removed to expose the conductive vias. A first conductive layer and second insulating layer can be formed around the conductive vias. A second conductive layer can be formed over the conductive vias. The notch can extend into the second insulating layer. | 2013-06-27 |
20130161825 | THROUGH SUBSTRATE VIA STRUCTURE AND METHOD FOR FABRICATING THE SAME - A through substrate via (TSV) structure is provided, including: a substrate; an opening formed in a portion of the semiconductor substrate; a dielectric layer formed on the sidewall of the opening; a conductive pillar formed inside the opening; and at least a portion of the dielectric layer is removed to form void. Also provided is a method for fabricating a through substrate via (TSV) structure. | 2013-06-27 |
20130161826 | SEMICONDUCTOR CHIP AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor chip includes a substrate, through-electrodes passing through the substrate, and a dielectric layer formed between the substrate and the through-electrodes and having a dielectric constant decreasing structure. | 2013-06-27 |
20130161827 | SEMICONDUCTOR CHIP HAVING PLURAL PENETRATION ELECTRODE PENETRATING THERETHROUGH - Disclosed herein is a semiconductor chip that includes: a plurality of penetration electrodes each penetrating between main and back surfaces of the semiconductor chip, the penetration electrodes including a plurality of first penetration electrodes, a second penetration electrode and a third penetration electrode; and a wiring configured to intersect with a plurality of regions, each of the regions being defined as a region between corresponding two of the first penetration electrodes, one end of the wiring being coupled to the second penetration electrode, the other end of the wiring being coupled to the third penetration electrode. | 2013-06-27 |
20130161828 | TSV VIA PROVIDED WITH A STRESS RELEASE STRUCTURE AND ITS FABRICATION METHOD - A TSV via structure comprising an upper part made on the side of the front face of a substrate in which electronic components are located and a lower part with height and cross-section smaller than the height and cross-section the upper part, the arrangement of the connection element in the substrate being such that it releases stresses generated by the different materials of said structure. | 2013-06-27 |
20130161829 | WAFER-TO-WAFER STACK WITH SUPPORTING POST - A wafer stack includes: a first wafer having a first substrate and a first device layer having therein at least a chip; a second wafer having a second substrate disposed above the first wafer; and at least a first metal post existing in the first device layer, and arranged between the first and the second substrates, without being electrically connected to the chip. | 2013-06-27 |
20130161830 | SEMICONDUCTOR CHIPS HAVING REDISTRIBUTED POWER/GROUND LINES DIRECTLY CONNECTED TO POWER/GROUND LINES OF INTERNAL CIRCUITS AND METHODS OF FABRICATING THE SAME - Provided are embodiments of semiconductor chips having a redistributed metal interconnection directly connected to power/ground lines of an internal circuit are provided. Embodiments of the semiconductor chips include an internal circuit formed on a semiconductor substrate. A chip pad is disposed on the semiconductor substrate. The chip pad is electrically connected to the internal circuit through an internal interconnection. A passivation layer is provided over the chip pad. A redistributed metal interconnection is provided on the passivation layer. The redistributed metal interconnection directly connects the internal interconnection to the chip pad through a via-hole and a chip pad opening, which penetrate at least the passivation layer. Methods of fabricating the semiconductor chip are also provided. | 2013-06-27 |
20130161831 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICES - A three-dimensional semiconductor device may include a substrate including wiring and contact regions and a thin film structure on the wiring and contact regions of the substrate. The thin-film structure may include a plurality of alternating wiring layers and inter-layer insulating layers defining a terraced structure in the contact region so that each of the wiring layers includes a contact surface in the contact region that extends beyond others of the wiring layers more distant from the substrate. A plurality of contact structures may extend in a direction perpendicular to a surface of the substrate with each of the contact structures being electrically connected to a contact surface of a respective one of the wiring layers. Related methods are also discussed. | 2013-06-27 |
20130161832 | SEMICONDUCTOR DEVICE WITH BURIED BIT LINE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a punch stop region formed in a substrate; a plurality of buried bit lines formed over the substrate; a plurality of pillar structures formed over the buried bit lines; a plurality of word lines extending to intersect the buried bit lines and being in contact with the pillar structures; and an isolation layer isolating the word lines from the buried bit lines. | 2013-06-27 |
20130161833 | Semiconductor Device and Method of Forming Extended Semiconductor Device with Fan-Out Interconnect Structure to Reduce Complexity of Substrate - A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. Contact pads are formed on a surface of the semiconductor die. The semiconductor die are separated to form a peripheral region around the semiconductor die. An encapsulant or insulating material is deposited in the peripheral region around the semiconductor die. An interconnect structure is formed over the semiconductor die and insulating material. The interconnect structure has an I/O density less than an I/O density of the contact pads on the semiconductor die. A substrate has an I/O density consistent with the I/O density of the interconnect structure. The semiconductor die is mounted to the substrate with the interconnect structure electrically connecting the contact pads of the semiconductor die to the first conductive layer of the substrate. A plurality of semiconductor die each with the interconnect structure can be mounted over the substrate. | 2013-06-27 |
20130161834 | HETEROGENEOUS INTEGRATION PROCESS INCORPORATING LAYER TRANSFER IN EPITAXY LEVEL PACKAGING - Methods and structures for heterogeneous integration of diverse material systems and device technologies onto a single substrate incorporate layer transfer techniques into an epitaxy level packaging process. A planar substrate surface of multiple epitaxial areas of different materials can be heterogeneously integrated with a substrate material. Complex assembly and lattice engineering is significantly reduced. Microsystems of different circuits made from different materials can be built from a single wafer Fab line employing the claimed processes. | 2013-06-27 |
20130161835 | MULTILAYER CONNECTION STRUCTURE - A three-dimensional stacked IC device includes a stack of at least first, second, third and fourth contact levels at an interconnect region. Each contact level has a conductive layer and an insulation layer. First, second, third and fourth electrical conductors pass through portions of the stack of contact levels. The first, second, third and fourth electrical conductors are in electrical contact with the first, second, third and fourth conductive layers, respectively. A dielectric sidewall spacer circumferentially surrounds the second, third and fourth electrical conductors so that the second, third and fourth electrical conductors only electrically contact the respective second, third and fourth conductive layers. | 2013-06-27 |
20130161836 | SEMICONDUCTOR PACKAGE HAVING INTERPOSER COMPRISING A PLURALITY OF SEGMENTS - Provided is a semiconductor package comprising a substrate, a semiconductor chip formed on the substrate, and an interposer including a plurality of segments which are separated from each other and arranged on the substrate to surround the semiconductor chip. And a stacked package for multiple chips including the semiconductor package with a plurality of segments of an interposer is provided. | 2013-06-27 |
20130161837 | SEMICONDUCTOR PACKAGE, PACKAGING SUBSTRATE AND FABRICATION METHOD THEREOF - A packaging substrate and a semiconductor package using the packaging substrate are provided. The packaging substrate includes: a substrate body having a die attach area, a circuit layer formed around the die attach area and having a plurality of conductive traces each having a wire bonding pad, and a surface treatment layer formed on the wire bonding pads. Therein, only one of the conductive traces is connected to an electroplating line so as to prevent cross-talk that otherwise occurs between conductive traces due to too many electroplating lines in the prior art. | 2013-06-27 |
20130161838 | ANISOTROPIC CONDUCTIVE FILM AND SEMICONDUCTOR DEVICE - A semiconductor device bonded by an anisotropic conductive film, the anisotropic conductive film including a phenoxy resin including a fluorene-substituted phenoxy resin; and a radically polymerizable resin including a fluorene-substituted acrylate. | 2013-06-27 |
20130161839 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same are provided. The device includes first and second line pattern units configured to extend substantially parallel to one another in a first direction and alternately disposed such that end portions of the first and second line pattern units are arranged in a diagonal direction, third and fourth pattern units configured to respectively extend from the end portions of the first and second line pattern units in a second direction crossing the first direction, first contact pad units respectively formed in the third line pattern units disposed a first distance from the end portions of the first line pattern units, and fourth contact pad units respectively formed in the fourth line pattern units disposed a second distance from the end portions of the second line pattern units. Here, the second distance is different from the first distance. | 2013-06-27 |
20130161840 | STRIPPER SOLUTIONS EFFECTIVE FOR BACK-END-OF-LINE OPERATIONS - Back end of line (BEOL) stripping solutions which can be used in a stripping process that replaces etching resist ashing process are provided. The stripping solutions are useful for fabricating circuits and/or forming electrodes on semiconductor devices for semiconductor integrated circuits with good efficiency and with low and acceptable metal etch rates. Methods for their use are similarly provided. The preferred stripping agents contain a polar aprotic solvent, water, an amine and a quaternary hydroxide that is not tetramethylammonium hydroxide. Further provided are integrated circuit devices and electronic interconnect structures prepared according to these methods. | 2013-06-27 |
20130161841 | ALIGNMENT MARK AND METHOD OF MANUFACTURING THE SAME - An alignment mark includes a plurality of mark units. Each mark unit includes a first element and a plurality of second elements. Each second element includes opposite first and second end portions. The plurality of second elements are arranged along a direction. The first element extends adjacent to the first end portions of the plurality of second elements and parallel to the direction of the plurality of second elements. | 2013-06-27 |
20130161842 | HUMIDIFYING APPARATUS - Humidifying apparatus includes a humidifier for emitting moist air into an external environment, and a fan assembly for generating an air current within the external environment for conveying the emitted moist air away from the humidifier. The fan assembly includes a device for creating an air flow and a nozzle comprising an interior passage for receiving the air flow and a mouth for emitting the air flow. The humidifier is located behind nozzle, the nozzle extending about and defining an opening through which both air from outside the nozzle and the moist air emitted from the humidifier are drawn by the air flow emitted from the mouth. | 2013-06-27 |
20130161843 | CARBURETTORS - A carburettor including a primary air passage, an adjustable throttle valve situated within the primary air passage, a fuel supply nozzle communicating with the primary air passage and connected to a fuel metering valve for varying the amount of fuel discharged through the nozzle and a rotary input shaft adapted to be connected to an engine speed control member and which is connected to the throttle valve to move the throttle valve between open and closed positions. The rotary input shaft is also connected to a carriage to move the carriage, the carriage carrying at least one elongate inclined ramp which extends in the direction of movement of the carriage and which is engaged by a follower connected to the valve member. Rotation of the input shaft results in movement of the throttle valve and in movement of the carriage and thus of the elongate ramp, wherein the follower is moved transverse to the length of the ramp and the valve member of the fuel metering valve is thus also moved. | 2013-06-27 |
20130161844 | METHOD FOR PRODUCING PLASTIC LENS - There is provided a method for producing a plastic lens in which, without heating a die, a resin injected and filled into a cavity can be maintained at a temperature higher than a glass transition temperature of the resin only for a time until the filling of the resin into the cavity terminates, whereby the generation of a surface defect such as jetting or a flow mark, or a weld line can be prevented. In producing the plastic lens having a predetermined lens shape by injecting and filling a molten raw material resin into a cavity | 2013-06-27 |
20130161845 | METHOD OF FORMING AN OPTICAL SURFACE ON A SOLAR COLLECTOR SHELL - A method of forming an optical surface on a solar collector that is made from a composite material adds epoxy to the collector. The epoxy is applied to a mandrel that has an outer surface shaped to conform to a concave side of the collector. The concave side of the collector is laid over the mandrel and into contact with the epoxy. The collector is set on the mandrel by first aligning one of the elongate edges of the collector with an elongate edge of the mandrel. Pivoting the collector about the interface defined between the edges of the collector and mandrel produces a wave front in the epoxy, so that when the collector is laid down onto the mandrel, a substantially uniform layer of epoxy is disposed between the collector and mandrel. Heating the resin bonds it to the collector and forms a substantially smooth optical quality surface. | 2013-06-27 |
20130161846 | Ophthalmic Device Molds And Related Methods - Ophthalmic device molds made from a first portion of a molding surface formed from a first polymer and a second portion of the molding surface formed from a second polymer are described. When combined, the first portion and the second portion of the molding surface form an entire molding surface suitable for molding an entire surface, such as an anterior surface or a posterior surface of an ophthalmic device. Methods of manufacturing ophthalmic devices using these molds, including contact lenses, are also described. | 2013-06-27 |
20130161847 | APPARATUS AND METHOD FOR FABRICATING ANTIMICROBIAL HYBRID MATERIALS OF NATURAL PRODUCT AND CARBON NANOMATERIALS - The present disclosure relates to an apparatus and a method for fabricating an antimicrobial hybrid material of a natural antimicrobial particle and a carbon nanomaterial, capable of fully utilizing the antimicrobial property of a natural antimicrobial material and a carbon nanomaterial by maximizing adsorption of the natural antimicrobial material on the carbon nanomaterial. | 2013-06-27 |
20130161848 | PROCESS FOR MAKING STERILE ARIPIPRAZOLE OF DESIRED MEAN PARTICLE SIZE - A process is provided for making sterile aripiprazole having an average particle size less than 100 microns but preferably greater than 25 microns employing an impinging jet crystallization procedure. The resulting bulk aripiprazole of desired particle size may be used to form a sterile freeze-dried aripiprazole formulation, which upon constitution with water and intramuscular injection releases aripiprazole over a period of at least about one week and up to about eight weeks. | 2013-06-27 |
20130161849 | PREPARATION OF YTTRIUM-CERIUM-ALUMINUM GARNET PHOSPHOR - A yttrium-cerium-aluminum garnet phosphor is prepared by mixing yttrium, cerium and aluminum compounds to form a raw material in which the Ce concentration is 4-15 mol % based on the sum of Y and Ce, and a molar ratio of Al to the sum of Y and Ce is 5/3 to 5.5/3, granulating the raw material into particles with an average particle size of 5-100 μm, melting the particles in a high-temperature plasma, and heat treating the resulting particles in a non-oxidizing atmosphere for crystallization. | 2013-06-27 |
20130161850 | AUTOCLAVE HEALTH MONITORING AND CONTROL SYSTEM - A bladder monitoring apparatus and method for monitoring an inflatable bladder during curing of composite material in an autoclave. The bladder may be wrapped with composite material and have an impermeable membrane sealed around the composite material. The method may include the steps of fluidly coupling a vacuum port of the impermeable membrane with a vacuum source and fluidly coupling a vent of the bladder with a first port of a flow meter located outward of the autoclave. A second port of the flow meter may also be fluidly coupled with atmosphere within the autoclave. The method may then include evacuating air from within the impermeable membrane. If a flow above a threshold flow is detected by the flow meter, the leak in the bladder may be located and repaired or a valve of the flow meter between the first and second ports may be closed. | 2013-06-27 |
20130161851 | METHOD AND APPARATUS FOR DETECTING GLASS BREAKAGE DURING A PROCESS FOR ENCAPSULATING A TEMPERED GLASS PANEL - An apparatus which accurately detects breakage of a tempered glass panel in an encapsulation die during a glass encapsulation process and rapidly reacts to the detection of such breakage to interrupt the encapsulation process, thus minimizing damage to the encapsulation die, and by so doing, reducing process downtime. A method of utilizing the apparatus is also a part of the invention. | 2013-06-27 |
20130161852 | CALIBRATING DEVICE FOR A BLOWN FILM TUBE - The invention describes a calibration device ( | 2013-06-27 |
20130161853 | SHRINKABLE FIBER FOR POROUS MOLDED BODY - To provide an add-in material to be added to a porous molded body base, the add-in material being capable of developing a pore of appropriate size efficiently without degrading the formability and productivity of a porous molded body, particularly a porous fired body when producing the porous molded body. A shrinkable fiber composed of a thermoplastic resin and to be dispersed in a base of a porous molded body, particularly a porous fired body, wherein the shrinkable fiber has a fiber diameter of 10 to 40 μm, a fiber length of 1 to 20 mm, and a dry-heat shrinkage percentage of at least 8% when subjected to heat treatment at 80° C. for 5 minutes. | 2013-06-27 |
20130161854 | METHOD FOR MANUFACTURING FOAM MATERIAL USING MOLTEN SLAG - A method for manufacturing a foam material by using a molten slag includes: introducing the molten slag maintained at 1400° C.-1500° C. into a pool for preserving heat, and adding a viscosity modifier and/or a color modifier to the molten slag to adjust a viscosity and/or a color a product manufactured. The molten slag is discharged into a foaming pour while adding a foaming agent to the molten slag, while controlling the foam and mold at 1250° C.-1400° C. The foamed and molded slag is maintained at 800° C.-1000° C. for 20-30 minutes in a non-reducing atmosphere, and then naturally cooled to a room temperature to obtain the foam material. The produced inorganic nonmetal foam material and products thereof have such characteristics as stable color quality, abrasion resistance, pressure resistance, small thermal conductivity, small shrinkage ratio, and excellent sound absorption, adsorption and filtering performances. | 2013-06-27 |
20130161855 | SYSTEMS AND METHODS FOR PRODUCING CABLE - One embodiment relates to a method for producing cable. The method includes applying an insulative coating to each of a plurality of conductors to form a plurality of insulated conductors. The method further includes taking up the plurality of insulated conductors in a twisting system to twist the plurality of insulated conductors together and apply a first portion of a desired twist to the plurality of insulated conductors. The method further includes paying off the plurality of insulated conductors from the twisting system to further twist the plurality of insulated conductors together and apply a second portion of a desired twist to the plurality of insulated conductors to form a twisted plurality of insulated conductors. | 2013-06-27 |
20130161856 | METHODS OF PRODUCING A TITANIUM DIOXIDE PIGMENT AND IMPROVING THE PROCESSABILITY OF TITANIUM DIOXIDE PIGMENT PARTICLES - A method of producing a titanium dioxide pigment is provided. Also provided is a method of improving the processability of titanium dioxide particles without adversely affecting the rheological properties of the titanium dioxide particles. | 2013-06-27 |
20130161857 | APPARATUS AND PROCESS FOR MIXING RUBBER COMPOUNDS - A process of manufacturing a rubber compound is disclosed. The process comprises providing a multiple shaft extruder device; feeding the multiple shaft extruder device with at least one polymer raw material or with a mixture of at least two different polymer raw materials; feeding the multiple shaft extruder device with at least one further raw material; mixing the at least one polymer raw material or the mixture of the different polymer raw materials and the at least one further raw material in the multiple shaft extruder device to prepare a rubber compound; and extruding the rubber compound from the multiple shaft extruder device. A plurality of multiple shaft extruder devices may be used in parallel or in sequence. | 2013-06-27 |
20130161858 | APPARATUS FOR MANUFACTURING A NETTED STRUCTURE AND METHOD FOR MANUFACTURING A NETTED STRUCTURE - The purpose of the invention is to eliminate water-permeable sheets and thus to eliminate various bothersome works related to the water-permeable sheets. | 2013-06-27 |
20130161859 | SIZING COMPOSITIONS, SIZED REINFORCING PRODUCTS AND METHODS FOR MAKING REINFORCED THERMOSET COMPOSITES - Methods are described for activating a glass fiber or flake to participate in polymerizing a resin. The methods may include sizing the glass fiber or flake with a sizing composition that includes a solution containing a polymerization initiator, and activating the polymerization initiator by forming a free radical moiety on the polymerization initiator that can initiate the polymerization of the resin. Additional methods of making a glass reinforced composite are described. The methods may include sizing glass fibers or flakes with a sizing composition that includes a solution containing a polymerization initiator, forming a free radical moiety on the polymerization initiator to make activated glass fibers or flakes, and contacting the activated glass fibers or flakes with a polymer resin. The activated glass fibers or flakes initiate the polymerization of the resin around the glass fibers or flakes to form the glass reinforced composite. | 2013-06-27 |
20130161860 | Oriented Film Produced In-Process For Use in the Stretch Film Market - Pre-stretched films may be used to increase the rate at which loads can be wrapped and to minimize the exertion required when using conventional stretch films. However, pre-stretched films must generally be stretched in a separate step and stored for several days in order for cling to fully develop. The present disclosure describes compositions, devices, systems, and methods for producing film that eliminate the stretching and storage steps. In particular, the present disclosure relates to the use of selected resins and an angled die to increase the level of orientation in the film as it is formed, thus eliminating the need to stretch the film in a separate step. The present disclosure also relates to the use of a cling agent which eliminates the storage time traditionally required to develop the film's cling properties. | 2013-06-27 |
20130161861 | PROCESS FOR PREPARING POLYSACCHARIDE FIBERS FROM AQUEOUS ALKALI METAL HYDROXIDE SOLUTION - This invention pertains to a novel processing for preparing fibers from poly(α(1→3)glucan). The fibers prepared according to the invention, have “cotton-like” properties, are useful in textile applications, and can be produced as continuous filaments on a year-round basis. The process comprises solution spinning a 5-20% solids concentration of poly(α(1→3)glucan) in an aqueous alkali metal hydroxide, in particular NaOH at concentration of 2 to 10 weight-%, and coagulating the spun fiber in an acid coagulation liquid. | 2013-06-27 |
20130161862 | Moulding Chamber Arrangement for a Mould-String Plant - Moulding chamber arrangement ( | 2013-06-27 |
20130161863 | DESIGNING AND MANUFACTURING VEHICLE FLOOR TRAYS - Points on a surface of a vehicle foot well are digitally measured with a coordinate measuring machine. A vehicle foot well surface model is recreated in an electronic memory to include these points. The foot well surface model is in turn used to construct a mold for a vehicle floor tray, which ensures a snug fit. | 2013-06-27 |
20130161864 | SUBSTRATE STRUCTURE AND METHOD FOR MAKING THE SAME - A substrate structure includes a support, a release layer releasably disposed on the support, and a flexible substrate disposed on the release layer. The release layer is made from a polymer composition including a polymer component obtained by subjecting a diamine component (A) and a tetracarboxylic dianhydride component (B) to a polymerization reaction. | 2013-06-27 |
20130161865 | Method Of Making Golf Ball With Material-Filled Grooves - A method of making a golf ball may include molding at least one core layer and molding an outer cover layer radially outward of the at least one core layer, from an outer cover layer material, including forming one or more grooves extending radially inward from an outer surface of the outer cover layer. The method may also include molding a groove material within the one or more grooves, the groove material having a compressibility that is different from a compressibility of the outer cover layer material. In addition, molding the groove material may include forming the groove material such that an outer surface of the groove material extends radially outward beyond the outer surface of the outer cover layer. | 2013-06-27 |
20130161866 | INJECTION MOULDING SOFT ELASTOMERS - A fabric web is led between mould parts which are subsequently closed. A liquid elastomer is injected into the mould for forming a soft elastomeric product bonded to the fabric web. As the mould is opened ejector pins on one mould part clamp the web against the other mould part for stripping the soft elastomeric product from the mould. After disengagement of the ejector pins the web is advanced to discharge the soft elastomeric product from the mould. | 2013-06-27 |
20130161867 | Molding Apparatus and a Method for Molding - An embodiment molding apparatus includes a main cavity and a buffer cavity connected with the main cavity. | 2013-06-27 |
20130161868 | IMPRINT LITHOGRAPHY APPARATUS AND DEVICE MANUFACTURING METHOD THEREFOR - An imprint lithography apparatus uses a mold having a pattern formed thereon and transfers the pattern to an imprint material fed to a substrate. The apparatus includes a light-receiving element; a detection system that irradiates a mark formed on the substrate and a mark formed on the mold with light which is reflected therefrom, and guides the light reflected from the mark formed on the substrate and from the mark formed on the mold to the light-receiving element; a relay optical system that causes the light reflected to focus between the mold and the detection system; an illumination system that emits illumination light for curing the imprint material; an optical element having a surface that transmits one of the illumination light and the light from the detection system and reflects the other; and a plate-shaped optical member that corrects aberration of the relay optical system. | 2013-06-27 |
20130161869 | METHOD OF MANUFACTURING FINE STRUCTURE BODY AND FINE STRUCTURE MOLD - The present invention is a method of manufacturing a fine structure body which manufactures the fine structure body by repeating a basic fine structure body forming step that forms a basic fine structure body by pressing a fine structure mold against a curable resin (photocurable resin film) on a surface of a base material and a release and moving step that releases the fine structure mold from the base material and moves the fine structure mold, wherein the fine structure mold includes at least a first mold depression pattern which is disposed at center area of it, and a second mold depression pattern which is disposed in at least one side part in circumference area of it, and a size of the second mold depression pattern is smaller than a size of the first mold depression pattern. | 2013-06-27 |
20130161870 | METHOD FOR PRODUCING SEVERAL INJECTION-MOLDED PARTS - A method for simultaneously producing several injection-molded parts. A mold is provided comprising a plurality of molding plates fluidically connected to each other and which combine form a plurality of mold cavities defining the contour of a finished injection-molded product. A material such as a plastic material is injected via an injection nozzle into one of the mold cavities such that the material flows successively through the mold cavities from one mold cavity to an adjacent mold cavity. | 2013-06-27 |
20130161871 | MOLDING APPARATUS - Described herein is a mold. The mold includes a first mold half and a second mold half. A molding cavity is definable between the first mold half and the second mold half within which a molded article is moldable. The mold also includes a core configured to form a seal on the molded article. The first mold half and the second mold half are configured to remain in a mold closed configuration with molding and stripping of the molded article. | 2013-06-27 |
20130161872 | Preservation of the Appearance of Pre-Printed Graphics on Hot Stretched Film - The present disclosure is concerned with improving the appearance of graphics printed on a flexible polymer film which is subsequently heated to a forming temperature and then drawn into a mold to form a cavity adapted for the packaging of an item, typically a food item. The improvement is effected by reducing the heat transfer to the portions of the film carrying the graphics thereby reducing the formability of these portions so that they stretch less than the rest of the film which is drawn into the mold. Typically the film is heated by contact with a heated platen. In such cases the reduced heat transfer can be effected by having zones of a cooler temperature which are adapted to be in registry with the portions of the film carrying the graphics or by covering the portions of the heated platen in registry with these graphics with an insulating material such as Teflon tape. The mouth of the cavity can then be closed by sealing to another flexible polymeric film. If the films used are heat shrinkable, the sealed package can be subjected to thermal conditions which cause it to shrink about the packaged item. | 2013-06-27 |
20130161873 | TETRAFLUOROETHYLENE COPOLYMER COMPOSITION FOR INJECTION MOLDING - A tetrafluoroethylene copolymer composition for injection molding having excellent resistance to chemical permeation and durability, comprised of polytetrafluoroethylene and copolymer of tetrafluoroethylene and perfluoro(alkyl vinyl ether). The composition has a melt flow rate of 12 g/10 min or greater, a flex life of 20,000 cycles or greater, and a nitrogen gas permeability of 0.8×10 | 2013-06-27 |
20130161874 | METHOD AND APPARATUS FOR FORMING THREE-DIMENSIONAL IMAGE - There are provided a method and apparatus for forming a three-dimensional image. The method and apparatus form an arbitrary colored image on the surface of a thermally expandable sheet by using surface image data. The method and apparatus form a mirror image, of which the density of a black component is adjusted in consideration of the influence of the density of the colored image on a bulge height of a thermally expandable layer so that an originally scheduled bulge height can be achieved, on the back of the thermally expandable sheet. The method and apparatus can achieve an intended bulge height by expanding the thermally expandable layer with thermal energy that is generated in the mirror image and the colored image when the thermally expandable sheet is irradiated with light including infrared wavelengths from the back of the thermally expandable sheet. | 2013-06-27 |
20130161875 | MONO-AND MULTI-LAYER BLOWN FILMS - An extruded air cooled blown film having
| 2013-06-27 |
20130161876 | Method Of Molding A Single-Piece Hollow Shell Including Perforations - A method of making a single-piece hollow shell is disclosed. A plurality of perforators is inserted into a mold and create an inner mold surface. A material is inserted into the mold to create a perforated hollow shell between the mold, the inner mold surface, and the perforated. | 2013-06-27 |