26th week of 2014 patent applcation highlights part 19 |
Patent application number | Title | Published |
20140175600 | VERTICALLY INTEGRATED SYSTEMS - Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer. | 2014-06-26 |
20140175601 | ANTI-FUSE STRUCTURE AND ANTI-FUSE PROGRAMMING METHOD - An anti-fuse structure includes a substrate having at least a shallow trench isolation formed therein, a notch formed between the substrate and the STI, an electrode structure formed on the substrate, the electrode structure filling the notch, and a doped region formed in the substrate on a side of the electrode structure opposite to the notch. | 2014-06-26 |
20140175602 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Characteristics of a semiconductor device are improved. A semiconductor device has a laminated insulating film formed above a lower-layer inductor. This laminated insulating film includes a first polyimide film, and a second polyimide film formed on the first polyimide film and having a second step between the first polyimide film and the second polyimide film. An upper-layer inductor is formed on the laminated insulating film. Since such a laminated structure of the first and second polyimide films is adopted, the film thickness of the insulating film between the lower-layer and upper-layer inductors can be increased, so that withstand voltage can be improved. Further, the occurrence of a depression or peeling-off due to defective exposure can be reduced, and step disconnection of a Cu (copper) seed layer or a plating defect due to the step disconnection can also be reduced. | 2014-06-26 |
20140175603 | Method of Forming an Asymmetric MIMCAP or a Schottky Device as a Selector Element for a Cross-Bar Memory Array - MIMCAP devices are provided that can be suitable for memory device applications, such as current selector devices for cross point memory array. The MIMCAP devices can have lower thermal budget as compared to Schottky diodes and controllable lower barrier height and lower series resistance as compared to MIMCAP tunneling diodes. The MIMCAP diode can include a low defect dielectric layer, a high defect dielectric layer, sandwiched between two electrodes having different work function values. | 2014-06-26 |
20140175604 | Two Step Deposition of Molybdenum Dioxide Electrode for High Quality Dielectric Stacks - Electrodes, which contain molybdenum dioxide (MoO | 2014-06-26 |
20140175605 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR APPARATUS WITH EMBEDDED CAPACITOR - A semiconductor chip includes a semiconductor substrate having one and the other surfaces and formed with a plurality of semiconductor devices; an internal wiring layer having multi-layered internal wiring lines which are formed over the one surface and are electrically connected with the plurality of semiconductor devices, an uppermost internal wiring line among the internal wiring lines being formed with a power supply pad and a ground pad; a dielectric layer formed over the uppermost internal wiring line in such a way as to expose the power supply pad and the ground pad; an external connection reinforcing line formed over the power supply pad or the ground pad which is exposed, and extending onto the dielectric layer; and an embedded capacitor constituted by the external connection reinforcing line, and the dielectric layer and a portion of the is uppermost internal wiring line which correspond to the external connection reinforcing line. | 2014-06-26 |
20140175606 | VARACTOR - A varactor is provided. A substrate includes a first surface, a second surface and a first opening and a second opening in the substrate. A conductive material is filling the first and second openings, to form a first through-wafer via (TWV) and a second through-wafer via. A first capacitor is coupled between the first through-wafer via and a first terminal. A second capacitor is coupled between the second through-wafer via and a second terminal. A capacitance of a depletion-region capacitor between the first through-wafer via and the second through-wafer via is determined by a bias voltage applied to the first through-wafer via and the second through-wafer via. | 2014-06-26 |
20140175607 | SEMICONDUCTOR DEVICE INTEGRATING PASSIVE ELEMENTS - The present invention provides a semiconductor device integrating passive elements, which applies to analog circuits, wherein capacitors, resistors and inductors are fabricated by a TVS technology. The semiconductor device comprises a substrate; at least one passive element arranged in the substrate; and at least one semiconductor integrated circuit formed in the substrate. The passive element includes a first conductive layer, a first dielectric layer and a second conductive layer, which are stacked sequentially. The first conductive layer and the second conductive layer cooperate with the first dielectric layer to form an equivalent element. The semiconductor circuit is electrically connected with the passive element through the first conductive layer and the second conductive layer to form bidirectional signal transmission paths. The passive elements can be formed on the back side of the substrate to reduce the area occupied by the passive elements in the substrate. | 2014-06-26 |
20140175608 | METHOD FOR INCLUDING DECOUPLING CAPACITORS INTO SEMICONDUCTOR CIRCUIT HAVING LOGIC CIRCUIT THEREIN AND SEMICONDUCTOR CIRCUIT THEREOF - A method for including decoupling capacitors into a semiconductor circuit having at least a logic circuit therein, includes: arranging a first decoupling capacitor and a second decoupling capacitor into a first area and a second area around the logic circuit respectively, wherein a gate oxide thickness of the first decoupling capacitor is different from a gate oxide thickness of the second decoupling capacitor, and a distance between the first area and the first logic circuit is shorter than a distance between the second area and the second logic circuit. | 2014-06-26 |
20140175609 | PRECISION POLYSILICON RESISTORS - Use of a replacement metal gate (RMG) process provides an opportunity to create precision polysilicon resistors alongside metal gate transistors. During formation of a sacrificial polysilicon gate, the precision polysilicon resistor can also be formed from the same polysilicon film. The polysilicon resistor can be slightly recessed so that a protective insulating layer can cover the resistor during subsequent replacement of the sacrificial gate with a metal gate. The final structure of the precision polysilicon resistor fabricated using such a process is more compact and less complex than existing structures that provide metal resistors for integrated circuits having metal gate transistors. Furthermore, the precision polysilicon resistor can be freely tuned to have a desired sheet resistance by either implanting the polysilicon film with dopants, adjusting the polysilicon film thickness, or both. | 2014-06-26 |
20140175610 | ELECTROSTATIC DISCHARGE DEVICES FOR INTEGRATED CIRCUITS - A junction diode array for use in protecting integrated circuits from electrostatic discharge can be fabricated to include symmetric and/or asymmetric junction diodes of various sizes. The diodes can be configured to provide low voltage and current discharge via unencapsulated contacts, or high voltage and current discharge via encapsulated contacts. Use of tilted implants in fabricating the junction diode array allows a single hard mask to be used to implant multiple ion species. Furthermore, a different implant tilt angle can be chosen for each species, along with other parameters, (e.g., implant energy, implant mask thickness, and dimensions of the mask openings) so as to craft the shape of the implanted regions. Isolation regions can be inserted between already formed diodes, using the same implant hard mask if desired. A buried oxide layer can be used to prevent diffusion of dopants into the substrate beyond a selected depth. | 2014-06-26 |
20140175611 | ELECTROSTATIC DISCHARGE (ESD) CLAMP - One or more techniques or systems for forming an electrostatic discharge (ESD) clamp are provided herein. In some embodiments, the ESD clamp includes a first pad and a second pad. For example, the first pad is a positive supply voltage (Vdd) pad and the second pad is a negative supply voltage (Vss) pad. In some embodiments, active regions and oxide regions are associated with substantially rounded shapes or obtuse angles. Additionally, metal regions are configured to be in contact with at least some of at least one of the active regions or the oxide regions and the first pad. In some embodiments, the metal regions are substantially wedge shaped. In this manner, an ESD clamp with enhanced performance is provided, at least because the respective active regions are substantially rounded or associated with obtuse angles, for example. | 2014-06-26 |
20140175612 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - There are provided a semiconductor device and a method of manufacturing the same. The semiconductor device includes a body layer of a first conductivity type; an active layer of a second conductivity type, contacting an upper portion of the body layer; and a field limiting ring of a first conductivity type, formed in an upper portion of the active layer. | 2014-06-26 |
20140175613 | Chip Positioning in Multi-Chip Package - Embodiments of the present invention include a substrate package, a method for multi chip packaging, and a multi-chip package. For example, the substrate package includes a first set of reference markers and a second set of reference markers. The first set of reference markers is disposed on the substrate package, where the first set of reference markers is configured to provide a first alignment for positioning a first integrated circuit (IC) and a second alignment for positioning a second IC on the substrate package. Further, the second set of reference markers is disposed at a different location on the substrate package than the first set of reference markers, where the second set of reference markers is configured to provide confirmation of the first alignment and the second alignment. | 2014-06-26 |
20140175614 | WAFER STACKING STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A wafer stacking structure includes a first wafer and a second wafer. The first wafer includes a first through silicon via (TSV) opening and a first TSV filling portion formed in the first TSV opening and including a concave structure. The second wafer includes a second TSV opening and a second TSV filling portion formed in the second TSV opening and including a convex structure. A front surface of the first wafer faces a front surface of the second wafer, and the convex structure of the second TSV filling portion is inserted into the concave structure of the first TSV filling portion. | 2014-06-26 |
20140175615 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device includes: forming a semiconductor element on a main surface of a substrate; forming a low melting glass film having a melting point of 450° C. or less on the main surface and the semiconductor element; heat treating the substrate while pressing the low melting glass film toward the main surface of the substrate with a pressurizing jig that is insulating or semi-insulating, and sintering the low melting glass film; and leaving the pressurizing jig on the low melting glass film after sintering the low melting glass film. | 2014-06-26 |
20140175616 | Composite of III-Nitride Crystal on Laterally Stacked Substrates - Group-III nitride crystal composites made up of especially processed crystal slices, cut from III-nitride bulk crystal, whose major surfaces are of {1-10±2}, {11-2±2}, {20-2±1} or {22-4±1} orientation, disposed adjoining each other sideways with the major-surface side of each slice facing up, and III-nitride crystal epitaxially present on the major surfaces of the adjoining slices, with the III-nitride crystal containing, as principal impurities, either silicon atoms or oxygen atoms. | 2014-06-26 |
20140175617 | OXYGEN-CONTAINING CERAMIC HARD MASKS AND ASSOCIATED WET-CLEANS - A method of forming an oxygen-containing ceramic hard mask film on a semiconductor substrate involves receiving a semiconductor substrate in a plasma-enhanced chemical vapor deposition (PECVD) process chamber and depositing forming by PEVCD on the substrate an oxygen-containing ceramic hard mask film, the film being etch selective to low-k dielectric and copper, resistant to plasma dry-etch and removable by wet-etch. The method may further involve removing the oxygen-containing ceramic hard mask film from the substrate with a wet etch. Corresponding films and apparatus are also provided. | 2014-06-26 |
20140175618 | TRANSITION METAL ALUMINATE AND HIGH K DIELECTRIC SEMICONDUCTOR STACK - Methods of forming a high K dielectric semiconductor stack are described. A semiconductor substrate is provided, in which the native oxide layer is removed. A transition metal aluminate layer is deposited onto the semiconductor substrate across discrete multiple regions in a combinatorial manner. A high K dielectric layer is deposited onto the transition metal aluminate layer across the discrete multiple regions in a combinatorial manner. The transition metal aluminate layer and the high K dielectric layer are patterned to form a plurality of high K dielectric semiconductor stacks across discrete multiple regions. A three-five semiconductor substrate or a germanium substrate can be used in methods of forming a high K dielectric semiconductor stack. | 2014-06-26 |
20140175619 | STRIPLINE AND REFERENCE PLANE IMPLEMENTATION FOR INTERPOSERS USING AN IMPLANT LAYER - An integrated circuit system includes an interposer substrate with an electrical reference plane, or “ground plane,” formed by a conductive semiconductor layer. The conductive semiconductor layer may be formed in a surface region of the interposer substrate, and in some embodiments is formed by performing an ion implant process on the surface region to increase the electrical conductivity of the surface region. Because the surface region is electrically coupled to an electrical ground of the integrated circuit system, the surface region functions as a ground plane that helps contain electric fields produced by signals routed through interconnects of the interposer substrate. Consequently, a ground plane can be formed on a surface of the interposer substrate without forming a metalization layer. | 2014-06-26 |
20140175620 | SEMICONDUCTOR DEVICE FABRICATION METHOD AND SEMICONDUCTOR DEVICE - There is provided a method of fabricating a semiconductor device, the method including: forming a first semiconductor region at a front surface of a substrate, the first semiconductor region including an active element that regulates current flowing in a thickness direction of the substrate; grinding a rear surface of the substrate; after the grinding, performing a first etching that etches the rear surface of the substrate with a chemical solution including phosphorus; after the first etching, performing a second etching that etches the rear surface with an etching method with a lower etching rate than the first etching; and after the second etching, forming a second semiconductor region through which the current is to flow, by implanting impurities from the rear surface of the substrate. | 2014-06-26 |
20140175621 | SYSTEMS AND METHODS FOR PROVIDING INTRAMODULE RADIO FREQUENCY ISOLATION - A radio frequency (RF) module comprises RF-shielding structure for providing three-dimensional electromagnetic interference shielding with respect to one or more RF devices disposed on the module. The RF-shielding may comprise wirebond structures disposed adjacent to or surrounding an RF device. Two or more intramodule devices may have wirebond structures configured to at least partially block certain types of RF signals disposed between the devices, thereby reducing effects of cross-talk between the devices. | 2014-06-26 |
20140175622 | SEGMENTED CONDUCTIVE TOP LAYER FOR RADIO FREQUENCY ISOLATION - A radio frequency (RF) module comprises a conductive top layer configured to improve RF interference-shielding functionality with respect to one or more RF devices disposed on the module. The conductive top layer may be segmented as to form one or more segments of the top layer that are at least partially electrically isolated from surrounding segments or devices. A module may have a plurality of devices disposed thereon, wherein separate, at least partially isolated, top conductive layers correspond to different devices of the module. The top layer may be etched or cut to achieve such segmentation. | 2014-06-26 |
20140175623 | Semiconductor Device and Method of Forming Discontinuous ESD Protection Layers Between Semiconductor Die - A semiconductor wafer has a plurality of semiconductor die separated by a saw street. The wafer is mounted to dicing tape. The wafer is singulated through the saw street to expose side surfaces of the semiconductor die. An ESD protection layer is formed over the semiconductor die and around the exposed side surfaces of the semiconductor die. The ESD protection layer can be a metal layer, encapsulant film, conductive polymer, conductive ink, or insulating layer covered by a metal layer. The ESD protection layer is singulated between the semiconductor die. The semiconductor die covered by the ESD protection layer are mounted to a temporary carrier. An encapsulant is deposited over the ESD protection layer covering the semiconductor die. The carrier is removed. An interconnect structure is formed over the semiconductor die and encapsulant. The ESD protection layer is electrically connected to the interconnect structure to provide an ESD path. | 2014-06-26 |
20140175624 | METHOD FOR MANUFACTURING A CHIP ARRANGEMENT, AND CHIP ARRANGEMENT - A method for manufacturing a chip arrangement in accordance with various embodiments may include: placing a chip on a carrier within an opening of a metal structure disposed over the carrier; fixing the chip to the metal structure; removing the carrier to thereby expose at least one contact of the chip; and forming an electrically conductive connection between the at least one contact of the chip and the metal structure. | 2014-06-26 |
20140175625 | SEMICONDUCTOR DEVICE INCLUDING AT LEAST ONE ELEMENT - A semiconductor device includes a chip, at least one element electrically coupled to the chip, an adhesive at least partially covering the at least one element, and a mold material at least partially covering the chip and the adhesive. | 2014-06-26 |
20140175626 | INTEGRATED CIRCUIT PACKAGE AND METHOD OF MANUFACTURE - An integrated circuit package has a leadframe having an open space extending therethrough. An integrated circuit device is attached to a portion of the upper surface of the leadframe. A shunt is located within the open space such that it is not in contact with any portion of the leadframe. | 2014-06-26 |
20140175627 | LEAD FRAME HAVING A PERIMETER RECESS WITHIN PERIPHERY OF COMPONENT TERMINAL - Embodiments described herein relate to manufacturing a device. The method includes etching at least one recess pattern in an internal surface of a lead frame, the at least one recess pattern including a perimeter recess that defines a perimeter of a mounting area. The method also includes attaching a component to the internal surface of the lead frame such that a single terminal of the component is attached in the mounting area and the single terminal covers the perimeter recess, wherein the perimeter recess has a size and shape such that the recess is proximate a perimeter of the single terminal. | 2014-06-26 |
20140175628 | COPPER WIRE BONDING STRUCTURE IN SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device comprises a first top electrode and a second top electrode at a front surface of the die, at least a Ni plating layer and an Au plating layer overlaying the Ni plating layer are formed on each of the first top electrode and the second top electrode. A copper clip attaches on the Au plating layer of the second top electrode. A gold (Au) stud bump is formed on the Au plating layer of the first top electrode with a copper wire connected on the stud bump. The Au stud bump is thicker than a thickness of the Au plating layer and thinner than a thickness of the copper clip to avoid copper wire NSOP (non-stick on pad) problem due to Ni plating layer diffusion during the solder reflow process in the copper clip attachment. | 2014-06-26 |
20140175629 | APPARATUS AND METHODS FOR REDUCING IMPACT OF HIGH RF LOSS PLATING - To reduce the radio frequency (RF) losses associated with high RF loss plating, such as, for example, Nickel/Palladium/Gold (Ni/Pd/Au) plating, an on-die passive device, such as a capacitor, resistor, or inductor, associated with a radio frequency integrated circuit (RFIC) is placed in an RF upper signal path with respect to the RF signal output of the RFIC. By placing the on-die passive device in the RF upper signal path, the RF current does not directly pass through the high RF loss plating material of the passive device bonding pad. | 2014-06-26 |
20140175630 | Semiconductor Package with Multiple Conductive Clips - One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. In this manner, the leadframe and the conductive clips provide efficient grounding or current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections. | 2014-06-26 |
20140175631 | SEMICONDUCTOR MODULE HAVING SLIDING CASE AND MANUFACTURING METHOD THEREOF - There is provided a semiconductor module capable of being easily manufactured and a manufacturing method thereof, the semiconductor module including a module substrate on which at least one electronic element is mounted, at least one external connection terminal fastened to the module substrate, and a case formed by coupling a first case and a second case, wherein the first case and the second case accommodate the module substrate at both ends of the module substrate and are coupled to each other. | 2014-06-26 |
20140175632 | THREE-DIMENSIONAL INTEGRATED CIRCUIT - A three-dimensional integrated circuit, including a first adhesive bonding layer, a first chip, a second chip, and an inter-stratum thermal pad, is provided. The first adhesive bonding layer has a first surface and a second surface opposite to each other. The first chip is disposed on the first surface of the first adhesive bonding layer. The first chip includes a hot zone. The second chip is disposed on the second surface of the first adhesive bonding layer. The inter-stratum thermal pad is embedded in the first adhesive bonding layer and faces to the hot zone. | 2014-06-26 |
20140175633 | THERMALLY ENHANCED SEMICONDUCTOR ASSEMBLY WITH EMBEDDED CHIP AND INTERPOSER AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a method of making a thermally conductive semiconductor assembly. In accordance with a preferred embodiment, the method includes: providing a chip; providing an interposer that includes a through via, a first contact pad on a first surface and a second contact pad on an opposite second surface; electrically coupling the chip to the first contact pad of the interposer by a conductive bump or a wire; providing a heat sink with a cavity; then attaching the chip and the interposer on the heat sink using an adhesive with the chip inserted into the cavity; and then forming a build-up circuitry on the second surface of the interposer. Accordingly, the heat sink can provide essential thermal dissipation for the embedded chip, and the interposer and build-up circuitry can respectively provide first and second level fan-out routing/interconnection for the embedded chip. | 2014-06-26 |
20140175634 | METHODS OF PROMOTING ADHESION BETWEEN UNDERFILL AND CONDUCTIVE BUMPS AND STRUCTURES FORMED THEREBY - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include modifying an underfill material with one of a thiol adhesion promoter, an azole coupling agent, surface modified filler, and peroxide based cross-linking polymer chemistries to greatly enhance adhesion in package structures utilizing the embodiments herein. | 2014-06-26 |
20140175635 | PACKAGING STRUCTURE - A packaging structure is provided. The packaging structure includes first and second chips, at least one surface of each of the first and second chips being an active surface and a common chip to which at least one of the first and second chips is electrically interconnected. The respective active surfaces of the first and second chips are directly electrically interconnected to one another in a face-to-face arrangement and are oriented transversely with respect to the common chip. | 2014-06-26 |
20140175636 | HIGH DENSITY INTERCONNECT DEVICE AND METHOD - Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards. | 2014-06-26 |
20140175637 | Back-to-back stacked integrated circuit assembly and method of making - An integrated circuit assembly includes a first substrate and a second substrate, with active layers formed on the first surfaces of each substrate, and with the second surfaces of each substrate coupled together. A method of fabricating an integrated circuit assembly includes forming active layers on the first surfaces of each of two substrates, and coupling the second surfaces of the substrates together. | 2014-06-26 |
20140175638 | SEMICONDUCTOR PACKAGES INCLUDING SEMICONDUCTOR CHIPS HAVING PROTRUSIONS AND METHODS OF FABRICATING THE SAME - The semiconductor package includes an upper semiconductor chip stacked on a package substrate and a support layer or a lower semiconductor chip disposed between the upper semiconductor chip and the package substrate. The upper semiconductor chip includes a protrusion downwardly extending from an edge thereof. The protrusion of the upper semiconductor chip is combined with a sidewall of the support layer or the lower semiconductor chip. Related methods are also provided. | 2014-06-26 |
20140175639 | Semiconductor Device and Method of Simultaneous Molding and Thermalcompression Bonding - A semiconductor device has a semiconductor die disposed over a substrate. The semiconductor die and substrate are placed in a chase mold. An encapsulant is deposited over and between the semiconductor die and substrate simultaneous with bonding the semiconductor die to the substrate in the chase mold. The semiconductor die is bonded to the substrate using thermocompression by application of force and elevated temperature. An electrical interconnect structure, such as a bump, pillar bump, or stud bump, is formed over the semiconductor die. A flux material is deposited over the interconnect structure. A solder paste or SOP is deposited over a conductive layer of the substrate. The flux material and SOP provide temporary bond between the semiconductor die and substrate. The interconnect structure is bonded to the SOP. Alternatively, the interconnect structure can be bonded directly to the conductive layer of the substrate, with or without the flux material. | 2014-06-26 |
20140175640 | Semiconductor Device and Method of Bonding Semiconductor Die to Substrate in Reconstituted Wafer Form - A semiconductor device has a plurality of semiconductor die disposed over a carrier. An electrical interconnect, such as a stud bump, is formed over the semiconductor die. The stud bumps are trimmed to a uniform height. A substrate includes a bump over the substrate. The electrical interconnect of the semiconductor die is bonded to the bumps of the substrate while the semiconductor die is disposed over the carrier. An underfill material is deposited between the semiconductor die and substrate. Alternatively, an encapsulant is deposited over the semiconductor die and substrate using a chase mold. The bonding of stud bumps of the semiconductor die to bumps of the substrate is performed using gang reflow or thermocompression while the semiconductor die are in reconstituted wafer form and attached to the carrier to provide a high throughput of the flipchip type interconnect to the substrate. | 2014-06-26 |
20140175641 | Method for Welding Gold-Silicon Eutectic Chip, and Transistor - Relating to electronic components, the present disclosure provides a method for welding a gold-silicon eutectic chip, and a transistor. The method for welding a gold-silicon eutectic chip includes: electroplating a gold layer with a thickness smaller than or equal to 1 micron on surfaces of a chip carrier; bonding multiple gold protrusions on the gold layer in a welding region; and rubbing a chip in the welding region at a eutectic temperature to form a welding layer. The transistor includes a chip, a chip carrier, and a middle layer connecting the chip and the chip carrier, where the welding middle layer is a welding layer obtained by using the above welding method. The present disclosure reduces an amount of gold in use and lowers a cost of gold-silicon eutectic welding to a relatively large extent, and, accordingly, cuts down the cost of a transistor. | 2014-06-26 |
20140175642 | Semiconductor Device and Method of Forming Interconnect Structure with Conductive Pads Having Expanded Interconnect Surface Area for Enhanced Interconnection Properties - A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is expanded by forming a plurality of recesses into the first conductive pads. The recesses can be an arrangement of concentric rings, arrangement of circular recesses, or arrangement of parallel linear trenches. Alternatively, the interconnect surface area of the first conductive pads is expanded by forming a second conductive pad over the first conductive pad. A semiconductor die has a plurality of interconnect structures formed over a surface of the semiconductor die. The semiconductor die is mounted to the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structure to the first conductive pads. A mold underfill material is deposited between the semiconductor die and substrate. | 2014-06-26 |
20140175643 | APPARATUSES AND METHODS TO ENHANCE PASSIVATION AND ILD RELIABILITY - Some embodiments of the present invention include apparatuses and methods relating to processing and packaging microelectronic devices that reduce stresses on and limit or eliminate crack propagation in the devices. | 2014-06-26 |
20140175644 | METHODS OF FORMING ULTRA THIN PACKAGE STRUCTURES INCLUDING LOW TEMPERATURE SOLDER AND STRUCTURES FORMED THERBY - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include attaching a device to a patch substrate, wherein the assembled device and patch substrate comprise a warpage, attaching the assembled device and patch substrate to an interposer to form a package structure, and then reflowing the package structure at a temperature below about 200 degrees Celsius to form a substantially flat package structure. | 2014-06-26 |
20140175645 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Embodiments relate to a method for manufacturing a semiconductor device including at least one of: (1) Forming a lower electrode pattern on a substrate. (2) Forming an etch stop film on/over the lower electrode pattern. (3) Forming a first interlayer insulating layer on/over the etch stop film. (4) Forming an upper electrode pattern on/over the first interlayer insulating layer. (5) Forming a second interlayer insulating layer on/over the upper electrode pattern. (6) Forming an etch blocking layer positioned between the lower electrode pattern and the upper electrode pattern which passes through the second interlayer insulating layer and the first interlayer insulating layer. (7) Forming a cavity which exposes a side of the etch blocking layer by etching the second interlayer insulating layer and the first interlayer insulating layer. (8) Forming a contact ball in the cavity. | 2014-06-26 |
20140175646 | PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING SAME - An exemplary package substrate includes a package substrate, a first connection substrate, a first chip, a dielectric adhesive sheet, a second chip, and a second connection substrate. The package substrate includes many first and second electrical contact pads. The first connection substrate includes many third and fourth electrical contact pads. Each fourth electrical contact pad is electrically connected to one first electrical contact pad. The first chip includes many first electrode pads. Each first electrode pad is electrically connected to the corresponding third electrical contact pad. The second chip is connected to the first chip by the dielectric adhesive sheet, and includes many second electrode pads. The second connection substrate includes many fifth and sixth electrical contact pads. Each fifth electrical contact pad is electrically connected to one second electrode pad, and each sixth electrical contact pad is electrically connected to one second electrical contact pad. | 2014-06-26 |
20140175647 | PACKAGED MICROELECTRONIC ELEMENTS HAVING BLIND VIAS FOR HEAT DISSIPATION - System and method for thermal management in a multi-chip packaged device. A microelectronic unit is disclosed, and includes a semiconductor element having atop surface and a bottom surface remote from the top surface. A semiconductor device including active elements is located adjacent to the top surface. Operation of the semiconductor device generates heat. Additionally, one or more first blind vias extend from the bottom surface and partially into a thickness of the semiconductor element. In that manner, the blind via does not contact or extend to the semiconductor device (defined as active regions of the semiconductor element, and moreover, is electrically isolated from the semiconductor device. A thermally conductive material fills the one or more first blind vias for heat dissipation. Specifically, heat generated by the semiconductor device thermally conducts from the semiconductor element, and is further distributed, transferred and/or dissipated through the one or more first blind vias to other connecting components. | 2014-06-26 |
20140175648 | Semiconductor Device and Power Supply Unit Utilizing the Same - A semiconductor device has pluralities of grid array terminals forming a grid array structure, e.g. a BGA structure, in which the output end of a built-in switch circuit is connected to multiple terminals of the grid array structure, thereby reducing the current that flows through each of the multiple terminals below a permissible level and minimizing the heat due to contact resistances of the multiple terminals in contact, with the IC socket of the semiconductor device. Each pair of nearest neighbors, of the multiple terminals is interposed by at least one further array terminal. The multiple terminals are all located at the outermost peripheral terminal positions of the grid array structure. Thus, the heat generated in the respective multiple terminals connected to the switch circuit is reduced, thereby minimizing the possibility of hazardous melting of the terminals. | 2014-06-26 |
20140175649 | ELECTRONIC DEVICE INCLUDING ELECTRICALLY CONDUCTIVE VIAS HAVING DIFFERENT CROSS-SECTIONAL AREAS AND RELATED METHODS - An electronic device may include a bottom interconnect layer having a first electrically conductive via therein. The electronic device may also include an integrated circuit (IC) carried by said bottom interconnect layer, and an encapsulation material on the bottom interconnect layer and surrounding the IC. The encapsulation layer may have a second electrically conductive via therein aligned with the first electrically conductive via. The second electrically conductive via may have a cross-sectional area larger than a cross-sectional area of the first electrically conductive via. | 2014-06-26 |
20140175650 | INTERCONNECTION WIRES OF SEMICONDUCTOR DEVICES - Disclosed are a method to fabricate interconnection wires of a semiconductor device in a way to utilize benefits of copper interconnection and low k dielectric insulation while avoiding the problem of low k damage due to etching processes, and so fabricated interconnection wires. The method saves fabrication time and cost by reduced number of steps and also resolves metal gap fill issue. The method may comprise providing layers of a substrate, an etch stop layer and a sacrificial layer, forming first spacers, forming first copper interconnecting wires, removing the first spacers; forming polymer-like second spacers by depositing plasma gases in an etching chamber, forming second metal interconnecting wires, removing the second spacers to define channels interwoven with alternating first and second metal interconnecting wires, forming an anti-diffusion barrier around each of the first and second metal interconnecting wires, and filling the channels with a dielectric material for insulation. | 2014-06-26 |
20140175651 | LANDING STRUCTURE FOR THROUGH-SILICON VIA - Embodiments of the present disclosure describe techniques and configurations associated with forming a landing structure for a through-silicon via (TSV) using interconnect structures of interconnect layers. In eon embodiment, an apparatus includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a device layer disposed on the first surface of the semiconductor substrate, the device layer including one or more transistor devices, interconnect layers disposed on the device layer, the interconnect layers including a plurality of interconnect structures and one or more through-silicon vias disposed between the first surface and the second surface, wherein the plurality of interconnect structures include interconnect structures that are electrically coupled with the one or more TSVs and configured to provide one or more corresponding landing structures of the one or more TSVs. Other embodiments may be described and/or claimed. | 2014-06-26 |
20140175652 | Barrier for Through-Silicon Via - A system and a method for protecting vias is disclosed. An embodiment comprises forming an opening in a substrate. A barrier layer disposed in the opening including along the sidewalls of the opening. The barrier layer may include a metal component and an alloying material. A conductive material is formed on the barrier layer and fills the opening. The conductive material to form a via (e.g., TSV). | 2014-06-26 |
20140175653 | SEMICONDUCTOR DEVICES COMPRISING INTERCONNECT STRUCTURES AND METHODS OF FABRICATION - Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material. | 2014-06-26 |
20140175654 | SURFACE MODIFIED TSV STRUCTURE AND METHODS THEREOF - Microelectronic elements and methods of their manufacture are disclosed. A microelectronic element may include a substrate including an opening extending through a semiconductor region of the substrate, a dielectric layer cover a wall of the opening within at least a first portion of the opening, a first metal disposed within the first portion of the opening, a second metal disposed within a second portion of the opening. The second metal may form at least part of a contact of the microelectronic element. | 2014-06-26 |
20140175655 | CHIP BONDING STRUCTURE AND MANUFACTURING METHOD THEREOF - A chip bonding structure at least includes a first substrate, a second substrate opposite to the first substrate, and a copper bonding structure sandwiched in between the first and the second substrates. A Cu—Cu bonding interface is within the copper bonding structure and is characterized with combinations of protrusions and recesses, and the copper crystallization orientation at one side of the Cu—Cu bonding interface is different from that at another side. | 2014-06-26 |
20140175656 | USE OF GRAPHENE TO LIMIT COPPER SURFACE OXIDATION, DIFFUSION AND ELECTROMIGRATION IN INTERCONNECT STRUCTURES - A contiguous layer of graphene is formed on exposed sidewall surfaces and a topmost surface of a copper-containing structure that is present on a surface of a substrate. The presence of the contiguous layer of graphene on the copper-containing structure reduces copper oxidation and surface diffusion of copper ions and thus improves the electromigration resistance of the structure. These benefits can be obtained using graphene without increasing the resistance of copper-containing structure. | 2014-06-26 |
20140175657 | METHODS TO IMPROVE LASER MARK CONTRAST ON DIE BACKSIDE FILM IN EMBEDDED DIE PACKAGES - Apparatus including a die including a device side with contact points; and a build-up carrier disposed on the device side of the die; and a film disposed on the back side of the die, the film including a markable material including a mark contrast of at least 20 percent. Method including forming a body of a build-up carrier adjacent a device side of a die; and forming a film on a back side of the die, the film including a markable material including a mark contrast of at least 20 percent. Apparatus including a package including a microprocessor disposed in a carrier; a film on the back side of the microprocessor, the film including a markable material including a mark contrast of at least 20 percent; and a printed circuit board coupled to at least a portion of the plurality of conductive posts of the carrier. | 2014-06-26 |
20140175658 | ANCHORING A TRACE ON A SUBSTRATE TO REDUCE PEELING OF THE TRACE - Sonic implementations pertain to a semiconductor device that includes a packaging substrate, a trace coupled to the packaging substrate, and a solder resist layer that covers part of the trace. The trace includes a first portion having a first width, and a second portion having a second width that is wider than the first width. In some implementations, the second portion having the second width increases the area of the trace coupled to the packaging substrate to reduce the likelihood of the trace peeling from the packaging substrate. In some implementations, the solder resist layer further includes an opening such that the second portion of the trace is exposed. In some implementations, the trace further includes a third portion located between the first portion and second portion of the trace and wherein the third portion of the trace is exposed through an opening in the solder resist layer. | 2014-06-26 |
20140175659 | SEMICONDUCTOR DEVICE INCLUDING AIR GAPS AND METHOD OF FABRICATING THE SAME - This technology provides a semiconductor device and a method of fabricating the same, which may reduce parasitic capacitance between adjacent conductive structures. The method of fabricating a semiconductor device may include forming a plurality of bit line structures over a substrate, forming contact holes between the bit line structures, forming sacrificial spacers over sidewalls of the contact holes, forming first plugs recessed into the respective contact holes, forming air gaps by removing the sacrificial spacers, forming capping structures capping the air gaps while exposing top surfaces of the first plugs, and forming second plugs over the first plugs. | 2014-06-26 |
20140175660 | STACK PACKAGES HAVING TOKEN RING LOOPS - Stack packages are provided. The stack package includes a substrate having first and second bond fingers and a plurality of semiconductor chips stacked on the substrate. Each of the plurality of semiconductor chips has an input bonding pad and an output bonding pad. A first interconnection electrically connects the first bond finger to the input bonding pad of a lowermost semiconductor chip of the plurality of semiconductor chips. A second interconnection electrically connects the output bonding pad of a lower semiconductor chip of the plurality of semiconductor chips to the input bonding pad of an upper semiconductor chip stacked on the lower semiconductor chip. A third interconnection electrically connects the output bonding pad of an uppermost semiconductor chip of the plurality of semiconductor chips to the second bond finger. | 2014-06-26 |
20140175661 | Semiconductor Device and Method of Making Bumpless Flipchip Interconnect Structures - A semiconductor device includes a substrate with contact pads. A mask is disposed over the substrate. Aluminum-wettable conductive paste is printed over the contact pads of the substrate. A semiconductor die is disposed over the aluminum-wettable conductive paste. The aluminum-wettable conductive paste is reflowed to form an interconnect structure over the contact pads of the substrate. The contact pads include aluminum. Contact pads of the semiconductor die are disposed over the aluminum-wettable conductive paste. The aluminum-wettable conductive paste is reflowed to form an interconnect structure between the contact pads of the semiconductor die and the contact pads of the substrate. The interconnect structure is formed directly on the contact pads of the substrate and semiconductor die. The contact pads of the semiconductor die are etched prior to reflowing the aluminum-wettable conductive paste. An epoxy pre-dot to maintain a separation between the semiconductor die and substrate. | 2014-06-26 |
20140175662 | POWER LAYOUT FOR INTEGRATED CIRCUITS - An integrated circuit with a power layout includes at least one power grid cell. Each power grid cell includes a first power layer configured to be electrically coupled to a first power supply voltage, and a second power layer separate from the first power layer and configured to be electrically coupled to a second power supply voltage different from the first power supply voltage. The first power layer has conductive lines configured to surround a conductive element electrically connected to the second power layer. | 2014-06-26 |
20140175663 | SEMICONDUCTOR DEVICE HAVING CONDUCTIVE VIA AND MANUACTURING PROCESS - In accordance with the present invention, there is provided a semiconductor device comprising a semiconductor die or chip, a package body and a through package body via. The semiconductor chip includes a plurality of conductive pads. The package body encapsulates a sidewall of the semiconductor chip, and has at least one hole formed therein having a sidewall which is of a prescribed first surface roughness value. The through package body via is disposed in the hole of the package body and comprises a dielectric material and at least one conductive interconnection metal. The dielectric material is disposed on the sidewall of the hole and defines at least one bore having a sidewall which is of a second surface roughness value less than the first surface roughness value. The interconnection metal is disposed within the bore. | 2014-06-26 |
20140175664 | DIELECTRIC SOLDER BARRIER FOR SEMICONDUCTOR DEVICES - The present disclosure relates to a dielectric solder barrier for a semiconductor die. In one embodiment, a semiconductor die includes a substrate, a semiconductor body on a first surface of the substrate, one or more first metallization layers on the semiconductor body opposite the substrate, a via that extends from a second surface of the substrate through the substrate and the semiconductor body to the one or more first metallization layers, and a second metallization layer on the second surface of the substrate and within the via. A portion of the second metallization layer within the via provides an electrical connection between the second metallization layer and the one or more first metallization layers. The semiconductor die further includes a dielectric solder barrier on the second metallization layer. Preferably, the dielectric solder barrier is on a surface of the portion of the second metallization layer within the via. | 2014-06-26 |
20140175665 | CHIP PACKAGE USING INTERPOSER SUBSTRATE WITH THROUGH-SILICON VIAS - A microelectronic package includes an interposer with through-silicon vias that is formed from a semiconductor substrate and one or more semiconductor dies coupled to the interposer. A first signal redistribution layer formed on the first side of the interposer electrically couples the one or more semiconductor dies to the through-silicon vias. A second redistribution layer is formed on a second side of the interposer, and is electrically coupled to the through-silicon vias. In some embodiments, a mold compound is connected to an edge surface of the interposer and is configured to stiffen the microelectronic package. | 2014-06-26 |
20140175666 | INTEGRATED CIRCUIT DEVICE WITH STITCHED INTERPOSER - Systems, methods, and devices are provided to enable an integrated circuit device of relatively higher capacity. Such an integrated circuit device may include at least two component integrated circuits that communicate with one another. Specifically, the component integrated circuits may communicate through a “stitched silicon interposer” that is larger than a reticle limit of the lithography system used to manufacture the interposer. To achieve this larger size, the stitched silicon interposer may be composed of at least two component interposers, each sized within the reticle limit and each separated from one another by a die seal structure. | 2014-06-26 |
20140175667 | SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR SYSTEM WITH THE SAME - A semiconductor integrated circuit may include a plurality of semiconductor chips configured to be stacked in three dimensions, a first group of through-chip vias configured to go through the plurality of semiconductor chips, respectively, and to be used for density extension of the semiconductor integrated circuit, and a second group of through-chip vias configured to go through the plurality of semiconductor chips, respectively, and to be used for a bandwidth extension of the semiconductor integrated circuit. Each of the plurality of semiconductor chips includes a path selection unit configured to select one of the first group of through-chip vias arranged in the semiconductor chip or one of the second group of through-chip vias arranged in the semiconductor chip in response to a mode switching signal, and an internal circuit configured to be selectively coupled to a through-chip via selected by the path selection unit. | 2014-06-26 |
20140175668 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a first interface block configured to transmit and receive signals within the same chip; a second interface block configured to transmit and receive signals to and from different semiconductor chips; and a switching block configured to select a signal path in which the signal transmission and reception of the first interface block is not performed through the second interface block, in response to a chip structure signal. | 2014-06-26 |
20140175669 | METHOD FOR FORMING A DUAL DAMASCENE STRUCTURE OF A SEMICONDUCTOR DEVICE, AND A SEMICONDUCTOR DEVICE THEREWITH - Forming a dual damascene structure includes forming a first insulation layer and a second insulation layer, forming a resist mask, forming a via hole down to a lower end of the first insulation layer, forming a hardmask layer in the via hole and on the second insulation layer using a spin-coating method, forming a resist mask, forming a first trench hole down to a lower end of the second insulation layer, respectively removing a part of the hardmask layer in the via hole and a part of the hardmask layer on the second insulation layer, forming a second trench hole by removing a part of the first insulation layer between a top corner of the hardmask layer remaining in the via hole and a bottom corner of the first trench hole, removing the hardmask layer, and filling the via hole and the second trench hole with a conductive material. | 2014-06-26 |
20140175670 | STACKED DIE PACKAGE - The formation of electronic assemblies is described. One embodiment includes first and second semiconductor die structures each including a front side and a backside, the front side including an active region and the backside including metal regions and non-metal regions thereon. The first and second semiconductor die structures include a plurality of vias, the vias forming electrical connections between the active region and the backside metal regions. The first and second semiconductor die structures are stacked together with at least one of the metal regions on the backside of the first semiconductor die structure in direct contact with at least one of the metal regions on the back side of the second semiconductor die structure. Other embodiments are described and claimed. | 2014-06-26 |
20140175671 | STRUCTURE FOR MICROELECTRONIC PACKAGING WITH BOND ELEMENTS TO ENCAPSULATION SURFACE - A structure may include bond elements having bases joined to conductive elements at a first portion of a first surface and end surfaces remote from the substrate. A dielectric encapsulation element may overlie and extend from the first portion and fill spaces between the bond elements to separate the bond elements from one another. The encapsulation element has a third surface facing away from the first surface. Unencapsulated portions of the bond elements are defined by at least portions of the end surfaces uncovered by the encapsulation element at the third surface. The encapsulation element at least partially defines a second portion of the first surface that is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some conductive elements are at the second portion and configured for connection with such microelectronic element. | 2014-06-26 |
20140175672 | HYBRID SUBSTRATE WITH HIGH DENSITY AND LOW DENSITY SUBSTRATE AREAS, AND METHOD OF MANUFACTURING THE SAME - Provided is a hybrid substrate with high density and low density substrate areas and a method of manufacturing the same. The hybrid substrate with high density and low density substrate areas includes a low density substrate layer having a cavity and a low density area, a high density substrate layer mounted in the cavity of the low density substrate layer and formed of a high density area having a higher pattern density than that of the low density area, an insulating support layer comprising a deposition area formed on upper portions, lower portions and the upper and lower portions of the high density substrate layer and the low density substrate layer, insulating layer vias passing through the deposition area of the insulating support layer and connected to patterns of the high density substrate layer and the low density substrate layer, and an outer pattern layer. | 2014-06-26 |
20140175673 | SEMICONDUCTOR PACKAGE - A semiconductor package is provided comprising a package substrate having an opening located in a central region thereof and a circuit pattern provided adjacent to the opening. A first semiconductor chip is located on the package substrate and includes first bonding pads. A pair of second semiconductor chips are spaced apart from each other across the opening and mounted between the package substrate and the first semiconductor chip. Each of the second semiconductor chips includes a second bonding pad. A connection element is further provided to electrically connect the second bonding pad to a corresponding one of the first bonding pads. | 2014-06-26 |
20140175674 | Package on Package Device - The present invention provides a package on package device. At least two components are sequentially soldered with each other. A size of a base plate of a component located below is greater than a size of an edge of a component located above. In the case of a package on package device, the size of the base plate of the component located below is greater than the size of the edge of the component located above. | 2014-06-26 |
20140175675 | DEVICES AND METHODS FOR STACKING INDIVIDUALLY TESTED DEVICES TO FORM MULTI-CHIP ELECTRONIC MODULES - A method for manufacturing an electronic multi-chip module that involves stacking at least six tested devices to form the module. These devices may be individually tested prior to assembling the electronic module. After individually testing the devices, the devices may be stacked one on top of the other to form an electronic multi-chip module having at least six stacked devices. Other embodiments may be described and claimed. | 2014-06-26 |
20140175676 | Method for Bonding of Group III-Nitride Device-on-Silicon and Devices Obtained Thereof - A method for flip chip bonding a GaN device formed on a silicon substrate is described. The method includes providing a silicon substrate having a GaN device thereon, the GaN device comprising at least one gallium-nitride layer near the silicon substrate and remote from the silicon substrate a dielectric layer comprising at least one via configured to electrically contact the at least one gallium-nitride layer, forming a stiffener layer over the GaN device leaving the at least one via exposed, flip chip bonding the GaN device to a submount, wherein the stiffener layer physically contacts the submount and the submount is electrically connected to the at least gallium-nitride layer through the via, and completely removing the silicon substrate exposing the GaN device. Preferably, the material of the stiffener layer comprises silicon, such as silicon, silicon-germanium, or silicon-carbide. | 2014-06-26 |
20140175677 | DICING TAPE-INTEGRATED FILM FOR SEMICONDUCTOR BACK SURFACE - The present invention provides a dicing tape-integrated film for semiconductor back surface, which includes: a dicing tape including a base material and a pressure-sensitive adhesive layer provided on the base material; and a film for flip chip type semiconductor back surface provided on the pressure-sensitive adhesive layer, in which the film for flip chip type semiconductor back surface contains a black pigment. | 2014-06-26 |
20140175678 | Semiconductor Device and Method of Manufacturing the Same - To achieve a reduction in cost of a semiconductor device, in a common board (a wiring board), a plurality of bonding leads each extend toward the center of the board, and a solder resist film as a die bonding region supporting a minimum chip is coated with a die bonding material. With this, even when a first semiconductor chip as a large chip is mounted, wire bonding can be performed without causing the die bonding material to cover the bonding leads. Thus, development cost can be reduced to reduce the cost of the semiconductor device (LGA). | 2014-06-26 |
20140175679 | SEMICONDUCTOR DEVICES, PACKAGE SUBSTRATES, SEMICONDUCTOR PACKAGES, PACKAGE STACK STRUCTURES, AND ELECTRONIC SYSTEMS HAVING FUNCTIONALLY ASYMMETRIC CONDUCTIVE ELEMENTS - A package stack structure may an upper package include an upper package substrate having a first edge and a second edge opposite to the first edge. The upper package substrate has a first region arranged near the first edge and a second region arranged near the second edge. A first upper semiconductor device is mounted on the upper package substrate. The package stack structure may also include a lower package having a lower package substrate and a lower semiconductor device. The lower package is connected to the upper package through a plurality of inter-package connectors. The plurality of the inter-package connectors may include first inter-package connectors configured to transmit data signals; second inter-package connectors configured to transmit address/control signals; third inter-package connectors configured to provide a supply voltage for an address/control circuit; and fourth inter-package connectors configured to provide a supply voltage for a data circuit. | 2014-06-26 |
20140175680 | ELECTRICAL CHARACTERISTICS OF PACKAGE SUBSTRATES AND SEMICONDUCTOR PACKAGES INCLUDING THE SAME - Package substrates are provided. The package substrate may include a power line and a ground line on a first surface of a substrate body; a plurality of signal lines on the first surface between the power line and the ground line; and a lower ground pattern and a lower power pattern positioned on a second surface of the substrate body opposite to the first surface. The lower ground pattern may be disposed to be opposite to the power line and the lower power pattern may be disposed to be opposite to the ground line. Related semiconductor packages are also provided. | 2014-06-26 |
20140175681 | ABSORBING EXCESS UNDER-FILL FLOW WITH A SOLDER TRENCH - One embodiment sets forth an integrated circuit package that includes a substrate, one or more devices mounted on the substrate, a layer of under-fill configured to secure the one or more devices on the substrate, and a solder trench formed in the substrate, where the aggregate volume of the solder trench is large enough to capture a flow of excess under-fill during fabrication. One advantage of the disclosed integrated circuit package is that the solder trench is used in lieu of solder dam structures, thereby allowing a stencil to be lowered closer to the substrate surface during fabrication, which facilitates depositing solder paste during fabrication. | 2014-06-26 |
20140175682 | Devices and Methods for Improved Delivery of Volatile Liquids - An emanation system is described comprising and emanation device and a replaceable refill of liquid, wherein the refill comprises: a sealed reservoir of a liquid containing one or more active materials wherein the active material comprises at least ona of: a fragrance; an insecticide; a fungicide; a pesticide; a sanitising material; and/or a pharmaceutical; a porous wick having a length which extends from the interior of the reservoir to the exterior thereof; a reservoir seal having at least one aperture through which the porous wick extends; and a hollow liquid conduit housed within the wick having a length substantially identical to the wick; and wherein tha device comprises: an air pump; a fluid conduit In fluid communication with tha air pump such that, in use, air pumped by the pump will flow through the fluid conduit; a nozzle located at the end of the fluid conduit remote from tha air pump; a elector constriction provided in the fluid conduit adjacent or substantially adjacent the nozzle; a liquid conduit engaging member provided adjacent the ejector constriction and in fluid communication with the fluid conduit at one end thereof, and configured at the other end to, In use, engage the hollow liquid conduit in the refill. | 2014-06-26 |
20140175683 | AROMATIC POLYAMIDE FILMS FOR SOLVENT RESISTANT FLEXIBLE SUBSTRATES - This disclosure, viewed from one aspect, relates to a solution of polyamide comprising: an aromatic polyamide, silane coupling agent and a solvent. The solution of polyamide can improve adhesion between the polyamide film and the base of glass or silicon wafer. | 2014-06-26 |
20140175684 | Methods and Equipment for Trimming Polarizers in Displays - An electronic device is provided with a display such as a liquid crystal display mounted in an electronic device housing. The display includes a glass display layer such as a glass color filter substrate. A polarizer layer is formed on the glass display layer. To ensure that the peripheral edge of the polarizer layer matches the peripheral edge of the glass display layer, a laser beam scanning system is used to trim edge portions of the polarizer layer that overhang the glass display layer. The laser beam scanning system includes a moving laser beam that makes multiple scans along the edge of the polarizer layer. To prevent damage to the glass display layer during trimming operations, a characteristic of the moving laser is modified in between successive scans such that the energy density of the laser cut is reduced as the laser beam approaches the surface of the glass. | 2014-06-26 |
20140175685 | Method for Making Silicone Hydrogel Contact Lenses - The instant invention pertains to a method and a fluid polymerizable composition for producing contact lenses with improved lens quality and with increased product yield. The method of the invention involves adding a water soluble and/or water dispersible quaternary ammonium cationic group containing silicone surfactant into a fluid polymerizable composition including a lens-forming material in an amount sufficient to reduce an averaged mold separation force by at least about 30% in comparison with that without the water soluble and/or water dispersible quaternary ammonium cationic group containing silicone surfactant. | 2014-06-26 |
20140175686 | Poorly Soluble Drug Containing Microspheres With Improved Bioavailability And Method Of Preparing The Same - A poorly soluble drug containing microsphere with improved bioavailability, an oral formulation comprising the same, and a method of preparing the same are provided, wherein the poorly soluble drug containing microsphere is a solid dispersion wherein the poorly soluble drug is dispersed in the water-soluble polymer carrier in a noncrystalline form by spray drying, thus increasing bioavailability of the poorly soluble drug. | 2014-06-26 |
20140175687 | CARBON-COATED LITHIUM TITANIUM SPINEL - A carbon-containing lithium titanium oxide containing spherical particle aggregate with a diameter of 1-80 μm, consisting of lithium titanium oxide primary particles coated with carbon. Also, a method for the production of such a carbon-containing lithium titanium oxide as well as an electrode containing such a carbon-containing lithium titanium oxide as active material as well as a lithium-ion secondary battery containing an above-described electrode. | 2014-06-26 |
20140175688 | METHODS OF MAKING CARBON FIBER FROM ASPHALTENES - Making carbon fiber from asphaltenes obtained through heavy oil upgrading. In more detail, carbon fiber is made from asphaltenes obtained from heavy oil feedstocks undergoing upgrading in a continuous coking reactor. | 2014-06-26 |
20140175689 | TUBING RESHAPING METHOD AND APPARATUS - A method for use in reshaping a deformed tubing section ( | 2014-06-26 |
20140175690 | INJECTION-MOLDING TOOL AND METHOD FOR MODIFYING SUCH AN INJECTION-MOLDING TOOL IN AN INJECTION-MOLDING MACHINE - An injection-molding tool ( | 2014-06-26 |
20140175691 | MOLD PROTECTION APPARATUS, MOLD PROTECTION METHOD AND MOLD CLAMPING APPARATUS - According to one embodiment, a mold protection apparatus for use in an opening/closing apparatus, the movable platen being formed to be movable in a direction towards or away from a fixed platen having a fixed mold and being fixedly provided with a movable mold, the mold protection apparatus comprises a deriving means, a calculating means, and a comparing means. The deriving means configured to obtain an actual operation drive force output from the motor. The calculating means configured to calculate a theoretical operation drive force of the motor. The comparing means configured to compare a difference between the actual operation drive force derived by the deriving means and the theoretical operation drive force calculated by the calculating means with a threshold value. | 2014-06-26 |
20140175692 | METHOD FOR MONITORING A TEMPERATURE CONTROL MEDIA SUPPLY - In a method of monitoring an apparatus for temperature control media supply of a tool of an injection molding machine, the apparatus for temperature control media supply has a feed and a return, between which at least one temperature control conduit is arranged, wherein at least one through-flow sensor is arranged. At least one temperature control conduit. At least one pressure drop is measured in the at least one temperature control conduit. At least one hydraulic resistance and/or at least one resistance change in the at least one temperature control conduit is calculated on the basis of at least one volume flow measured with the at least one through-flow sensor and on the basis of the at least one measured pressure drop, and the at least one hydraulic resistance and/or the at least one resistance change is visually represented. | 2014-06-26 |
20140175693 | Method of Fabricating a Porous Orthopedic Implant - A tissue scaffold fabricated from bioinert fiber forms a rigid three-dimensional porous matrix having a bioinert composition. Porosity in the form of interconnected pore space is provided by the space between the bioinert fiber in the porous matrix. Strength of the porous matrix is provided by bioinert fiber fused and bonded into the rigid three-dimensional matrix having a specific pore size and pore size distribution. The tissue scaffold supports tissue in-growth to provide osteoconductivity as a tissue scaffold, used for the repair of damaged and/or diseased bone tissue. | 2014-06-26 |
20140175694 | MANUFACTURING METHOD FOR FIBER-REINFORCED RESIN SHEET AND MANUFACTURING DEVICE THEREFOR - Provided is a manufacturing method for a fiber-reinforced resin sheet, the method being able to favorably impregnate a reinforcing-fiber base material with a thermoplastic resin. A fiber-reinforced resin sheet S is manufactured by introducing a reinforcing-fiber base material F in sheet form and a thermoplastic resin P into the gap between a pair of impregnating rolls | 2014-06-26 |
20140175695 | MELT PROCESSING PLANT - The present invention relates to a melt processing plant, comprising a melt charger for charging a processing head, in particular palletizing head, with melt, wherein upstream of the processing head a diverter valve for discharging the melt during a starting and/or retooling phase is associated to the melt charger, and to a method for melt processing in such melt processing plant. In accordance with the invention, a portioning device for portioning the discharged melt into melt portions is associated to the diverter valve, wherein a cooling device for cooling the melt portions to at least partly solidified chunks of material is provided. | 2014-06-26 |
20140175696 | System and Method for Forming Fiber Reinforced Polymer Tape - Systems and methods for forming fiber reinforced polymer tapes are disclosed. A method may include, for example, traversing a polymer impregnated roving through a system comprising an inlet and an outlet, applying a consolidation pressure within the system to the polymer impregnated roving, and applying a smoothing pressure within the system to the polymer impregnated roving. The method may further include adjusting a temperature of the polymer impregnated roving with a heat transfer device between the inlet and the outlet, the heat transfer device having a temperature different from a temperature of the polymer impregnated roving at the inlet. | 2014-06-26 |
20140175697 | Modified Long Chain Polyamide - A modified long chain polyamide is provided. The modified long chain polyamide is polymerized by monomers comprising a long-aliphatic-chain monomer, and equimolar of an aromatic diacid and polyethyleneoxy diamine. A fiber made from the modified long chain polyamide is also provided. | 2014-06-26 |
20140175698 | METHOD AND APPARATUS EMPLOYING MODULAR ENGAGEABLE COMPONENTS FOR FORMATION OF MAINTENANCE HOLE PLATFORMS - A method for forming a maintenance hole base for the bottom surface of a maintenance shaft using a configurable modular mold and thermoforming or rotational molding. The modular mold is formed of individual members of groups of central core components engageable to surrounding periphery components to yield a mold which will form the appropriate engagement and communication pathways for the base when installed. Polymeric material is employed with the mold to yield a finished component configured for use in the base of the maintenance shaft. | 2014-06-26 |
20140175699 | MOLD FOR INJECTION-MOLDING A GOLF BALL, AND GOLF BALL MANUFACTUING METHOD - The invention provides a mold for injection-molding a golf ball, which mold has a cavity inner wall with a vertical diameter connecting both poles in a vertical direction thereof that is longer than a horizontal diameter connecting both poles in a horizontal direction thereof. A method of manufacturing golf balls using such a mold is also provided. The use of this mold eliminates molding problems that arise when molding the outermost cover layer of a golf ball, enabling the cover to be stably molded and also making it possible to easily and reliably obtain golf balls of high symmetry in which a cover of uniform thickness has been formed. | 2014-06-26 |