26th week of 2009 patent applcation highlights part 30 |
Patent application number | Title | Published |
20090161390 | Synchronous Rectification Control Circuit Assembly - A synchronous rectification control circuit assembly includes a first transformer, a reference voltage generator, a first PWM control signal generating circuit, a second PWM control signal generating circuit, a first synchronous rectification circuit, and a second synchronous rectification circuit. When the output voltage rises, the conduction time of the first synchronous rectification circuit and the second synchronous rectification circuit are relatively regulated to lower the output voltage, maintaining stability of the output voltage. | 2009-06-25 |
20090161391 | DOUBLE-ENDED ISOLATED DC-DC CONVERTER - In a double-ended isolated DC-DC converter, by using a main transformer and first and second pulse transformers, a first power switch of a primary side circuit and a first synchronous rectifier of a secondary side circuit are driven with complementary timing, and a second power switch of the primary side circuit and a second synchronous rectifier of the secondary side circuit are driven with complementary timing. A first turn-off edge signal and a first turn-on edge signal generated in a primary side control circuit are transmitted to the secondary side via the first pulse transformer so as to generate a driving signal of the first synchronous rectifier. In addition, a second turn-off edge signal and a second turn-on edge signal generated in a primary side circuit are transmitted to the secondary side via the second pulse transformer so as to generate a driving signal of the second synchronous rectifier. | 2009-06-25 |
20090161392 | DC COMPONENT ELIMINATION AT OUTPUT VOLTAGE OF PWM INVERTERS - A control system for a PWM inverter may reduce a DC component of an output of the inverter. An output voltage signal may be attenuated with a low-pass filter to produce a signal with a high DC content. A duty cycle of an output of the low pass filter may be determined with a zero-crossing detector. A calculation may be performed to determine a magnitude of a DC offsetting voltage that may offset the DC component of the inverter output. The inverter may be commanded to produce a DC offsetting voltage with an opposite polarity from the DC component of the inverter output. The opposite polarity DC offsetting voltage may effectively cancel the DC component of the inverter output. A monitoring system may employ an alternate system for determining the level of the DC component, thus providing a desirable redundancy to the system. | 2009-06-25 |
20090161393 | PWM INVERTER - There is provided a PWM inverter capable of preventing a phase error from occurring in generating a PWM signal even in the case where a carrier wave frequency is not sufficiently higher than a signal wave frequency. A PWM signal generating section ( | 2009-06-25 |
20090161394 | ELECTRONIC DEVICE AND POWER SUPPLY UNIT THEREOF - An exemplary electronic device includes a controller, a first convertor, a second convertor, and a switching unit. The first convertor is configured for receiving a first voltage from an external power supply and converting the first voltage into a second voltage. The controller is coupled to the first convertor for generating a start signal when receiving the second voltage. The second convertor is connected to the controller for receiving the first voltage, converting the first voltage into a third voltage to power an operating unit of the electronic device, and converting the first voltage into a fourth voltage to power the controller when receiving the start signal. The switching unit is coupled to the controller and the first convertor for disabling the first convertor when the controller receives the fourth voltage. A related power supply unit is also provided. | 2009-06-25 |
20090161395 | HIGH OUTPUT CURRENT SPLIT PACKAGE A/C ADAPTER - A power adapter, including an AC input terminal, an AC-DC power converter, a DC-DC power converter, and an output terminal, wherein the AC-DC power converter and the DC-DC power converter are separate components, and wherein the power AC input terminal, AC-DC power converter, DC-DC power converter and the output terminal are connected sequentially via a plurality of cords. | 2009-06-25 |
20090161396 | Synchronous rectifier control device and forward synchronous rectifier circuit - Disclosed are a synchronous rectifier control device and a forward synchronous rectifier circuit. The synchronous rectifier control device is coupled with the secondary side of the forward synchronous rectifier circuit, comprising a condition detecting unit, a reference time circuit and a synchronous signal generator. The condition detecting unit receives at least one reference signal and a detecting signal in response to the condition of the secondary side of the forward synchronous rectifier circuit, and accordingly generates a first synchronous control signal. The reference time circuit is coupled with the condition detecting unit, and generates a reference time signal in response to the first synchronous control signal. The synchronous signal generator generates a second synchronous control signal in response to the first synchronous control signal and the reference time signal. | 2009-06-25 |
20090161397 | COMPUTER POWER SUPPLY - A power supply for a computer includes a transformer, a rectifier, a pulse width modulation (PWM) controller, a relay, a power switch, and a battery. The PWM controller includes a voltage terminal and a pulse terminal. The relay includes a switch and an inductance coil. An alternating current (AC) power supply is connected to a primary inductance coil of the transformer via the rectifier. A secondary inductance coil of the transformer provides a standby voltage. A positive voltage terminal of the rectifier is connected to the pulse terminal of the PWM controller via the primary inductance coil of the transformer. The switch is connected between the positive voltage terminal of the rectifier and the voltage terminal of the PWM controller. The inductance coil and the power switch are connected in series between the battery and ground. The power switch is controlled by powering on or off the computer. | 2009-06-25 |
20090161398 | METHOD OF CONTROLLING A THREE LEVEL CONVERTER - A system and method are disclosed for controlling an inverter to provide an alternating inverter voltage to a load for a transition in which a change in active power (P) and/or reactive power (Q) within a transition time (T | 2009-06-25 |
20090161399 | Super leakage current cut-off device for ternary content addressable memory - A super leakage current cut-off device for a ternary content addressable memory (TCAM) is provided. For various operations of the TCAM, the device uses the high-end and low-end power gating control transistors to turn on/off the don't-care cells to reduce the leakage current passing through the don't-care cells. | 2009-06-25 |
20090161400 | Leakage current cut-off device for ternary content addressable memory - A leakage current cut-off device for a ternary content addressable memory is provided. The storage cell of a ternary content addressable memory may be in the active mode, data-retention mode and cut-off mode. This invention applies a multi-mode data retention power gating device to the storage cell of the ternary content addressable memory to reduce the leakage current through the storage cell in the data-retention mode and the cut-off mode, and support the full speed operation in the active mode. | 2009-06-25 |
20090161401 | Multi-die Memory, Apparatus and Multi-die Memory Stack - The multi-die memory comprises a first die and a second die. The first die comprises a first group of memory banks, and the second die comprises a second group of memory banks. The first group of memory banks and the second group of memory banks are coupled to a common memory interface. The common memory interface couples the multi-die memory with an internal connection. | 2009-06-25 |
20090161402 | DATA STORAGE AND STACKABLE CONFIGURATIONS - A first memory device and second memory device have a same input/output layout configuration. To form a stack, the second memory device is secured to the first memory device. To facilitate connectivity, the second memory device is rotationally offset with respect to the first memory device in the stack to align outputs of the first memory device with corresponding inputs of the second memory device. The rotational offset of the second memory device with respect to the first memory device aligns one or more outputs of the first memory device with one or more respective inputs of the second memory device. Based on links between outputs and inputs from one memory device to another in the stack, the stack of memory devices can include paths facilitating one or more series connection configurations through he memory devices. | 2009-06-25 |
20090161403 | SEMICONDUCTOR MEMORY DEVICE HAVING A PLURALITY OF CHIPS AND CAPABILITY OF OUTPUTTING A BUSY SIGNAL - One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips. | 2009-06-25 |
20090161404 | Asymmetric dipolar ring - A device having a dipolar ring surrounding an interior region that is disposed asymmetrically on the ring. The dipolar ring generates a toroidal moment switchable between at least two stable states by a homogeneous field applied to the dipolar ring in the plane of the ring. The ring may be made of ferroelectric or magnetic material. In the former case, the homogeneous field is an electric field and in the latter case, the homogeneous field is a magnetic field. | 2009-06-25 |
20090161405 | DATA STORAGE MEDIUM AND ASSOCIATED METHOD - A data storage medium includes | 2009-06-25 |
20090161406 | NON-VOLATILE MEMORY AND METHOD FOR FABRICATING THE SAME - A non-volatile memory including a diode and a memory cell is described. The diode includes a doped region, a metal silicide layer, and a patterned doped semiconductor layer. The doped region of a first conductive type is formed in a substrate. The metal silicide layer is formed on the substrate. The patterned doped semiconductor layer of a second conductive type is formed on the metal silicide layer. The memory cell is formed on the substrate and coupled with the diode. | 2009-06-25 |
20090161407 | Drive Method of Nanogap Switching Element and Storage Apparatus Equipped with Nanogap Switching Element - A nanogap switching element is equipped with an inter-electrode gap portion including a gap of a nanometer order between a first electrode and a second electrode. A switching phenomenon is caused in the inter-electrode gap portion by applying a voltage between the first and second electrodes. The nanogap switching element is shifted from its low resistance state to its high resistance state by receiving a voltage pulse application of a first voltage value, and shifted from its high resistance state to its low resistance state by receiving a voltage pulse application of a second voltage value lower than the first voltage value. When the nanogap switching element is shifted from the high resistance state to the low resistance state, a voltage pulse of an intermediate voltage value between the first and second voltage values is applied thereto before the voltage pulse application of the second voltage value thereto. | 2009-06-25 |
20090161408 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a memory cell array including memory cells arranged in matrix each having a selective transistor and a variable resistance element having an electric resistance changed from a first state to a second state by applying a first write voltage and from the second state to the first state by applying a second write voltage. A first write current for a first writing operation to change the electric resistance from the first state to the second state is larger than a second write current for a second writing operation to change it from the second state to the first state. A second memory cell number of memory cells subjected to the second writing operation at a time is greater than a first memory cell number of memory cells subjected to the first writing operation at a time. At least the second memory cell number is plural. | 2009-06-25 |
20090161409 | CHARGE MAPPING MEMORY ARRAY FORMED OF MATERIALS WITH MUTABLE ELECTRICAL CHARACTERISTICS - A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic. | 2009-06-25 |
20090161410 | SEVEN TRANSISTOR SRAM CELL - The present disclosure provides a seven transistor static random access memory (7T SRAM) cell. In one embodiment, the 7T SRAM cell includes a pair of cross-coupled inverters configured to provide a memory element having first and second storage nodes. The 7T SRAM cell also includes a Read isolation transistor having a control element connected to one of the storage nodes of the cross-coupled transistor inverters and configured to provide a buffered Read output. The 7T SRAM cell further includes a Read pass gate transistor controlled by a Read word line and connected between the Read isolation transistor and a read bit line. Additionally, the 7T SRAM cell still further includes a Write pass gate transistor controlled by a Write word line and connected between one of the storage nodes of the cross-coupled inverters and a Write bit line to write either state of the memory element. | 2009-06-25 |
20090161411 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a word line; a bit line crossing the word line; a memory cell connected to intersection of the word line and the bit line; and a sense circuit connected to sense node coupled to the bit line. The sense circuit includes a first transistor of the first conduction type having a gate connected to the sense node, a second transistor of the second conduction type having a source connected to a first power supply, a drain connected to the sense node, and a gate connected to the drain of the first transistor, a third transistor having a source connected to the first power supply, a drain connected to the drain of the first transistor, and a gate connected to a control signal line, and a fourth transistor having a source connected to a second power supply, a drain connected to the source of the first transistor, and a gate connected to the control signal line. The sense circuit is activated with a control signal given to the control signal line. | 2009-06-25 |
20090161412 | SEMICONDUCTOR MEMORY - In a semiconductor memory including word lines and bit lines arranged in a matrix and a plurality of memory cells provided at intersections of the word lines and the bit lines, a bit line precharge circuit is provided for controlling the potential of a low-data holding power supply coupled to memory cells provided on a corresponding one of the bit lines. In a write operation, the bit line precharge circuit controls the potential of a low-data holding power supply of a memory cell corresponding to a selected bit line to be higher than the potential of a low-data holding power supply of a memory cell corresponding to an unselected bit line. | 2009-06-25 |
20090161413 | MRAM Device with Shared Source Line - In a particular embodiment, a memory device includes a first memory cell and a second memory cell. The memory device also includes a first bit line associated with the first memory cell and a second bit line associated with the second memory cell. The memory device also includes a source line coupled to the first memory cell and coupled to the second memory cell. | 2009-06-25 |
20090161414 | Spin Torque Magnetic Memory and Offset Magnetic Field Correcting Method Thereof - An object of the present invention corrects fluctuation of a writing current between cells in a magnetic random access memory using spin torque magnetization reversal. The present invention includes a magneto-resistive effect element that is disposed between a bit line and a word line, a first variable resistance element that is connected to one end of the bit line, a second variable resistance element that is connected to the other end of the bit line, a first voltage applying unit that applies voltage to the first variable resistance element, and a second voltage applying unit that applies voltage to the second variable resistance element, when a writing operation is performed, an offset magnetic field is applied to a free layer of the magneto-resistive effect element by flowing a variable current between the first voltage applying unit and the second voltage applying unit based on a predetermined resistance value. | 2009-06-25 |
20090161415 | INTEGRATED CIRCUIT FOR SETTING A MEMORY CELL BASED ON A RESET CURRENT DISTRIBUTION - An integrated circuit includes an array of resistance changing memory cells and a first circuit. The first circuit is configured to set a selected memory cell to a crystalline state by applying a decreasing stair step pulse to the selected memory cell. The pulse is based on a reset current distribution for the array of memory cells. | 2009-06-25 |
20090161416 | OPTIMIZED PHASE CHANGE WRITE METHOD - A system of writing data to a phase change random access memory (PCRAM) on an integrated circuit (IC), and a design structure including the IC embodied in a machine readable medium are disclosed. The system includes an array of phase change elements with a plurality of devices providing independent control of a row access and a column access to the PCRAM. A column line (bit line) is pre-charged to a single predetermined level prior to enabling current flow to a corresponding selected phase change element. A current flow in the phase change element with a row (word line) is initiated once the column (bit line) has been pre-charged, to write data to the PCRAM cell. The current flow is terminated in the phase change element by closing the column line (bit line) preferably by quenching. | 2009-06-25 |
20090161417 | Two cell per bit phase change memory - A phase change memory array may have a plurality of cells in which a bit is determined by a single cell. In addition, a portion of the array may include a plurality of cells which are combined so that two cells form one bit of memory. One of the combined cells is programmed to the complementary state of the other of the combined cells. Thus, the bit is determined by reading the indicator bit which is correctly programmed and comparing it to the complement cell. As a result, the bit may be very reliable because the read window is twice as wide as that used in a conventional phase change memory which compares the selected bit current to a reference current that is midway between the programmed and unprogrammed states. | 2009-06-25 |
20090161418 | PHASE CHANGE MEMORY DEVICE HAVING DECENTRALIZED DRIVING UNITS - A phase change memory device includes a plurality of intersecting bit lines and word lines. A cell array including a plurality of unit phase change resistance cells is formed at intersections of the plurality of bit lines and the plurality of word lines. A plurality of sub word line driving units are configured to drive the word lines in response to a plurality of sub word line signals. A plurality of main word line driving units are configured to drive the sub word line driving units in response to a main word line signal. A precharge unit is configured to precharge the word lines. In the phase change memory device, the driving units are decentralized. | 2009-06-25 |
20090161419 | NONVOLATILE MEMORY, MEMORY SYSTEM, AND METHOD OF DRIVING - Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a first program operation using a first internally generated step-up voltage, and second logic state data to a second group of memory cells during a second program operation using an externally supplied step-up voltage. | 2009-06-25 |
20090161420 | FIELD-EMITTER-BASED MEMORY ARRAY WITH PHASE-CHANGE STORAGE DEVICES - Embodiments of the present invention include systems and methods for three-terminal field-emitter triode devices, and memory arrays utilizing the same. In other embodiments, the field-emitter devices include a volume-change material, capable of changing a measurable electrical property of the devices, and/or three-dimensional memory arrays of the same. | 2009-06-25 |
20090161421 | PHASE CHANGE MEMORY DEVICES AND SYSTEMS, AND RELATED PROGRAMMING METHODS - A phase change memory device performs a program operation by receiving program data to be programmed in selected memory cells, sensing read data already stored in the selected memory cells by detecting respective magnitudes of verify currents flowing through the selected memory cells when a verify read voltage is applied to the selected memory cells, determining whether the read data is identical to the program data, and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, programming the one or more selected memory cells with the program data. | 2009-06-25 |
20090161422 | Magnetic Tunnel Junction Device with Separate Read and Write Paths - In an embodiment, a device is disclosed that includes a magnetic tunnel junction (MTJ) structure. The device also includes a read path coupled to the MTJ structure and a write path coupled to the MTJ structure. The write path is separate from the read path. | 2009-06-25 |
20090161423 | MAGNETIC RANDOM ACCESS MEMORY - An MRAM having a first cell array group ( | 2009-06-25 |
20090161424 | THERMALLY ASSISTED MAGNETIC WRITE MEMORY - A thermally assisted magnetic write memory including of memory points or memory cells, each of which includes a double magnetic tunnel junction separated from one another by a layer made from an antiferromagnetic material, and whereof the stacking order of the layers constituting them is reversed with regard to one another. Each of the magnetic tunnel junctions includes a reference layer, a storage layer, an insulating layer inserted between the reference and storage layers, constituting the tunnel barrier of the magnetic tunnel junction concerned. The blocking temperature of the layer is lower than the blocking temperature of the reference layer of the corresponding magnetic tunnel junction. The product RA resistance x area of the two tunnel barriers is different. Each memory point a way to heat the storage layers to a temperature above the blocking temperature of the layers. | 2009-06-25 |
20090161425 | METHOD OF DETERMINING A FLAG STATE OF A NON-VOLATILE MEMORY DEVICE - In a method of determining a flag state of a non-volatile memory device, an arithmetic logic unit of a microcontroller is employed without an additional circuit. The method includes providing n flag state information about n flag cells, resetting an entire flag state information value, sequentially reading first to n flag state information, increasing the entire flag state information value depending on a read result of the first to n flag state information, and determining a flag state by comparing the entire flag state information value and a critical value. | 2009-06-25 |
20090161426 | MEMORY PROGRAMMING METHOD AND DATA ACCESS METHOD - A memory programming method is provided. A first programming operation is performed to program a multi level cell from an initial state to a first target state, which corresponds to a storage data and has a first threshold voltage range. A flag bit of the NAND flash is set to a first state to indicate that the first programming operation has been performed. A second programming operation is performed to program the multi level cell from the first target state to a second target state, which corresponds to the storage data and has a second threshold voltage range. The flag bit is set to a second state to indicate that the second programming operation has been performed. | 2009-06-25 |
20090161427 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive. | 2009-06-25 |
20090161428 | LOAD BALANCING BY USING CLOCK GEARS - An electronic device is capable of monitoring internal components to predict changes in processing power needs. When a prediction is made, a clock control circuit can be instructed to increase the clock signal frequency in response to a predicted increase in processing power needs, or decrease the clock signal frequency in response to a predicted decrease in processing power needs. The control circuit can further balance other clock signal frequencies in order to satisfy constraints such as a power supply constraint. | 2009-06-25 |
20090161429 | DYNAMIC COLUMN REDUNDANCY REPLACEMENT - A dynamic column redundancy replacement system for programming and reading a non-volatile memory system includes an input data replacement logic block and an output data replacement logic block. A column redundancy match logic block compares a user address to latched fuse addresses of bad columns and identifies address matches to facilitate the replacement of bits from defective memory cells with replacement redundancy bits. For a program mode of operation, a multi-bit data program redundancy register stores actual redundant input data information and a FIFO register masks internal operations of the memory controller logic while a user is sending data. For a read mode of operation, actual redundant output information is stored in a multi-bit data read redundancy register such that, if a match is found, data from the shift register is replaced with redundant data bits and sent to the data output terminal to provide dynamic replacement of data bits from defective non-volatile memory cells. | 2009-06-25 |
20090161430 | BIT MAP CONTROL OF ERASE BLOCK DEFECT LIST IN A MEMORY - Systems and methods that facilitate bad block management in a memory device that comprises nonvolatile memory are presented. One or more memory blocks of a memory device are each associated with one or more additional, dedicated bits that facilitate indicating whether the associated memory block is defective. These additional bits, called bad block bits, can be stored in a hardware-based storage mechanism within the memory device. Once a defect is detected in a memory block, at least one of the associated bad block bits can be set to indicate that the memory block is defective. If at least one of the bad block bits associated with a memory block indicates a memory block is defective, access to the memory block can be prevented. | 2009-06-25 |
20090161431 | BUILT-IN SELF-REPAIR METHOD FOR NAND FLASH MEMORY AND SYSTEM THEREOF - A built-in self-test system applied to NAND flash memory comprises a built-in self-test circuit, a built-in redundancy-analysis circuit, a content addressable memory, a spare memory, a page-mode processor and an address generator. The built-in self-test circuit is configured to test for defective data in a NAND flash memory. The built-in redundancy-analysis circuit is connected to the built-in self-test circuit. The content addressable memory is connected to the built-in redundancy-analysis circuit for storing the address of the defective data. The spare memory is electrically connected to the content addressable memory. The page-mode processor is configured to generate a page address signal and a compensation signal according to an address signal of the NAND flash memory. The address generator is configured to generate a current address signal according to the page address signal and compensation signal to the content addressable memory. | 2009-06-25 |
20090161432 | FLASH MEMORY DEVICE AND OPERATING METHOD THEREOF - A flash memory device includes a plurality of memory cell blocks, a control unit, a program speed calculation unit, a voltage generator and a block select unit. Each memory cell block includes a string having a drain select transistor, a plurality of memory cells, a novel cell and a source select transistor. The control unit generates a block select signal in response to an address signal and generates an operation control signal in response to a command signal. The program speed calculation unit decides a level of an initial program voltage based on threshold voltages detected after a program operation of the novel cells. The voltage generator generates operating voltages including the initial program voltage of the level according to the operation control signal. The block select unit transfers the operating voltages to a memory cell block corresponding to the block select signal. | 2009-06-25 |
20090161433 | Regulation of Source Potential to Combat Cell Source IR Drop - Techniques are presented for dealing with possible source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits of a non-volatile memory. The error is caused by a voltage drop across the resistance of the source path to the chip's ground when current flows. For this purpose, the memory device includes a source potential regulation circuit, including an active circuit element having a first input connected to a reference voltage and having a second input connected as a feedback loop that is connectable to the aggregate node from which the memory cells of a structural block have their current run to ground. A variation includes a non-linear resistive element connectable between the aggregate node and ground. | 2009-06-25 |
20090161434 | Read, Verify Word Line Reference Voltage to Track Source Level - A non-volatile memory device has individual pages of memory cells to be sensed in parallel. The memory device includes a source level tracking circuit coupled to receive a predetermined word line voltage from a word line voltage supply and the voltage level at the aggregate source node of one or more pages and coupled to provide to word lines of the memory an output voltage during the sensing operation, where the source level tracking circuit includes an op amp whereby the output voltage is the word line voltage offset by an amount to track the voltage level at the aggregate node and compensate for source bias errors due to a finite resistance in the ground loop. | 2009-06-25 |
20090161435 | NON-VOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - When performing a program operation, a non-volatile memory device comprising a multi-plane performs a cache write operation by employing a page buffer circuit of a plane that does not perform the program operation. A data line mux transfers an externally input first data to a page buffer unit of a plane, which will be programmed, according to a plane select signal, transfers a second data to a page buffer unit of a plane on which a program operation is not performed, while the program of the selected plane is performed, and after the first data is programmed, provides a data transfer path between one page buffer unit and the other page buffer unit according to a data transfer control signal. | 2009-06-25 |
20090161436 | SEMICONDUCTOR MEMORY DEVICE - The semiconductor memory device related to an embodiment of the present invention including a memory string in which a plurality of memory cells are connected, a bit line connected to an end of the memory string, a power supply circuit which generates a voltage or a current related to an operation state of each memory cell, a sense amplifier which supplies a control voltage or a control current which controls an operation state of each memory cell via the bit line according to the voltage or the current generated in the power circuit, and a transient response adjustment circuit which adjusts the transient response characteristics of the voltage or the current generated in the power supply circuit when the sense amplifier supplies to the bit line the control voltage or the control current which shifts the memory string from a first operation state to a second operation state. | 2009-06-25 |
20090161437 | HIERARCHICAL COMMON SOURCE LINE STRUCTURE IN NAND FLASH MEMORY - Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic unit corresponding to each NAND flash cell block. For source-line page programming, the distribution line may be called a Global Common Source Line (GCSL). In an array of NAND flash cell blocks, only one NAND flash cell block is selected at a time for programming. To reduce power consumption, only the selected NAND flash cell block receives a value on the CSL that is indicative of the value on the GCSL. Additionally, the CSLs of non-selected NAND flash cell blocks may be disabled through an active connection to ground. | 2009-06-25 |
20090161438 | METHODS OF FORMING AND PROGRAMMING FLOATING-GATE MEMORY CELLS HAVING CARBON NANOTUBES - Floating-gate memory cells having carbon nanotubes interposed between the substrate and the tunnel dielectric layer facilitate ballistic injection of charge into the floating gate. The carbon nanotubes may extend across the entire channel region or a portion of the channel region. For some embodiments, the carbon nanotubes may be concentrated near the source/drain regions. For some embodiments, the tunnel dielectric layer may adjoin the substrate in at least a portion of the channel region. | 2009-06-25 |
20090161439 | Nonvolatile Semiconductor Memory Device - According to an aspect of the present invention, it is provided: a nonvolatile semiconductor memory device comprising: a plurality of bit lines arranged in a first direction; a plurality of source lines arranged in the first direction, the plurality of source lines being parallel to the plurality of bit lines, the plurality of source lines being distinct from the plurality of bit lines; a plurality of memory gate lines arranged in a second direction perpendicular to the first direction; a plurality of memory cells arranged in a matrix, each of the plurality of memory cells including a p type MIS nonvolatile transistor having a first terminal, a second terminal, a channel between the first terminal and the second terminal, a gate insulation film formed on the channel, a gate electrode connected to one corresponding memory gate line of the plurality of memory gate lines, and a carrier storage layer formed between the gate insulation film and the gate electrode, the first terminal being connected to one corresponding bit line of the plurality of bit lines and the second terminal being connected to one corresponding source line of the plurality of source lines. | 2009-06-25 |
20090161440 | INTEGRATED CIRCUITS AND DISCHARGE CIRCUITS - An integrated circuit is provided. The integrated circuit includes a memory device and a discharge circuit. The discharge circuit discharges the well voltage line and the first voltage line of the memory device after the end of the erasing period and includes a first and second switch circuit and a first and second control voltage supplier. The first switch circuit is coupled between the well voltage line, the first voltage line and a second supplier. The second switch circuit is coupled between the first switch circuit and a reference voltage. The first control voltage supplier is coupled to the first switch circuit and supplies a first control voltage to turn on the first switch circuit during a first discharge period. The second control voltage supplier is coupled to the second switch circuit, and supplies a second control voltage to turn on the second switch circuit during a second discharge period. | 2009-06-25 |
20090161441 | Nonvolatile semiconductor memory and method for driving the same - To provide a NOR-type nonvolatile semiconductor memory that can inject electric charge into a charge accumulation layer through the use of an FN tunnel current without compromising an increase in the packing density of memory cells. The above problem is solved by a nonvolatile semiconductor memory in which nonvolatile semiconductor memory cells are arranged in a matrix, each nonvolatile semiconductor memory cell having an island semiconductor layer in which a drain diffusion layer formed in the upper part of the island semiconductor layer, a source diffusion layer formed in the lower part of the island semiconductor layer, a charge accumulation layer formed on a channel region of the side wall sandwiched between the drain diffusion layer and the source diffusion layer via a gate insulation film, and a control gate formed on the charge accumulation layer are formed. Further, bit lines connected to the drain diffusion layer are laid out in a column direction, control gate lines are laid out in a row direction, and source lines connected to the source diffusion layer are laid out in the column direction. | 2009-06-25 |
20090161442 | Data Processing System - A data processing system comprising a memory array having a plurality of memory cells ( | 2009-06-25 |
20090161443 | PAGE BUFFER OF NON-VOLATILE MEMORY DEVICE AND PROGRAMMING METHOD OF NON-VOLATILE MEMORY DEVICE - A page buffer includes a first register, a second register and a data I/O unit. The first register temporarily stores data to be programmed into cells included in a first memory cell block group, or reads and stores data of a corresponding memory cell. The second register temporarily stores data to be programmed into cells included in a second memory cell block group, or reads and stores data of a corresponding memory cell. The data I/O unit inputs specific data to the first register and the second register, or outputs data stored in the first register and the second register. | 2009-06-25 |
20090161444 | PAGE BUFFER AND PROGRAMMING METHOD OF A NON-VOLATILE MEMORY DEVICE - A page buffer includes a first ground voltage supply unit for applying a ground voltage to first and second registers according to a level of a sense node, and a second ground voltage supply unit for applying the ground voltage to the first and second registers irrespective of a level of the sense node. A method of programming a non-volatile memory device includes storing a high-level data in a first node of a first register of a plurality of page buffers, precharging a sense node with a high level, resetting the data stored in the first node of the first register according to a voltage level of the sense node, precharging the sense node with a high level, storing external data in the first node according to a voltage level of the sense node, and performing a program operation according to the data stored in the first node. | 2009-06-25 |
20090161445 | SEMICONDUCTOR MEMORY DEVICE AND DATA MASKING METHOD OF THE SAME - A semiconductor memory device has a data masking function during a write operation. The semiconductor memory device includes a data mask input unit that receives a data mask signal. A data input unit receives data and delays the output of the data more than the output of the data mask signal. A write driver selectively drives the data outputted from the data input unit according to the data mask signal outputted from the data mask input unit. The semiconductor memory device ensures that the data mask signal is inputted into the write driver prior to the input of the data, thus preventing a timing mismatch between data and the data masking signal and poor data masking. | 2009-06-25 |
20090161446 | INPUT CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE ENSURING ENABLED DATA INPUT BUFFER DURING DATA INPUT - An input circuit of a semiconductor memory device that prevents data from being input into a data input buffer prior to the enablement of the data input buffer. The input circuit includes an input buffer enabling control unit that generates an input buffer enabling signal which is enabled before a point at which data is input and which has an enabling period of at least a predetermined burst length. A data input buffer is controlled by the input buffer enabling signal, and the data input buffer buffers and outputs the data during the enabling period of the input buffer enabling signal. | 2009-06-25 |
20090161447 | SEMICONDUCTOR MEMORY INPUT/OUTPUT DEVICE - A semiconductor memory input/output device includes selection pads used to input and output signals for multiple operation modes and having multiple functions, a control signal generator for outputting setting signals and a mask control signal, a lower input/output unit including a lower output buffer for outputting a read data strobe signal to a selection pad and a lower input buffer for receiving a lower data mask signal from the selection pad, and selecting one operation of the lower output buffer and the lower input buffer, and an upper input/output unit including an upper output buffer for outputting an inverted read data strobe signal to the second selection pad and an upper input buffer for receiving an upper data mask signal from the second selection pad, and selecting one operation of the upper output buffer and the upper input buffer. | 2009-06-25 |
20090161448 | SEMICONDUCTOR MEMORY DEVICE OVERDRIVING FOR PREDETERMINED PERIOD AND BITLINE SENSE AMPLIFYING METHOD OF THE SAME - A semiconductor memory device overdriving for a predetermined period when sense amplifying a bitline. An overdriving control unit generates an overdriver enabling signal having an enabling period including a point to enable a bitline sense amplifier and a point to select a column. An overdriver provides an overdrive voltage of a level higher than that of a normal pull-up drive voltage to a pull-up node of the bitline sense amplifier in response to the overdriver enabling signal. The data line pair provides a sufficient difference in potential even for a tRCD_min condition by preventing a drop in the potential of the bitline using the overdrive operation when selecting a column. | 2009-06-25 |
20090161449 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device has memory cells provided at intersections of word lines and bit lines, a precharge circuit connected to the bit lines, and a write circuit. The write circuit includes a column selection circuit controlled by a write control signal, a transistor for controlling a potential of a selected bit line so that the potential of the selected bit line is a first potential (e.g., 0 V), a capacitance element for controlling the potential of the selected bit line so that the potential of the selected bit line is a second potential (e.g., a negative potential) that is lower than the first potential, and a clamp circuit for clamping the second potential when a power supply voltage becomes high. | 2009-06-25 |
20090161450 | STORAGE DATA UNIT USING HOT CARRIER STRESSING - The memory comprises at least two data storage units using hot carrier stressing damage to store data. Each data storage unit comprises the first terminal, the second terminal and a third terminal. When the first cross voltage between the second and third terminals is higher than the first threshold voltage and the second cross voltage between the first and third terminals is higher than the second threshold voltage, the data storage unit is in the first writing operation. | 2009-06-25 |
20090161451 | DUAL FUNCTION COMPATIBLE NON-VOLATILE MEMORY DEVICE - A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physical ports and core circuits of the memory device are asynchronous and synchronous input and output signal paths or circuits. The signal paths include shared or dedicated buffers coupled to the ports, asynchronous and synchronous command decoders, a network of switches, and a mode detector. The mode detector determines the operating mode of the dual function memory device from a port, and provides the appropriate switch selection signal. The network of switches routes the input or output signals through the asynchronous or synchronous circuits in response to the switch selection signal. The appropriate command decoder interprets the input signals and provides common control logic with the necessary signals for initiating the corresponding operation. | 2009-06-25 |
20090161452 | Systems and methods for clean DQS signal generation in source-synchronous DDR2 interface design - A method and circuit for generating a signal to synchronize DQ data transfer in memory interface design is presented. The presented method includes receiving a strobe signal having a preamble period before and post-amble period after data transfer burst synchronization signal edge transitions, determining a timing location of the strobe signal preamble period, determining a timing location of the strobe signal post-amble period, and generating a clean strobe signal that tracks the data transfer burst synchronization edge transitions of the strobe signal after the strobe signal preamble begins and before the strobe signal post-amble ends based on the respective determined timing locations of the strobe signal preamble and post-amble periods. In this manner, DQ data transfer may be synchronized according to the burst synchronization signal edge transitions and errors caused by strobe signal level jitter during the preamble and post-amble periods are reduced. | 2009-06-25 |
20090161453 | METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM - A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period. In a variation of this system, the phase detector on the memory chip is configured to receive signals including a clock signal, a marking signal and a data-strobe signal from the memory controller, wherein the marking signal includes a pulse which marks a specific clock cycle in the clock signal. In this variation, the phase detector is configured to use the marking signal to window the specific clock cycle in the clock signal, and to use the data-strobe signal to capture the windowed clock signal, thereby creating a feedback signal which is returned to the memory controller to facilitate calibration of the timing relationship. | 2009-06-25 |
20090161454 | RINGING MASKING DEVICE HAVING BUFFER CONTROL UNIT - A ringing masking device includes a data strobe buffer unit buffering a data strobe signal and outputting a rising pulse and a falling pulse synchronized with a buffer signal. A buffer control unit latches a burst end signal to generate a buffer control signal and outputs the buffer control signal according to a control of a pulse signal generated in synchronization with the buffer signal. | 2009-06-25 |
20090161455 | DATA INPUT APPARATUS WITH IMPROVED SETUP/HOLD WINDOW - In the data input apparatus, a data delay unit outputs data input from outside the data input apparatice. The data delay unit varies the degree of delay in response to a test mode signal. A data alignment signal generating unit receives a first signal synchronized with an external clock signal and a second signal synchronized with a data strobe signal, and the data alignment signal generating unit outputs one of the first signal and the second signal as a data alignment signal in response to the test mode signal. A data alignment unit is synchronized with the data alignment signal to align the data delayed in the data delay unit. The data input apparatus improves the setup/hold window when a semiconductor memory device is in the test mode. | 2009-06-25 |
20090161456 | Semiconductor memory device which delays refreshment signal for performing self-refreshment - A semiconductor memory device having two refreshment modes of auto-refreshment and partial self-refreshment imposed on memory cells includes a command decoder which detects one of the refreshment modes from an input command, outputs type data which indicates the detected refreshment mode, and outputs a refreshment signal which indicates the start of refreshment; a mode register in which the type data is set; a signal selection circuit which determines whether or not the refreshment signal is to be delayed, in accordance with the type data set in the mode register, and outputs the refreshment signal, which is delayed or not delayed in accordance with the result of the determination, as a refreshment start signal; and a control circuit which reads the type data set in the mode register based when receiving the refreshment start signal, and performs refreshment corresponding to the type data. | 2009-06-25 |
20090161457 | Semiconductor storage device having redundancy area - A semiconductor storage device is provided with: a memory cell array which includes a normal area and a redundancy area which replaces a defective memory cell in the normal area; a normal area refresh circuit which performs a CBR refresh operation of a memory cell which is connected to a word line in the normal area; and a redundancy area refresh circuit which performs a CBR refresh operation of a memory cell which is connected to a word line in the redundancy area in parallel with the CBR refresh operation of the memory cell in the normal area. | 2009-06-25 |
20090161458 | CIRCUIT AND METHOD FOR TESTING MULTI-DEVICE SYSTEMS - A method and system for high speed testing of memories in a multi-device system, where individual devices of the multi-device system are arranged in a serial interconnected configuration. High speed testing is achieved by first writing test pattern data to the memory banks of each device of the multi-device system, followed by local test read-out and comparison of the data in each device. Each device generates local result data representing the absence or presence of a failed bit position in the device. Serial test circuitry in each device compares the local result data with global result data from a previous device. The test circuitry compresses this result of this comparison and provides it to the next device as an updated global result data. Hence, the updated global result data will represent the local result data of all the previous devices. | 2009-06-25 |
20090161459 | Dynamic Random Access Memory With Low-Power Refresh - A technique to reduce refresh power in a DRAM is disclosed. In one embodiment, all of the DRAM memory cells are refreshed at a first rate and a subset of the memory cells are refreshed a second rate greater than the first rate. In another embodiment, the DRAM has a refresh controller that generates a refresh address and controls the refresh of the memory cells addressed by the refresh address. A marker memory is used by the refresh controller to determine which of the memory cells requires refreshing at a rate faster than the refresh rate of the remaining memory cells. Also disclosed is a method to determine which of the memory cells are to be refreshed at the faster rate and to store the results in the marker memory. | 2009-06-25 |
20090161460 | RETENTION TEST SYSTEM AND METHOD FOR RESISTIVELY SWITCHING MEMORY DEVICES - A retention test system and method for resistively switching memory devices is disclosed. One embodiment provides a plurality of memory cells configured to be changed over between a first state of high electrical resistance and a second state of low electrical resistance, wherein the system is configured to apply a bias voltage to at least one memory cell of the memory device to be tested. | 2009-06-25 |
20090161461 | SEMICONDUCTOR MEMORY DEVICE MAINTAINING WORD LINE DRIVING VOLTAGE - A semiconductor memory for maintaining a word line driving voltage includes a cell array and a sense amplifier adjacent to the cell array. A dummy cell is formed at a peripheral portion of the cell array in such a manner that a dummy bit line and a word line intersect. A control circuit switches the connection state between a first section of the dummy bit line passing through the cell array and a second section of the dummy bit line passing through the sense amplifier. The connection state switches according to the operation mode of the cell array. The dummy bit line is floated when the operation mode is an active mode and a precharge voltage is provided to the dummy bit line when the operation mode is a precharge mode. | 2009-06-25 |
20090161462 | CONTROLLING AC DISTURBANCE WHILE PROGRAMMING - A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation. | 2009-06-25 |
20090161463 | CIRCUIT PROVIDING COMPENSATED POWER FOR SENSE AMPLIFIER AND DRIVING METHOD THEREOF - The present invention discloses a circuit providing a power for a sense amplifier that stabilizes a power voltage supplied to the sense amplifier by compensating a noise generated in the power voltage when the sense amplifier operates with an selectively generated decoupling noise. The circuit providing a power for a sense amplifier includes a sense amplifying circuit sensing and amplifying data loaded on a bit line with a first power. A power supplying unit provides the first power to the sense amplifying circuit. A decoupling unit generates a decoupling noise with a second power and provides the decoupling noise to the first power voltage. The decoupling noise is maintained for a period including a time point of an operation of the sense amplifying circuit and a predetermined time thereafter. | 2009-06-25 |
20090161464 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array which includes a plurality of memory cells which are arrayed in a matrix at intersections between a plurality of word lines and a plurality of bit lines and a power supply circuit which includes a first band gap reference circuit which outputs a first output voltage, and a second band gap reference circuit which outputs a second output voltage having lower temperature characteristics than the first output voltage on a low temperature side, and generates a power supply voltage on the basis of the second output voltage at a time of a data write operation of the memory cells. | 2009-06-25 |
20090161465 | Non-volatile Memory Device Having High Speed Serial Interface - A non-volatile memory device comprises an interface circuit for receiving a plurality of signals. The plurality of signals provides multiplexed address and data and command signals in a serial format. An input buffer stores a plurality of the plurality of signals received in serial format and reconstitutes the address, data and command signals, and has an output. A command circuit receives the output of the input buffer and stores the command signals therefrom. An address circuit receives the output of the input buffer and stores the address signals therefrom. A data buffer circuit receives the output of the input buffer and stores the data signals therefrom. An array of non-volatile memory cells stores data from and provides data to the data buffer in response to address signals from the address decoder. A state machine is connected to the command circuit and controls the array of non-volatile memory cells. An output buffer receives data from the data buffer circuit and provides data to the interface circuit. | 2009-06-25 |
20090161466 | EXTENDING FLASH MEMORY DATA RETENSION VIA REWRITE REFRESH - Providing for extended data retention of flash memory devices by program state rewrite is disclosed herein. By way of example, a memory cell or group of memory cells can be evaluated to determine a program state of the cell(s). If the cell(s) is in a program state, as opposed to a natural or non-programmed state, a charge level, voltage level and/or the like can be rewritten to a default level associated with the program state, without erasing the cell(s) first. Accordingly, conventional mechanisms for refreshing cell program state that require rewriting and erasing, typically degrading storage capacity of the memory cell, can be avoided. As a result, data stored in flash memory can be refreshed in a manner that mitigates loss of memory integrity, providing substantial benefits over conventional mechanisms that can degrade memory integrity at a relatively high rate. | 2009-06-25 |
20090161467 | MEMORY DEVICE AND REFRESH METHOD THEREOF - A memory device and a refresh method are provided herein. The memory device includes a memory array having memory rows. When an array refresh strobe (ARS) signal is received, it is determined whether the memory rows are required to be refreshed according to tag flags and reset statuses corresponding to the memory rows. When a row refresh strobe (RRS) signal is received, it is determined whether to refresh one of the memory rows according to a plurality of parameters including a value of a row to refresh counter, a value of a refresh deadline counter and/or a queue. When it is decided to start a refresh operation, one of the memory rows is selected according to the tag flag and the status, and the status of the selected memory row is updated after the selected memory row is refreshed. | 2009-06-25 |
20090161468 | SEMICONDUCTOR MEMORY, MEMORY SYSTEM, AND MEMORY ACCESS CONTROL METHOD - A semiconductor memory is provided, the semiconductor memory including a memory core that includes a plurality of memory cells, a refresh generation unit that generates a refresh request for refreshing the memory cell, a core control unit that performs an access operation in response to an access request, a latency determination unit that activates a latency extension signal upon a conflict between activation of a chip enable signal and the refresh request and that deactivates the latency extension signal in response to deactivation of the chip enable signal, a latency output buffer that outputs the latency extension signal, and a data control unit that changes a latency from the access request to a transfer of data to a data terminal during the activation of the latency extension signal. | 2009-06-25 |
20090161469 | SEMICONDUCTOR INTEGRATED CIRCUIT AND SYSTEM - The semiconductor integrated circuit comprises: a first buffer circuit that outputs a first output signal to an output terminal on receipt of a first input signal; a second buffer circuit that includes a circuit having a similar configuration to the first buffer circuit, that outputs a second output signal on receipt of the first input signal, and that outputs the second output signal based on a check signal; a third buffer circuit that outputs a third output signal based on the check signal; a determination circuit that receives the second output signal and the third output signal and activates a detection signal, in response to the detection that the second output signal is behind the third output signal; and a fourth buffer circuit that operates during the activation of the detection signal and outputs the third output signal to the output terminal, on receipt of the first input signal. | 2009-06-25 |
20090161470 | CIRCUIT FOR DYNAMIC READOUT OF FUSED DATA IN IMAGE SENSORS - A circuit for reading fused data, an image sensing apparatus, a method of reading fused data and a method of manufacturing a circuit for reading fused data. The circuit includes a fuse and a capacitive component configured to provide a data input signal to a data input node of a one bit data storage unit and a signal delay component configured to provide a delayed signal to a clock input terminal of the one bit data storage unit. The method of operating the circuit includes applying a signal to the fuse and to the signal delay element, delaying the signal in the delay element, providing a delayed signal from the delay element to a clock input of a one bit storage element, and providing the signal from the fuse and the capacitive component to a data input of the one bit storage element. | 2009-06-25 |
20090161471 | Power supply device - A power supply device is provided according to the present invention. The power supply device is applicable to electronic device, which has a non-volatile memory and a power supply circuit that provides power to the non-volatile memory. The power supply device includes: a power consuming unit for providing the non-volatile memory with a power release path; a control unit electrically connected to the power supply circuit, the non-volatile memory, and the power consuming unit, has and having a first connection end, a switching end, and a second connection end for being selectively electrically connected to the first connection end or the second connection end via the switching end. When the switching end is electrically connected to the first connection end, the power release path between the power consuming unit and the non-volatile memory is disenabled to allow the non-volatile memory to operate normally, and when the switching end is electrically connected to the second connection end, the power release path between the power consuming unit and the non-volatile memory is enabled, thereby executing discharging process of the non-volatile memory via the power consuming unit, and solving many disadvantages of prior art. | 2009-06-25 |
20090161472 | MEMORY VOLTAGE CONTROL CIRCUIT - A memory voltage control circuit includes two slots, a control circuit, a voltage conversion circuit, and a switch circuit. The two slots are able to efficiently process different memory types. The control circuit receives memory identification signals from the two slots. The control circuit administers the output voltage of the voltage conversion circuit according to the memory identification signals. The memory identification signals determine whether the switch circuit is to be turned on or off. This will control whether the output voltage of the voltage conversion circuit will go to the first or the second slot. | 2009-06-25 |
20090161473 | METHOD AND APPARATUS FOR MANAGING BEHAVIOR OF MEMORY DEVICES - A method of managing power consumption by a memory in a memory device includes determining whether the device is powered by a depletable power supply, and if it is determined that the device is powered by a depletable power supply, changing a behavior of the memory to regulate power consumed by the memory. | 2009-06-25 |
20090161474 | REVERSIBLE-POLARITY DECODER CIRCUIT AND METHOD - Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks. | 2009-06-25 |
20090161475 | SYSTEM FOR PROVIDING READ CLOCK SHARING BETWEEN MEMORY DEVICES - A system for providing read clock sharing between memory devices. The system includes a memory device having an external clock receiver, a read clock receiver, and a phase comparator. The phase comparator synchronizes an internal read clock generated at the memory device. The phase comparator additionally synchronizes one of an external clock received by the external clock receiver and an external read clock received by the read clock receiver. The results of the synchronizing are utilized to refresh the internal read clock. The memory device also includes a mechanism, a read clock driver and a mode register fit. The mechanism is utilized to select between the external clock and the external read clock as input to the phase comparator. The read clock driver outputs the internal read clock generated at the memory device to a read clock output pin. The mode register bit controls the selection of the mechanism, the enabling and disabling of the read clock receiver and the enabling and disabling of the read clock driver. | 2009-06-25 |
20090161476 | KNEADING SCREW AND EXTRUDER - A kneading screw is disclosed which comprises a screw body, the screw body comprising a feed section and a kneading section, the feed section comprising screw segments for feeding a to-be-kneaded material to a downstream side and the kneading section comprising kneading segments for kneading the material. The screw body is provided within the kneading section with a multi-stage portion which gradually changes axially in rotating outside diameter. It is preferable that the multi-stage portion be constituted by kneading segments of plural kneading discs different in rotating outside diameter. With such a construction, it is possible to avoid stress concentration on an axial part of the kneading screw and thereby prevent breaking of a spline shaft and abnormal wear of kneading flights. | 2009-06-25 |
20090161477 | DOUGH PROCESSING MACHINE - A dough processing device has a support frame, a dough feed device, a dough portioning device, a dough kneading device and a dough transfer device. The latter transfers at least one dough portion from at least one portioning chamber of the dough portioning device to at least one kneading chamber of the dough kneading device during transfer time periods. An adjustment device serves for defining a vertical distance between the transfer device and the kneading chamber. This results in a dough processing machine in which a reliable transfer of dough portions from the at least one portioning chamber to the at least one kneading chamber is ensured even in the case of a high throughput. | 2009-06-25 |
20090161478 | DOUGH EXTRACTION SYSTEM FOR BATCH MIXER - A cutting mechanism is mounted to a tub of a dough mixing apparatus including an internal mixing chamber having a rotatable agitator assembly for forming dough. After the dough is formed, the tub is rotated and the cutting mechanism is automatically shifted from a non-cutting position, wherein an elongated blade element of the cutting mechanism is located remote from the agitator assembly so as to not interfere with the dough forming process in the internal mixing chamber, to a cutting position, wherein the elongated blade element is arranged directly adjacent an operational path of mixing elements of the agitator assembly to slice the dough, whereupon the dough readily falls from the agitator assembly for enhanced discharge of the dough from the tub. The cutting mechanism can be integrated into a breaker bar or separately mounted in the tub. | 2009-06-25 |
20090161479 | APPARATUS AND METHOD FOR USING RECIPROCATING HAND-HELD POWER TOOL FOR MIXING PAINT - An apparatus and method for shaking a can of paint or bottle of aerosol spray paint. The apparatus comprises a cradle securely fastened to a tang and at least one strap for securing a can or bottle into the cradle. One end of the tang is shaped so as to be received in a chuck of a hand-held power tool such as a variable speed reciprocating saw. The apparatus is useful for quickly and effectively mixing relatively small cans of paint near in time and place to using the paint. | 2009-06-25 |
20090161480 | Device for producing a ready-to-use filler material by mixing a binder component and a hardener component | 2009-06-25 |
20090161481 | Machine for Mixing Hair Colors - A countertop apparatus dispenses hair coloring, developers and bleach in specified quantities and mixes them, substantially reducing the manual labor involved in performing such tasks. A housing has an upstanding back wall and a bottom wall. A plurality of hair color tube stations is mounted on a forward side of the back wall and a hair color tube squeezing device is positioned at each hair color tube station. The hair color tube squeezing device includes a pair of confronting rollers that engage the trailing end of an inverted hair color tube. A plurality of developer reservoirs and a bleach hopper are also mounted to the apparatus. First and second mixing bowls receive and mix hair coloring and developer at first and second stations, and a third mixing bowl receives and mixes bleach and developer at a third station. Operation of the apparatus is keypad-controlled. | 2009-06-25 |
20090161482 | MIXING DEVICE CONFIGURED TO MIX FOODSTUFF - A mixing device for mix foodstuff includes a base housing at least one motor. The mixing device further includes a jar for containing the foodstuff. The mixing device has a first operating configuration wherein the foodstuff is blended within the jar. The mixing device includes at least one travel mug for containing the foodstuff. The mixing device has a second operating configuration wherein the foodstuff is mixed within the at least one travel mug. The jar and the at least one travel mug are separately removably mountable to the base. The at least one travel mug is removably mountable within the jar for storage. | 2009-06-25 |
20090161483 | HELICAL RIBBON MIXING GEAR - The invention relates to a helical ribbon mixing gear with a mixing vessel ( | 2009-06-25 |
20090161484 | MIXING DEVICE - A mixing device for mixing nail polish and other liquids. There is: a tubular housing member; a compressible tubular casing member, disposed in an interior of the tubular housing member; a shaft member, coupled to the tubular housing member; a power module, in communication with the shaft member; and a control module, in communication with the power module, configured to control the provision of energy from the power module to the shaft member. The control module includes a timer module. The compressible tubular casing member is removably disposed in an interior of the tubular housing member. The power module comprises a motor. There is also a storage container, coupled to an end of the shaft member opposite the tubular housing member. The timer module is coupled to an exterior of the storage container; and the power module is disposed within the storage container. | 2009-06-25 |
20090161485 | FORWARD LOOKING SYSTEMS AND METHODS FOR POSITIONING MARINE SEISMIC EQUPMENT - Systems and methods for positioning one or more spread elements of a marine seismic spread are described. One system comprises a seismic vessel-mounted acoustic Doppler current meter adapted to ascertain at least the horizontal component of the current velocity vector at a point ahead of the seismic vessel, and one or more controllers adapted to use the ascertained current velocity vector to control position of one or more seismic spread elements. It is emphasized that this abstract is provided to comply with the rules requiring an abstract, which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72( | 2009-06-25 |
20090161486 | Method for regularizing offset distribution in towed seismic streamer data - Seismic data from towed marine streamers are sorted into two-dimensional common midpoint gathers of traces. The gathered traces are ordered by offset. The offset distribution of the ordered traces is regularized. The source and receiver coordinates of the regularized traces are adjusted to reflect the regularizing. | 2009-06-25 |
20090161487 | TECHNIQUE AND SYSTEM TO CANCEL NOISE IN MEASUREMENTS PROVIDED BY SENSORS OF A MULTI-COMPONENT STREAMER - A technique includes determining a displacement of an acoustic sensor while in tow. Based on the determined displacement of the sensor, a measurement that is acquired by the sensor is compensated to remove noise from the measurement. | 2009-06-25 |
20090161488 | Method to Estimate Ray Parameter for Seismograms - Method for estimating one or more ray parameters for seismograms. In one implementation, the method may include selecting a reference seismogram from a gather of seismograms, selecting a set of seismograms neighboring the reference seismogram, generating a set of seismic interferograms from the reference seismogram and the selected set of seismograms, slant stacking the set of seismic interferograms to generate a ray parameter seismic interferogram corresponding to the reference seismogram and estimating a ray parameter from the ray parameter seismic interferogram. | 2009-06-25 |
20090161489 | Pest Deterrent - An improved in-ground pest deterrent composed of a hollow plastic spike which houses a sonic pulse producer and is battery powered in which the sonic pulse producing circuitry is fixed and shielded within the housing such that when a removable battery sleeve is removed, the sonic pulse producing circuitry remains within the housing. | 2009-06-25 |