25th week of 2010 patent applcation highlights part 36 |
Patent application number | Title | Published |
20100157594 | LED LAMP - An LED (light emitting diode) lamp includes a lamp body and a plurality of light emitting modules embedded in an outer surface of the lamp body. The outer surface of the lamp body is directed to different sides. Each light emitting module comprises a heat dissipating member and an LED module received in each light emitting module. The heat dissipating member includes a cylinder with an opening facing outwardly and a plurality of fins extending downwardly from a bottom of the cylinder into an inside of the lamp body. | 2010-06-24 |
20100157595 | LED MODULE AND PACKAGING METHOD THEREOF - A light-emitting diode (LED) module and an LED packaging method. As the LED module is packaged under the consideration of candela distribution, each of the lead frames of the LED chips packaged in the LED module is bended for tilting the LED chips by different angles to exhibit various lighting effects. Meanwhile, in the LED packaging method, a plurality of LED chips can be loaded on board rapidly and aligned by one operation to result in less deviation in the candela distribution curve. | 2010-06-24 |
20100157596 | Low-profile light-emitting diode lamp structure - A low-profile light-emitting diode (LED) lamp includes a base, a cover, a heat dissipation plate, an LED module, a circuit board, and a light guide hood. The base and the cover respectively form a base opening and a cover opening. The base and the cover include a recess-projection mating structure therebetween to form an outer water sealing wall and an inner water sealing wall that surround the base opening and the cover opening. The light guide hood, the circuit board, and the LED module are arranged inside the inner water sealing wall. The base and the cover are fixed together through recess-projection mating formed between posts and holes to also realize water resistance. The heat generated by the LED module is dissipated by the heat dissipation plate, which is set on an outer surface of the base and is provided with a plurality of convection chambers that induce heat convection. | 2010-06-24 |
20100157597 | LED LAMP - An LED lamp includes a lamp frame, a reflector received in the lamp frame, a plurality of LED modules received in the lamp frame and an envelope covering an opening of the lamp frame. The lamp frame is made of a material with a good heat conductivity and thermally connects the LED modules. The reflector includes a plurality of interconnecting reflecting cells, each reflecting cell separating a corresponding LED module from others. Each LED module faces to a corresponding reflecting cell and light emitted therefrom is reflected by the reflecting cell to radiate out of the envelope. | 2010-06-24 |
20100157598 | Light set with surface mounted light emitting components - A light set with surface mounted light emitting components includes a first conducting wire and a second conducting wire disposed adjacent to the first conducting wire. The first and second conducting wires are correspondingly formed at a predetermined interval with a plurality of first and second contact-pad areas, respectively, at where a first and a second conductor of the first and the second conducting wire, respectively, are exposed. At least one surface mounted light emitting component is straddled on and between the corresponding first and the second contact-pad areas with two leads of the light emitting component electrically connected to the first and the second conductor via a conductive material, so that the surface mounted light emitting component and the first and second conducting wires are in an electrical contact state. | 2010-06-24 |
20100157599 | Method and Apparatus for Forming a Thermal Interface for an Electronic Assembly - A method and apparatus are provided for forming a thermal interface for an electronic product. A thermally conductive polymer having an adhesive layer formed thereon is provided, a surface of an electronic assembly is pressed against the adhesive layer, and the adhesive layer is allowed to cure so that the thermally conductive polymer and the electronic assembly are in thermal communication with each other. The electronic assembly could be pressed against the thermally conductive polymer using a press and die assembly having a pad for supporting the polymer and a controller for controlling operation of the press. The thermally conductive polymer is bonded to the electronic assembly so that no air pockets or voids are formed therebetween. | 2010-06-24 |
20100157600 | POINTLESS ILLUMINATION DEVICE - The present invention relates to a pointless illumination device, comprising: a body; a cover, made of a light spreading material which can uniformly spread out the light of a plurality of light emitting devices; a light source module; a first contact portion; and a second contact portion. The light emitted from the light source module is uniformly spread through the cover so that the phenomenon of pointwise illumination does not exist in the illumination device. | 2010-06-24 |
20100157601 | Individually controllable multi-color illumination units - Individually controllable multi-colored illumination units, including light beads and a light wand, the beads preferably connected to the wand or to each other through conductivity elements providing electric conductivity for at least four separate lines through the connection while providing for full relative rotation and limited swivel between the connection elements. | 2010-06-24 |
20100157602 | Lighting - The invention relates to a lighting apparatus | 2010-06-24 |
20100157603 | Stage light fixture and method for controlling said light fixture - A stage light fixture is provided with:
| 2010-06-24 |
20100157604 | Stage light fixture and light fixture assembly comprising said stage light fixture - A stage light fixture is provided with a main body extending along a longitudinal axis and having an outer surface; a light source arranged inside the main body at a first end of the main body and suitable to emit a light beam substantially along the axis; and with an objective lens arranged at a second end of the main body; the main body is provided with a plurality of inserts to fix to the outer surface, by means of a magnetic coupling, a filter suitable to intercept the light beam which crosses the objective lens; the inserts are made of a magnetic material and/or of a metallic material suitable to be attracted by a magnetic material. | 2010-06-24 |
20100157605 | LIGHT EMITTING DIODE LAMP - A light emitting diode lamp includes a lampshade and a light source. The lampshade is a portion of a hollow ellipsoid with one focus of the ellipsoid located therein. The lampshade is symmetric to a major axis of the ellipsoid. The lampshade has a vertex located on the major axis and defines a light extraction opening at one end thereof opposite to the vertex. A reflecting layer is formed on an inner surface of the lampshade. The light source is received in the lampshade and localized at the one focus of the ellipsoid. The light source includes a plurality of light emitting diodes facing the inner surface of the lampshade and the light extraction opening, respectively. | 2010-06-24 |
20100157606 | DEVICE FOR COOLING AN OPTICAL MODULE FOR A MOTOR VEHICLE HEADLIGHT - A lighting and/or signaling device comprising at least one optical module equipped with a cooling unit, comprising at least one heat conductor, one end of which is placed spaced from the cooling unit, and is provided with a plurality of deflectors which channel a flow of cold air towards a heat-exchange surface of the cooling unit. | 2010-06-24 |
20100157607 | SOLID STATE OPTICAL SYSTEM - A light fixture includes a solid state light emitter having first and second light-emitting portions configured to emit first and second portions of the light, respectively. The light fixture also includes a reflector having a first reflective surface positioned in the path of the light and including a first substantially parabolic section configured to reflect the first portion of the light, and a second substantially parabolic section adjacent the first substantially parabolic section and configured to reflect the second portion of the light. The second substantially parabolic section has a focal length greater than that of the first substantially parabolic section. The light fixture also includes a stray light reflector having a second reflective surface facing the first reflective surface. The first reflective surface reflects a part of the light toward the stray light reflector, and the stray light reflector is configured to reflect the part of the light. | 2010-06-24 |
20100157608 | STRUCTURE OF LIGHT-EMITTING DIODE LIGHTING TUBE - A light-emitting diode lighting tube includes a casing, an aluminum base board, which is fit into the casing and carries a plurality of light-emitting diodes, at least two reflective members respectively arranged on opposite sides of the light-emitting diodes, and first and second end caps respectively mounted to opposite ends of the casing. The casing has a radial cross-section forming an opening extending in an axial direction of the casing. The aluminum base board is fit to retention sections formed beside the opening. The two reflective members are arranged on opposite sides of the LEDs for reflecting lights emitting from the LEDs. | 2010-06-24 |
20100157609 | BRIGHTNESS ENHANCEMENT FILM - A brightness enhancement film includes a substrate, a plurality of light-gathering units, and a plurality of micro-lenses. The substrate includes a first surface and a second surface that is opposite the first surface. The light-gathering units are mounted on the first surface, with the light-gathering units being aligned and spaced from each other in a first direction to form columns of the light-gathering units and the columns being arranged in a second direction to form a matrix of the light-gathering units, with each of the light-gathering units including a top face and a plurality of stepped portions on a peripheral surface of the light-gathering unit between the top face and the first surface. And the micro-lenses mounted on the first surface, with each of the micro-lenses being located between two adjacent light-gathering units in the first direction and between another two adjacent light-gathering units in the second direction. | 2010-06-24 |
20100157610 | LED LAMP - An LED lamp includes a housing, an LED module, a fixing bracket and a power driver source. The housing includes a base plate and first and second sidewalls extending downwardly from two opposite edges of the base plate, respectively. A light emitting window is defined between free, bottom ends of the first and the second sidewalls and located under the base plate. The base plate has a heat absorbing surface facing the light emitting window and a heat dissipating surface opposite to the heat absorbing surface. A plurality of fins are provided on the heat dissipating surface of the base plate. The LED module, which is received in the housing and mounted on the heat absorbing surface of the base plate, faces the light emitting window. The fixing bracket is mounted on the housing and located above the base plate of the housing. | 2010-06-24 |
20100157611 | LIGHT FIXTURE WITH ADJUSTABLE AND FIXABLE MOUNT - A light fixture has a bracket adapted to be fixed to a wall or ceiling surface and having a leg formed with a leg hole, and a bolt fixed in the fixture housing and projecting therefrom along an axis through the leg hole. A ring engageable over an outer profiled end of the bolt can fit complementarily therewith. An annular disk fits over the ring, has a back face turned toward and engageable around the ring with the leg, and is formed with a radially extending threaded bore holding a radial screw engageable radially inward with the ring to rotationally lock the disk on the ring. The disk and leg fit are locked together so they cannot relatively rotate. An axial screw engaged through the disk and ring with the bolt engages axially inward with the disk to press the disk against the leg and the leg against the housing. | 2010-06-24 |
20100157612 | HEAT RADIATING MEMBER, CIRCUIT BOARD USING THE HEAT RADIATING MEMBER, ELECTRONIC COMPONENT MODULE, AND METHOD OF MANUFACTURING THE ELECTRONIC COMPONENT MODULE - A circuit board using a heat radiating member that can cool an electronic component sufficiently without causing a substrate to break, increasing the total weight of the substrate, lowering the productivity, or increasing cost and device size. A circuit board has a substrate main body ( | 2010-06-24 |
20100157613 | LAMP HOLDER, BACKLIGHT DEVICE USING THE SAME, AND DISPLAY USING THE SAME - A lamp holder includes a mounting portion, a lamp holding part which is connected to the mounting portion, and includes an end capable of surrounding a peripheral surface of a lamp, and is capable of being elastically opened and deformed during attaching and detaching of the lamp. The lamp holder also includes a recessed portion positioned at a surface of the lamp holding part that is opposite to the lamp and located at a position between an end portion and a connecting region of a mounting portion, such that the recessed portion allows the lamp holding part to bend so that the end portion is displaced in a direction away from the peripheral surface of the lamp. | 2010-06-24 |
20100157614 | SWITCHING PROCEDURE OF THE MOTOR VEHICLE HEADLIGHT LIGHTING MODE - An automatic headlight switching procedure for motor vehicles, designed to emit a beam of light from one lighting mode to another lighting mode. The process features the steps of when the headlights are in a first lighting mode, detecting the backscatter of the headlight beam onto a phenomenon of visibility disturbance; increasing the lighting range of the headlight beam in relation to a maximum authorized range in accordance with the detected backscatter; and switching the headlights to a second lighting mode when the backscatter is below a first determined threshold. | 2010-06-24 |
20100157615 | LUMINAIRES COMPRISING WAVEGUIDES - In certain embodiments, architectural lighting comprises a luminaire with a light source and a waveguide having forward and rearward surfaces. The waveguide can be disposed with respect to the light source such that light from the light source is input into the waveguide and guided therein. The waveguide can include a plurality of turning features that turn the light guided within the waveguide out the forward surface and one or more mounting fixtures for mounting the luminaire on an architectural structure. Some embodiments include a luminaire comprising a light source, a waveguide, turning features, and a lamp stand. Other embodiments are also described. | 2010-06-24 |
20100157616 | VEHICLE LIGHTING EQUIPMENT - A vehicle lighting equipment is provided with: a light source in which a light emitting diode is employed; and a transparent lens on which a light emitted from the light source is incident and from which the incident light is emergent. | 2010-06-24 |
20100157617 | Vehicle Lamp Assembly - The present invention provides various lamp assembly configurations for motorized vehicles. In one embodiment, the lamp assembly includes a light source, such as a light emitting diode (LED) module, that is operable to generate light. The light source is attached to the vehicle structure, located on the interior of the vehicle adjacent to the aperture. A light guide is operatively connected to the light source. The light guide is configured to transmit light generated by the light source to preselected locations along the exterior of the vehicle structure, and diffuse the light. The light guide is attached to the vehicle structure, located on the exterior of the vehicle adjacent to the aperture in opposing relation to the light source. The cross-sectional area of the aperture formed through the vehicle structure is less than the cross-sectional areas of the LED module body and the light emitting segment of the light guide. | 2010-06-24 |
20100157618 | ASSEMBLY STRUCTURE OF VEHICLE ROOM LAMP - The present invention provides an assembly structure of a vehicle room lamp which can be manufactured at low cost and high productivity, and has a low weight. The assembly structure includes an inner housing including a body which has a first surface and a second surface, a bracket portion formed in an outer periphery of the body, and a guide rod extending from the second surface; an outer housing attached to the inner housing on the first surface; a ceiling part including an opening through which the outer housing attached to the inner housing, and an edge of the opening which is supported by the bracket portion; and a reinforcement including a guide hole into which the guide rod is inserted. | 2010-06-24 |
20100157619 | LIGHT PIPE WITH UNIFORMLY LIT APPEARANCE - A light pipe having substantially uniform brightness along a length thereof is disclosed. The light pipe includes a first end for receiving a plurality of light rays, a reflective portion for directing the received light rays in a pre-determined internal light pattern, wherein the reflective portion includes a plurality of reflective elements, and an emitting portion for emitting the light rays in a pre-determined light distribution pattern. | 2010-06-24 |
20100157620 | ENHANCED VISUALIZATION ILLUMINATION SYSTEM - A first light source producing a first light beam with a first intensity and a second light source producing a second light beam with a second intensity. A light filter device receives the first light beam and transmits a filtered portion of the first light beam. A first angling device reflects the filtered portion of the first light beam in a first angled direction and a second angling device reflects the second light beam in a second angled direction. A mirror receives and in turn reflects the filtered portion of the first light beam reflected by the first angling device and the second light beam reflected by the second angling device to form a converged light beam with a third intensity. | 2010-06-24 |
20100157621 | LIGHT EMITTING DEVICE WITH LED OPTICAL FIBER COUPLING - An exemplary light emitting device includes light emitting diodes optical fibers, and a light guide body. Each optical fiber includes a light input end and a light output end. Each light emitting diode is optically coupled to the light input end of a corresponding optical fiber. The light guide body includes a light incident surface and a light emitting surface. The light output end of each optical fiber is optically coupled to the light guide body at the light incident surface such that light output from the light output end is capable of emitting from the light guide body through the light emitting surface. | 2010-06-24 |
20100157622 | CONTROLLING BEAM INTENSITY IN AN OPHTHALMIC FIBER OPTIC ILLUMINATION SYSTEM USING ROTATABLE PLATE ARRAYS - An ophthalmic illumination system includes a collimated light beam focused onto an optical fiber for transmission of the light beam to an ophthalmic light probe. A light attenuator includes a pair of arrays positioned serially in a path for the collimated beam. The arrays are movable in parallel in the path about a rotational axis orthogonal to the path and between the arrays. Each array includes a plurality of regularly spaced-apart parallel plates, the parallel plates of one array being non-parallel to the plates of the other array. | 2010-06-24 |
20100157623 | Planar light-emitting apparatus - A planar light-emitting apparatus includes a light source, a light-guiding member configured to allow light from the light source to propagate therethrough, a reflecting member disposed such that the reflecting member faces the light-guiding member, the reflecting member reflecting the light propagating through the light-guiding member, and an adhesive member configured to attach the light-guiding member and the reflecting member to each other. A distribution of an adhesive region of the adhesive member on a surface of the light-guiding member is determined on the basis of a brightness distribution of the planar light-emitting apparatus in the case where the adhesive member is uniformly distributed on the surface of the light-guiding member, and the adhesive member is formed between the light-guiding member and the reflecting member in accordance with the distribution of the adhesive region. | 2010-06-24 |
20100157624 | Light Guide Plate and Backlight Module - A light guide plate includes a first light guide body having a light incident plane, a first connection surface, and recesses and a second light guide body having a light emitting plane, a second connection surface opposite to the light emitting plane, and protrusions. The recesses are disposed on the first connection surface. Each of the recesses has a bottom plane parallel to the light emitting plane. The light incident plane intersects with the first connection surface. The first connection surface contacts the second connection surface. The protrusions are disposed on the second connection surface and fill the recesses respectively. Cross-sectional planes of each protrusion parallel to the light emitting plane decrease gradually in a direction towards the bottom plane of the corresponding recess. A terminal thickness of the second light guide body is less than that of the first one. | 2010-06-24 |
20100157625 | METHOD FOR DISPLAYING MULTIPLE VIEWS - Disclosed is a method for displaying multiple views, including forming a light guide plate having edge faces forming different-direction light incidence surfaces, setting light sources corresponding to the different-direction light incidence surfaces respectively, operating the light sources that correspond to the different-direction light incidence surfaces to respectively give off lights in a fast and intermittently alternating manner, deflecting the lights to respective predetermined orientations with the light guide plate, further deflecting the lights to desired orientations with optic films set on the light emission surface of the light guide plate, and operating a liquid crystal panel to realize control of signals for different images so as to show multiple views with the light sources that give off lights in different directions and the signals of the different images. | 2010-06-24 |
20100157626 | LIGHT GUIDE PLATE, METHOD FOR MANUFACTURING THE SAME AND BACKLIGHT UNIT USING THE SAME - Disclosed are a film-type light guide plate capable of readily securing mass-production and realizing low weight and slimness, a method for manufacturing the same and a backlight unit using the same. The method includes loading a base film on a movable first conveyor belt, coating a liquid ultraviolet curable resin on the first surface of the base film, rotating a surface-treated roll on the coated ultraviolet curable resin to form a prism pattern provided with a first protrusion pattern, and curing the prism pattern using an ultraviolet lamp. | 2010-06-24 |
20100157627 | OUTPUT VOLTAGE DETECTING CIRCUIT AND SWITCHING POWER SUPPLY HAVING SUCH OUTPUT VOLTAGE DETECTING CIRCUIT - An output voltage detecting circuit includes a conducting structure, a voltage regulator, a first resistor and a second resistor. The conducting structure includes a power output return terminal, a first contact and a second contact. A compensating voltage is generated between the first and second contacts when an output current flows through the first and second contacts. The voltage regulator adjusts a first current according to a voltage across a first circuit terminal and the ground terminal of the voltage regulator, thereby generating a detecting signal according to the first current. An output voltage across the positive power output terminal and the power output return terminal is subject to voltage division by the first and second resistors to generate a divided voltage. The voltage across the first circuit terminal and the ground terminal of the voltage regulator is equal to a difference between the divided voltage and the compensating voltage. | 2010-06-24 |
20100157628 | METHOD AND DEVICE FOR SENSING A CURRENT FLOWING THROUGH AN OUTPUT INDUCTOR OF A PWM DRIVEN CONVERTER - A device generates a signal representative of a current flowing through a load inductor of a converter, the converter having a first transformer including a primary winding driven with a pulse width modulated (PWM) voltage signal. The device may include a sense inductor magnetically coupled to the load inductor, and an integrator configured to integrate a voltage drop on the sense inductor and to generate a first signal representative of the current flowing through the load inductor with an offset. The device may further include a second transformer to be magnetically coupled to the primary winding of the first transformer and generating a second signal representative of a current flowing through the primary winding, and a peak detector configured to sample and hold a peak value of the second signal at every cycle of the PWM voltage signal. The device may also include an adder configured to generate the signal representative of the current flowing through the load inductor as a sum of the first signal and the peak value of the second signal. | 2010-06-24 |
20100157629 | SEMICONDUCTOR LASER APPARATUS - A switching power supply includes: a blanking period generating circuit for prohibiting a main switching element from being turned on from the time the main switching element is turned on to the time a blanking time elapses; a soft start period generating circuit for generating a soft start period from the start of the oscillation of the main switching element to the lapse of a soft start time; and a blanking time adjusting circuit for generating a signal for shortening the blanking time in the soft start period as compared with after the lapse of the soft start period. | 2010-06-24 |
20100157630 | FLYBACK POWER SUPPLY WITH FORCED PRIMARY REGULATION - A flyback converter with forced primary regulation is disclosed. An example flyback converter includes a coupled inductor including a first winding, a second winding, and a third winding. The first winding is coupled to an input voltage and the second winding is coupled to an output of the power converter. A switched element is coupled to the second winding. A secondary control circuit is coupled to the switched element and the second winding. The secondary control circuit is coupled to switch the switched element in response to a difference between a desired output value and an actual output value to force a current in the third winding that is representative of the difference between the desired output value and the actual output value. A primary switch is coupled to the first winding. A primary control circuit is coupled to the primary switch and the third winding. The primary control circuit is coupled to switch the primary switch to regulate the output of the power converter in response to the forced current. | 2010-06-24 |
20100157631 | AUDIBLE NOISE REDUCTION IN A POWER SUPPLY TRANSFOMER - This disclosure relates to a switching power supply with regulated voltage suppression to reduce transformer audio noise. | 2010-06-24 |
20100157632 | Energy Conversion Systems With Power Control - In one embodiment, a power conversion system may include a controller to cause a power stage to control power to or from an energy storage device. In another embodiment, a power conversion system may include a push-pull stage and an energy storage device following the push-pull stage. In another embodiment, an integrated circuit may include power control circuitry to provide power control to a power converter, and a power switch coupled to the power control circuitry to operate the power converter. In another embodiment, a power conversion system may include two or more power converters having power control. | 2010-06-24 |
20100157633 | REDUNDANT CURRENT VALVE CONTROL IN A HIGH VOLTAGE POWER TRANSMISSION SYSTEM - A method and device for providing redundant control of a controllable current valve in a converter of a power transmission system. A first converter control unit sends a first valve control signal. A first active/standby indicator is associated with the first converter. A second converter control unit sends a second valve control signal. A second active/standby indicator is associated with the second converter control unit. The device also includes a valve control unit. An active/standby indicator indicates if a corresponding converter control unit is active or standby. Only one indicator indicates an active unit at a given point in time. The valve control unit receives the active/standby indicators and valve control signals, selects a valve control signal to be applied if the corresponding active/standby indicator indicates an active converter control unit and controls the current valve using the selected valve control signal. | 2010-06-24 |
20100157634 | Power inverter control for grid-tie transition - A control system for a power inverter is disclosed. The power inverter may be configured to supply power to a grid. The control system may include a plurality of output voltage sensors and a plurality of output current sensors configured to measure output line voltages and output line currents of the power inverter. The control system may further include a controller coupled to the power inverter. The controller may be configured to provide a control signal associated with a disturbance frequency to the power inverter. The controller may be further configured to determine an output power of the power inverter based on the output line voltages and output line currents, and determine an amplitude of oscillation in the output power caused by the disturbance frequency. The controller may also be configured to detect an islanding condition, if the amplitude of oscillation is below a threshold. The control system may further include an interface circuit coupled to the controller and configured to disconnect the grid from the power inverter if the islanding condition is detected. | 2010-06-24 |
20100157635 | PREDICTIVE CURRENT CONTROL IN DRIVING A LOAD IN A PWM MODE - A pulse width modulated current control method and system architecture may achieve the high performance of an advanced current control for full-bridge stages, in terms of accuracy, error, speed, and frequency response, but with a reduced complexity in terms of used analog circuits, being comparable with that of an elementary peak current control. The only analog blocks used may be a current sense transducer, i.e. a series resistor or a sense-FET, and a comparator for the current sensing while the rest of the control circuitry is digital. | 2010-06-24 |
20100157636 | CONTROLLER FOR SWITCHING POWER CONVERTER DRIVING BJT BASED ON PRIMARY SIDE ADAPTIVE DIGITAL CONTROL - A controller of an AC/DC flyback switching power supply uses adaptive digital control approaches to control the switching operation of a BJT power switch based on primary-side feedback to regulate the secondary-side constant output voltage and output current, without using the input line voltage. Switching-cycle by switching-cycle peak current control and limit are achieved based on the sensed primary-side current rather than the input line voltage in both constant-voltage and constant-current modes, operating in PWM, PFM and/or combinations of a plurality of PWM and PFM modes. The controller IC does not need a separate pin and ADC circuitry for sensing the input line voltage. The controller IC directly drives the BJT base, and dynamically adjusts the BJT base current amplitude cycle by cycle based on load change | 2010-06-24 |
20100157637 | GREEN-ENERGY POWER GENERATOR FOR ELECTRICAL DISCHARGE MACHINE - This invention relates a green-energy power generator for electrical discharge machine, which comprise: an alternating current (AC) power supply, an AC-to-DC power converter, a DC-to-DC power converter, a current limiting unit, a time limiting unit, and a control unit. It can reduce the unnecessary energy consumption and achieve the objective of energy saving. | 2010-06-24 |
20100157638 | Energy Conversion Systems With Power Control - In one embodiment, a power conversion system includes a controller to provide power control to a converter, and a distortion mitigation circuit. In another embodiment, a system includes a converter to transfer power between a power source and a load having fluctuating power demand, and a controller to provide power control, where the controller may selectively disable the power control. In another embodiment, a power conversion system includes a controller to generate a drive signal to provide power control to a power path in response to a sense signal from the power path, where the sense signal is taken from other than the input of the power path, or the drive signal is applied to the power path at other than a first power stage. | 2010-06-24 |
20100157639 | Inverter Comprising Normally Conductive Gate-Controlled Semiconductor Switches - An inverter comprises two input lines; an inverter bridge connected between the input lines and including at least one half-bridge comprising two normally conductive gate-controlled semiconductor switches; a controller which supplies control voltages to the gates of the semiconductor switches in an operative state of the inverter; and a DC voltage source for supplying an auxiliary control voltage to the gates of the semiconductor switches in an inoperative state of the inverter so as to hold the inverter bridge in a non-conductive state between the input lines. The DC voltage source has a charging unit connected between the input lines in series with a further normally conductive gate-controlled semiconductor switch, o and charging a storage unit for electric charge, which is connected to the gate of the further semiconductor switch such that this switch becomes non-conductive, when the storage unit has been sufficiently charged for providing the auxiliary control voltage. | 2010-06-24 |
20100157640 | Electric Power Converter - The present invention provides a highly reliable electric power converter reduced in parasitic inductance. | 2010-06-24 |
20100157641 | MEMORY DEVICE WITH ADAPTIVE CAPACITY - A method for data storage in a memory ( | 2010-06-24 |
20100157642 | MITIGATION OF CHARGE SHARING IN MEMORY DEVICES - One embodiment relates to a memory element disposed on a substrate. The memory element includes first and second interlocked data storage elements adapted to cooperatively store the same datum. An output of the first data storage element is coupled to an input node of the second data storage element. An output of the second data storage element is coupled to an input of the first data storage element. An isolation element in the substrate is arranged laterally between storage nodes of the first and second data storage elements. The isolation element is arranged to limit charge sharing between the storage nodes of the first and second data storage elements. Other methods and systems are also disclosed. | 2010-06-24 |
20100157643 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes non-inversion repeaters that non-invert data and output the inverted data; and inversion repeaters that invert data and output the inverted data. The non-inversion repeaters or the inversion repeaters are arranged on a first data line and a second data line at a predetermined distance, respectively, which are parallel with each other and the most adjacent to each other and the non-inversion repeater or the inversion repeater is arranged at first positions corresponding to the first data line and the second data line, respectively. The non-inversion repeaters are arranged on one of the first data line and the second data line while the inversion repeaters are arranged on the other first data line and the second data line, at second positions except for the first arrangement positions of positions corresponding to the first data line and the second data line, respectively. | 2010-06-24 |
20100157644 | Configurable memory interface to provide serial and parallel access to memories - The invention relates to an interface for providing multiple modes of accessing data, including serial and parallel modes. Controllable non-volatile memory interfaces are described, including a serial module configured to provide a serial connection between a non-volatile memory array and another non-volatile memory array. The serial module can provide access to the non-volatile memory array. A mode module can be configured to determine which type of interface operation (i.e., serial mode or parallel mode) will be used for the non-volatile memory array and the another non-volatile memory array. In some cases, a controller can be configured to select the serial module independent of the mode module. Circuitry for performing data operations on the non-volatile memories can be fabricated FEOL on a substrate and the non-volatile memories can be fabricated BEOL directly on top of the substrate in one or more layers of memory. | 2010-06-24 |
20100157645 | MEMORY MODULE AND LAYOUT METHOD THEREFOR - The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector. | 2010-06-24 |
20100157646 | METHODS AND APPARATUS FOR DISABLING A MEMORY-ARRAY PORTION - A memory device having a plurality of storage locations disposed along a plurality of generally parallel lines includes, connected to the lines, a decoder circuit for selecting one line, and, connected to each line, a line-disabling circuit for selectively preventing the line from being energized during line selection. | 2010-06-24 |
20100157647 | Memory access circuits and layout of the same for cross-point memory arrays - An integrated circuit includes a substrate including active circuitry fabricated on the substrate and a cross-point memory array formed above the substrate. The cross-point memory array can include conductive array lines arranged in different directions, and re-writable memory cells. Further, the integrated circuit can also include a memory access circuit configured to perform data operations on the cross-point memory array. The integrated circuit can include a cross-point memory array interface layer positioned between the substrate and the cross-point array and including conductive paths configured to electrically couple portions of the memory access circuit with a subset of the conductive array lines. At least one layer of cross-point memory arrays can be formed over the substrate. The memory cells can be two-terminal memory cells that store data as a plurality of conductivity profiles (e.g., resistive states) that can be non-destructively determined by applying a read voltage across the terminals. | 2010-06-24 |
20100157648 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH FUSE ELEMENTS AND CONTROL METHOD THEREFORE - A semiconductor integrated circuit device includes a first block, a second block, and a control section. The first block includes a first fuse, a first switching configured to write data to the first fuse, a first holding portion capable of holding a first instruction, and a first instruction portion configured to turn on the first switching when a second instruction is given thereto with the first instruction. The second block includes a second fuse, a second switching configured to write data to the second fuse, a second holding portion capable of holding the first instruction, and a second instruction portion configured to turn on the second switching when the second instruction is given thereto with the first instruction. The control section issues the second instruction at a point in time when the first instruction is held in the first and second holding portions. | 2010-06-24 |
20100157649 | TRANSISTOR BIT CELL ROM ARCHITECTURE - An apparatus and method for providing a read-only memory (ROM) bit cell having one each of a PMOS transistor and an NMOS transistor, which has reduced static and dynamic electric power losses, are described. In particular, the bit cell does not require a pre-charge transistor. The sense amplifier for determining the voltages on ROM bit lines may be a digital inverter, address decoding may be simplified since there are no timing requirements with respect to transistor pre-charge, and chips containing a plurality of ROM bit cell may be readily programmed. In one embodiment of the invention, each bit cell includes one PMOS transistor having its source in electrical connection with a voltage source, its drain connected or unconnected to a bit line, and its gate connected to an inverted version of the word line signal; and one NMOS transistor having its source connected to a lower voltage source, its drain connected or disconnected to the bit line, and its gate connected to the word line. The bit cell is programmed during the ROM generation by connecting the drain of either the PMOS (logic level 1) or the NMOS (logic level 0) to the bit line. | 2010-06-24 |
20100157650 | FERROELECTRIC MEMORY - A ferroelectric memory according to an embodiment of the present invention includes a memory cell array including plural memory cells, and provided with plural word lines, plural bit lines, and plural plate lines, each of the plate lines corresponding to at least two of the word lines, an access control circuit configured to perform an access operation to a selected cell which is selected from the memory cells, and a refresh control circuit configured to perform a refresh operation, in a background of the access operation, on a refresh cell which is selected from the memory cells, the refresh control circuit performing the refresh operation when a plate line connected to the selected cell and a bit line connected to the selected cell are at the same potential after the access operation. | 2010-06-24 |
20100157651 | Method of programming a nonvolatile memory device containing a carbon storage material - A nonvolatile memory cell includes a steering element located in series with a storage element, where the storage element comprises a carbon material. A method of programming the cell includes applying a reset pulse to change a resistivity state of the carbon material from a first state to a second state which is higher than the first state, and applying a set pulse to change a resistivity state of the carbon material from the second state to a third state which is lower than the second state. A fall time of the reset pulse is shorter than a fall time of the set pulse. | 2010-06-24 |
20100157652 | Programming a memory cell with a diode in series by applying reverse bias - A method of programming a memory cell comprises applying a reverse bias to the memory cell using a temporary resistor in series with the memory cell. The memory cell comprises a diode and a resistivity switching material element in series. The state of the resistivity switching material element changes from a first initial state to a second state different from the first state. | 2010-06-24 |
20100157653 | Quad memory cell and method of making same - A non-volatile memory device includes a first electrode, a diode steering element, at least three resistivity switching storage elements, and a second electrode. The diode steering element electrically contacts the first electrode and the at least three resistivity switching storage elements. The second electrode electrically contacts only one of the at least three resistivity switching storage elements. | 2010-06-24 |
20100157654 | Balancing A Signal Margin Of A Resistance Based Memory Circuit - A resistance based memory circuit is disclosed. The circuit includes a first transistor load of a data cell and a bit line adapted to detect a first logic state. The bit line is coupled to the first transistor load and coupled to a data cell having a magnetic tunnel junction (MTJ) structure. The bit line is adapted to detect data having a logic one value when the bit line has a first voltage value, and to detect data having a logic zero value when the bit line has a second voltage value. The circuit further includes a second transistor load of a reference cell. The second transistor load is coupled to the first transistor load, and the second transistor load has an associated reference voltage value. A characteristic of the first transistor load, such as transistor width, is adjustable to modify the first voltage value and the second voltage value without substantially changing the reference voltage value. | 2010-06-24 |
20100157655 | RESISTIVE MEMORY AND DATA WRITE-IN METHOD - An ReRAM of the present invention includes a high speed write-in region and a main memory region, only memory cells designated to have the storage state out of the memory cells corresponded to data are set to the storage state in the high speed write-in region. The data written in the memory cell array are transferred to the main memory region, the memory cells of the memory cell array corresponded to the data transferred from the high speed write-in region are reset to the no-storage state in the main memory region, only the memory cells designated to have the storage state out of the memory cells are set, and all memory cells are reset to the no-storage state, or the initial state, in the high speed write-in region. | 2010-06-24 |
20100157656 | RESISTANCE CHANGE MEMORY - A resistance change memory of an aspect of the present invention including memory cells including resistance change memory element, word lines connected to the memory cells, a row decoder which activates the word lines, redundant cells used instead of defective cells, a redundant word line connected to redundant cells, a redundant row decoder which activates the redundant word line, a control circuit in which defect address information indicating the word line connected to the defective cell is stored and which remedies the defective cell, and regions provided in a memory cell array and a redundant cell array and identified based on column address information, wherein the control circuit replaces a part of the word line connected to the defective cell with a part of the redundant word line in accordance with each of the regions, and allows the redundant row decoder to activate the replaced redundant word line. | 2010-06-24 |
20100157657 | Multi-resistive state memory device with conductive oxide electrodes - A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO | 2010-06-24 |
20100157658 | Conductive metal oxide structures in non-volatile re-writable memory devices - A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s). | 2010-06-24 |
20100157659 | Digital potentiometer using third dimensional memory - A digital potentiometer using third dimensional memory includes a switch configured to electrically couple one or more resistive elements with a first pin and a second pin, and a non-volatile register configured to control the switch. In one example, the non-volatile register can include a BEOL non-volatile memory element, such as a third dimensional memory element. The non-volatile register can include a FEOL active circuitry portion that is electrically coupled with the BEOL non-volatile memory element to implement the non-volatile register. The resistive elements can be BEOL resistive elements that can be fabricated on the same plane or a different plane than the BEOL non-volatile memory elements. The BEOL non-volatile memory elements and the BEOL resistive elements can retain stored data in the absence of power and the stored data can be non-destructively determined by application of a read voltage. | 2010-06-24 |
20100157660 | MULTIPLE-VALUED DRAM - Provided herein is an MV DRAM device capable of storing multiple value levels using an SET device. The device includes one or more word lines; one or more bitlines; a DRAM cell connected to intersections of the word lines and the bitlines; a current source transistor having a source connected to a power supply voltage and a gate and a drain connected to the bitlines; an SET (single electron transistor) device having a gate connected to the bitlines and a source connected to the ground voltage; and a transistor connected between the bitlines and the drain of the SET device, wherein the gate of the transistor is connected to the ground voltage. According to the MV DRAM device of the present invention, since two or more multiple value data are stored in a cell, it is possible to increase the storage density of the device. In addition, since the MV DRAM device only needs to enable the word lines in order to rewrite the data, thereby requiring only a small amount of current flow, it is suitable for a low-power application. | 2010-06-24 |
20100157661 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first write bit line, a second write bit line, a write word line, a first read bit line, a read word line, and a memory cell array including a plurality of memory cells, and arranged the plurality of memory cells in a matrix fashion, wherein the memory cells including a first inverter including a first PMOS transistor and a first NMOS transistor, a second inverter including a second PMOS transistor, and a second NMOS transistor, and including an input terminal and an output terminal connected to an output terminal and an input terminal of the first inverter, respectively, a first write transfer transistor connected between a first write bit line and the output terminal of the first inverter, and including a gate connected to a write word line, a second write transfer transistor connected between a second write bit line and the output terminal of the second inverter, and including a gate connected to the write word line, a first read driver transistor including a gate connected to the input terminal of any one of the first inverter and the second inverter, and a first read transfer transistor connected to a first read bit line through the first read driver transistor, and including a gate connected to a read word line, the first read transfer transistor shared by at least two of the memory cells in the memory cell array. | 2010-06-24 |
20100157662 | MRAM AND METHOD FOR WRITING IN MRAM - In one embodiment of the present invention, an MRAM is an MRAM including: a plurality of write word lines; a plurality of bit lines provided so as to intersect with the write word lines; and TMR elements provided at respective intersections of the write word lines and the bit lines. Each of the TMR elements includes a first ferromagnetic layer of which magnetization direction is variable, a second ferromagnetic layer of which magnetization direction is fixed, and a tunnel wall which is sandwiched between the first ferromagnetic layer and the second ferromagnetic layer. The bit line is provided, for example, so as to bulge in the direction in which the write word line extends at the intersection of the bit line and the write word line, so that a magnetic wall is introduced at a desired position of the bit line. Further, a current fed through the bit line is fed through the first ferromagnetic layer at the time of data writing. This makes it possible to provide the MRAM having a gigabit-class capacity. | 2010-06-24 |
20100157663 | Information storage device and method of operating the same - An information storage device includes a memory region having a magnetic track and a write/read unit, and a control circuit connected to the memory region. First and second switching devices are connected to both ends of the magnetic track, and a third switching device is connected to the write/read unit. The control circuit controls the first to third switching devices, and supplies operating current to at least one of the magnetic track and the write/read unit. | 2010-06-24 |
20100157664 | MAGNETORESISTIVE MEMORY CELL USING FLOATING BODY EFFECT, MEMORY DEVICE HAVING THE SAME, AND METHOD OF OPERATING THE MEMORY DEVICE - A magnetoresistive memory cell includes an MTJ device and a select transistor. The select transistor includes a first conduction-type semiconductor layer, a gate electrode formed by disposing a gate insulating layer on top of the semiconductor layer, and first and second diffusion regions formed in the semiconductor layer to be spaced apart from each other and to have a second conduction type. A part of the semiconductor layer between the first and second diffusion regions is formed as an electrically floating body region. By using a high-performance select transistor with a floating body effect, high integration of a magnetoresistive memory device may be achieved. | 2010-06-24 |
20100157665 | MEMORY CELL DEVICE AND PROGRAMMING METHODS - A memory device including a memory cell comprising phase change material is described along with methods for programming the memory device. A method for programming disclosed herein includes determining a data value for the memory cell, and applying a pulse pair to store the data value. The pulse pair includes an initial pulse having a pulse shape adapted to preset the phase change material in the memory cell to a normalizing resistance state, and a subsequent pulse having a pulse shape adapted to set the phase change material from the normalizing resistance state to a resistance corresponding to the determined data value. | 2010-06-24 |
20100157666 | METHOD FOR READING SEMICONDUCTOR MEMORIES AND SEMICONDUCTOR MEMORY - A phase change memory cells including a memory element or a threshold device is read using a read current which does not threshold either the memory element or the threshold device in the case of both a set and a reset memory element. As a result, higher currents may be avoided, increasing read endurance. A sensing circuit includes a charging rate detector coupled to a selected address line and sensing a rate of change of a voltage on the selected address line. | 2010-06-24 |
20100157667 | Capacitorless DRAM memory cell comprising a partially-depleted MOSFET device comprising a gate insulator in two parts - The capacitorless DRAM memory cell is constituted by a partially-depleted MOSFET device successively comprising a base substrate, a buried insulator, a floating substrate from semiconducting material including a channel, the gate insulator and a gate. The gate comprises a first zone doped by a first type of dopant and a second zone doped by a second type of dopant. The channel is doped by the second type of dopant. The gate insulator comprises a first part corresponding to the first doped zone and a second part corresponding to the second doped zone of the gate. The first part of the gate insulator has a higher tunnel resistance than the second part. Data storage is realized by means of charge carrier transportation from the gate to the floating substrate through the lower tunnel resistance part of the gate insulator. | 2010-06-24 |
20100157668 | Memory device and method of operating and fabricating the same - A memory transistor including a substrate, a tunnel insulating pattern on the substrate, a charge storage pattern on the tunnel insulating pattern, a blocking insulating pattern on the charge storage pattern, and a gate electrode on the blocking insulating pattern, the blocking insulating pattern surrounding the gate electrode and methods of operating and fabricating the same. A nonvolatile memory may further include a plurality of memory transistors in series and a plurality of auxiliary structures between each of the plurality of unit transistors in series. Each of the plurality of auxiliary structures may be a dummy mask pattern or an assistant gate structure. | 2010-06-24 |
20100157669 | Floating Gate Inverter Type Memory Cell And Array - A non-volatile memory (NVM) cell and array includes a control capacitor, tunneling capacitor, CMOS inverter and output circuit. The CMOS inverter includes PMOS and NMOS inverter transistors. The control capacitor, tunneling capacitor and PMOS and NMOS inverter transistors share a common floating gate, which is programmed/erased by Fowler-Nordheim tunneling. The output circuit includes PMOS and NMOS select transistors. The PMOS inverter and select transistors share a common source/drain region. Similarly, the NMOS inverter and select transistors share a common source/drain region. This configuration minimizes the required layout area of the non-volatile memory cell and allows design of arrays with smaller footprints. Alternately, the tunneling capacitor may be excluded, further reducing the required layout area of the NVM cell. In this case, the NMOS inverter transistor functions as a tunneling capacitor for programming and erasing the cell, and the PMOS inverter transistor functions as a tunneling capacitor for erasing the cell. | 2010-06-24 |
20100157670 | High voltage switching circuitry for a cross-point array - Circuitry for generating voltage levels operative to perform data operations on non-volatile re-writeable memory arrays are disclosed. In some embodiments an integrated circuit includes a substrate and a base layer formed on the substrate to include active devices configured to operate within a first voltage range. Further, the integrated circuit can include a cross-point memory array formed above the base layer and including re-writable two-terminal memory cells that are configured to operate, for example, within a second voltage range that is greater than the first voltage range. Conductive array lines in the cross-point memory array are electrically coupled with the active devices in the base layer. The integrated circuit also can include X-line decoders and Y-line decoders that include devices that operate in the first voltage range. The active devices can include other active circuitry such as sense amps for reading data from the memory cells, for example. | 2010-06-24 |
20100157671 | DATA REFRESH FOR NON-VOLATILE STORAGE - Techniques are disclosed to refresh data in a non-volatile storage device often enough to combat erroneous or corrupted data bits, but not so often as to interfere with memory access or to cause excessive stress on the memory cells. One embodiment includes determining to perform a refresh of data stored in a first group of non-volatile storage elements in a device based on a condition of data in the first group, determining that a second group of non-volatile storage elements in the device should undergo a refresh procedure based on when the second group of non-volatile storage elements were last programmed relative to when the first group of non-volatile storage elements were last programmed, and performing the refresh procedure on the second group of non-volatile storage element. | 2010-06-24 |
20100157672 | Wordline Temperature Compensation - A nonvolatile memory includes a temperature dependent read window. One or more temperature compensated wordline voltage supply circuits provide temperature compensated wordline signal(s) to the nonvolatile memory. The temperature compensated wordline signals change as the temperature dependent read window changes. | 2010-06-24 |
20100157673 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF READING THE SAME - A non-volatile semiconductor memory device capable of preventing reading failure during the occurrence of the FG-FG coupling effect is disclosed. The non-volatile semiconductor memory device includes a memory cell array, each cell of which stores at least two bits, such as LSB and MSB, using different threshold voltages. In addition, the device includes a control circuit for controlling the data-reading operation of the memory cell array. When the reading operation of the memory cells of a first word line is performed, the memory cells of a second word line adjacent to the first word line are examined to determine whether the writing operation of the MSB is performed. If the writing operation of the MSB is performed, a pre-charge voltage of the bit lines connecting to the memory cells of the first word line is reduced to a predetermined voltage for canceling out the raising of the threshold voltage caused by the coupling effect between gate electrodes. | 2010-06-24 |
20100157674 | Two Levels of Voltage Regulation Supplied for Logic and Data Programming Voltage of a Memory Device - Systems and methods involve the use of a flash memory device having multiple flash memory cells. A first interface is adapted to receive power for selectively programming each flash memory cell. A second interface is adapted to receive power supplied to logic level circuitry to perform the selection of flash memory cells to be supplied with power from the first input during a write operation. | 2010-06-24 |
20100157675 | PROGRAMMING ORDERS FOR REDUCING DISTORTION IN ARRAYS OF MULTI-LEVEL ANALOG MEMORY CELLS - A method for data storage includes predefining an order of programming a plurality of analog memory cells that are arranged in rows. The order specifies that for a given row having neighboring rows on first and second sides, the memory cells in the given row are programmed only while the memory cells in the neighboring rows on at least one of the sides are in an erased state, and that the memory cells in the given row are programmed to assume a highest programming level, which corresponds to a largest analog value among the programming levels of the cells, only after programming all the memory cells in the given row to assume the programming levels other than the highest level. Data is stored in the memory cells by programming the memory cells in accordance with the predefined order. | 2010-06-24 |
20100157676 | NAND FLASH MEMORY - A NAND flash memory that is read while a selected bit line and a non-selected bit line are adjacent to each other, has a memory cell array having a plurality of blocks each of which is composed of a plurality of memory cell units, each of said memory cell units having a plurality of electrically rewritable memory cells that are connected to each other and composed of a p-type well surrounded by an n-type well formed in a p-type semiconductor substrate, drain-side select gate transistors each of which connects a memory cell unit to a bit line and is connected to a drain-side select gate line at the gate thereof, and source-side select gate transistors each of which connects a memory cell unit to a source line and is connected to a source-side select gate line at the gate thereof; a row decoder that is connected to word lines, the drain-side select gate lines and the source-side gate line of said memory cell array, and applies a signal voltage to word lines, the drain-side select gate lines and the source-side gate line of said memory cell array for selecting a block; and a sense amplifier that is controlled by a column decoder and makes a selection from said bit lines of said memory cell array, wherein, in a block that is not selected by said row decoder, said bit line selected by said sense amplifier is charged in a state where the drain-side select gate line, the source-side select gate line and the p-type semiconductor substrate are set at a ground potential, and the source lines, the n-type wells, the p-type wells and a bit line that is not selected by said sense amplifier are in a floating state. | 2010-06-24 |
20100157677 | NON-VOLATILE SEMICONDUCTOR MEMORY - A non-volatile semiconductor memory device is provided so that chip size may not increase and occurrence of misreading induced by capacitance of adjacent global bit lines GBL may be prevented, and includes: a non-volatile memory cell array for recording data by setting a threshold voltage for each memory cell transistor serially connected between selection transistors on terminals of a selected bit line; and a control circuit | 2010-06-24 |
20100157678 | NON-VOLATILE MEMORY WITH BOOST STRUCTURES - A non-volatile memory having boost structures. Boost structures are provided for individual NAND strings and can be individually controlled to assist in programming, verifying and reading processes. The boost structures can be commonly boosted and individually discharged, in part, based on a target programming state or verify level. The boost structures assists in programming so that the programming and pass voltage on a word line can be reduced, thereby reducing side effects such as program disturb. During verifying, all storage elements on a word line can be verified concurrently. The boost structure can also assist during reading. In one approach, the NAND string has dual source-side select gates between which the boost structure contacts the substrate at a source/drain region, and a boost voltage is provided to the boost structure via a source-side of the NAND string. | 2010-06-24 |
20100157679 | MONITOR STRUCTURE FOR MONITORING A CHANGE OF A MEMORY CONTENT - A monitor structure for monitoring a change of a memory content in a memory field of a non-volatile memory comprising a reference transistor in the memory field and a monitor transistor. The monitor transistor and the reference transistor comprise a common floating gate. Moreover, the memory field is arranged in a first well, and the monitor transistor in a second well. The first well and the second well are of different doping types. | 2010-06-24 |
20100157680 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor region, a tunnel insulating film formed on the semiconductor region, a charge-storage insulating film formed on the tunnel insulating film, a block insulating film formed on the charge-storage insulating film, and a control gate electrode formed on the block insulating film, wherein the tunnel insulating film comprises a first region which is formed on a surface of the semiconductor region and contains silicon and oxygen, a second region which contains silicon and nitrogen, a third region which is formed on a back surface of the charge-storage insulating film and contains silicon and oxygen, and an insulating region which is formed at least between the first region and the second region or between the second region and the third region, and contains silicon and nitrogen and oxygen and the second region is formed between the first region and the third region. | 2010-06-24 |
20100157681 | Read, Verify Word Line Reference Voltage to Track Source Level - A non-volatile memory device has individual pages of memory cells to be sensed in parallel. The memory device includes a source level tracking circuit coupled to receive a predetermined word line voltage from a word line voltage supply and the voltage level at the aggregate source node of one or more pages and coupled to provide to word lines of the memory an output voltage during the sensing operation, where the source level tracking circuit includes an op amp whereby the output voltage is the word line voltage offset by an amount to track the voltage level at the aggregate node and compensate for source bias errors due to a finite resistance in the ground loop. | 2010-06-24 |
20100157682 | METHOD OF ENHANCING CHARGE STORAGE IN AN E2PROM CELL - A method is provided for enhancing charge storage in an E | 2010-06-24 |
20100157683 | APPARATUS AND METHOD FOR REDUCED PEAK POWER CONSUMPTION DURING COMMON OPERATION OF MULTI-NAND FLASH MEMORY DEVICES - System and method for executing a global memory command in a multi-chip non-volatile memory device having a plurality of non-volatile memories. The global memory command is received at each non-volatile memory concurrently. The memory command is initiated at different times relative to receiving the global memory command for at least two of the plurality of non-volatile memory to mitigate peak power consumption. | 2010-06-24 |
20100157684 | FLASH MEMORY PROGRAM INHIBIT SCHEME - A method for minimizing program disturb in Flash memories. To reduce program disturb in a NAND Flash memory cell string where no programming from the erased state is desired, a local boosted channel inhibit scheme is used. In the local boosted channel inhibit scheme, the selected memory cell in a NAND string where no programming is desired, is decoupled from the other cells in the NAND string. This allows the channel of the decoupled cell to be locally boosted to a voltage level sufficient for inhibiting F-N tunneling when the corresponding wordline is raised to a programming voltage. Due to the high boosting efficiency, the pass voltage applied to the gates of the remaining memory cells in the NAND string can be reduced relative to prior art schemes, thereby minimizing program disturb while allowing for random page programming. | 2010-06-24 |
20100157685 | PROGRAMMING IN A MEMORY DEVICE - Methods for programming a memory device, memory devices, and a memory systems are provided. According to at least one such method, a selected memory cell is programmed by a series of programming pulses. The series of programming pulses are configured in sets of programming pulses where each set has the same quantity of pulses and each programming pulse in the set has substantially the same amplitude (i.e., programming voltage). The amplitude of the programming pulses of subsequent sets is increased by a step voltage from the previous amplitude. | 2010-06-24 |
20100157686 | Method and Apparatus for Programming Nonvolatile Memory - A nonvolatile memory has logic which performs a programming operation, that controls a series of programming bias arrangements to program at least a selected memory cell of the memory array with data. The series of programming bias arrangements include multiple sets of changing gate voltage values to the memory cells. | 2010-06-24 |
20100157687 | Method for Erasing a Flash Memory Cell or an Array of Such Cells Having Improved Erase Coupling Ratio - A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”). In addition, a ground voltage is applied to erase gates other than the first alternating gates (“second alternating gates”). In a second method to erase the flash memory cell, a pulse of a first positive voltage is applied to the first alternating gates and a negative voltage is applied to the second alternating gates and to all control gates. | 2010-06-24 |
20100157688 | PUSH-PULL MEMORY CELL CONFIGURED FOR SIMULTANEOUS PROGRAMMING OF N-CHANNEL AND P-CHANNEL NON-VOLATILE TRANSISTORS - A method of for programming a push-pull memory cell to simultaneously program a p-channel non-volatile transistor and an n-channel non-volatile transistor includes driving to 0 v wordlines for any row in which programming of memory cells is to be inhibited; driving to a positive voltage wordlines any row in which programming of memory cells is to be performed; driving to a positive voltage the bitlines for any column in which programming of memory cells is to be inhibited; driving to a negative voltage the bitlines for any column in which programming of memory cells is to be performed; driving to one of 0 v and a negative voltage a center wordline for any row in which programming of memory cells is to be inhibited; and driving to one of 0 v and a positive voltage the center wordline for any row in which programming of memory cells is to be performed. | 2010-06-24 |
20100157689 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of nonvolatile memory cells ( | 2010-06-24 |
20100157690 | Semiconductor Memory Device of Single Gate Structure - A single gate semiconductor memory device includes a high-potential well on an upper portion of a semiconductor substrate; a first well on an upper portion of the high potential second conductive type well; a second well spaced apart from the first well on the upper portion of the high potential well and across the high-potential well; a floating gate on the first well and the second well; a first ion implantation region in the first well on one side of the floating gate; a second ion implantation region in the first well on an opposite side of the floating gate; a first complementary ion implantation region in the first well next to the second ion implantation region; a third ion implantation region in the second well on one side of the floating gate; and a second complementary ion implantation region in the second well on the opposite side of the floating gate. | 2010-06-24 |
20100157691 | Dual Port PLD Embedded Memory Block to Support Read-Before-Write in One Clock Cycle - A method for a read-before-write functionality for a memory within a programmable logic device (PLD) is provided. The method begins when a read operation and a write operation are initiated through two different ports of a memory simultaneously to access the same address in the memory. In order to prevent the write operation from proceeding prior to the read operation, a read-before-write control logic is provided to the control block of the port that supports the write operation. Thus, the write operation is paused until the control block of the port that supports the write operation receives a signal from a read sense amplifier indicating that the read operation is complete. The read sense amplifier is capable of detecting the completion of a read operation by monitoring the voltage difference of the read bitline. When this voltage difference reaches a threshold value, the read sense amplifier triggers a write wordline signal. The enabling of the write wordline signal causes, the data to be written to the memory. | 2010-06-24 |
20100157692 | Distributed VDC for SRAM Memory - An integrated circuit structure includes a memory. The memory includes a first memory macro and a second memory macro identical to the first memory macro. A first power block is connected to the first memory macro and is configured to provide a regulated voltage to the first memory macro. The first power block has a first input and a first output. A second power block substantially identical to the first power block is connected to the second memory macro and is configured to provide the regulated voltage to the second memory macro. The second power block has a second input and a second output. The first input and the second input are interconnected. The first output and the second output are interconnected. | 2010-06-24 |
20100157693 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a memory cell array including a plurality of word lines, a plurality of bit lines intersecting the plurality of word lines, and a plurality of binary-data holding memory cells arranged at the intersections of the word lines and the bit lines; and a control unit operative to change in the storage capacity of the memory cell array and change in the address space required for access to the memory cell based on a control signal. | 2010-06-24 |