25th week of 2022 patent applcation highlights part 86 |
Patent application number | Title | Published |
20220200583 | INVERTER CIRCUIT, DIGITAL-TO-ANALOG CONVERSION CELL, DIGITAL-TO-ANALOG CONVERTER, TRANSMITTER, BASE STATION AND MOBILE DEVICE - An inverter circuit is provided. The inverter circuit includes a first node for coupling to a first electrical potential and a second node for coupling to a second electrical potential different from the first electrical potential. Further, the inverter circuit includes a third node configured to output an output signal of the inverter circuit. The inverter circuit includes a plurality of transistors of a first conductivity type coupled in series between the first node and the third node. Additionally, the inverter circuit includes a plurality of transistors of a second conductivity type coupled in series between the third node and the second node. The second conductivity type is different from the first conductivity type. The inverter circuit further includes at least one coupling path comprising a capacitive element. The at least one coupling path is coupled between a source terminal of one of the plurality of transistors of the first conductivity type and a source terminal of one of the plurality of transistors of the second conductivity type. | 2022-06-23 |
20220200584 | Processing System, Related Integrated Circuit and Method - A processing system comprising a first sub-circuit configured to be powered by a first supply voltage and a second sub-circuit configured to be powered by a second supply voltage. The first sub-circuit comprises a general-purpose input/out register. The second sub-circuit comprises: a storage circuit configured to selectively store configuration data from the general-purpose input/out register; an input/output interface, at least one peripheral and a selection circuits to exchange signals of the peripherals, and the stored configuration data with the input/output interface. A power management circuit is configured to manage a normal operating mode, and a low-power mode during which the configuration data are maintained stored and the first sub-circuit is switched off. The power management circuit activates the low-power mode in response to receiving a command, and resumes the normal operating mode in response to a wake-up event. | 2022-06-23 |
20220200585 | RADIATION HARDENED FLIP-FLOP CIRCUIT FOR MITIGATING SINGLE EVENT TRANSIENTS - A flip-flop circuit comprises a pass gate, a feedback inverter, and an interleaved filter. The pass gate comprises a clock input and an inverting clock input. The feedback inverter includes a feedback input coupled to both the clock input and the inverting clock input of the pass gate. The interleaved filter comprises a delay circuit including a delay output, a C-gate element, and a blocking inverter. The C-gate element includes a C-gate input and a C-gate output. The C-gate input is coupled to the delay output of the delay circuit and the pass gate, and the C-gate output is coupled to the feedback input of the feedback inverter. The blocking inverter includes a blocking input and a blocking output. The blocking input is coupled to the delay output of the delay circuit, and the blocking output is coupled to the feedback input of the feedback inverter. | 2022-06-23 |
20220200586 | LOW-SWING SCHMITT TRIGGERS - Systems and methods are disclosed for low-swing Schmitt triggers. For example, an apparatus includes a Schmitt trigger including an input node, an output node, and a feedback node that is configured to bear a feedback voltage level that is a sum of an input voltage level at the input node and an attenuated voltage level of the output node; a current source connected to the output node; a voltage sensor connected to the feedback node and configured to cause the current source to pull up an output voltage level at the output node responsive to the feedback voltage level crossing a threshold. | 2022-06-23 |
20220200587 | SYSTEMS AND METHODS TO REDUCE DIFFERENTIAL-TO-DIFFERENTIAL FAR END CROSSTALK - A method of manufacturing an electrical system for reducing differential-to-differential far end crosstalk (DDFEXT) includes converting a first S parameter representative of a design of a first electrical system into a differential-only S parameter, generating a second differential-only S parameter configured to add even-mode propagation delay and odd-mode propagation delay of the differential-only S parameter of the electrical system such that a total even-mode propagation delay and odd-mode propagation delay of the differential-only S parameter are substantially equivalent, and reconfiguring a second electrical system from the differential-only S parameter and the second differential-only S parameter. | 2022-06-23 |
20220200588 | CURRENT STEERING COMPARATOR AND CAPACITOR CONTROL METHOD - A current steering comparator includes an amplifier circuit, a bias circuit, a latch circuit, and a detector circuit. The amplifier circuit is configured to compare a first input signal with a second input signal during a comparison phase, in order to output a first signal and a second signal. The bias circuit is configured to utilize a tunable capacitor to bias the amplifier circuit during the comparison phase. The latch circuit is configured to generate a first output signal and a second output signal according to the first signal and the second signal during the comparison phase. The detector circuit is configured to detect the first output signal and the second output signal according to a predetermined clock signal to generate a control signal, in order to adjust the tunable capacitor. | 2022-06-23 |
20220200589 | SWITCH UNIT - A switch unit is configured to provide reverse current protection. The switch unit comprises an input terminal, an output terminal, a switch device, an operational amplifier, and a voltage difference circuit. The switch device is coupled between the input terminal and the output terminal. The voltage difference circuit receives the voltage of the output terminal for generating a first signal, where the first signal is greater than the voltage of the output terminal. The operational amplifier is coupled to the input terminal and the first signal for generating a second signal to control the switch device. | 2022-06-23 |
20220200590 | SHORT CIRCUIT DETECTION CIRCUIT - A method for detecting a short circuit includes driving a transistor in response to a drive signal, forming a drain signal of the transistor, generating an inverted signal in response to the drain signal, generating a detect signal when the inverted signal and a control signal are active, and providing the drive signal in an active logic state when the control signal is active and the detect signal is inactive, and in an inactive logic state otherwise. | 2022-06-23 |
20220200591 | POWER SUPPLY CONTROL DEVICE, OPEN FAILURE DETECTION METHOD AND COMPUTER PROGRAM - In a first series circuit of a power supply control device, a first switch and a first resistor are connected in series. In a second series circuit, a second switch and a second resistor are connected in series. The second series circuit is connected in parallel to the first series circuit. An electric current detection circuit detects an electric current value of an electric current flowing through the first resistor. In a case where specific data is stored in a storage unit, a control unit (open failure detection unit) detects an open failure of the first switch or the second switch on the basis of the electric current value detected by the electric current detection circuit. In a case where the storage unit does not store the specific data, the control unit does not detect the open failure. | 2022-06-23 |
20220200592 | PROTECTIVE CIRCUIT FOR A SEMICONDUCTOR SWITCH - A protective circuit for a semiconductor switch includes a clamp diode, an NPN bipolar transistor, a PNP bipolar transistor, a capacitor connected in parallel with the base-emitter path of the PNP bipolar transistor, and at least three resistors. The bipolar transistors are connected to a thyristor structure that is connected to the cathode of the clamp diode. A first resistor is connected in parallel with the base-emitter path of the NPN bipolar transistor. A first terminal of the second resistor is connected to the base of the PNP bipolar transistor. Either a third resistor is connected in parallel with the base-emitter path of the PNP bipolar transistor, or a first terminal of the third resistor is connected to the emitter of the PNP bipolar transistor and the second terminal of the third resistor is connected to the second terminal of the second resistor. | 2022-06-23 |
20220200593 | ANALOG COMPARATOR CIRCUIT FOR COMMUNICATION INTERFACES WITHIN A VEHICLE - A vehicle analog comparator circuit for communication interfaces designed to detect an actuation of an actor. The circuit comprises a unit for producing a supply voltage for supplying the actor, a unit for producing a reference voltage to be compared with the supply voltage, a transistor input stage, a node point EDMx between the actor, the unit for producing a supply voltage and the transistor input stage, and a digital evaluation unit to process the output signal from the transistor input stage such that whether or not the actor is actuated is detected. The transistor input stage comprises a transistor circuit with a first transistor is connected to the node point EDMx, and a second transistor connected to the reference voltage. A collector resistance for limiting the collector current of the second transistor, as well as a base resistance for the two transistors. Alternatively, a current mirror is provided. | 2022-06-23 |
20220200594 | CAPACITIVE SENSOR DEVICE WITH SELECTIVE LOADING AND COUPLING MEASUREMENT MODE - A capacitive measurement circuit for a capacitive sensing device having a plurality of antenna electrodes includes: a measurement signal voltage source, a remotely controllable switching unit, and a current measurement circuit. The switching unit includes a plurality of ports and switching members that are configured to provide connections between selected ports. The measurement signal voltage source and the current measurement circuit are operatively connected to a distinct port. Each antenna electrode is individually connectable to a distinct port. The switching unit is configured to connect, within a same measurement cycle, each of the antenna electrodes to the voltage output port and the current measurement circuit for loading mode operation. The switching unit is further configured to connect at least one of the antenna electrodes to the voltage output port and at least one other antenna electrode of the antenna electrodes to the current measurement circuit for coupling mode operation. | 2022-06-23 |
20220200595 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first line; a second line that is not connected to the first line and is provided to transfer a signal having a level same as a level of a signal transferred through the first line; and another line different from the first line and the second line. In a line layer, a distance between the first line and the second line is longer than a distance between the first line and the other line, and is longer than a distance between the second line and the other line. | 2022-06-23 |
20220200596 | DRIVER CIRCUIT OF VOLTAGE TRANSLATOR - A driver circuit of a voltage translator includes a bias voltage generator, a drive voltage generator, an output voltage generator, and a filter circuit. The bias voltage generator is configured to receive a supply voltage, a first input voltage, and a feedback voltage, and generate a bias voltage. The feedback voltage controls an amplitude of the bias voltage. The drive voltage generator is configured to receive the supply voltage, the first input voltage, and the bias voltage, and generate a drive voltage. The output voltage generator is configured to receive the supply voltage, a second input voltage, and the drive voltage, and generate an output voltage. The drive voltage controls a slew rate of the output voltage. The filter circuit is configured to receive the output voltage, and generates and provides the feedback voltage to the bias voltage generator. | 2022-06-23 |
20220200597 | SWITCHING DEVICE AND SYSTEM HAVING THE SWITCHING DEVICE FOR CONVERTING A DIFFERENTIAL INPUT SIGNAL - In a switching device and a system for converting a differential input signal into a ground-referenced output signal using a control signal, error states are detected, and detected error states lead to the deactivation of the ground-referenced output signal and are indicated on the control signal in addition. | 2022-06-23 |
20220200598 | Level Shifter Including Dummy Circuit and Method of Manufacturing the Same - The present disclosure provides a technology for a level shifter that allows the selection of a single-stage level shifter or a two-stage level shifter by a simple alteration to wiring. When the single-stage level shifter is selected, some circuits may remain as dummy circuits. | 2022-06-23 |
20220200599 | STACKABLE TIMER - An system-on-a-chip (“SoC”) is provided. In some examples, the SoC includes a processor and a plurality of timer circuit blocks including at least a first timer circuit block and a second timer circuit block. Each of the plurality of timer circuit blocks may be selectively coupled by at least one of a first programmable matrix and a second programmable matrix. In some examples, the first programmable matrix may be configured to couple a second trigger input of the first timer circuit block with a first trigger output of the second timer circuit block. In some examples, the second programmable matrix is configured to couple a second fault input of the first timer circuit block with a first fault output of the second timer circuit block. | 2022-06-23 |
20220200600 | LOW POWER FERROELECTRIC BASED MAJORITY LOGIC GATE MULTIPLIER - A new class of multiplier cells (analog or digital) is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from first and second majority gates. The multiplier cell can also be implemented with a combination of two majority gates with majority and AND functions integrated in each of them. The two majority gates are coupled. Each of the first and second majority logic gates comprise a capacitor with non-linear polar material. The first and second majority gates receive the two inputs A and B that are to be multiplied. Other inputs received by the first and second majority gates are carry-in input, a sum-in input, and a bias voltage. The bias voltage is a negative voltage, which produces an integrated AND function in conjunction with a majority function. The second majority gate receives additional inputs, which are inverted output of the first majority gate. | 2022-06-23 |
20220200601 | MAJORITY LOGIC GATE BASED FLIP-FLOP WITH NON-LINEAR POLAR MATERIAL - A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The sequential circuit includes a 3-input majority gate having first, second, and third inputs, and a first output. The sequential circuit includes a driver coupled to the first output, wherein the driver is to generate a second output. The sequential circuit further includes an exclusive-OR (XOR) gate to receive a clock and the second output, wherein the XOR gate is to generate a third output which couples to the second input, where the first input is to receive a data, and wherein the third input is to receive the second output. | 2022-06-23 |
20220200602 | FERROELECTRIC BASED LATCH - A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The sequential circuit includes a 3-input majority gate having first, second, and third inputs, and a first output. The sequential circuit includes a driver coupled to the first output, wherein the driver is to generate a second output. The sequential circuit further includes an exclusive-OR (XOR) gate to receive a clock and the second output, wherein the XOR gate is to generate a third output which couples to the second input, where the first input is to receive a data, and wherein the third input is to receive the second output. | 2022-06-23 |
20220200603 | DIRECT BI-DIRECTIONAL GRAY CODE COUNTER - A bi-directional Gray code counter includes a first set of logic circuitry configured to receive an input having a first sequence of bits representing a first value. The first set of logic circuitry is further configured to convert the first sequence of bits to a second sequence of bits representing the first value. The bi-directional Gray code counter further includes a second set of logic circuitry and third second set of logic circuitry. The second set of logic circuitry is configured to compare the second sequence of bits to a bit index pattern. The third set of logic circuitry is configured to transition one bit in the first sequence of bits from a first state to a second state to form a third sequence of bits representing a second value. The one bit is transitioned in response to the second sequence of bits being compared to the bit index pattern. | 2022-06-23 |
20220200604 | DIGITAL SYSTEM SYNCHRONIZATION - A semiconductor package includes source clock circuitry to generate a source clock signal. Reference clock circuitry generates a reference clock signal. A first timing circuit includes a first source clock input to receive the source clock signal. First fan-out circuitry distributes the received source clock signal as a first distributed clock signal to a first set of clocked devices. A first delay circuit delays the received source clock signal by a first delay value based on a first phase difference between the first distributed clock signal and the reference clock signal. | 2022-06-23 |
20220200605 | INTEGRATED CIRCUIT AND OPERATION METHOD THEREOF - An integrated circuit may include a receiver configured to receive a first data signal based on an m | 2022-06-23 |
20220200606 | MULTI-MODAL DATA-DRIVEN CLOCK RECOVERY CIRCUIT - Multi-mode non-return-to-zero (NRZ) and orthogonal differential vector signaling (ODVS) clock and data recovery circuits having configurable sub-channel multi-input comparator (MIC) circuits for forming a composite phase-error signal from a plurality of data-driven phase-error signals generated using phase detectors in a plurality of receivers configured as ODVS sub-channel MICs generating orthogonal sub-channel outputs in a first mode and a separate first and second data driven phase-error signal from two receivers of a plurality of receivers configured as NRZ receivers in a second mode. | 2022-06-23 |
20220200607 | PHASE LOCK LOOP (PLL) WITH OPERATING PARAMETER CALIBRATION CIRCUIT AND METHOD - A calibration scheme is used to control PLL bandwidth and contain its spread. In open loop, the VCO control voltage is swept over a range of values and VCO output frequency is measured at each control voltage level. The gain KVCO is determined for each measured output frequency and a corresponding current magnitude for the variable magnitude charge pump is calculated from a ratio of a constant to the gain KVCO and correlated in a look-up table to the measured output frequency. Once calibration is completed, the PLL loop is closed and a calculated current magnitude is fetched from the look-up table based on a desired output frequency for the PLL circuit. The variable magnitude charge pump circuit is then controlled to generate a charge pump current with a magnitude corresponding to the fetched charge pump current magnitude. | 2022-06-23 |
20220200608 | DIGITAL PHASE-FREQUENCY DETECTOR WITH SPLIT CONTROL LOOPS FOR LOW JITTER AND FAST LOCKING - A digital phase-frequency detector characterizes a delay between two input clock signals using a ring oscillator. A cycle count of a ring oscillator signal circulating through a loop in the ring oscillator during the delay provides a coarse measurement of the delay. A phase of the ring oscillator signal in the loop at the end of the delay provides a fine measurement of the delay. A digital phase-locked loop may control an oscillation frequency of a digitally-controlled oscillator responsive to the fine measurement of the delay and control a division within a clock divider responsive to the coarse measurement of the delay. | 2022-06-23 |
20220200609 | PHASE LOCKING CIRCUIT - A phase locking circuit includes: a phase comparator; a pulse generation circuit; a charge pump circuit; a loop filter circuit; and a voltage-controlled oscillator. The phase comparator samples a first level in synchronization with a received reference clock, and generates a first signal to be initialized to a second level that is different from the first level by using a feedback clock. The pulse generation circuit generates a second signal in accordance with the reference clock, and controls a phase of as output signal of the voltage-controlled oscillator to be the feedback clock to have a predetermined value by inputting the first signal and the second signal as a control voltage to the voltage-controlled oscillator through the charge pump circuit and the loop filter circuit. | 2022-06-23 |
20220200610 | CLOCKING SYSTEM AND A METHOD OF CLOCK SYNCHRONIZATION - A device and method of clock synchronization for external memory interface. The device, and method, generating a clock output from a phase lock loop block via a sub-module clocking component; multiplexing the clock output through a global clock into different clock domains; clocking the data and an address or a command path by each clock domain; clocking the phase compensation FIFO by clock domain and clock phase alignment clock; generating the pointer for the phase compensation FIFO from central pointer generator block; and synchronizing the pointer of the adjacent intellectual property module with a parent intellectual property module. | 2022-06-23 |
20220200611 | FIELD PROGRAMMABLE PLATFORM ARRAY - An integrated circuit (IC) chip including clock generation circuitry to generate a clock signal. Clock interface circuitry is coupled to the clock generation circuitry and includes multiple transmit pins that are distributed across a mounting surface of the IC chip. Each of the multiple transmit pins is configured to transmit a respective version of the clock signal to one or more off-chip devices. Multiple receiver pins are distributed across the mounting surface of the IC chip and correspond to the multiple transmit pins. Each of the multiple receiver pins is configured to receive respective arrival clock signals from the one or more off-chip devices. Delay compensation circuitry is coupled to the clock interface circuitry and includes multiple delay circuits. Each delay circuit is configured to delay a given clock signal fed to a given transmit pin by a given delay value to establish global timing alignment of the arrival clock signals at the one or more external devices. | 2022-06-23 |
20220200612 | ATOMIC RESONATOR - This atomic resonator for causing a resonance frequency by CPT resonance includes: a gas cell having alkali metal atoms enclosed; a photodetector configured to detect light having passed through the gas cell and convert the light to an electric signal; a high-frequency oscillator configured to receive the electric signal and output the signal after a frequency thereof is divided by two; and a laser light source configured to modulate and introduce, into the gas cell, light based on the signal output from the high-frequency oscillator. The high-frequency oscillator has an injection-locked frequency divider circuit including an acoustic resonator as an oscillation element. | 2022-06-23 |
20220200613 | INPUT BUFFER CIRCUIT, ANALOG-TO-DIGITAL CONVERTER SYSTEM, RECEIVER, BASE STATION, MOBILE DEVICE AND METHOD FOR OPERATING AN INPUT BUFFER CIRCUIT - An input buffer circuit for an analog-to-digital converter is provided. The input buffer circuit includes a buffer amplifier. The buffer amplifier includes a first input node and a second input node each configured to receive a respective one of a first input signal and a second input signal forming a differential input signal pair for the analog-to-digital converter. The buffer amplifier further includes a first output node and a second output node each configured to output a respective one of a first buffered signal and a second buffered signal. In addition, the input buffer circuit includes feedback circuitry. The feedback circuitry is configured to generate, based on the first buffered signal and the second buffered signal, a first feedback signal and a second feedback signal for mitigating a respective unwanted signal component at the first input node and the second input node related to a limited reverse isolation of the amplifier buffer. The feedback circuitry is further configured to supply the first feedback signal to the first input node and the second feedback signal to the second input node. | 2022-06-23 |
20220200614 | METHOD FOR PRECISELY DETECTING A SIGNAL FOR EXAMPLE OF A SENSOR - A method for precise acquisition of a signal of a sensor, by an evaluation and control unit which has a multiplexer at whose inputs there is at least one reference voltage whose voltage value is known, a ground potential of the reference voltage, a measurement signal of the exhaust gas sensor, and a ground potential of the measurement signal. A computer is connected downstream from the multiplexer via a transmission path and via an ADC that converts a voltage between its two inputs into a digital value. The method provides that a plurality of individual measurements are carried out in which switching states of the multiplexer are modified, and digital values are subsequently acquired at the output of the ADC. The computer calculates a measurement value, corrected with regard to offset and gain, from these digital values. | 2022-06-23 |
20220200615 | REFERENCE BUFFER CIRCUIT, ANALOG-TO-DIGITAL CONVERTER SYSTEM, RECEIVER, BASE STATION AND MOBILE DEVICE - A reference buffer circuit for an analog-to-digital converter is provided. The reference buffer circuit includes a first input node configured to receive a first bias signal of a first polarity from a first signal line. Further, the reference buffer circuit includes a second input node configured to receive a second bias signal of a second polarity from a second signal line. Additionally, the reference buffer circuit includes a first output node configured to output a first reference signal of the first polarity. A first buffer amplifier is coupled between the first input node and the first output node. The reference buffer circuit includes in addition a second output node configured to output a second reference signal of the second polarity. A second buffer amplifier is coupled between the second input node and the second output node. Further, the reference buffer circuit includes a first coupling path comprising a first capacitive element. The first coupling path is coupled between the first output node and the second input node. In addition, the reference buffer circuit includes a second coupling path comprising a second capacitive element. The second coupling path is coupled between the second output node and the first input node. | 2022-06-23 |
20220200616 | Transceiver and method and system for controlling an analog-to-digital converter in an observation path in the transceiver - A method and system for controlling an analog-to-digital converter (ADC) in an observation path in a transceiver. The transceiver includes a transmit path, a receive path, and an observation path. The observation path includes an analog buffer and an observation ADC. A controller generates a control signal to control sampling events at the observation ADC to activate the observation ADC at combined uniform and non-uniform sampling instants. The controller may also generate a second control signal indicating whether digital data obtained by the observation ADC is valid or not. The digital data generated by the observation ADC at non-uniform sampling instants is indicated as invalid and digital data generated by the observation ADC at uniform sampling instants is indicated as valid. The digital data indicated as invalid may be discarded and the digital data indicated as valid is used for calibration of the transmit path or the receive path. | 2022-06-23 |
20220200617 | Segmented digital-to-analog converter with subtractive dither - A segmented digital-to-analog converter (DAC) includes DAC segments, an overrange DAC, and a dither control circuit. Each DAC segment includes a plurality of DAC cells for generating an analog output signal based on input data to each DAC segment. The overrange DAC generates an analog output signal based on a control signal. The dither control circuit adds a dither to first input data supplied to a higher-order DAC segment, subtract a portion of the dither from second input data supplied to a lower-order DAC segment, and generate the control signal for subtracting a remaining portion of the dither from an output of the segmented DAC in an analog domain. The dither added to the first input data may be one of +1, 0, and −1 and the portion of the dither subtracted from the second input data may be a half of the dither added to the first input data. | 2022-06-23 |
20220200618 | Method and system for digital pre-distortion using look-up table - A digital predistortion system and method for pre-distorting an input to a non-linear system. The digital predistortion system includes a digital predistortion circuit and a memory. The digital predistortion circuit is configured to receive input data and modify the input data using at least one look-up table. The at least one look-up table is addressed by a signed real value of the input data. The memory is configured to store the at least one look-up table. The at least one look-up table is implemented based on a generalized memory polynomial model. | 2022-06-23 |
20220200619 | MCU MODE FOR SPI COMMUNICATION BETWEEN PRECISION CONVERTERS AND MICROCONTROLLERS - A data acquisition device comprises an analog-to-digital converter (ADC) circuit configured to produce a digital value from an analog input signal. The ADC circuit includes a signal input, a mode input, a serial output, and logic circuitry. The logic circuitry is configured to shift bits of the digital value out the serial output and change an order of the bits shifted out the serial output according to the mode input. | 2022-06-23 |
20220200620 | DELAY FOLDING SYSTEM AND METHOD - A system for converting a voltage into output codes includes logic gates for processing delay signals based on earlier and later arriving signals generated by preamplifiers, delay comparators for generating digital signals representative of most significant bits of respective codes, and for transmitting delay residue signals representative of less significant bits of the codes, and an auxiliary delay comparator for generating an auxiliary digital signal for use in generating the output codes. A system may include logic gates for generating delay signals based on earlier and later arriving signals, delay comparators for generating digital signals representative of most significant bits of respective codes, and for transmitting delay residue signals representative of less significant bits, and a multiplexer system for transmitting a selected one of the residue signals. | 2022-06-23 |
20220200621 | METHOD OF VERNIER DIGITAL-TO-ANALOG CONVERSION - A method of Vernier digital-to-analog conversion, the method including: performing conversion of a reference signal Y using a control code X=M+α | 2022-06-23 |
20220200622 | DATA TRANSMISSION METHOD AND A DATA TRANSMISSION DEVICE - A data transmission method for transmitting a data signal using four data signal levels during a unit interval and transmitting a data bus inversion (DBI) signal using two DBI signal levels during the unit interval, the method including: receiving n (n is a natural number) data, each of the n data including a first bit and a second bit; counting the number of data in which the first bit and the second bit have the same value among the n data; in response to the counting result being less than or equal to a predetermined number, transmitting the n data using the four data signal levels, together with a DBI signal having a first DBI signal level; and in response to the counting result being greater than the predetermined number, transmitting data, which is obtained by changing a value of either of the first bit and the second bit of the n data, using the four data signal levels, together with a DBI signal having a second DBI signal level different from the first DBI signal level. | 2022-06-23 |
20220200623 | METHOD AND APPARATUS FOR EFFICIENT DEFLATE DECOMPRESSION USING CONTENT-ADDRESSABLE DATA STRUCTURES - Apparatus and method for efficient compression block decoding using content-addressable structure for header processing. For example, one embodiment of an apparatus comprises: a header parser to extract a sequence of tokens and corresponding length values from a header of a compression block, the tokens and corresponding length values associated with a type of compression used to compress a payload of the compression block; and a content-addressable data structure builder to construct a content-addressable data structure based on the tokens and length values, the content-addressable data structure builder to write an entry in the content-addressable data structure comprising a length value and a count value, the count value indicating a number of times the length value was previously written to an entry in the content-addressable data structure. | 2022-06-23 |
20220200624 | LOSSLESS COMPRESSION AND DECOMPRESSION METHOD FOR TEST VECTOR - The present invention discloses a lossless compression method for a test vector, comprises following steps: S | 2022-06-23 |
20220200625 | METHODS AND APPARATUS FOR UNIFIED SIGNIFICANCE MAP CODING - Methods and apparatus are provided for unified significance map coding. An apparatus includes a video encoder ( | 2022-06-23 |
20220200626 | FLEXIBLE COMPRESSION HEADER AND CODE GENERATION - An embodiment of an integrated circuit may comprise a hardware compressor to compress data, the hardware compressor including circuitry to store input data in a history buffer, compute one or more code tables based on the input data, and compute a compression stream header based on the computed one or more code tables. Other embodiments are disclosed and claimed. | 2022-06-23 |
20220200627 | SYSTEMS AND METHODS FOR OPTIMIZING WAVEFORM CAPTURE COMPRESSION AND CHARACTERIZATION - A method to automatically optimize waveform captures from an electrical system includes capturing at least one energy-related waveform using at least one Intelligent Electronic Device (IED) in the electrical system. The at least one captured energy-related waveform is analyzed to determine if the at least one captured energy-related waveform is capable of being compressed, while maintaining relevant attributes for characterization, analysis and/or other use. In response to determining the at least one captured energy-related waveform is capable of being compressed, while maintaining relevant attributes for characterization, analysis, and/or use, the at least one captured energy-related waveform may be compressed using at least one compression technique to generate at least one compressed energy-related waveform. One or more actions may be taken based on or using the at least one compressed energy-related waveform. | 2022-06-23 |
20220200628 | ZERO PADDING APPARATUS FOR ENCODING VARIABLE-LENGTH SIGNALING INFORMATION AND ZERO PADDING METHOD USING SAME - A zero padding apparatus and method for variable length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder. | 2022-06-23 |
20220200629 | RECEIVER RECEIVING A SIGNAL INCLUDING PHYSICAL LAYER FRAMES, AND INCLUDING A CONVOLUTIONAL DEINTERLEAVER AND A DEINTERLEAVER SELECTOR - A receiver is arranged for receiving a signal comprising an interleaved symbol stream. The receiver comprises a convolutional deinterleaver comprising a plurality of delay portions each of which is arranged to delay symbols from the symbol stream from an input to an output by a different amount, the delay portions being arranged in a sequence. An input selector is configured to input the symbols from the symbol stream to the delay portions so that successive symbols are input in accordance with the sequence of the delay portions. An output selector configured to read the symbols from the delay portions by successively selecting the symbols from the outputs of the delay portions in accordance with the sequence of the delay portions to form a deinterleaved symbol stream. | 2022-06-23 |
20220200630 | Data Reliability for Extreme Temperature Usage Conditions in Data Storage - Systems, methods, and apparatus related to memory devices such as solid state drives. In one approach, data is received from a host system (e.g., data to be written to an SSD). The received data is encoded using a first error correction code to generate first parity data. A temperature at which memory cells of a storage device (e.g., the SSD) will store the received data is determined. In response to determining the temperature, a first portion of the received data is identified (e.g., data in memory storage that is error-prone at a predicted higher temperature that has been determined based on output from an artificial neural network using sensor(s) input). The identified first portion is encoded using a second error correction code to generate second parity data. The second error correction code has a higher error correction capability than the first error correction code. The encoded first portion, the first parity data, and the second parity data are stored in the memory cells of the storage device. | 2022-06-23 |
20220200631 | CLOUD-BASED SOLID STATE DEVICE (SSD) WITH DYNAMICALLY VARIABLE ERROR CORRECTING CODE (ECC) SYSTEM - Example apparatus and methods control an error correcting code (ECC) approach for data stored on a solid state device (SSD). The control may be based on a property (e.g., reliability, error state, speed) of an SSD, or on an attribute of the data to be stored. Approaches including a hybrid rateless Reed-Solomon ECC approach or a fountain code ECC approach may be selected. Example apparatus and methods may store padded portions of an ECC at different locations in an SSD. Example apparatus and methods may dynamically generate performance test data about the SSD, and dynamically control the ECC approach based on the performance test data. Different types or numbers of ECC may be produced, stored, and provided for different data sets stored at different SSDs or at different physical locations within an SSD. The SSD may be local, or may be part of a cloud-based storage system. | 2022-06-23 |
20220200632 | SYSTEM AND METHOD FOR RECEPTION OF WIRELESS LOCAL AREA NETWORK PACKETS WITH BIT ERRORS - A method in a first wireless device (WD) supporting wireless communication with a second WD is described. A plurality of wireless packets is received from the second WD including at least a first wireless packet. At least another wireless packet of the plurality of wireless packets is one of a retry packet and a repeat packet of the first packet. Each wireless packet of the plurality of wireless packets includes a plurality of bits and a first group of bits. For each received wireless packet, the plurality of bits corresponding to the received wireless packet is de-spread, and the first group of bits is correlated with a predetermined group of bits. The method further includes performing a majority vote based on the correlation of the first group of bits of each received wireless packet and creating a corrected packet based in part on the majority vote. | 2022-06-23 |
20220200633 | SYSTEM AND METHOD FOR SOFT DECODING WITHOUT ADDITIONAL READS - A controller of a memory system performs a soft decoding without additional reads. The controller applies each of read voltages to cells to obtain a corresponding cell count and corresponding data, stores the obtained data, and processes the stored data. The controller determines a set of parameters, based on (i) the read voltages, (ii) cell counts corresponding to the read voltages and (iii) a non-negative regularization parameter. The controller estimates an optimal read voltage based on the set of parameters, generates log-likelihood ratio (LLR) values using the processed data and the optimal read voltage and performs soft decoding using the LLR values. | 2022-06-23 |
20220200634 | RATE MATCHING FOR BLOCK ENCODING - Various aspects of the disclosure relate to rate matching techniques for block encoding. In some aspects, a decision regarding whether to use repetition-based rate matching or puncture-based rate matching is made based on a block size of information being encoded. In some aspects, repetition-based rate matching uses a bit-reversal permutation technique. | 2022-06-23 |
20220200635 | ANALYSIS CHANNELIZERS WITH EVEN AND ODD INDEXED BIN CENTERS - Analysis channelizers are provided. In one embodiment, the channelizer includes an M-path filter receiving an input signal; a circular buffer in communication with the M-path filter; and an M-point inverse fast Fourier transform (IFFT) circuit in communication with the circular buffer, such that the channelizer aligns spectra of the input signal with spectral responses an odd length, non-maximally decimated filter bank by alternating sign heterodyne of the input signal. The channelizer applies an equivalency theorem to the non-maximally decimated filter bank formed by an odd length polyphaser filter. Advantageously, the M-path filter does not require on-line signal processing to obtain odd-indexed filter centers. In another embodiment, the channelizer alternates a sign heterodyne of a filter coefficient weight. | 2022-06-23 |
20220200636 | MULTIBAND RECEIVERS FOR MILLIMETER WAVE DEVICES - We disclose multiband receivers for millimeter-wave devices, which may have reduced size and/or reduced power consumption. One multiband receiver comprises a first band path comprising a first passive mixer configured to receive a first input RF signal having a first frequency and to be driven by a first local oscillator signal having a frequency about ⅔ the first frequency; a second band path comprising a second passive mixer configured to receive a second input RF signal having a second frequency and to be driven by a second local oscillator signal having a frequency about ⅔ the second frequency; and a base band path comprising a third passive mixer configured to receive intermediate RF signals during a duty cycle and to be driven by a third local oscillator signal having a frequency about ⅓ the first frequency or about ⅓ the second frequency during the duty cycle. | 2022-06-23 |
20220200637 | HIGH-PERFORMANCE FILTER BANK CHANNELIZERS - High-performance filter bank channelizers are provided. In one embodiment, a heterodyne signal shifts an input spectrum of the input signal by an offset between input and output centers, and operates at a high input sample rate. In another embodiment, the channelizer includes an input commutator receiving and commutating an input signal, an M-path polyphaser filter in communication with the commutator, and an M-path inverse discrete Fourier transform module processing outputs of the polyphaser filter, wherein the M-path polyphaser filter introduces a plurality of phase rotations in a time domain resulting in a workload reduction for a processor on which the channelizer is implemented. Still other embodiments includes a resampling channelizer, a half-band filter, and a cascaded half-band filter. | 2022-06-23 |
20220200638 | WIRELESS CHIP TO CHIP COMMUNICATION WITH SELECTIVE FREQUENCY MULTIPLEXING WITH DIFFERENT MODULATION SCHEMES - A transmitter for chip to chip communication may include a modulator and a transmit frequency converter. The modulator may modulate a first received signal according to a first modulation scheme. The modulator may also modulate a second received signal according to a second modulation scheme. The transmit frequency converter may center the first received signal on a first frequency that does not comprise a phase within a radio frequency (RF) domain to generate a first centered signal. The transmit frequency converter may also center the second received signal on a second frequency that comprises a phase within the frequency band to generate a second centered signal. The second centered signal may be orthogonal to the first centered signal. A frequency gap may be positioned between the first centered signal and the second centered signal within the frequency band. | 2022-06-23 |
20220200639 | CAPACITOR SUBSTITUTION IN A STACKED RESONATOR BASED ANTENNAPLEXER - An improved antennaplexer provides improved harmonic and intermodulation distortion (IMD) rejection. Aspects of the antennaplexer can substitute one or more of the resonators in the stacked resonator circuit with a capacitor. The introduction of the capacitor can reduce the non-linearity of the received signals. In some cases, the capacitor may be a metal-insulator-metal (MIM) capacitor. Advantageously, the combination of the stacked resonators and the capacitor substitution for a resonator improves the linearity of the antennaplexer and provides for sharper rejection of undesired signals. Thus, the wireless device can support a greater number of frequency bands and/or frequency bands that are more likely to cause harmonic interference and/or IMD distortion. In some cases, the harmonic interference or IMD interference may be reduced by up to 15 dB compared to existing filters or antennaplexers. | 2022-06-23 |
20220200640 | ELECTRONIC DEVICE INCLUDING 5G ANTENNA MODULE - An electronic device may include a first PCB including a non-conductive region and a conductive region operating as a ground, a first wireless communication circuit disposed on the first PCB, and a 5th generation (5G) antenna module disposed adjacent to the first PCB. The 5G antenna module may include at least one second PCB including an antenna array and a conductive layer operating as a ground of the antenna array and a second wireless communication circuit electrically connected to the antenna array. The second PCB may include a first portion and a second portion having a predetermined angle with the first portion. The first portion may be disposed adjacent to the non-conductive region and at least part of the second portion may be disposed adjacent to the conductive region. The first wireless communication circuit may be electrically connected to a first point of the conductive layer included in the first portion and transmitting or receiving a first RF signal in a first frequency band by using the conductive region and at least part of the conductive layer. The second wireless communication circuit may transmit or receive a second RF signal in a second frequency band by using the antenna array. Besides, various embodiments as understood from the specification are also possible. | 2022-06-23 |
20220200641 | RADIO-FREQUENCY MODULE AND COMMUNICATION DEVICE - A radio-frequency module includes a module substrate having a major surface on which a ground electrode pattern is formed and an integrated circuit disposed on the major surface of the module substrate. The integrated circuit includes a control/power supply circuit having at least one of a control circuit and a power supply circuit and a second electrical circuit having at least one of an amplifier, a switch, and a filter. In plan view, the ground electrode pattern overlaps at least a part of the control/power supply circuit and does not overlap at least a part of the second electrical circuit. | 2022-06-23 |
20220200642 | COMMUNICATION DEVICE - Various aspects provide a transceiver and a communication device including the transceiver. In an example, the transceiver includes an amplifier circuit including an amplifier stage with an adjustable degeneration component, the amplifier stage configured to amplify a received input signal with an adjustable gain, an adjustable feedback component coupled to the amplifier stage; and a controller coupled to the amplifier stage and to the adjustable feedback component and configured to adjust the adjustable feedback component based on an adjustment of the adjustable degeneration component. | 2022-06-23 |
20220200643 | METHOD AND SYSTEM FOR DIGITAL FEED-FORWARD LINEARIZATION - A method and system for digital feed-forward linearization. The system includes a main transmit path and an auxiliary transmit path. The main transmit path includes circuitries configured to process a transmit signal for transmission. The main transmit path includes a power amplifier (PA) for amplifying the transmit signal. The auxiliary transmit path includes circuitries configured to generate, in a digital domain, a distortion error signal corresponding to a distortion introduced to the transmit signal due to a non-linear characteristics of the PA in the main transmit path and convert the distortion error signal to an analog distortion error signal. The analog distortion error signal is combined with an output of the PA in the main transmit path. The auxiliary transmit path comprises a PA model circuit that mimics the behavior of the PA to generate a distorted transmit signal in a digital domain. | 2022-06-23 |
20220200644 | DEVICE FOR CONTROLLING A SCANNING ACTIVE ANTENNA - A device for controlling the efficiency of a scanning active antenna includes at least two transmission paths Tx | 2022-06-23 |
20220200645 | STACKED RESONATOR BASED ANTENNAPLEXER - An improved antennaplexer provides improved harmonic and intermodulation distortion (IMD) rejection. In some cases, the improved antennaplexer can provide improved second and third order IMD rejection. The antennaplexer uses stacked or split resonators to reduce harmonic interference. The stacked resonators may function similar to a voltage divider. By dividing the signal across the resonators of the stacked resonators, it is easier to reject the undesired harmonics for each of the reduced signals, thereby improving harmonic rejection. By splitting the resonators of the antennaplexer, a square root effect may be achieved for the harmonic distortion and an improvement of up to 6 dB can be obtained. Further, an improvement in the third harmonic of up to 9× can be achieved. Moreover, the division of the signal over the stacked resonators may improve the linearity of the filtered signal. | 2022-06-23 |
20220200646 | RECONSTRUCTION OF CLIPPED SIGNALS - Using information contained in clipped samples from aualog-to-digital (ADC) conversion to improve receiver performance, by, for example, reducing the clipping distortion caused by ADCs due to its data resolution constraints. This provides an advantage over existing solutions, which perform suboptimally because the existing solution discard information in tire clipped samples. | 2022-06-23 |
20220200647 | FURNITURE HAVING LOAD-BEARING OR NON-LOAD BEARING STRUCTURES FOR STORAGE OF WATER OR OTHER MATERIAL - Furniture pieces which incorporate load-bearing or non-load bearing structures in which water or other material may be stored. By incorporating such storage capacity within furniture, a user may take advantage of space that would otherwise be unused or unusable to unobtrusively and conveniently store an emergency water supply or other desired material. | 2022-06-23 |
20220200648 | METHODS AND DEVICES FOR DEVICE ORIENTATION TO IMPROVE SIGNAL QUALITY AND SAR COMPLIANCE - Devices and methods for automatically determining and suggesting an optimal device orientation with respect to a partner communication device. The methods and devices may include features to determine a position of a user with respect to the device; estimate a direction of a partner communication device; perform a comparison of the direction of the partner communication device with the position of the user; and based on the comparison, determine whether to generate an instruction to suggest a change in orientation of the device. | 2022-06-23 |
20220200649 | DOCKING SLEEVE WITH ELECTRICAL ADAPTER - A protective arrangement for an electronic device includes a flexible cover having a panel and a skirt that form an interior cavity to receive an electronic device; and an adapter fixedly positioned in the flexible cover and having a male plug with connectors extending into the interior cavity of the flexible cover for mating with a female socket of the device and a contactor with contacts adjacent outwardly from the flexible cover and electrically coupled to one or more of the connectors of the plug. A docking cradle or external adapter can receive the electronic device and cover. | 2022-06-23 |
20220200650 | VARIABLE STRIDE COUNTING FOR TIMED-TRIGGERS IN A RADIO FREQUENCY FRONT END (RFFE) BUS - Systems and methods for variable stride counting for timed-triggers in a radio frequency front end (RFFE) bus modify how a master clock controls counters in slaves. In particular, instead of having the master clock change a counter at a slave device on a one-to-one clock tick-to-counter change, exemplary aspects of the present disclosure contemplate allowing a bus ownership master (BOM) to select a stride size wherein each clock tick causes the counter to change by the size of the stride. Clock ticks are then sent less frequently over the clock line of the RFFE bus. In this fashion, fewer clock ticks are required to change the counter to the trigger event. | 2022-06-23 |
20220200651 | RF SYSTEM AND ELECTRONIC DEVICE - A radio frequency (RF) system is provided. The RF system includes an RF transceiver, an RF processing circuit, a transfer switch module, a first antenna, a second antenna, a third antenna, and a fourth antenna. The RF transceiver is coupled with the RF processing circuit. The RF processing circuit is coupled with the transfer switch module. The transfer switch module is coupled with the first antenna, the second antenna, the third antenna, and the fourth antenna. When the RF system operates in a non-standalone (NSA) mode, the first antenna is configured for transmission in a first low band (LB) and primary reception in the first LB, the second antenna is configured for transmission in a second LB and primary reception in the second LB, the third antenna is configured for diversity reception in the second LB, and the fourth antenna is configured for diversity reception in the first LB. | 2022-06-23 |
20220200652 | MANUFACTURING METHOD OF ELECTRONIC DEVICE - The disclosure provides a manufacturing method of an electronic device. The manufacturing method of the electronic device includes steps as follows. A substrate is provided. A first opening is formed and penetrates the substrate. A polymer layer is formed in the first opening. The polymer layer is in contact with a sidewall of the substrate at the first opening. | 2022-06-23 |
20220200653 | Time Synchronization Method and Apparatus - A time synchronization method and apparatus includes determining a time difference between reference time and system time of an artificial intelligence device, where the reference time is timed by an internal clock of the artificial intelligence device and is aligned based on a satellite timing signal, or the reference time is timed by an internal clock of the artificial intelligence device; and adjusting the system time based on a preset step value if the time difference is greater than a preset value. | 2022-06-23 |
20220200654 | IMPULSE-RADIO RECEIVER AND METHOD - A communication device and method include a reconfigurable receiver that is reconfigurable between communication, ranging and radar modes. The reconfigurable receiver includes a mixer configured to mix digital samples with a carrier phase estimate signal and configured to generate in-phase digital samples based on the carrier phase estimate. The reconfigurable receiver further includes a symbol correlator configured to correlate against the in-phase digital samples and generate correlated data, and a symbol binning unit configured to bin the correlated data and generate a first order channel impulse response estimate. The reconfigurable receiver yet further includes a multiplexer configured to switch the digital samples to the symbol binning unit when the reconfigurable receiver is configured in radar mode and to switch the correlated data to the symbol binning unit when the reconfigurable receiver is configured in a ranging mode. | 2022-06-23 |
20220200655 | INTELLECTUAL PROPERTY SECURITY LOCKING APPARATUS AND METHOD - A clock buffer or driver is gated pending reception of verifiable crypto keys. These clock buffer or divers remain gated, thus disabling a processor from any meaningful function, till crypto keys are decoded, verified, and applied to the clock buffer or driver. A low frequency pseudorandom frequency hopping time sequence is generated and used for randomizing spread-spectrum to modulate a reference clock (or output clock) of a frequency synthesizer. This hopping time sequence holds the key to unlocking the crypto keys. The PWM modulated crypto keys are carried by the hopping time sequence. To decode the PWM modulated crypto keys, the hopping time sequence is used. The reference clock which is modulated with crypto keys in the spread-spectrum is sent to a decoder (in a processor) along with the hopping time sequence. The crypto keys are decoded and then used to un-gate the clock buffer. | 2022-06-23 |
20220200656 | DEVICE RANGING USING UWB - UWB ranging methods and apparatus are disclosed. The method comprises a ranging communication with a plurality of responder devices, the ranging communication comprising: transmitting, by an initiator device, a polling signal in a time slot; receiving a respective response from each of the plurality of responder devices, overlapping and in a next time slot, each response comprising: synchronization bits, and a frame comprising Start of Frame Delimiter, and a Scrambled Timestamp Sequence; wherein the STS comprises a sequence of segments each preceded by a respective guard interval, wherein a specific one of the segments comprises data derived from a ranging key and a responder-identifier each unique to the respective responder among the plurality of responders, wherein a sequence-number of the specific segment is unique to the respective response, and wherein a remainder of the segments each comprise the same data derived from a predetermined common key and predetermined common data. | 2022-06-23 |
20220200657 | Signal transceiving apparatus and method having echo-canceling mechanism - The present invention discloses a signal transceiving apparatus having echo-canceling mechanism. A mixer circuit includes a Wheatstone bridge and a transformer winding circuit. The Wheatstone bridge includes another transformer winding circuit and a variable load and includes a first input terminal, a first output terminal, a second input terminal and a second output terminal located at each two neighboring arms in an order. A transmission circuit is coupled to the first input terminal and the second input terminal to perform signal transmission through the mixer circuit. A receiving circuit is coupled to the first output terminal and the second output terminal to perform signal receiving through the mixer circuit. A control circuit adjusts the impedance of the variable load when a residual echo noise amount does not satisfy a minimum echo noise amount condition, and stops to adjust the impedance when the residual echo noise amount satisfies the condition. | 2022-06-23 |
20220200658 | POWER EXTENDER FOR SMART-HOME CONTROLLERS USING 2-WIRE COMMUNICATION - A method of powering a controller using an intermediate device with power from an environmental system may include receiving current from a power wire from the environmental system; passing the current from the power wire to a second command wire from the controller; monitoring the current flowing between the power wire and the second command wire while the current is below a threshold indicative of an amount of current used to power the controller from the environmental system; detecting when the current flowing between the power wire and the second command wire exceeds the threshold indicating that the controller is sending a command to the environmental system to perform the function; and sending a command to environmental system using a first command wire from the environmental system after detecting that the current exceeds the threshold. | 2022-06-23 |
20220200659 | RETROMODULATION METHOD OF A CONTACTLESS COMMUNICATION, AND CORRESPONDING TRANSPONDER - A contactless communication method comprises retro-modulation of a carrier signal received at the terminals of an antenna in an alternation of modulated states and unmodulated states. The modulated state comprises a modulation of a load at the terminals of the antenna at zero impedance, and the transitions from the modulated state to the unmodulated state are controlled at an instant determined by a first delay. | 2022-06-23 |
20220200660 | FILE TRANSMISSION/RECEPTION DEVICE AND CONTROL METHOD OF FILE TRANSMISSION/RECEPTION DEVICE - According to one embodiment, a file transmission/reception device includes a communication direction managing unit and an application unit. The communication direction managing unit, in near field communication, cuts off a connection with an opposing device in a case where a conflict occurs with the opposing device, and, after being reconnected to the opposing device, switches the file transmission/reception device to any one mode of a master mode and a slave mode. The application unit performs transmission, reception, or transmission/reception of a file between the opposing device and the file transmission/reception device in the master mode or the slave mode in accordance with a mode specified by the communication direction managing unit. | 2022-06-23 |
20220200661 | APPARATUS AND METHOD FOR PERFORMING WIRELESS POWER TRANSMISSION ON BASIS OF OUT-BAND COMMUNICATION IN WIRELESS POWER TRANSMISSION SYSTEM - According to one aspect of the present invention, a wireless power receiver for receiving wireless power on the basis of out-band communication is provided. The receiver comprises: a power pick-up circuit configured to receive wireless power from a wireless power transmitter at an operating frequency; and a communication/control circuit configured to perform at least one of in-band communication using the operating frequency and out-band communication using a frequency other than the operating frequency. Here, on the basis of at least one of the received voltage in the power pick-up circuit and a received signal strength indicator (RSSI) of a first signal related to the out-band communication, the communication/control circuit may perform a power interruption procedure for interrupting transmission of the wireless power and a disconnection procedure for releasing the connection of the out-band communication. | 2022-06-23 |
20220200662 | MAGNETIC FIELD COMMUNICATION METHOD AND APPARATUS USING GMI MAGNETOMETER - A magnetic field communication method and apparatus using a giant magnetoimpedance (GMI) magnetometer are disclosed. The magnetic field communication apparatus includes a GMI magnetometer configured to detect a first communication signal based on a received magnetic field signal, a first signal extractor configured to extract a second communication signal comprising a message signal from the first communication signal, a second signal extractor configured to extract a third communication signal by removing a magnetization frequency signal from the second communication signal, and a third signal extractor configured to extract the message signal by removing a carrier wave frequency signal from the third communication signal. | 2022-06-23 |
20220200663 | PROCESSING CIRCUIT MODULE AND METHOD FOR MANUFACTURING NONCONTACT COMMUNICATION MEDIUM - A processing circuit module includes a lead frame including a pair of leads electrically connectable to one end and the other end of an antenna coil of a substrate on which the antenna coil configured to induce power with application of a magnetic field from an outside is formed, and a processing circuit that is electrically connected to the pair of leads. The lead frame and the processing circuit are modularized. | 2022-06-23 |
20220200664 | ACTIVE SET MANAGEMENT FOR MULTIPLE-INPUT MULTIPLE-OUTPUT COMMUNICATIONS - Aspects of the disclosure relate to an active set management scheme implemented by a scheduler in a multiple-input multiple-output (MIMO) network that minimizes capacity and interference issues. For example, the scheduler can initially group each base station into a separate active set. The scheduler can then analyze each active set to determine whether the active set is a good or bad based on the level of interference in and the number of MIMO receive dimensions available in the respective active set. If the scheduler determines that an active set is a bad, the scheduler can determine a set of metrics that each represent a capacity and link quality that would result if the bad active set is combined with another active set. Based on the set of metrics, the scheduler can combine the bad active set with another active set, and repeat this process until no bad active sets remain. | 2022-06-23 |
20220200665 | BEAM STEERING APPARATUS AND METHOD - An apparatus and method for beam steering is disclosed. The apparatus comprises: a beam forming signal generator configured to generate a beam forming signal for applying to at least one of amplitude and phase shift circuitry associated with an antenna array to provide a radiation pattern. A determining means is provided that is configured to determine a signal strength of interfering signals received at the antenna array within a user equipment and to determine a dominant interfering ratio indicative of a strength of a strongest interfering signal relative to a strength of other interfering signals. A comparator is provided that is configured to compare the dominant interfering ratio to a predetermined ratio value and where the dominant interfering ratio exceeds the predetermined ratio value to generate a control signal for controlling the beam forming signal generator to generate a radiation pattern comprising a beam and at least one steered null. | 2022-06-23 |
20220200666 | HIGH-RESOLUTION CODEBOOK FOR DISTRIBUTED MIMO TRANSMISSION - A method for operating a user equipment (UE) comprises: receiving information associated with a channel state information (CSI) report, the information including a third-domain (TD) parameter | 2022-06-23 |
20220200667 | APPARATUS, METHOD AND COMPUTER PROGRAM - There is provided an apparatus, said apparatus comprising means for receiving a multiple input multiple output signal from a network, determining a frequency domain basis subset for each layer of the multiple input multiple output signal, determining from the frequency domain basis subset a number, M | 2022-06-23 |
20220200668 | COMMUNICATIONS METHOD AND DEVICE - Disclosed are a communications method and device. The method includes: sending, by a network device, configuration information to a terminal device; determining, by the terminal device, channel state information CSI measurement behavior and/or CSI feedback related information, where the channel state information CSI measurement behavior and/or the CSI feedback related information are/is related to the configuration information; and performing, by the terminal device, CSI measurement based on the configuration information and the CSI measurement behavior and/or the CSI feedback related information, to obtain at least one piece of CSI, and sending all or some of the at least one piece of CSI to the network device. It can be learned that, in a scenario in which a plurality of transmission modes are supported, according to the foregoing method, the terminal device can measure CSI, and feed back the measured CSI to the network device. | 2022-06-23 |
20220200669 | PARALLEL PRECODING FOR DOWNLINK TRANSMISSION - Apparatuses, systems, and techniques to determine precoding weights for fifth-generation (5G) new radio (NR) downlink transmission in parallel. In at least one embodiment, a parallel processor includes one or more circuits to perform precoding for a 5G downlink signal using two or more processing threads in parallel. | 2022-06-23 |
20220200670 | METHOD AND APPARATUS FOR ROBUST MIMO TRANSMISSION - A method for operating a user equipment (UE) comprises receiving information about a downlink (DL) transmission transmitted from N | 2022-06-23 |
20220200671 | UPLINK TRANSMISSIONS IN WIRELESS COMMUNICATIONS - Methods, apparatus, and systems for using multiple messages by the base station to indicate sub-band information without incurring big signaling overhead are described. In one example aspect, a wireless communication method includes receiving, by a user device from a base station, a first message that includes a first set of information for configuring a transmission from the user device to the base station. The first message includes one or more fields indicating an association between the first message and a second message for configuring the transmission. The method includes receiving, by the user device, the second message from the base station. The second message includes a second set of information for configuring the transmission. The method also includes performing the transmission based on the first and the second set of information. | 2022-06-23 |
20220200672 | BASE STATION AND BASE STATION COMMUNICATION METHOD - This base station comprises: a control unit that allocates, on the basis of a doppler shift estimated using an uplink reference signal, a downlink reference signal common to a plurality of beams; and a transmission unit that transmits the common downlink reference signal via the plurality of beams. According to this base station communication method, the base station allocates, on the basis of a doppler shift estimated using an uplink reference signal, a downlink reference signal common to a plurality of beams, and transmits the common downlink reference signal via the plurality of beams. | 2022-06-23 |
20220200673 | Adaptive Kronecker Product MIMO Precoding for a Multi-Antenna Network Entity and a Wireless Communication Device and Corresponding Methods - A network entity comprises a plurality of antenna elements arranged in one or more two dimensional (2D) arrays having one or more columns and rows. The network entity configured to determine at least one set of one or more precoding vectors related to the plurality of antenna elements, wherein each set of precoding vectors is associated with a different Kronecker product tradeoff parameter L≥1; and transmit, at least one set of a plurality of Cell Specific Reference Signals (CRS) to be used to estimate channel state information (CSI) based on the at least one set of precoding vectors and/or at least one Kronecker product tradeoff parameter L. | 2022-06-23 |
20220200674 | FULL POWER UPLINK TRANSMISSION FOR ADVANCED WIRELESS COMMUNICATION SYSTEMS - A method of a user equipment (UE) for an uplink (UL) transmission is provided. The method comprises transmitting, to a base station (BS), UE capability information including a full power transmission capability of the UE, receiving, from the BS, configuration information indicating an UL codebook, identifying the UL codebook to use for the UL transmission based on the configuration information, and transmitting, to the BS, the UL transmission based on the UL codebook, where the UL codebook for l layers includes K | 2022-06-23 |
20220200675 | TRANSMISSION CONFIGURATION INDICATION (TCI) STATE AND BEAM SWITCHING - Techniques for changing a Transmission Configuration Indication (TCI) state by a user equipment (UE) operating in a wireless communications system are provided. The UE receives a first message including a TCI state change command from a network and determines, based on the first message, whether a time offset/frequency offset (TO/FO) and a reception (Rx) beam for a new TCI state are known by the UE. Based on the determination, the UE calculates a time delay of the UE to be prepared to receive a reference signal with the new TCI state, generates a second message indicating the time delay of the UE for the new TCI state, and transmits the second message to the network. | 2022-06-23 |
20220200676 | TECHNIQUES FOR DYNAMIC BEAMFORMING MITIGATION OF MILLIMETER WAVE BLOCKAGES - Methods, systems, and devices for wireless communications are described. A user equipment (UE) may communicate with other network devices as part of a wireless communications system. The UE may identify a blockage corresponding to one or more antenna arrays of a set of antenna arrays based on using a first set of beam weights, which may correspond to a static beamforming codebook of the one or more antenna arrays. The UE may switch from a static beamforming codebook-based beam weight determination to a dynamic beamforming codebook-based beam weight determination. The UE may then determine a second set of beam weights to use for the one or more antenna arrays based on the dynamic beamforming codebook-based beam weight determination. The UE may then communicate using the one or more antenna arrays according to the second set of beam weights. | 2022-06-23 |
20220200677 | WIRELESS COMMUNICATION APPARATUS AND WIRELESS COMMUNICATION METHOD - A wireless communication apparatus includes: a plurality of antenna elements; a processor that outputs an in-phase signal and a quadrature signal; a splitter that distributes the in-phase signal and the quadrature signal to the antenna elements; and a plurality of quadrature modulators that generate transmission signals of a radio frequency by performing quadrature modulation on the in-phase signals and the quadrature signals. The processor is configured to execute a process including applying a first frequency shift according to a transmission beam direction to a first oscillation signal that is supplied to the quadrature modulators, digitally modulating transmission data to generate the in-phase signal and the quadrature signal, and performing complex multiplication to the in-phase signal and the quadrature signal with a second oscillation signal to which a second frequency shift opposite from the first frequency shift is applied. | 2022-06-23 |
20220200678 | COMMUNICATION DEVICES AND METHODS - A first communication device that simultaneously transmits to a group of two or more second communication devices using multi-user multiple input multiple output (MU-MIMO) communication performs beamforming training with a selected second communication device of said group of second communication devices by transmitting one or more training units, wherein an analog beamforming training matrix and/or a digital beamforming training matrix adapted for beamforming training with the selected second communication device are applied on the one or more training units, receiving from the selected second communication device feedback in response to the transmitted transmit packets, and determining, for use in the simultaneous transmission of data to a group of two or more second communication devices including the selected second communication device, an updated analog beamforming matrix and/or an updated digital beamforming matrix based at least on the received feedback. | 2022-06-23 |
20220200679 | Parallel Beamforming Training with Coordinated Base Stations - This document describes techniques and apparatuses for parallel beamforming training with coordinated base stations. In particular, a user equipment (UE) uses time-division multiplexing (TDM) to perform parallel beamforming training with multiple base stations within a coordination set. The TDM interleaves beamforming training signals associated with different base stations. In other words, at least one beamforming training signal associated with a first base station occurs between two beamforming training signals associated with a second base station. Example types of beamforming training signals include downlink pilot signals, uplink feedback signals, uplink pilot signals, and downlink feedback signals. In some situations, the different types of beamforming training signals are further interleaved together based on expected rates at which channel conditions change. By interleaving beamforming training signals, narrow beams can be formed to support millimeter-wave (mmW) communications at cell edges. | 2022-06-23 |
20220200680 | METHOD AND APPARATUS FOR BEAM MANAGEMENT AFTER CHANNEL SETUP - Methods and apparatuses for beam management after channel setup. A method of operating a user equipment (UE) includes receiving at least one of synchronization signal/physical broadcast channel block (SSB) or channel state information reference signal (CSI-RS), measuring the at least one of the SSB or the CSI-RS, and determining downlink (DL) quasi-co-location (QCL) properties for DL communication based on the at least one of the SSB or the CSI-RS. The method further includes determining an uplink (UL) spatial domain filter for UL communication, receiving DL channels using the determined DL QCL properties until only one of only one joint TCI state or only one DL TCI state is configured, activated, or indicated to the UE, and transmitting UL channels using the determined UL spatial domain filter until only one of only one joint TCI state or only one UL TCI state is configured, activated, or indicated to the UE. | 2022-06-23 |
20220200681 | APPARATUS AND METHOD FOR LOW OVERHEAD FREQUENCY-AVERAGED BEAM PATTERN FEEDBACK IN MILLIMETER WAVE POSITIONING SYSTEMS - The position of a mobile device is estimated using angle based positioning measurements. The angle based positioning measurements are generated using transmit (Tx) beams or receive (Rx) beams from one or more base stations that generate the beams over an ultra-wide bandwidth, which produces frequency and spatial distortions and impairments in an array gain response. The array gain distribution variation as a function of angle and frequency for the set of beam weights used in beamforming is conveyed to indicate the frequency and spatial distortions. The array gain distribution variation may be provided to the mobile device in assistance data for a sub-band that is only a portion of the allocated bandwidth for the base stations, or as an aggregation of the array gain distribution variation for a plurality of sub-bands of the allocated bandwidth to reduce the overhead in signaling. | 2022-06-23 |
20220200682 | METHODS AND APPARATUS FOR GROUP BEAM REPORTING FOR BEAM SQUINT - The present disclosure relates to methods and devices for wireless communication of an apparatus, e.g., a UE and/or a base station. In one aspect, the apparatus may measure a plurality of beams from a base station or a UE, the plurality of beams corresponding to a plurality of subbands of a wideband channel. The apparatus may also determine whether the plurality of beams include one or more candidate beam groups for each subband of the plurality of subbands. Additionally, the apparatus may transmit, upon determining that the plurality of beams include one or more candidate beam groups for at least one subband of the plurality of subbands, an indication of the one or more candidate beam groups for the at least one subband of the plurality of subbands. | 2022-06-23 |