25th week of 2022 patent applcation highlights part 78 |
Patent application number | Title | Published |
20220199783 | TRANSITION METAL DICHALCOGENIDE NANOSHEET TRANSISTORS AND METHODS OF FABRICATION - A transistor includes a first channel layer over a second channel layer, where the first and the second channel layers include a monocrystalline transition metal dichalcogenide (TMD). The transistor structure further includes a source structure coupled to a first end of the first and second channel layers, a drain structure coupled to a second end of the first and second channel layers, a gate structure between the source material and the drain material, and between the first channel layer and the second channel layer. The transistor further includes a spacer laterally between the gate structure and the and the source structure and between the gate structure and the drain structure. A liner is between the spacer and the gate structure. The liner is in contact with the first channel layer and the second channel layer and extends between the gate structure and the respective source structure and the drain structure. | 2022-06-23 |
20220199784 | CRYSTALLINE OXIDE THIN FILM, MULTILAYER BODY AND THIN FILM TRANSISTOR - A crystalline oxide thin film contains an In element, a Ga element and an Ln element, in which the In element is a main component, the Ln element is at least one element selected from the group consisting of La, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu, and an average crystal grain size D | 2022-06-23 |
20220199785 | WRAPPED-AROUND CONTACT FOR VERTICAL FIELD EFFECT TRANSISTOR TOP SOURCE-DRAIN - A semiconductor structure and a method of making the same includes a first recessed region in a semiconductor structure, the first recessed region defining a first opening with a first positive tapering profile, as at least part of the first positive tapering profile, widening the first opening in a direction towards a top source/drain region of the semiconductor structure at a first tapering angle, and a top source/drain contact within the first opening, the top source/drain contact surrounding a surface of the top source/drain region. The semiconductor structure further includes a protective liner located at an interface between a bottom portion of the top source/drain region, a top spacer adjacent to the top source/drain region and a dielectric material between two consecutive top source/drain regions, the protective liner protects the top source/drain regions during contact patterning. | 2022-06-23 |
20220199786 | SEMICONDUCTOR DEVICE - Provided is a highly reliable semiconductor device in which an influence on device characteristics can be reduced while improving a high temperature and high humidity bias resistance of a termination structure (termination region) of a chip by a relatively simple method. The semiconductor device includes an active region disposed on a main surface of a semiconductor substrate, and a termination region disposed on the main surface so as to surround the active region. The termination region includes an interlayer insulating film formed on the main surface of the semiconductor substrate, and an organic protective film formed so as to cover the interlayer insulating film. An insulating film having a thickness of 100 nm or less and containing nitrogen is provided between the interlayer insulating film and the organic protective film. | 2022-06-23 |
20220199787 | LOW CAPACITANCE LOW RC WRAP-AROUND-CONTACT - A field effect transistor is provided. The field effect transistor includes a first source/drain on a substrate, a second source/drain on the substrate, and a channel region between the first source/drain and the second source/drain. The field effect transistor further includes a metal liner on at least three sides of the first source/drain and/or the second source/drain, wherein the metal liner covers less than the full length of a sidewall of the first source/drain and/or the second source/drain. The field effect transistor further includes a metal-silicide between the metal liner and the first source/drain and/or the second source/drain, and a conductive contact on the metal liner on the first source/drain and/or the second source/drain, wherein the conductive contact is a conductive material different from the conductive material of the metal liner. | 2022-06-23 |
20220199788 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A nitride-based semiconductor device includes a buffer, a first nitride-based semiconductor layer, a shield layer, a second nitride-based semiconductor layer, S/D electrodes, and a gate electrode. A first nitride-based semiconductor layer is disposed over the buffer. A shield layer is disposed between the buffer and the first nitride-based semiconductor layer and includes a first isolation compound that has a bandgap greater than a bandgap of the first nitride-based semiconductor layer, in which the first isolation compound is made of at least one two-dimensional material which includes at least one metal element. A second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap less than the bandgap of the first isolation compound and greater than the bandgap of the first nitride-based semiconductor layer. The pair of S/D electrodes and the gate electrode are disposed over the second nitride-based semiconductor layer. | 2022-06-23 |
20220199789 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a first active pattern disposed on a substrate, a device isolation layer filling a trench that defines the first active pattern, a first channel pattern and a first source/drain pattern disposed on the first active pattern in which the first channel pattern includes semiconductor patterns stacked and spaced apart from each other, a gate electrode that extends and runs across the first channel pattern, a gate dielectric layer disposed between the first channel pattern and the gate electrode, and a first passivation pattern disposed between the device isolation layer and a first sidewall of the first active pattern. The first passivation pattern includes an upper part that protrudes upwardly from the device isolation layer, and a lower part buried in the device isolation layer. The gate dielectric layer covers the upper part of the first passivation pattern. | 2022-06-23 |
20220199790 | SEMICONDUCTOR DEVICE - A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode. | 2022-06-23 |
20220199791 | SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF - Disclosed are a semiconductor structure and a forming method thereof. In one form, a forming method includes: providing a base, including a substrate and a plurality of fins protruding from the substrate, an interlayer dielectric layer formed on the substrate, a gate opening formed in the interlayer dielectric layer, the gate opening spanning the fin and exposing a part of a top and a part of a sidewall of the fin, and a source/drain doped region formed in the fins on two sides of the gate opening, where the substrate includes a first region and a second region adjacent to each other, to respectively form transistors, the gate opening located in either of the first region and the second region extends to the other region and exposes the fin of the other region, and a position of the exposed fin of the other region is used as an interconnect position; forming a gate dielectric layer covering a bottom and a sidewall of the gate opening and the fin in the gate opening conformally; removing the gate dielectric layer on a surface of the fin at the interconnect position, to expose the surface of the fin at the interconnect position; and forming a gate structure in the gate opening after the surface of the fin at the interconnect position is exposed. The present disclosure enlarges a process window for electrical connection. | 2022-06-23 |
20220199792 | FIN SHAPING USING TEMPLATES AND INTEGRATED CIRCUIT STRUCTURES RESULTING THEREFROM - Fin shaping using templates, and integrated circuit structures resulting therefrom, are described. For example, integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has a vertical portion and one or more lateral recess pairs in the vertical portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack. A second source or drain region is at a second side of the gate stack opposite the first side of the gate stack. | 2022-06-23 |
20220199793 | SEMICONDUCTOR DEVICES - A semiconductor device includes a plurality of semiconductor structures disposed on a substrate, a first conductive pattern, a first conductive pattern, a gate insulation pattern, a second conductive pattern and a second impurity region. Each of the semiconductor structures includes a first semiconductor pattern that has a linear shape that extends in a first direction and second semiconductor patterns that protrude from an upper surface of the first semiconductor pattern in a vertical direction. The semiconductor structures are spaced apart from each other in a second direction perpendicular to the first direction. The first conductive pattern is formed between the first semiconductor patterns. The first impurity region is formed in an opening in the first semiconductor pattern adjacent to a first sidewall of the second semiconductor pattern. The first impurity region includes an impurity diffusion harrier pattern and a polysilicon pattern doped with impurities | 2022-06-23 |
20220199794 | BIDIRECTIONAL POWER DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed are a bidirectional power device and a method for manufacturing the same. The bidirectional power device includes a semiconductor layer, a plurality of trenches located in the semiconductor layer, a gate dielectric layer located on an inner wall of each of the plurality of trenches, a control gate located at a lower portion of each of the plurality of trenches, a shield gate located at an upper portion of each of the plurality of trenches and an isolation layer located between the control gate and the shield gate. When the bidirectional power device is turned off, charges of a source region and a drain region are depleted by the shield gate through a shield dielectric layer, thereby improving voltage withstand property. When the bidirectional power device is turned on, the source region and/or the drain region and the semiconductor layer provide a low-impedance conduction path. | 2022-06-23 |
20220199795 | GALLIUM NITRIDE COMPONENT AND DRIVE CIRCUIT THEREOF - This application provides a gallium nitride component and a drive circuit thereof. The gallium nitride component includes: a substrate; a gallium nitride GaN buffer layer formed on the substrate; an aluminum gallium nitride AlGaN barrier layer formed on the GaN buffer layer; and a source, a drain, and a gate formed on the AlGaN barrier layer. The gate includes a P-doped gallium nitride P-GaN cap layer formed on the AlGaN barrier layer, and a first gate metal and a second gate metal formed on the P-GaN cap layer. A Schottky contact is formed between the first gate metal and the P-GaN cap layer, and an ohmic contact is formed between the second gate metal and the P-GaN cap layer. In the technical solution provided in this application, the gallium nitride component is a normally-off component, and is conducive to design of a drive circuit. In addition, the gallium nitride component has a hybrid gate structure that includes a Schottky gate and an ohmic gate, so that not only gate leakage currents in a conduction process can be reduced to reduce driving power consumption, but also a large quantity of electron holes can be injected into the AlGaN barrier layer during conduction to optimize a dynamic resistance, thereby improving component reliability. | 2022-06-23 |
20220199796 | MULTI THRESHOLD VOLTAGE FOR NANOSHEET - A semiconductor structure including nanosheet stacks on a substrate, each nanosheet stack including alternating layers of sacrificial semiconductor material and semiconductor channel material and a crystallized gate dielectric layer surrounding the semiconductor channel layers of a first subset of the nanosheet stacks, a dipole layer on top of the crystallized gate dielectric and surrounding the layers of semiconductor channel material of the first subset of the nanosheet stacks and a gate dielectric modified by a diffused dipole material surrounding the semiconductor channel layers of a second subset of the nanosheet stacks. A method including forming nanosheet stacks on a substrate, each nanosheet stack including alternating layers of sacrificial semiconductor material and semiconductor channel material, removing sacrificial semiconductor material layers of the set of nanosheet stacks, forming a gate dielectric surrounding the semiconductor channel layers of the nanosheet stacks, and crystalizing the gate dielectric of a subset of the nanosheet stacks. | 2022-06-23 |
20220199797 | LOCALIZED SPACER FOR NANOWIRE TRANSISTORS AND METHODS OF FABRICATION - A transistor includes a first channel layer over a second channel layer, an epitaxial source structure coupled to a first end of the first and second channel layers and an epitaxial drain structure coupled to a second end of the first and second channel layers. The transistor includes a gate between the epitaxial source structure and the epitaxial drain structure, where the gate is above the first channel layer and between the first channel layer and the second channel layer. The transistor includes a first spacer of a first material, between the first and second channel layers includes. The first spacer has at least one convex sidewall that is between the gate and the epitaxial source structure and between the gate and the epitaxial drain structure. The transistor also includes a second spacer of a second material having substantially vertical sidewalls above the first channel layer. | 2022-06-23 |
20220199798 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate that includes a peripheral region, a first active pattern on the peripheral region, a first source/drain pattern on the first active pattern, a first channel pattern formed on the first active pattern and connected to the first source/drain pattern, wherein the first channel pattern includes semiconductor patterns that are stacked and spaced apart from each other, a first gate electrode that extends in a first direction and crosses the first channel pattern, a gate insulating layer interposed between the first gate electrode and the first channel pattern, a first gate contact disposed on the first gate electrode and that extends in the first direction, and a first dielectric layer interposed between the first gate electrode and the first gate contact. The first dielectric layer is interposed between the first gate contact and the first gate electrode and extends in the first direction. | 2022-06-23 |
20220199799 | THIN FILM TRANSISTORS HAVING BORON NITRIDE INTEGRATED WITH 2D CHANNEL MATERIALS - Thin film transistors having boron nitride integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a first gate stack above a substrate. A 2D channel material layer is above the first gate stack. A second gate stack is above the 2D channel material layer, the second gate stack having a first side opposite a second side. A first conductive contact is adjacent the first side of the second gate stack and in contact with the 2D channel material layer. A second conductive contact is adjacent the second side of the second gate stack and in contact with the 2D channel material layer. A hexagonal boron nitride (hBN) layer is included between the first gate stack and the 2D channel material layer, between the second gate stack and the 2D channel material layer, or both. | 2022-06-23 |
20220199800 | SEMICONDUCTOR DEVICE HAVING A SILICON CARBIDE DRIFT ZONE OVER A SILICON CARBIDE FIELD STOP ZONE - A semiconductor device includes a silicon carbide (SiC) drift zone over a SiC field stop zone and/or a SiC semiconductor substrate. A concentration of Z | 2022-06-23 |
20220199801 | NOVEL METHOD TO FORM SINGLE CRYSTAL MOSFET AND FEFET - Embodiments disclosed herein include a semiconductor devices with back end of line (BEOL) transistor devices. In an embodiment, a semiconductor device comprises a semiconductor substrate and a BEOL stack over the semiconductor substrate. In an embodiment, a field effect transistor (FET) is embedded in the BEOL stack. In an embodiment, the FET comprises a channel, a gate dielectric over the channel, where the gate dielectric is single crystalline, a gate electrode over the gate dielectric, and a source electrode and a drain electrode passing through the gate dielectric to contact the channel. | 2022-06-23 |
20220199802 | Implantation Enabled Precisely Controlled Source And Drain Etch Depth - A method of fabricating a high electron mobility transistor is disclosed. The method comprises using an ion implantation process to amorphize a portion of the barrier layer to a specific depth. The etch rate of this amorphized portion is much faster than that of the rest of the barrier layer. In this way, the depth of the recessed regions into which the source and drain contacts are disposed is more tightly controlled. Further, the etching process may be a wet or dry etch process. The roughness of the recessed region may also be improved using this approach. | 2022-06-23 |
20220199803 | SEMICONDUCTOR DEVICE AND FORMING METHOD THEREOF - A method includes forming a gate structure over a substrate; forming a first gate spacer and a second gate spacer on opposite sidewalls of the gate structure, respectively; implanting a first dopant of a first conductivity type into the substrate form a lightly doped source region adjacent to the first gate spacer, and a lightly doped drain region adjacent to the second gate spacer; forming a patterned mask over a first portion of the lightly doped drain region, while leaving a second portion of the lightly doped drain region exposed; and with the patterned mask in place, implanting a second dopant of the first conductivity type into the substrate, resulting in converting the second portion of the lightly doped drain region into a drain region. | 2022-06-23 |
20220199804 | Integrated CMOS Source Drain Formation With Advanced Control - A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform. | 2022-06-23 |
20220199805 | METHOD OF MAKING A VERTICALLY-ALIGNED THREE DIMENSIONAL SEMICONDUCTOR STRUCTURE - A method for making a three-dimensional semiconductor structure includes: providing a substrate, forming a first insulating layer on the substrate, and defining at least one channel hole in the first insulating layer; forming a first epitaxial layer in each channel hole and forming a second epitaxial layer stacked on the first epitaxial layer; forming a sacrificial layer on the first insulating layer and exposing the second epitaxial layer relative to the sacrificial layer, forming another first epitaxial layer on the second epitaxial layer; forming a second insulating layer on the sacrificial layer, and forming another second epitaxial layer stacking on the another first epitaxial layer; repeating to form a plurality of sacrificial layers and a plurality of second insulating layers alternately stacked on the first insulating layer, and repeating to form a plurality of first epitaxial layers and a plurality of second epitaxial layers alternately stacked on the substrate. | 2022-06-23 |
20220199806 | ION IMPLANTATION TO FORM TRENCH-BOTTOM OXIDE OF MOSFET - Disclosed herein are methods for forming MOSFETs. In some embodiments, a method may include providing a device structure including a plurality of trenches, and forming a mask over the device structure including within each of the plurality of trenches and over a top surface of the device structure. The method may further include removing the mask from within the trenches, wherein the mask remains along the top surface of the device structure, and implanting the device structure to form a treated layer along a bottom of the trenches. In some embodiments, the method may further include forming a gate oxide layer along a sidewall of each of the trenches and along the bottom of the trenches, wherein a thickness of the oxide along the bottom of the trenches is greater than a thickness of the oxide along the sidewall of each of the trenches. | 2022-06-23 |
20220199807 | FABRICATION OF THIN FILM FIN TRANSISTOR STRUCTURE - Thin film transistors fabricated using a spacer as a fin are described. In an example, a method of forming a fin transistor structure includes patterning a plurality of backbone pillars on a semiconductor substrate. The method may then include conformally depositing a spacer layer over the plurality of backbone pillars and the semiconductor substrate. A spacer etch of the spacer layer is then performed to leave a sidewall of the spacer layer on a backbone pillar to form a fin of the fin transistor structure. Other embodiments may be described and claimed | 2022-06-23 |
20220199808 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. In one form, a forming method includes: providing a base, a gate structure, a source-drain doping region, and an interlayer dielectric layer; removing the gate structure located in an isolation region to form an isolation opening and expose the top and side walls of a fin located in the isolation region; performing first ion-doping on the fin under the isolation opening to form an isolation doped region, a doping type of the isolation doped region being different from a doping type of the source-drain doping region; and filling the isolation opening with an isolation structure after the doping, the isolation structure straddling the fin of the isolation region. In embodiments and implementations of the present disclosure, the isolation doped region is formed, a doping concentration of inversion ions in the fin of the isolation region can thus be increased, and a barrier of a P-N junction formed by the source-drain doping region and the fin of the isolation region can be increased accordingly, to prevent the device from generating a conduction current in the fin of the isolation region during operation, thereby implementing isolation between the fin of the isolation region and the fin of other regions. Moreover, there is no need to perform a fin cut process. Hence the fin is made into a continuous structure, which helps prevent stress relief in the fin. | 2022-06-23 |
20220199809 | FET DEVICE AND A METHOD FOR FORMING A FET DEVICE - According to an aspect there is provided a FET device. The FET device comprises a common source body portion and a set of source layer prongs protruding therefrom in a first lateral direction. First dielectric layer portions are arranged in spaces between the source layer prongs. The device further comprises a common drain body portion and a set of drain layer prongs protruding in the first lateral direction. Second dielectric layer portions are arranged in spaces between the drain layer prongs. The device further comprises a gate body comprising a common gate body portion and a set of gate prongs protruding therefrom in a second lateral direction opposite the first lateral direction. Each gate prong is formed intermediate a respective pair of first and second dielectric layer portions. The device further comprises a channel region comprising a set of channel layer portions. Each channel layer portion extends between a respective pair of source and drain layer prongs. The channel layer portions are arranged in spaces between the gate prongs. There is also provided a method for forming a FET device. | 2022-06-23 |
20220199810 | LATERAL BIPOLAR JUNCTION TRANSISTOR DEVICE AND METHOD OF MAKING SUCH A DEVICE - A non-uniform base width bipolar junction transistor (BJT) device includes: a semiconductor substrate, the semiconductor substrate having an upper surface; and a BJT device, the BJT device comprising a collector region, a base region, and an emitter region positioned in the semiconductor substrate, the base region being positioned between the collector region and the emitter region; the base region comprising a top surface and a bottom surface, wherein a first width of the top surface of the base region in a base width direction of the BJT device is greater than a second width of the bottom surface of the base region in the base width direction of the BJT device. | 2022-06-23 |
20220199811 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a technology that suppresses the removal of collector layers in the planarization process while suppressing the snapback phenomenon. A semiconductor device related to a technology disclosed in the present specification includes a drain layer of first conductivity type in a part of a lower surface a drift layer, a plurality of collector layers of second conductivity type in parts of the lower surface of the drift layer, and a dummy layer of the first conductivity type interposed between the plurality of collector layers in parts of the lower surface of the drift layer, in which a width of the dummy layer | 2022-06-23 |
20220199812 | TRANSISTORS WITH MONOCRYSTALLINE METAL CHALCOGENIDE CHANNEL MATERIALS - Transistor structures with monocrystalline metal chalcogenide channel materials are formed from a plurality of template regions patterned over a substrate. A crystal of metal chalcogenide may be preferentially grown from a template region and the metal chalcogenide crystals then patterned into the channel region of a transistor. The template regions may be formed by nanometer-dimensioned patterning of a metal precursor, a growth promoter, a growth inhibitor, or a defected region. A metal precursor may be a metal oxide suitable, which is chalcogenated when exposed to a chalcogen precursor at elevated temperature, for example in a chemical vapor deposition process. | 2022-06-23 |
20220199813 | HIGH ELECTRON MOBILITY TRANSISTOR DEVICE HAVING AN ALUMINUM-DOPED BUFFER LAYER - A high electron mobility transistor (HEMT) device is disclosed. The HEMT device includes a substrate with epitaxial layers over the substrate that includes a buffer layer having a dopant comprising aluminum, wherein the concentration of aluminum within the buffer layer is between 0.5% and 3%. The epitaxial layer further includes a channel layer over the buffer layer and a barrier layer over the channel layer. A gate contact is disposed on a surface of the epitaxial layers. A source contact and a drain contact are also disposed on the surface of the epitaxial layers, wherein the source contact and the drain contact are spaced apart from the gate contact and each other. | 2022-06-23 |
20220199814 | Planar High-Electron-Mobility Transistor - The present application discloses a planar High-Electron-Mobility Transistor (HEMT), which includes a hetero-junction consisting of a first semiconductor epitaxial layer and a second semiconductor epitaxial layer, and two-dimensional electron gas located at an interface of the hetero-junction; a bottom surface of a gate trench of a trench gate is located at a bottom of the two-dimensional electron gas to cut off the two-dimensional electron gas; when gate-source voltage is higher than or equal to threshold voltage, an inversion layer is formed on a surface of the first semiconductor epitaxial layer covered by side surfaces and a bottom surface of a gate conductive material layer, and the source-end and drain-end two-dimensional electron gas is conducted to enable the device to be on; when the gate-source voltage is lower than the threshold voltage, the source-end and drain-end two-dimensional electron gas is cut off to enable the device to be off. | 2022-06-23 |
20220199815 | GROUP III NITRIDE-BASED TRANSISTOR DEVICE - In an embodiment, a Group III nitride-based transistor device is provided that includes a Group III nitride-based body and a p-type Schottky gate including a metal gate on a p-doped Group III nitride structure. The p-doped Group III nitride structure includes an upper p-doped GaN layer in contact with the metal gate and having a thickness d | 2022-06-23 |
20220199816 | pGaN ENHANCEMENT MODE HEMTs WITH DOPANT DIFFUSION SPACER - III-N e-mode high electron mobility transistors (HEMTs) including a dopant diffusion spacer between an impurity-doped III-N material layer and a III-N polarization layer of the HEMT material stack. The spacer may be a substantially undoped III-N material, such as GaN. With the diffusion spacer, P-type impurities within the pGaN are setback from the polarization layer sufficiently to avoid significant levels of P-type impurities from entering the III-N material interface where the 2DEG resides. With the diffusion spacer, clustering of impurities near the 2DEG may be avoided and a III-N e-mode HEMT may achieve higher drive currents. | 2022-06-23 |
20220199817 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A nitride-based semiconductor device includes a buffer, a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a gate electrode, a first S/D electrode, and a second S/D electrode. The buffer includes at least one layer of a nitride-based semiconductor compound doped with an acceptor at a top-most portion of the buffer. The first nitride-based semiconductor layer is disposed over the buffer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The gate electrode and the first and second S/D electrodes are disposed over the second nitride-based semiconductor layer. Profiles of the first and second S/D electrodes are asymmetric with respect to the gate electrode, such that a bottom surface of the first S/D electrode is deeper than that of the second S/D electrode with respect to the gate electrode. | 2022-06-23 |
20220199818 | HIGH HOLE MOBILITY TRANSISTOR (HHMT) AND METHOD OF MANUFACTURING THE SAME - The present disclosure relates to a semiconductor device and a method of fabricating the same. The semiconductor device includes: a substrate including a vertical interface; a channel layer disposed outside the vertical interface; and a channel supply layer disposed outside the channel layer; wherein a vertical two-dimensional electron gas 2DEG or two-dimensional hole gas 2DHG is formed in the channel layer adjacent to an interface between the channel layer and the channel supply layer. | 2022-06-23 |
20220199819 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present disclosure relates to a semiconductor device, comprising: a groove; a first channel layer positioned within the groove; and a first barrier layer positioned within the groove, wherein a first heterojunction having a vertical interface is included between the first channel layer and the first barrier layer and 2DEG or 2DHG is formed in the first heterojunction. The present disclosure also relates to a method of manufacturing a semiconductor device. | 2022-06-23 |
20220199820 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device | 2022-06-23 |
20220199821 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a heterojunction field effect transistor, and the heterojunction field effect transistor includes a barrier layer provided in an upper layer portion of a channel layer of a first nitride semiconductor, being formed of a second nitride semiconductor hetero-joined to the first nitride semiconductor, first and second impurity regions provided, being spaced each other with the barrier layer interposed therebetween, a source electrode and a drain electrode which are provided on the first and second impurity regions, respectively, an insulating film which is so provided as to come into contact with at least a region of the barrier layer excluding an edge portion thereof on the side of the source electrode, a gate insulating film which is in contact with the edge portion of the barrier layer and covers the insulating film, and a gate electrode which is so provided on the gate insulating film. | 2022-06-23 |
20220199822 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A nitride-based semiconductor device includes a buffer, a first nitride-based semiconductor layer, a shield layer, a second nitride-based semiconductor layer, a pair of S/D electrodes, and a gate electrode. The first nitride-based semiconductor layer is disposed over the buffer and forms a first interface with the buffer. The shield layer includes a first isolation compound and is interposed between the buffer and the first nitride-based semiconductor layer. The first isolation compound has a bandgap greater than a bandgap of the buffer and greater than a bandgap of the first nitride-based semiconductor layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap less than the bandgap of the first isolation compound and greater than the bandgap of the first nitride-based semiconductor layer. The S/D electrodes and a gate electrode are disposed over the second nitride-based semiconductor layer. | 2022-06-23 |
20220199823 | SEMICONDUCTOR DEVICE - One object is to provide a semiconductor device capable of suppressing forward voltage degradation and loss during turn-on. A vertical MOSFET includes a semiconductor substrate | 2022-06-23 |
20220199824 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A voltage withstanding structure disposed in an edge termination region is a spatial modulation junction termination extension (JTE) structure formed by a combination of a JTE structure and a field limiting ring (FLR) structure. All FLRs configuring the FLR structure are surrounded by an innermost one of p | 2022-06-23 |
20220199825 | SEMICONDUCTOR STRUCTURE WITH TRENCH JUNCTION BARRIER SCHOTTKY (TJBS) DIODE - A semiconductor structure includes: a U-metal-oxide-semiconductor field-effect transistor (UMOS) structure; and a trench junction barrier Schottky (TJBS) diode, wherein an insulating layer of a sidewall of the TJBS diode does not have a side gate, | 2022-06-23 |
20220199826 | SEMICONDUCTOR ON INSULATOR ON WIDE BAND-GAP SEMICONDUCTOR - A semiconductor device includes a first semiconductor structure. The first semiconductor structure includes a first semiconductor material having a band-gap. The first semiconductor structure has a first surface. An insulating layer has first and second opposing surfaces. The first surface of the insulating layer is on the first surface of the first semiconductor structure. A second semiconductor structure is on the second surface of the insulating layer and includes a second semiconductor material having a band-gap that is smaller than the band-gap of the first semiconductor material. A floating electrode couples the first semiconductor structure to the second semiconductor structure. | 2022-06-23 |
20220199827 | TRANSISTOR DEVICE - A transistor device includes a semiconductor body having a substantially planar main surface, a source region extending to the main surface and having a first conductivity type, a body region extending to the main surface and having a second conductivity type, a drain region extending to the main surface and having the first conductivity type, a drift region having the first conductivity type, and a gate electrode arranged on the main surface laterally between the source and drain regions and electrically insulated from the semiconductor body by an insulation structure. The insulation structure includes a gate dielectric arranged on the main surface and a shallow trench arranged in the drift region and filled with electrically insulating material. The shallow trench has at least partly a wedge shape and the electrically insulating material has an upper surface that is substantially planar and extends substantially parallel to the main surface. | 2022-06-23 |
20220199828 | FIN TRANSISTORS WITH DOPED CONTROL LAYER FOR JUNCTION CONTROL - In a described example, an integrated circuit includes a substrate of a semiconductor material, a source region, a gate region, a drain region and a fin structure formed on the substrate. The fin structure includes the gate region, the source region and a drift region between the gate region and the drain region. A doped control layer is formed along at least one sidewall of the fin structure over the drift region. | 2022-06-23 |
20220199829 | Thin Film Transistor and Display Apparatus Comprising the Same - A thin film transistor and a display apparatus comprising the same are provided, in which the thin film transistor comprises an active layer, a barrier layer on the active layer; a gate insulating layer on the barrier layer; and a gate electrode on the gate insulating layer, wherein at least a portion of the gate electrode overlaps at least a portion of the active layer, and the barrier layer includes an oxide semiconductor material and has a resistivity greater than a resistivity of the active layer and has a thickness less than a thickness of the active layer. | 2022-06-23 |
20220199830 | METAL OXIDE TRANSISTOR, DISPLAY PANEL AND DISPLAY APPARATUS - A metal oxide transistor, display panel and display apparatus are provided. The metal oxide transistor has characteristics of low off-state leakage current and high conductivity. In an embodiment, the metal oxide transistor includes first gate electrode, an active layer, second gate electrode, and source-drain electrode. Source-drain electrode includes source electrode and drain electrode. Active layer includes active sub-layers, active sub-layer includes metal oxide and has semiconductor zone. Active sub-layers includes first active sub-layer, second active sub-layer and third active sub-layer, first active sub-layer is located between second active sub-layer and first gate electrode, and third active sub-layer is located between second active sub-layer and second gate electrode. Semiconductor zone of first active sub-layer has an oxygen ion doping concentration C | 2022-06-23 |
20220199831 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region. | 2022-06-23 |
20220199832 | SEMICONDUCTOR DEVICE - A semiconductor device with small variations in transistor characteristics is provided. The semiconductor device includes an oxide; a first conductor and a second conductor provided apart from each other over the oxide; an insulator in a region between the first conductor and the second conductor over the oxide; and a conductor over the insulator. A side surface of the oxide, a top surface of the first conductor, a side surface of the first conductor, a top surface of the second conductor, and a side surface of the second conductor include regions in contact with a nitride containing silicon. | 2022-06-23 |
20220199833 | FIELD-EFFECT TRANSISTOR (FET) WITH SELF-ALIGNED FERROELECTRIC CAPACITOR AND METHODS OF FABRICATION - A memory device structure includes a transistor structure including a gate electrode over a top surface of a fin and adjacent to a sidewall of the fin, a source structure coupled to a first region of the fin and a drain structure coupled to a second region of the fin, where the gate electrode is between the first and the second region. A gate dielectric layer is between the fin and the gate electrode. The memory device structure further includes a capacitor coupled with the transistor structure, the capacitor includes the gate electrode, a ferroelectric layer on a substantially planar uppermost surface of the gate electrode and a word line on the ferroelectric layer. | 2022-06-23 |
20220199834 | WIMPY VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR WITH DIPOLE LINERS - A semiconductor structure may include a bottom source drain, a top source drain, a gate stack. The top source drain is above the gate stack and the bottom source drain is below the gate stack. The semiconductor structure may also include a bottom spacer and a top spacer. The gate stack is between the bottom spacer and the top spacer. The bottom spacer and the top spacer each comprise a dipole liner. The dipole liner includes a first layer and a second layer. The second layer may be in direct contact with the first layer. The second layer may be made of different material than the first layer. The first layer may be made of silicon oxide. The second layer may be made of silicon nitride or aluminum oxide. The first layer may be in direct contact with the gate stack, the top source drain, and the bottom source drain. | 2022-06-23 |
20220199835 | Display Device and Method for Manufacturing the Same - Provided are a display device and a method for manufacturing the same. The display device includes: a connection source electrode and a connection drain electrode connected to a first source electrode a the first drain electrode, respectively by penetrating an isolation insulating layer and a second interlayer dielectric layer to enhance a characteristic of an element and reliability of the display device. | 2022-06-23 |
20220199836 | VERTICAL CHANNEL THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A vertical channel thin film transistor includes substrate, lower source/drain electrode, spacer layer, upper source/drain electrode covering portion of upper surface of the spacer layer, interlayer insulating pattern covering portion of upper surface of the upper source/drain electrode and upper surface of the spacer layer exposed by the upper source/drain electrode, contact hole disposed on the lower source/drain electrode and passing through the interlayer insulating pattern, the upper source/drain electrode, and the spacer layer, active pattern covering inner wall and bottom surface of the contact hole and extending over upper surface of the upper source/drain electrode and upper surface of the interlayer insulating pattern, gate insulating pattern filling portion of the contact hole and extending along upper surface of the active pattern, and gate electrode filling portion of the contact hole and extending along upper surface of the gate insulating pattern. | 2022-06-23 |
20220199837 | PILLAR-SHAPED SEMICONDUCTOR DEVICE HAVING CONNECTION MATERIAL LAYER FOR ANCHORING WIRING CONDUCTOR LAYER AND METHOD FOR PRODUCING THE SAME - An SGT circuit includes a first conductor layer which contains a semiconductor atom, which is in contact with an N | 2022-06-23 |
20220199838 | ENCAPSULATION FOR TRANSITION METAL DICHALCOGENIDE NANOSHEET TRANSISTOR AND METHODS OF FABRICATION - A transistor includes a channel layer including a transition metal dichalcogenide (TMD) material, an encapsulation layer on a first portion of the channel layer, a gate electrode above the encapsulation layer, a gate dielectric layer between the gate electrode and the encapsulation layer. The transistor further includes a source contact on a second portion of the channel layer and a drain contact on a third portion of the channel layer, where the gate structure is between drain contact and the source contact. | 2022-06-23 |
20220199839 | COMPOSITIONAL ENGINEERING OF SCHOTTKY DIODE - Embodiments disclosed herein include semiconductor devices with Schottky diodes in a back end of line stack. In an embodiment, a semiconductor device comprises a semiconductor layer, where transistor devices are provided in the semiconductor layer, and a back end stack over the semiconductor layer. In an embodiment, a diode is in the back end stack. In an embodiment, the diode comprises a first electrode, a semiconductor region over the first electrode, and a second electrode over the semiconductor region. In an embodiment, a first interface between the first electrode and the semiconductor region is an ohmic contact, and a second interface between the semiconductor region and the second electrode is a Schottky contact. | 2022-06-23 |
20220199840 | PHOTODETECTOR WITH IMPROVED DETECTION RESULT - The invention relates to different aspects of a photodetector ( | 2022-06-23 |
20220199841 | SEMICONDUCTOR WAFER, RADIATION DETECTION ELEMENT, RADIATION DETECTOR, AND PRODUCTION METHOD FOR COMPOUND SEMICONDUCTOR MONOCRYSTALLINE SUBSTRATE - Provided is a stable CdZnTe monocrystalline substrate having a small leakage current even when a high voltage is applied and having a lower variation in resistivity with respect to variations in applied voltage values. A semiconductor wafer comprising a cadmium zinc telluride monocrystal having a zinc concentration of 4.0 at % or more and 6.5 at % or less and a chlorine concentration of 0.1 ppm by mass or more and 5.0 ppm by mass or less, wherein the semiconductor wafer has a resistivity of 1.0×10 | 2022-06-23 |
20220199842 | SOLAR CELL EMITTER REGION FABRICATION USING SELF-ALIGNED IMPLANT AND CAP - Methods of fabricating solar cell emitter regions using self-aligned implant and cap, and the resulting solar cells, are described. In an example, a method of fabricating an emitter region of a solar cell involves forming a silicon layer above a substrate. The method also involves implanting, through a stencil mask, dopant impurity atoms in the silicon layer to form implanted regions of the silicon layer with adjacent non-implanted regions. The method also involves forming, through the stencil mask, a capping layer on and substantially in alignment with the implanted regions of the silicon layer. The method also involves removing the non-implanted regions of the silicon layer, wherein the capping layer protects the implanted regions of the silicon layer during the removing. The method also involves annealing the implanted regions of the silicon layer to form doped polycrystalline silicon emitter regions. | 2022-06-23 |
20220199843 | METHOD OF MANUFACTURING A PHOTOVOLTAIC CELL - Method of manufacturing a photovoltaic cell, comprising the steps of:
| 2022-06-23 |
20220199844 | Silicon Wafer/Cell, Photovoltaic Cell Module and Carrier, Design and Arrangement Method - A silicon wafer/cell, a photovoltaic cell module and a carrier, and a design and arrangement method are provided. The silicon wafer/cell is shaped as a rectangle or a quasi-rectangle with chamfered corners, with two adjacent side lengths of x and y, where x≠y, wherein the quasi-rectangle with chamfered corners has a chamfered area not more than 5% of its total area. The photovoltaic cell module is formed by arraying a plurality of the above-mentioned cells. The carder has an opening, the length of the opening of the carrier is equal to that of a short side of the silicon wafer/cell, and the silicon wafer/cell can be inserted into the opening along its long-side direction. | 2022-06-23 |
20220199845 | Architecture for Efficient Monolithic Bifacial Perovskite-CdSeTe Tandem Thin Film Solar Cells and Modules - An optoelectronic device comprising two photovoltaic absorber materials of CdSeTe and perovskite and their functional component layers that are monolithically integrated into a bifacial tandem solar cell structure. | 2022-06-23 |
20220199846 | PHOTOVOLTAIC CELL - A photovoltaic cell may include a hydrogenated amorphous silicon layer including a n-type doped region and a p-type doped region. The n-type doped region may be separated from the p-type doped region by an intrinsic region. The photovoltaic cell may include a front transparent electrode connected to the n-type doped region, and a rear electrode connected to the p-type doped region. The efficiency may be optimized for indoor lighting values by tuning the value of the H2/SiH4 ratio of the hydrogenated amorphous silicon layer. | 2022-06-23 |
20220199847 | AVALANCHE PHOTODETECTOR (VARIANTS) AND METHOD FOR MANUFACTURING THE SAME (VARIANTS) - An APD includes a photoconverter and at least one avalanche amplifier of the photocurrent, the amplifier having two layers—a contact layer and a multiplication layer, wherein the multiplication layer is formed on top of the entire conductive wafer, while the contact layer of at least one avalanche amplifier is formed on top of a certain area of the multiplication layer. Meanwhile, outside the contact layer, the multiplication layer functions as a photoconverter. This makes it possible for photocarriers to get into the avalanche amplifier effectively and unimpeded. In order to mitigate the influence of parasite near-surface charge carriers on the avalanche amplifier, its multiplication region is deepened in relation to the upper surface of the photoconverter region. The proposed APD embodiment with less dark current seeping from peripheral areas of the instrument provides higher threshold sensitivity that allows it be on par with state of the art. | 2022-06-23 |
20220199848 | ARRAY SUBSTRATE, DIGITAL X-RAY DETECTOR INCLUDING THE SAME, AND METHOD FOR MANUFACTURING THE SAME - A lower electrode of a PIN diode and a second protective layer covering the PIN diode are formed not using separate mask processes, but using the same mask process using the same mask, thereby reducing the number of mask processes and thus increasing process efficiency. Further, the lower electrode of the PIN diode is patterned and then the second protective film covering the PIN diode is patterned such that both the former patterning and the latter patterning are carried out using a single mask process, thereby reduce increase in defects due to foreign materials or stains. | 2022-06-23 |
20220199849 | OPTICAL CONTROL SWITCH AND ELECTRONIC DEVICE COMPRISING SAME - An optically-controlled switch is provided. The optically-controlled switch includes a circuit board including a transmission line and a photoconductive switching region that is adjacent to the transmission line and has electrical properties controllable by light and a laser located on the circuit board and configured to emit light toward the photoconductive switching region. | 2022-06-23 |
20220199850 | AUTOMATED ASSEMBLY AND MOUNTING OF SOLAR CELLS ON PANELS - A method of fabricating a solar cell array module or panel comprising providing a support, providing a face sheet having a top side and an opposite bottom side, mounting the bottom side of the face sheet on the support, dispensing an adhesive on a plurality of discrete predefined regions on the top side of the face sheet where a string of solar cell assemblies is to be mounted using an automated process, positioning and mounting an interconnected string of solar cell assemblies on the adhesive regions on the top side of the face sheet using machine vision, and applying heat or pressure to bond the interconnected string of solar cell assemblies to the adhesive regions on the top side of the face sheet. | 2022-06-23 |
20220199851 | METHOD AND APPARATUS TO ADD LIGHT SOURCES TO A PRINT - A method is disclosed. For example, the method includes printing an image on a substrate, applying an adhesive on select portions of the image, coupling the image to a wave guide such that the adhesive contacts a surface of the wave guide, and providing a light through the wave guide such that the light is emitted through the wave guide and the adhesive and the light is reflected by the select portions of the image back through the adhesive and the wave guide. | 2022-06-23 |
20220199852 | DISPLAY DEVICE AND METHOD OF MANUFACTURING DISPLAY DEVICE - A display device and a method of manufacturing a display device are provided. A method of manufacturing a display device may include: forming a sacrificial layer on a carrier glass; forming a first substrate layer on the sacrificial layer, the first substrate layer including an organic insulation material; forming a first through-hole in the first substrate layer, the first through-hole passing through the first substrate layer; forming a wiring on an upper surface of the first substrate layer, the wiring extending into the first through-hole; sequentially forming a circuit layer, an emission layer, and an encapsulation layer on the wiring; separating the sacrificial layer and the carrier glass from the first substrate layer by irradiating the sacrificial layer with a laser; and attaching a driving element on a lower surface of the first substrate layer, the driving element being electrically connected to the wiring through the first through-hole. | 2022-06-23 |
20220199853 | Method for producting an optoelectronic device comprising microleds - A method for producing an optoelectronic device having nitride-based microLEDs includes providing an assembly having at least one growth substrate and a nitride structure, where the nitride structure has a semipolar nitride layer that includes an active stack and crystallites extending from facets of the growth substrate with a crystalline orientation {111} to the first face of the semipolar nitride layer and providing an integrated control circuit featuring electric connection pads. The assembly is placed on the integrated control circuit, the growth substrate and the crystallites are removed, and trenches are formed in the stack so as to delimit a plurality of islets, each islet being configured to form a microLED. | 2022-06-23 |
20220199854 | METHOD FOR PRODUCING GROUP 13 ELEMENT NITRIDE CRYSTAL LAYER, AND SEED CRYSTAL SUBSTRATE - It is provided a seed crystal layer, composed of a group 13 nitride crystal selected from gallium nitride, aluminum nitride, indium nitride or the mixed crystals thereof, on an alumina layer on a single crystal substrate. By annealing under reducing atmosphere at a temperature of 950° C. or higher and 1200° C. or lower, convex-concave morphology is formed on a surface of the seed crystal layer so as to have an RMS value of 180 nm to 700 nm measured by an atomic force microscope. On the surface of the seed crystal layer, it is grown a group 13 nitride crystal layer composed of a group 13 nitride crystal selected from gallium nitride, aluminum nitride, indium nitride or the mixed crystals thereof. | 2022-06-23 |
20220199855 | NITRIDE SEMICONDUCTOR LIGHT EMITTING ELEMENT - A nitride semiconductor light emitting element includes: an n-side nitride semiconductor layer; a p-side nitride semiconductor layer; and an active layer disposed between the n-side nitride semiconductor layer and the p-side nitride semiconductor layer and comprising a plurality of stacks, each comprising a well layer and a barrier layer. The well layers include, successively from the n-side nitride semiconductor layer side, a first well layer, a second well layer, and a third well layer that is positioned closest to the p-side nitride semiconductor layer among the well layers. A thickness of the second well layer is greater than a thickness of the first well layer. A thickness of the third well layer is greater than the thickness of the second well layer. Among the barrier layers, the first barrier layer, which is positioned between the third well layer and the p-side nitride semiconductor layer, is doped with a p-type impurity. | 2022-06-23 |
20220199856 | LED CHIP AND DISPLAY APPARATUS INCLUDING THE SAME - A display apparatus is provided. The display apparatus includes a display panel; and a light emitting diode (LED) chip configured to emit light to the display panel. The LED chip includes: a light emitting layer configured to emit light; a semiconductor layer provided on the light emitting layer; and a growth substrate provided on the semiconductor layer. The light emitting layer is arranged to be biased toward a first side of the growth substrate such that a center of an upper surface of the growth substrate is provided between a center of the light emitting layer and a center of the semiconductor layer. | 2022-06-23 |
20220199857 | UNIT PIXEL AND DISPLAYING APPARATUS INCLUDING THE UNIT PIXEL - A unit pixel and a displaying apparatus including the unit pixel are provided. The unit pixel includes a transparent substrate, and a plurality of light emitting devices arranged on the transparent substrate. The transparent substrate includes at least one light scattering line disposed therein so as to correspond to each of the plurality of light emitting devices. | 2022-06-23 |
20220199858 | METAL OXIDE SEMICONDUCTOR-BASED LIGHT EMITTING DEVICE - An optoelectronic semiconductor light emitting device configured to emit light having a wavelength in the range from about 150 nm to about 425 nm is disclosed. In embodiments, the device comprises a substrate having at least one epitaxial semiconductor layer disposed thereon, wherein each of the one or more epitaxial semiconductor layers comprises a metal oxide. An epitaxial semiconductor layer of the device can include a first single crystal oxide material. The first single crystal oxide material can include: at least one of magnesium, nickel, and zinc; at least one of aluminum and gallium; and oxygen. The first single crystal oxide material can also include a cubic crystal symmetry. | 2022-06-23 |
20220199859 | METAL OXIDE SEMICONDUCTOR-BASED LIGHT EMITTING DEVICE - An optoelectronic semiconductor light emitting device configured to emit light having a wavelength in the range from about 150 nm to about 425 nm is disclosed. In embodiments, the device comprises a substrate having at least one epitaxial semiconductor layer disposed thereon, wherein each of the one or more epitaxial semiconductor layers comprises a metal oxide. At least one of the epitaxial semiconductor layers can include single crystal A | 2022-06-23 |
20220199860 | SEMICONDUCTOR COMPONENT WITH OXIDIZED ALUMINUM NITRIDE FILM AND MANUFACTURING METHOD THEREOF - The present disclosure is a light-emitting diode (LED) with oxidized aluminum nitride (oxidized-AlN) film, which includes a substrate, an aluminum nitride buffer (AlN-buffer) layer, an oxidized-AlN film and a light-emitting diode epitaxial structure. The AlN-buffer layer is disposed on a patterned surface of the substrate, wherein the patterned surface is formed with a plurality of protrusions and a bottom portion. The oxidized-AlN film is disposed on the AlN-buffer layer on the protrusions, and with none disposed on the AlN-buffer layer on the bottom portion. The LED epitaxial structure includes gallium nitride compound crystal formed on the oxidized-AlN film and the AlN-buffer layer, to effectively reduce defect density of the gallium nitride compound crystal and to improve a luminous intensity of the LED. | 2022-06-23 |
20220199861 | Light Emitting Device And Projector - A light emitting device includes n columnar parts, and an electrode configured to inject an electrical current into the n columnar parts, wherein each of the n columnar parts includes a first semiconductor layer, a second semiconductor layer different in conductivity type from the first semiconductor layer, and a light emitting layer disposed between the first semiconductor layer and the second semiconductor layer, when viewed from a stacking direction of the first semiconductor layer and the light emitting layer, p first columnar parts out of the n columnar parts fail to overlap an outer edge of the electrode, q second columnar parts out of the n columnar parts overlap the outer edge of the electrode, a number of the second columnar parts centers of which overlap the electrode out of the q second columnar parts is larger than a number of the second columnar parts centers of which fail to overlap the electrode, and n=p+q is fulfilled. | 2022-06-23 |
20220199862 | INTERMEDIATE SUBSTRATE AND FABRICATION METHOD OF DISPLAY PANEL - Embodiments of the present disclosure provide an intermediate substrate, including: a first substrate; a black photoresist layer on a side of the first substrate; and a plurality of light emitting devices on a side of the black photoresist layer away from the first substrate. Each of the plurality of light emitting devices has a light-exiting side for emergence of light emitted by the light emitting device, the light-exiting side is in contact with the black photoresist layer, and the light emitting device includes a driving electrode for introducing a driving signal. | 2022-06-23 |
20220199863 | LIGHT EMITTING ELEMENT, METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE INCLUDING THE SAME - A method for manufacturing a light emitting element includes forming a first semiconductor layer on a substrate, the first semiconductor layer including a semiconductor of a first type; forming an active layer on the first semiconductor layer; forming a second semiconductor layer on the active layer, the second semiconductor layer including a semiconductor of a second type different from the first type; performing an etching process of removing at least a portion of each of the first semiconductor layer, the active layer, and the second semiconductor layer in a direction toward the first semiconductor layer from the second semiconductor layer; and forming a first insulating layer to surround an outer surface of the active layer. The first insulating layer is formed by a wet process. | 2022-06-23 |
20220199864 | METHOD FOR MANUFACTURING LIGHT-EMITTING ELEMENT - A method for manufacturing a light-emitting element includes: providing a semiconductor stacked body including a first semiconductor layer, an active layer, and a second semiconductor layer, formed in this order on a substrate; exposing a surface of the first semiconductor layer by removing the substrate; and forming a protective film on the surface of the first semiconductor layer by performing steps including: forming a first layer on the surface of the first semiconductor layer by chemical vapor deposition while introducing a source gas to a film formation chamber at a first flow rate, and forming a second layer on the first layer by chemical vapor deposition while introducing a source gas to the film formation chamber at a second flow rate, the second flow rate being less than the first flow rate. | 2022-06-23 |
20220199865 | DISPLAY SUBSTRATE, SPLICED DISPLAY PANEL AND DISPLAY APPARATUS - Provided are a display substrate, a tiled display panel and a display device, relating to the field of display technology. The display substrate comprises a base substrate, and a plurality of light-emitting units, a protective layer and a connecting wire which are sequentially stacked in a direction away from the base substrate. One end of the connecting wire is connected to the plurality of light-emitting units through a via hole provided in the protective layer, and the other end is used for connecting a drive circuit, that is, the drive circuit can be directly provided at a side of the protective layer away from the base substrate. When a plurality of display substrates are tiled to form a tiled display panel, there is no need to bend a flexible circuit board at sides of each display substrate, and therefore, the gap between every two adjacent display substrates is small, and the display effect is good. | 2022-06-23 |
20220199866 | SEMICONDUCTOR OPTICAL DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR OPTICAL DEVICE - A semiconductor optical device, in which a light emitting region and a modulator region are integrated, includes a first mesa disposed in the light emitting region, protruding in a direction that intersects a light propagation direction, and including an active layer, first and second buried layers disposed on the first mesa in a direction that intersects the light propagation direction and sequentially stacked in a direction in which the first mesa protrudes, a first semiconductor layer disposed on the first mesa and the second buried layer, a second mesa disposed in the modulator region and including a light absorption layer, and a third buried layer disposed on the second mesa. The first semiconductor layer and the first buried layer each have a first conductivity type. The second buried layer has a second conductivity type different from the first conductivity type, and the third buried layer is a semi-insulating semiconductor layer. | 2022-06-23 |
20220199867 | LIGHT EMITTING DEVICE AND PLANAR LIGHT SOURCE - A light emitting device includes a light emitting element, lateral walls surrounding the light emitting element, a first light-transmissive member and a light shielding member. The lateral walls includes first to fourth lateral walls. The first and second lateral walls define a first opening therebetween. The second and third lateral walls define a second opening therebetween. The third and fourth lateral walls define a third opening therebetween. The fourth and first lateral walls define a fourth opening therebetween. In the top view, a first straight line passing through the first and third openings extends in a first direction, and a second straight line passing through the second and fourth openings extends in a second direction orthogonal to the first direction. The first light-transmissive member is arranged on or above the light emitting element and the lateral walls. The light shielding member is arranged on or above the first light-transmissive member. | 2022-06-23 |
20220199868 | Optoelectronic Semiconductor Device and Method for Manufacturing an Optoelectronic Semiconductor Device - In an embodiment a method for manufacturing an optoelectronic semiconductor device includes providing a semiconductor body having an active region configured to generate electromagnetic radiation and a coupling-out surface along a main radiation direction, forming a mask layer having a plurality of recesses on the coupling-out surface on the semiconductor body, depositing metallic separators in the recesses and applying a wavelength conversion element to the coupling-out surface of the semiconductor body such that the metallic separators are at least partially embedded therein. | 2022-06-23 |
20220199869 | LIGHT EMITTING DIODE STRUCTURE - A light emitting diode structure including a light emitting unit having a blue LED chip to produce a first light beam, a first light conversion layer disposed on the light emitting unit to convert a part of the first light beam into a second light beam, and a second light conversion layer disposed on the first light conversion layer to convert another part of the first light beam into a third light beam is provided. A remaining part of the first light beam, the second light beam, and the third light beam are superposed to form a working light beam whose spectrum includes a first wave band ranging from 350 nm to 660 nm and a second wave band ranging from 660 nm to 1000 nm. A power of the working light beam in the second wave band is higher than that in the first wave band. | 2022-06-23 |
20220199870 | DISPLAY DEVICE - A display device includes a substrate; a first electrode and a second electrode disposed in an emission area and a sub-region and spaced apart from each other in a first direction; a first insulating layer disposed on the first electrode and the second electrode; light emitting elements disposed on the first insulating layer in the emission area, and including ends disposed on the first and second electrodes, respectively; and a second insulating layer disposed on the first insulating layer. The second insulating layer includes a fixing pattern; a support pattern portion; and a connection portion electrically connecting the fixing pattern and the support pattern portion, and the fixing pattern includes a first region that contacts an outer surface of the light emitting elements and a second region that does not contact the outer surface of the light emitting elements. | 2022-06-23 |
20220199871 | BEAM-SHAPING SECONDARY OPTICAL COMPONENTS FOR MICRO LIGHT EMITTING DIODES - The invention is directed towards employing semiconductor-based waveguides as secondary optical components that reduce the beam divergence of light generated by LEDs. A lighting source includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes an LED. The second semiconductor die is bonded to the first semiconductor device and includes a crystalline waveguide having a first waveguide surface, a second waveguide surface, and a waveguide body. The first waveguide surface receives light from the LED. The waveguide body is comprised of a crystalline material that transmits the received light from the first waveguide surface to the second waveguide surface. The second waveguide surface emits the received portion of the light with a second beam divergence that is significantly less than the first beam divergence. | 2022-06-23 |
20220199872 | MICRO LIGHT-EMITTING DIODE DISPLAY PANEL AND METHOD FOR PRODUCING THE SAME - The present invention relates to a micro light-emitting diode display panel and a method for producing the same. A backplane and a light-emitting diode display layer are subjected to a bonding process to form eutectic structures between the backplane and light-emitting diodes of the light-emitting diode display layer. Then, an adhesive bonding layer including a resin material and conducting materials is formed on a surface of the backplane, and a heating process is performed, thereby causing the conducting materials to form a plurality of metallic bridge connection structures. Therefore, a bonding between the light-emitting diode and the backplane is reinforced, and tensile strength of the micro light-emitting diode display panel is enhanced. | 2022-06-23 |
20220199873 | OPTOELECTRONIC COMPONENT AND METHOD FOR PRODUCING AN OPTOELECTRONIC COMPONENT - An optoelectronic component is specified, with an optoelectronic semiconductor chip which, in operation, is configured to emit or detect electromagnetic radiation, a connection carrier, on which the semiconductor chip is arranged, an electrically conductive connection, which is electrically conductively connected to the semiconductor chip and/or the connection carrier, and an electrically insulating material, which surrounds the semiconductor chip and/or the connection carrier at least in places, wherein the electrically conductive connection is arranged in places on the electrically insulating material. Furthermore, a method for producing an optoelectronic component is specified. | 2022-06-23 |
20220199874 | TRANSPARENT DISPLAY DEVICE AND TILED DISPLAY DEVICE INCLUDING THE SAME - A transparent display device includes a substrate, a main light emitting diode, a main transmission region, a sub-light emitting diode, a sub-transmission region, and a driving circuit. The substrate includes a main display area and a peripheral area adjacent to the main display area. The main light emitting diode is disposed in the main display area. The main transmission region is disposed in the main display area and adjacent to the main light emitting diode. The sub-light emitting diode is disposed in the peripheral area. The sub-transmission region is disposed in the peripheral area and adjacent to the sub-light emitting diode. The driving circuit is disposed in the peripheral area and overlaps, in a plan view, the sub-light emitting diode. | 2022-06-23 |
20220199875 | ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF - An electronic device and a manufacturing method thereof are disclosed. The manufacturing method of the electronic device includes following steps: providing a substrate; forming a first compressible layer on the substrate; forming a first bonding pad on the first compressible layer; providing an electronic component; forming a second bonding pad on the electronic component; and bonding the electronic component with the substrate by contacting the second bonding pad with the first bonding pad. | 2022-06-23 |
20220199876 | ELECTROLUMINESCENCE DISPLAY APPARATUS - An electroluminescence display apparatus includes a pixel and a sensing circuit supplying a pixel reference voltage to the pixel through a reference voltage line during display driving and sensing a pixel current, flowing in the pixel, through the reference voltage line during sensing driving succeeding the display driving operation. The sensing circuit includes a sensing channel terminal connected to the reference voltage line, a first switch between the sensing channel terminal and an input terminal for the pixel reference voltage, an integrator amplifier including a first input terminal, a second input terminal, and an output terminal, an input terminal for an integrator reference voltage connected to the second input terminal, a second switch between the first input terminal and the output terminal, a first capacitor between the sensing channel terminal and the first input terminal, and a second capacitor between the sensing channel terminal and the output terminal. | 2022-06-23 |
20220199877 | METHOD OF MANUFACTURING LIGHT-EMITTING DEVICE, AND LIGHT-EMITTING DEVICE - A method of manufacturing a light-emitting device includes: a providing step including providing a plurality of light sources, each of the light sources having an upper surface including a light-emitting portion, a lower surface opposite to the upper surface, and lateral surfaces between the upper surface and the lower surface, wherein each of the light sources includes an external connection terminal at the lower surface, and wherein the plurality of light sources are ranked in terms of at least one of luminous flux or chromaticity; an extracting step including extracting a plurality of light sources in a desired rank from the plurality of light sources; and a bonding step including bonding the lateral surfaces of adjacent ones of the plurality of extracted light sources via a bonding member such that the upper surfaces and the lower surfaces of the light sources are exposed from the bonding member and such that the bonding member is spaced apart from the external connection terminals. | 2022-06-23 |
20220199878 | LIGHT-EMITTING DEVICE - A light-emitting device includes a support member that includes a wiring layer comprising a connection portion, and a hole portion; a light source located on a first surface of the support member, the light source including a positive electrode and a negative electrode; and a conductive member located in the hole portion, the conductive member connecting the connection portion and one of the positive electrode or the negative electrode. The hole portion includes a first hole portion, and a second hole portion communicating with the first hole portion. The first hole portion overlaps said one of the positive electrode or the negative electrode that is connected with the conductive member in a plan view. The second hole portion includes a first portion overlapping the first hole portion in a plan view, and a second portion extending in a first direction from the first portion toward a connection portion side. | 2022-06-23 |
20220199879 | MICRO-LED BOARD AND DISPLAY DEVICE - A micro-LED board includes a substrate, wiring, a first insulating layer, a micro-LED, and a light-blocking layer. The wiring, the first insulating layer, and the micro-LED are located on the substrate in an order of the wiring, the first insulating layer, and the micro-LED. The micro-LED overlaps the wiring. The light-blocking layer is located between the first insulating layer and the micro-LED, at least partially crosses a portion of the wiring directly below the micro-LED, and has an area that does not overlap a positive electrode and a negative electrode. | 2022-06-23 |
20220199880 | DISPLAY MODULE PACKAGE - A display module package includes a semiconductor chip, a wiring member disposed on the semiconductor chip, including an insulating layer and a wiring layer, and contacting at least a portion of the semiconductor chip, a light emitting device array disposed on the wiring member and including a plurality of light emitting devices disposed on one surface, wherein the wiring member is between the semiconductor chip and the light emitting device, and a molding member disposed on the wiring member, sealing part of the light emitting device array, and having an opening for exposing the plurality of light emitting devices. | 2022-06-23 |
20220199881 | MICRO PATTERNS CREATED ON THE SURFACE TO CONTROL PLACEMENT AND UNIFORMITY OF MATERIAL WITH VISCOSITY - Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate and a compute die on the package substrate. In an embodiment, an optics die is on the package substrate, and an integrated heat spreader (IHS) is over the compute die and the optics die. In an embodiment, channels are disposed on a surface of the IHS facing the package substrate. | 2022-06-23 |
20220199882 | LIGHT EMITTING DIODE CHIP-SCALE PACKAGE AND METHOD FOR MANUFACTURING SAME - The present invention provides a LED chip scale package, comprising: a light emitting diode chip having a pad electrically connected to an external object on one side thereof, a phosphor silicon film surrounding the light emitting diode chip so that a bonding surface of the pad is exposed to an outside, and a metal layer connected to the bonding surface and expanding a surface area of the pad, and a method for manufacturing the same. | 2022-06-23 |