25th week of 2022 patent applcation highlights part 76 |
Patent application number | Title | Published |
20220199583 | 3D PACKAGE CONFIGURATION - A novel 3D package configuration is provided by stacking a plurality of semiconductor package units or a folded flexible circuit board structure on a package substrate and electrically connected therewith based on the foldable characteristics of the flexible circuit board, and the high temperature resistance of the flexible circuit board which is suitable for insulating layer process, metal layer process, photolithography process, etching and development process, to make conventional semiconductor dies of various functions be bonded on one die and/or two side of a flexible circuit board and electrically connected therewith in advance. | 2022-06-23 |
20220199584 | FOLDABLE DOLL WITH PROJECTION FUNCTION - A foldable doll includes: a doll body which is a hollow structure; a projection lamp disposed in the doll body; a power connector electrically connected to the projection lamp; a supporting assembly for supporting the doll body; a plurality of supporting rings sewn on the doll body; a blower connected to the doll body and electrically connected to the power connector. The projection lamp includes a lamp cover, a motor, and a projection unit. The motor includes a rotation shaft, and the projection unit is fixedly disposed on the rotation shaft and configured to emit and project light on the lamp cover. The blower is electrically connected to the power connector. In an unfolded state, the doll body is propped up by the supporting assembly, and in a folded state, the supporting assembly is detached from the doll body, and the doll body automatically collapses by gravity. | 2022-06-23 |
20220199585 | DIODE DISCRETE DEVICE, CIRCUIT WITH BYPASS FUNCTION, AND CONVERTER - This application provides a diode discrete device, a circuit with a bypass function, and a converter. The diode discrete device is used in a circuit with a bypass function, and the diode discrete device includes a discrete device package, a first diode, and a second diode. The first diode is a main circuit diode, the second diode is a bypass diode, first performance of the first diode is better than first performance of the second diode, and the first performance includes a reverse recovery charge and reverse recovery time. The first diode and the second diode are packaged into the discrete device package, and an anode of the first diode is connected to an anode of the second diode, or a cathode of the first diode is connected to a cathode of the second diode. The diode discrete device can improve integration and power density of the circuit. | 2022-06-23 |
20220199586 | MICRO LIGHT-EMITTING DIODE DISPLAY AND PACKAGE METHOD THEREOF - A micro light-emitting diode (micro LED) display and a package method thereof are described. The micro LED display includes a substrate, various micro LED chips, and an encapsulation film. The substrate includes a wire. The micro LED chips are disposed on a surface of the substrate and are electrically connected to the wire. A light-emitting surface of each of the micro LED chips is set with at least one micro structure, and each micro structure has a top end. The encapsulation film encapsulates the micro LED chips, and covers the surface of the substrate. The top ends of the micro structures are located in a light-emitting surface of the encapsulation film. | 2022-06-23 |
20220199587 | LIGHT SOURCE ASSEMBLY, METHOD FOR MAKING SAME, AND DISPLAY DEVICE - A light source assembly, a method for making same, and a display device using same are disclosed. The light source assembly includes a circuit substrate, an opaque and light-reflecting colloidal layer on the circuit substrate, micro light-emitting elements electrically connected to the circuit substrate, a base layer, a layer of convex lenses, and a layer of immediately-adjacent concave lenses. The colloidal layer defines grooves. At least two micro light-emitting elements each emitting light of a different color are arranged in each groove. The base layer is infilled into each groove and covers each micro light-emitting element. Each groove is covered by a convex lens which converges the emitted light. Each concave lens, covering one convex lens, substantially corrects optical path deviations of light of different wavelengths (that is, different colors), so reducing chromatic aberrations. | 2022-06-23 |
20220199588 | ELECTRONIC DEVICE AND DISPLAY METHOD OF ELECTRONIC DEVICE - The disclosure provides an electronic device and a display method thereof. The electronic device includes a display panel and a light source module. The light source module is disposed at a side of the display panel. The light source module includes a first group of light-emitting units and a second group of light-emitting units that are alternately arranged, wherein the first group of light-emitting units and the second group of light-emitting units emit a light alternately, and each of a plurality of display pixels is adapted to alternately receive the light from the first group of light-emitting units and the second group of light-emitting units. | 2022-06-23 |
20220199589 | LED CHIPS AND DEVICES WITH TEXTURED LIGHT-EXTRACTING PORTIONS, AND FABRICATION METHODS - Pixelated-LED chips include substrate sidewalls with sidewall involutions and/or increased sidewall surface area regions to affect light extraction therefrom. A LED lighting device incorporates a superstrate that supports lumiphoric material and includes sidewalls with sidewall involutions and/or increased sidewall surface area regions. Methods for fabricating sidewall features may include etching (e.g., deep etching) of substrate or superstrate materials, such as by using an etch mask having edges with non-linear shapes to produce and/or enhance sidewall involutions when an etchant is supplied through the etch mask to selectively consume substrate or superstrate material. | 2022-06-23 |
20220199590 | LIGHT-EMITTING DIODE PACKAGING MODULE - A light-emitting diode (LED) packaging module includes a plurality of LED chips spaced apart from one another, an encapsulating layer that fills in a space among the LED chips, a light-transmitting layer disposed on the encapsulating layer, a wiring assembly disposed on and electrically connected to the LED chips, and an insulation component that covers the encapsulating layer and the wiring assembly. Each of the LED chips includes an electrode assembly including first and second electrodes. The light-transmitting layer includes a light-transmitting layer that has a light transmittance greater than that of the encapsulating layer. | 2022-06-23 |
20220199591 | LIGHT-EMITTING DEVICE PACKAGE AND ELECTRONIC DEVICE - Embodiments of the present disclosure relate to a light-emitting device package and an electronic device. In an embodiment, a light-emitting device package is provided that includes a lead frame, at least two light-emitting devices mounted on the lead frame and configured to emit different wavelengths of a same color of light, and a phosphor configured to emit light having a color different from the color of light emitted from the at least two light-emitting devices. The embodiments of the present disclosure also relate to an electronic device including the light-emitting device package as a light source. According to the embodiments of the present disclosure, various expressible color spaces can be selectively expressed. | 2022-06-23 |
20220199592 | LIGHT-EMITTING DIODE PACKAGING MODULE - A light-emitting diode (LED) packaging module includes light-emitting units arranged in an array having m row(s) and n column(s), an encapsulating layer, and a wiring assembly, where m and n each independently represents a positive integer. Each of the light-emitting units includes LED chips each including a chip first surface, a chip second surface, a chip side surface, and an electrode assembly disposed on the chip second surface. The encapsulating layer covers the chip side surface and fills a space among the LED chips. The wiring assembly is disposed on the chip second surface and is electrically connected to the electrode assembly. | 2022-06-23 |
20220199593 | SEMICONDUCTOR DEVICE WITH DUMMY THERMAL FEATURES ON INTERPOSER - A semiconductor device includes a bottom package, a top package stacked on the bottom package, and an interposer disposed between the bottom package and the top package. The top package is electrically connected to the interposer through a plurality of peripheral solder balls. At least a dummy thermal feature is disposed on the interposer and surrounded by the plurality of peripheral solder balls. | 2022-06-23 |
20220199594 | DISPLAY APPARATUS HAVING DISPLAY MODULE AND METHOD OF MANUFACTURING THE SAME - Provided is a display module including: a substrate including a mounting surface on which a plurality of inorganic light emitting diodes (LEDs) are mounted, a side surface, and a rear surface disposed opposite to the mounting surface; a front cover bonded to and covering the mounting surface; a metal plate bonded to the rear surface; and a side cover configured to surround the side surface, wherein the front cover extends to an area outside of the mounting surface in a first direction in which the mounting surface extends, and wherein the side cover is provided to extend, in a second direction in which the mounting surface faces, from an upper side of the metal plate to a lower end of a region of the front cover to seal the side surface from an outside. | 2022-06-23 |
20220199595 | INTEGRATED CIRCUIT PACKAGE HAVING A REDISTRIBUTION LAYER ABOVE A POWER MANAGEMENT INTEGRATED CIRCUIT - A packaged assembly for integrated circuits having a redistribution layer (RDL) above a power management integrated circuit (PMIC) die for vertical connectivity from the PMIC die to another component of the packaged assembly (e.g., a wireless communication module) and techniques for fabrication thereof. An exemplary packaged assembly for integrated circuits includes: a first RDL; a second RDL disposed below the first RDL; a PMIC die disposed between the first RDL and the second RDL; a first passive component disposed adjacent to the PMIC die and between the first RDL and the second RDL; and a second passive component, wherein a first terminal of the second passive component is coupled to the PMIC die via the first RDL, and wherein a second terminal of the second passive component is coupled to the first passive component via the first RDL. | 2022-06-23 |
20220199596 | DISPLAY AND MANUFACTURING METHOD THEREOF - The present invention is a display and manufacturing method thereof, including a thin film substrate, a plurality of packaging layers, and a stretch-resistant unit, wherein one side of the thin film substrate has a plurality of pixel areas, each pixel area contains at least one light-emitting element, and each packaging layer respectively covers one of the pixel areas to form an island-shape structure, and there is a spacing between any two adjacent island-shape structures, and each stretch-resistant unit deposed at the spacing and connects the adjacent island-shape structures. | 2022-06-23 |
20220199597 | DISPLAY DEVICE - A display device integrates a driver IC and a micro-LED into a micro-LED module to encapsulate the related circuitry together. The stretchable conductive material is disposed on the flexible substrate to effectively reduce the problem of rising resistances caused by stretching. Specifically, both the driver IC and the micro-LED are disposed on the substrate, or the driver IC is served as a substrate to carry the micro-LEDs to encapsulate into the micro-LED module. Then, the stretchable conductive material is utilized to dispose on the flexible substrate to form the display device adapted for non-plane surface. | 2022-06-23 |
20220199598 | DISPLAY DEVICE - A display device includes a first electrode extended in a first direction, a second electrode spaced apart from the first electrode in a second direction and extended in the first direction, a first insulating layer on the first and second electrodes, light-emitting elements on the first insulating layer, each having at least an end disposed on the first electrode or the second electrode, a second insulating layer disposed on the light-emitting elements and extended in the first direction, and a first connection electrode disposed on the first electrode and electrically contacting the light-emitting elements, a second connection electrode disposed on the second electrode and electrically contacting the light-emitting elements. Each of the first and second connection electrodes includes a main portion electrically contacting the light-emitting elements, and a subsidiary portion having a width smaller than a width of the main portion and electrically connected to the main portion. | 2022-06-23 |
20220199599 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A display device having a pad area and a display area is provided. The display device includes: a substrate; a pad structure on the substrate in the pad area; and a display element part on the substrate in the display area. The pad structure includes a first pad pattern, a second pad pattern on the first pad pattern, and a third pad pattern on the second pad pattern, and the display element part includes a light emitting element configured to emit light in a display direction. The second pad pattern has a first area and a second area, the second pad pattern and the third pad pattern do not contact each other in the first area, and the second pad pattern and the third pad pattern contact each other in the second area. | 2022-06-23 |
20220199600 | OPTICAL MULTICHIP PACKAGE WITH MULTIPLE SYSTEM-ON-CHIP DIES - Embodiments described herein may be related to apparatuses, processes, and techniques related to disaggregating co-packaged SOC and photonic integrated circuits on an multichip package. The photonic integrated circuits may also be silicon photonics engines. In embodiments, multiple SOCs and photonic integrated circuits may be electrically coupled, respectively, into modules, with multiple modules then incorporated into an MCP using a stacked die structure. Other embodiments may be described and/or claimed. | 2022-06-23 |
20220199601 | SEMICONDUCTOR DEVICE PACKAGES HAVING STACKED SEMICONDUCTOR DICE - Semiconductor device packages may include a bottom-most semiconductor die, at least one intermediate semiconductor die stacked over the bottom-most semiconductor die, and a top-most semiconductor die located on a side of a farthest intermediate semiconductor die from the bottom-most semiconductor die opposite the bottom-most semiconductor die. The bottom-most semiconductor die and each intermediate semiconductor die may include vias extending therethrough. The bottom-most semiconductor die may have a larger foot print than each intermediate semiconductor die and the top-most semiconductor die. A dielectric material may be located between each of the semiconductor dice, at least sections of the dielectric material extending contiguously from between adjacent semiconductor dice, over sidewalls thereof, and laterally beyond the lateral peripheries all but the bottom-most semiconductor die | 2022-06-23 |
20220199602 | DUAL COOL POWER MODULE WITH STRESS BUFFER LAYER - Described implementations provide wireless, surface mounting of at least two semiconductor die on die attach pads (DAPs) of the semiconductor package, where the at least two semiconductor die are electrically connected by a clip. A stress buffer layer may be provided on the clip, and a heatsink may be provided on the stress buffer layer. The heatsink may be secured with an external mold material. | 2022-06-23 |
20220199603 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor device includes a first interconnection including a first extending portion extending in a first direction, and a first curved portion curved with respect to the first extending portion. The device further includes a second interconnection including a second extending portion extending in the first direction and adjacent to the first extending portion in a second direction, and a second curved portion curved with respect to the second extending portion. The device further includes a first plug provided on the first curved portion, or on a first non-opposite portion included in the first extending portion and not opposite to the second extending portion in the second direction. The device further includes a second plug provided on the second curved portion, or on a second non-opposite portion included in the second extending portion and not opposite to the first extending portion in the second direction. | 2022-06-23 |
20220199604 | MULTI-CHIP STRUCTURE INCLUDING A MEMORY DIE STACKED ON DIE HAVING PROGRAMMABLE INTEGRATED CIRCUIT - Some examples described herein provide for a multi-chip structure including one or more memory dies stacked on a die having a programmable integrated circuit (IC). In an example, a multi-chip structure includes a package substrate, a first die, and a second die. The first die includes a programmable IC, and the programmable IC includes a memory controller. The first die is on and attached to the package substrate. The second die includes memory. The second die is stacked on the first die. The memory is communicatively coupled to the memory controller. | 2022-06-23 |
20220199605 | REPAIR TECHNIQUES FOR MICRO-LED DEVICES AND ARRAYS - What is disclosed are structures and methods for repairing emissive display systems. Various repairing techniques embodiments in accordance with the structures and methods are provided to conquer and mitigate the defected pixels and to increase the yield and reduce the cost of emissive displays systems. | 2022-06-23 |
20220199606 | Optical Systems Fabricated by Printing-Based Assembly - Provided are optical devices and systems fabricated, at least in part, via printing-based assembly and integration of device components. In specific embodiments the present invention provides light emitting systems, light collecting systems, light sensing systems and photovoltaic systems comprising printable semiconductor elements, including large area, high performance macroelectronic devices. Optical systems of the present invention comprise semiconductor elements assembled, organized and/or integrated with other device components via printing techniques that exhibit performance characteristics and functionality comparable to single crystalline semiconductor based devices fabricated using conventional high temperature processing methods. Optical systems of the present invention have device geometries and configurations, such as form factors, component densities, and component positions, accessed by printing that provide a range of useful device functionalities. Optical systems of the present invention include devices and device arrays exhibiting a range of useful physical and mechanical properties including flexibility, shapeability, conformability and stretchablity. | 2022-06-23 |
20220199607 | WAFER TRUST VIA LOCATION LOCKED CIRCUIT LAYOUT WITH MEASURABLE INTEGRITY - Techniques to determine whether the design of integrated circuit (IC) has been tampered with during wafer manufacturing by using an enhanced library and layout methodology. The enhanced library may include location sensitive cells networked together in a mesh architecture where paths through the mesh can be used to detect relative position of location sensitive cells. The techniques further include algorithms that fill any unused space on an IC with additional elements from the enhanced library to minimize the opportunity to modify the IC by including additional circuit function or manipulating the layout. By physically locking down the circuit placement such that there is no available area and gives improved ability to detect changes in the physical location behavior of the circuit, therefore reduces the risk that unauthorized circuit manipulation will go undetected. | 2022-06-23 |
20220199608 | INTEGRATED CIRCUIT WITH BACKSIDE POWER RAIL AND BACKSIDE INTERCONNECT - Disclosed embodiments herein relate to an integrated circuit including metal rails. In one aspect, the integrated circuit includes a first layer including a first metal rail and a second layer including a second metal rail, where the second layer is above the first layer along a first direction. In one aspect, the integrated circuit includes a third layer including an active region of a transistor, where the third layer is above the second layer along the first direction. In one aspect, the integrated circuit includes a fourth layer including a third metal rail, where the fourth layer is above the third layer along the first direction. In one aspect, the integrated circuit includes a fifth layer including a fourth metal rail, where the fifth layer is above the fourth layer along the first direction. | 2022-06-23 |
20220199609 | NOVEL ESD PROTECTION DECOUPLED FROM DIFFUSION - Embodiments disclosed herein include semiconductor devices with electrostatic discharge (ESD) protection of the transistor devices. In an embodiment, a semiconductor device comprises a semiconductor substrate, where a transistor device is provided on the semiconductor substrate. In an embodiment, the semiconductor device further comprises a stack of routing layers over the semiconductor substrate, and a diode in the stack of routing layers. In an embodiment, the diode is configured to provide electrostatic discharge (ESD) protection to the transistor device. | 2022-06-23 |
20220199610 | SUBSTRATE-LESS ELECTROSTATIC DISCHARGE (ESD) INTEGRATED CIRCUIT STRUCTURES - Substrate-less electrostatic discharge (ESD) integrated circuit structures, and methods of fabricating substrate-less electrostatic discharge (ESD) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin and a second fin protruding from a semiconductor pedestal. An N-type region is in the first and second fins. A P-type region is in the semiconductor pedestal. A P/N junction is between the N-type region and the P-type region, the P/N junction on or in the semiconductor pedestal. | 2022-06-23 |
20220199611 | INSULATED-GATE BIPOLAR TRANSISTOR WITH INTEGRATED SCHOTTKY BARRIER - In an example, an electronic device includes a first well having a first conductivity type within a semiconductor substrate and a second well having a second opposite conductivity type within the semiconductor substrate and touching the first well. The device further includes a third well having the first conductivity type within the second well. A metallic structure in direct contact with at least a portion of a surface of the third well thereby forms a Schottky barrier between the third well and the metallic structure. | 2022-06-23 |
20220199612 | SWITCH CHIP WITH BOND WIRES REPLACING TRACES IN A DIE - A switch chip includes a first switch device, a first ESD protection device and a second ESD protection device. The first switch device is electrically coupled between a first pad and a second pad. The first ESD protection device is electrically coupled to a third pad which is electrically coupled to the first pad by a first bond wire. The second ESD protection device is electrically coupled to a fourth pad which is electrically coupled to the second pad by a second bond wire. | 2022-06-23 |
20220199613 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a transistor and a capacitor. The transistor includes a first conductor and a second insulator over a first insulator; a third insulator over the first conductor and the second insulator; a fourth insulator over the third insulator; a first oxide over the fourth insulator; a second oxide and a third oxide over the first oxide; a second conductor in contact with a top surface of the third insulator, a side surface of the fourth insulator, a side surface of the first oxide, a side surface of the second oxide, and a top surface of the second oxide; a third conductor in contact with the top surface of the third insulator, a side surface of the fourth insulator, a side surface of the first oxide, a side surface of the third oxide, and a top surface of the third oxide; a fourth oxide over the first oxide; a fifth insulator over the fourth oxide; and a fourth conductor over the fifth insulator. The capacitor includes a fifth conductor over the first insulator, the third insulator over the fifth conductor, and the second conductor over the third insulator. | 2022-06-23 |
20220199614 | RC IGBT and Method of Producing an RC IGBT - An RC IGBT includes an IGBT section and a diode section. At least some of a plurality of diode mesas in the diode section are coupled to the drift region via a second anode region electrically connected to the emitter terminal of the RC IGBT. The second anode region extends deeper along the vertical direction as compared to trenches in the diode section. | 2022-06-23 |
20220199615 | SUBSTRATE-LESS VERTICAL DIODE INTEGRATED CIRCUIT STRUCTURES - Substrate-less vertical diode integrated circuit structures, and methods of fabricating substrate-less vertical diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a semiconductor fin in a dielectric layer, the semiconductor fin having a top and a bottom, and the dielectric layer having a top surface and a bottom surface. A first epitaxial semiconductor structure is on the top of the semiconductor fin. A second epitaxial semiconductor structure is on the bottom of the semiconductor fin. A first conductive contact is on the first epitaxial semiconductor structure. A second conductive contact is on the second epitaxial semiconductor structure. | 2022-06-23 |
20220199616 | SEMICONDUCTOR DEVICES - A semiconductor device includes a substrate including a boundary region between first and second regions, first active patterns on the first region, second active patterns on the second region, and an isolation insulating pattern on the boundary region between the first and second active patterns. A width of at least some of the first active patterns have different widths. Widths of the second active patterns may be equal to each other. A bottom surface of the isolation insulating pattern includes a first bottom surface adjacent to a corresponding first active pattern, a second bottom surface adjacent to a corresponding second active pattern, and a third bottom surface between the first bottom surface and the second bottom surface. The third bottom surface is located at a different height from those of the first and second bottom surfaces with respect to a bottom surface of the substrate. | 2022-06-23 |
20220199617 | METAL OXIDE SEMICONDUCTOR DEVICE AND METHOD OF CONSTRUCTION THEREFOR - A metal oxide semiconductor, MOS, device ( | 2022-06-23 |
20220199618 | INTEGRATED CIRCUIT DEVICE - An integrated circuit (IC) device includes a fin-type active region extending longitudinally in a first lateral direction on a substrate. A nanosheet is apart from a fin top surface of the fin-type active region in a vertical direction. An inner insulating spacer is between the substrate and the nanosheet. A gate line includes a main gate portion and a sub-gate portion. The main gate portion extends longitudinally in a second lateral direction on the nanosheet. The sub-gate portion is integrally connected to the main gate portion and between the substrate and the nanosheet. A source/drain region is in contact with the inner insulating spacer and the nanosheet. The source/drain region includes a single crystalline semiconductor body and at least one lower stacking fault surface linearly extending from the inner insulating spacer through the single crystalline semiconductor body. | 2022-06-23 |
20220199619 | GATE DIELECTRICS FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTORS TRANSISTORS AND METHODS OF FABRICATION - A complementary metal oxide semiconductor (CMOS) transistor includes a first transistor with a first gate dielectric layer above a first channel, where the first gate dielectric layer includes Hf | 2022-06-23 |
20220199620 | RIBBON OR WIRE TRANSISTOR STACK WITH SELECTIVE DIPOLE THRESHOLD VOLTAGE SHIFTER - Integrated circuitry comprising a ribbon or wire (RoW) transistor stack within which the transistors have different threshold voltages (V | 2022-06-23 |
20220199621 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a first word line extending in a vertical direction; a second word line spaced apart from the first word line in a first horizontal direction and extending in the vertical direction; a first semiconductor pattern of a ring-shaped horizontal cross-section surrounding the first word line and constituting a portion of a first cell transistor; a second semiconductor pattern of a ring-shaped horizontal cross-section surrounding the second word line and constituting a portion of a second cell transistor; a cell capacitor between the first semiconductor pattern and the second semiconductor pattern and including a first electrode, a second electrode, and a capacitor dielectric film; a first bit line opposite the cell capacitor with respect to the first semiconductor pattern and extending in a second horizontal direction; and a second bit line opposite the cell capacitor with respect to the second semiconductor pattern. | 2022-06-23 |
20220199622 | RESISTIVE MEMORY CELL AND ASSOCIATED CELL ARRAY STRUCTURE - A cell array structure includes a first resistive memory cell. The first resistive memory cell includes a well region, a first doped region, a merged region, a first gate structure, a second gate structure and a first metal layer. The first doped region is formed under a surface of the well region. The merged region is formed under the surface of the well region. The first gate structure is formed over the surface of the well region between the first doped region and the merged region. The first gate structure includes a first insulation layer and a first conductive layer. The second gate structure is formed over the merged region. The second gate structure includes a second insulation layer and a second conductive layer. The first metal layer is connected with the first doped region. | 2022-06-23 |
20220199623 | METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE WITH CAPACITOR LANDING PAD - The present disclosure provides a method for manufacturing a semiconductor structure with capacitor landing pads. The method includes the following operations: providing a semiconductor substrate; forming a bit line structure protruding from the semiconductor substrate; depositing a landing pad layer to cover the bit line structure; planarizing a top surface of the landing pad layer; limning a trench in the landing pad layer to form the capacitor landing pads; forming an air gap within a sidewall of the bit line structure; and filling a first dielectric layer in the trench to seal the air gap. | 2022-06-23 |
20220199624 | ARRAYS OF DOUBLE-SIDED DRAM CELLS INCLUDING CAPACITORS ON THE FRONTSIDE AND BACKSIDE OF A STACKED TRANSISTOR STRUCTURE - Monolithic two-dimensional (2D) arrays of double-sided DRAM cells including a frontside bit cell over a backside bit cell. Each double-sided cell includes a stacked transistor structure having at least a first transistor over a second transistor. Each double-sided cell further includes a first capacitor on a frontside of the stacked transistor structure and electrically coupled to a source/drain of the first transistor. Each double-sided cell further includes a second capacitor on a backside of the stacked transistor structure and electrically coupled to a source/drain of the second transistor. Frontside cell addressing interconnects are electrically coupled to other terminals of at least the first transistor while one or more backside addressing interconnects are electrically coupled to at least one terminal of the second transistor or second capacitor. | 2022-06-23 |
20220199625 | SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - A semiconductor memory device in which performance and reliability are improved, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line extending in a first direction on a substrate, an interlayer insulation film that includes a cell trench extending in a second direction intersecting the first direction, on the substrate, a first gate electrode and a second gate electrode that are spaced apart from each other in the first direction and each extend in the second direction, inside the cell trench, a channel layer that is inside the cell trench and is electrically connected to the conductive line, on the first gate electrode and the second gate electrode, and a gate insulation layer interposed between the first gate electrode and the channel layer, and between the second gate electrode and the channel layer. | 2022-06-23 |
20220199626 | VERTICAL NON-VOLATILE MEMORY DEVICES HAVING A MULTI-STACK STRUCTURE WITH ENHANCED PHOTOLITHOGRAPHIC ALIGNMENT CHARACTERISTICS - A vertical-type nonvolatile memory device has a multi-stack structure with reduced susceptibility to mis-alignment of a vertical channel layer. This nonvolatile memory device includes: (i) a main chip area including a cell area and an extension area arranged to have a stepped structure, with the cell area and the extension area formed in a multi-stack structure, and (ii) an outer chip area, which surrounds the main chip area and includes a step key therein. The main chip area includes a first layer on a substrate and a second layer on the first layer. A lower vertical channel layer is arranged in the first layer. The step key includes an alignment vertical channel layer, and a top surface of the alignment vertical channel layer is lower than a top surface of the lower vertical channel layer. | 2022-06-23 |
20220199627 | REPLACEMENT CHANNEL PROCESS FOR THREE-DIMENSIONAL DYNAMIC RANDOM ACCESS MEMORY - Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) devices and replacement channel processes for fabricating 3D DRAM devices. In an example, a gate dielectric layer is formed on a sacrificial material, and a gate electrode is formed on the gate dielectric layer. After the gate electrode is formed, the sacrificial material is removed and replaced by a semiconductor material. A channel region of a device (e.g., a transistor) that includes the gate dielectric layer and gate electrode is formed in the semiconductor material. The channel region can be vertical or horizontal with respect to a main surface of a substrate on which the device is formed. A capacitor can be formed, such as before or after the semiconductor material is formed, and is electrically connected to the semiconductor material. The device and the capacitor together can form at least part of a 3D DRAM cell. | 2022-06-23 |
20220199628 | THIN FILM TRANSISTORS HAVING A BACKSIDE CHANNEL CONTACT FOR HIGH DENSITY MEMORY - An integrated circuit (IC) structure in a memory device is described. In an example, the IC structure includes a memory cell including a bitline (BL) extending along a first direction and a channel extending along a second direction above and diagonal to the BL. In the example, a wordline (WL) extends in a third direction perpendicular to the first direction of the BL and intersects with the channel to control a current in the channel along a gated channel length. In some examples, the channel is electrically coupled on a first side to a storage capacitor via a storage node contact (SNC) and on a second side to the BL via a bit line contact (BLC) located on an underside or backside of the channel. | 2022-06-23 |
20220199629 | Multi-Transistor Stack Bitcell Architecture - Various implementations described herein are related to a device having multiple transistors in a single stack arranged as a cross-coupled bitcell latch. Also, the multiple transistors may be disposed in a multi-transistor stack configuration that is formed within a single monolithic semiconductor die. In some implementations, the multiple transistors may be arranged as a bitcell for single-port memory applications. | 2022-06-23 |
20220199630 | MEMORY DEVICE AND SRAM CELL - A device includes a first horizontal-gate-all-around (HGAA) transistor, a second HGAA transistor, a first vertical-gate-all-around (VGAA) transistor, and a second VGAA transistor. The first HGAA transistor and the second HGAA transistor are adjacent to each other. The first VGAA transistor is over the first HGAA transistor. The second VGAA transistor is over the second HGAA transistor. A top surface of the first VGAA transistor is substantially coplanar with a top surface of the second VGAA transistor. | 2022-06-23 |
20220199631 | FERROELECTRIC SEMICONDUCTING FLOATING GATE FIELD-EFFECT TRANSISTOR - Non-volatile memory devices utilizing polarizable ferroelectric-semiconductor materials as the floating gate in floating-gate field-effect metal oxide transistors are described. Such materials can be annealed at temperatures less than 450° C., and fields below about 250 kV/cm can be used for changing polarization of the ferroelectric semiconductor materials, leading to devices capable of high endurance (>10 | 2022-06-23 |
20220199632 | READ ONLY MEMORY - The present description concerns a ROM including at least one first rewritable memory cell. | 2022-06-23 |
20220199633 | INTEGRATION OF A FERROELECTRIC MEMORY DEVICE WITH A TRANSISTOR - Approaches for integrating FE memory arrays into a processor, and the resulting structures are described. Simultaneous integrations of regions with ferroelectric (FE) cells and regions with standard interconnects are also described. FE cells include FE capacitors that include a FE stack of layers, which is encapsulated with a protection material. The protection material protects the FE stack of layers as structures for regular logic are fabricated in the same die. | 2022-06-23 |
20220199634 | Methods of Forming Structures Containing Leaker-Devices and Memory Configurations Incorporating Leaker-Devices - Some embodiments include an integrated assembly having first electrodes with top surfaces, and with sidewall surfaces extending downwardly from the top surfaces. The first electrodes are solid pillars. Insulative material is along the sidewall surfaces of the first electrodes. Second electrodes extend along the sidewall surfaces of the first electrodes and are spaced from the sidewall surfaces by the insulative material. Conductive-plate-material extends across the first and second electrodes, and couples the second electrodes to one another. Leaker-devices electrically couple the first electrodes to the conductive-plate-material and are configured to discharge at least a portion of excess charge from the first electrodes to the conductive-plate-material. Some embodiments include methods of forming integrated assemblies. | 2022-06-23 |
20220199635 | PLATE LINE ARCHITECTURES FOR 3D-FERROELECTRIC RANDOM ACCESS MEMORY (3D-FRAM) - Plate line architectures for 3D-Ferroelectric Random Access Memory (3D-FRAM) are described. In an example, a memory device includes a plurality of bitlines along a first direction and a plurality of wordlines along a second direction orthogonal to the first direction. An access transistor is at an intersection of a first one of the bitlines and a first one of the wordlines. A series of alternating plate lines and insulating material are fabricated over the access transistor. Two or more ferroelectric capacitors are over the access transistor and through the series of alternating plate lines and an insulating material such that a first one of the ferroelectric capacitors is coupled to a first one of the plate lines and a second one of the ferroelectric capacitors is coupled to a second one of the plate lines, and wherein the two or more ferroelectric capacitors are each coupled to and controlled by the access transistor. | 2022-06-23 |
20220199636 | Improving Surface Topography by Forming Spacer-Like Components - A wafer having a first region and a second region is provided. A first topography variation exists between the first region and the second region. A first layer is formed over the first region and over the second region of the wafer. The first layer is patterned. A patterned first layer causes a second topography variation to exist between the first region and the second region. The second topography variation is smoother than the first topography variation. A second layer is formed over the first region and the second region. At least a portion of the second layer is formed over the patterned first layer. | 2022-06-23 |
20220199637 | METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS - A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive material and insulative material arranged in tiers. The stack structure has blocks separated from one another by first dielectric slot structures. Each of the blocks comprises two crest regions, a stadium structure interposed between the two crest regions in a first horizontal direction and comprising opposing staircase structures each having steps comprising edges of the tiers of the stack structure, and two bridge regions neighboring opposing sides of the stadium structure in a second horizontal direction orthogonal to the first horizontal direction and having upper surfaces substantially coplanar with upper surfaces of the two crest regions. At least one second dielectric slot structure is within horizontal boundaries of the stadium structure in the first horizontal direction and partially vertically extends through and segmenting each of the two bridge regions. Memory devices, electronic systems, and methods of forming microelectronic devices are also described. | 2022-06-23 |
20220199638 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a stacked layer body including a first stacked portion in which first conductive layers are stacked, and which includes a stair-like first end, and a second stacked portion which is provided on an upper layer side of the first stacked portion, in which second conductive layers are stacked, and which includes a stair-like second end, a first stopper insulating layer covering at least a part of the first end, a second stopper insulating layer including a cover portion covering the second end and an extension portion extending from the cover portion, and a first contact penetrating through the extension portion and being connected to a corresponding one of the first conductive layers. | 2022-06-23 |
20220199639 | THREE-DIMENSIONAL MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present disclosure provides a three-dimensional memory device and a method for manufacturing the same. The three-dimensional memory device includes a plurality of tiles, and each tiles includes a plurality of blocks, and each blocks includes a gate stacked structure, a conductive layer, first ring-shaped channel pillars, source/drain pillars, and charge storage structures. The gate stacked structure is disposed on the substrate and includes gate layers electrically insulated from each other. The conductive layer is disposed between the substrate and the gate stacked structure. The first ring-shaped channel pillars are disposed on the substrate and located in the gate stacked structure. The source/drain pillars are disposed on the substrate, and each of the first ring-shaped channel pillars are configured with two source/drain pillars disposed therein. Each of the charge storage structures is disposed between the corresponding gate layer and the corresponding first ring-shaped channel pillar. The conductive layer in one of the tiles is isolated from the conductive layers in the other tiles. | 2022-06-23 |
20220199640 | Integrated Assemblies, and Methods of Forming Integrated Assemblies - Some embodiments include an integrated assembly having a first memory region, a second memory region, and an intermediate region between the first and second memory regions. The intermediate region has a first edge proximate the first memory region and has a second edge proximate the second memory region. Channel-material-pillars are arranged within the first and second memory regions. Conductive posts are arranged within the intermediate region. Doped-semiconductor-material is within the intermediate region and is configured as a substantially H-shaped structure having a first leg region along the first edge, a second leg region along the second edge, and a belt region adjacent the panel. Some embodiments include methods of forming integrated assemblies. | 2022-06-23 |
20220199641 | MICROELECTRONIC DEVICES INCLUDING TIERED STACKS INCLUDING CONDUCTIVE STRUCTURES ISOLATED BY SLOT STRUCTURES, AND RELATED ELECTRONIC SYSTEMS AND METHODS - A microelectronic device comprises a stack structure comprising a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, strings of memory cells vertically extending through the block structures of the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, an additional stack structure vertically overlying the stack structure and comprising a vertical sequence of additional conductive structures and additional insulative structures arranged in additional tiers, first pillars extending through the additional stack structure and vertically overlying the strings of memory cells, each of the first pillars horizontally offset from a center of a corresponding string of memory cells, second pillars extending through the additional stack structure and vertically overlying the strings of memory cells, and additional slot structures comprising a dielectric material extending through at least a portion of the additional stack structure and sub-dividing each of the block structures into sub-block structures, the additional slot structures horizontally neighboring the first pillars. Related microelectronic devices, electronic systems, and methods are also described. | 2022-06-23 |
20220199642 | VERTICAL TYPE SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A vertical type semiconductor device includes a substrate that has a plurality of trenches, a support pattern that fills the plurality of trenches and protrudes from a top surface of the substrate, a semiconductor layer disposed on the substrate that fills a space between the support patterns, a stacked structure disposed on the support pattern and the semiconductor layer that includes a plurality of insulation layers and a plurality of first conducive patterns that are alternately and repeatedly stacked, and a plurality of channel structures that penetrate through the structure and the semiconductor layer and that extend into the support pattern. Each channel structure includes a channel layer. At least a portion of the channel layer makes contact with the semiconductor layer. | 2022-06-23 |
20220199643 | 3-DIMENSIONAL NOR MEMORY ARRAY ARCHITECTURE AND METHODS FOR FABRICATION THEREOF - A method addresses low cost, low resistance metal interconnects and mechanical stability in a high aspect ratio structure. According to the various implementations disclosed herein, a replacement metal process, which defers the need for a metal etching step in the fabrication process until after all patterned photoresist is no longer present. Under this process, the conductive sublayers may be both thick and numerous. The present invention also provides for a strut structure which facilitates etching steps on high aspect ratio structures, which enhances mechanical stability in a high aspect ratio memory stack. | 2022-06-23 |
20220199644 | Foundational Supports within Integrated Assemblies - Some embodiments include an integrated assembly having a base (e.g., a monocrystalline silicon wafer), and having memory cells over the base and along channel-material-pillars. A conductive structure is between the memory cells and the base. The channel-material-pillars are coupled with the conductive structure. A foundational structure extends into the base and projects upwardly to a level above the conductive structure. The foundational structure locks the conductive structure to the base to provide foundational support to the conductive structure. | 2022-06-23 |
20220199645 | Memory Arrays, and Methods of Forming Memory Arrays - Some embodiments include a method of forming an assembly (e.g., a memory array). A first opening is formed through a stack of alternating first and second levels. The first levels contain silicon nitride, and the second levels contain silicon dioxide. Some of the silicon dioxide of the second levels is replaced with memory cell structures. The memory cell structures include charge-storage regions adjacent charge-blocking regions. Tunneling material is formed within the first opening, and channel material is formed adjacent the tunneling material. A second opening is formed through the stack. The second opening extends through remaining portions of the silicon dioxide, and through the silicon nitride. The remaining portions of the silicon dioxide are removed to form cavities. Conductive regions are formed within the cavities. The silicon nitride is removed to form voids between the conductive regions. Some embodiments include memory arrays. | 2022-06-23 |
20220199646 | Integrated Assemblies Comprising Conductive Levels Having Two Different Metal-Containing Structures Laterally Adjacent One Another, and Methods of Forming Integrated Assemblies - Some embodiments include a memory device having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include first regions, and include second regions laterally adjacent to the first regions. The first regions have a first vertical thickness and at least two different metal-containing materials along the first vertical thickness. The second regions have a second vertical thickness at least as large as the first vertical thickness, and have only a single metal-containing material along the second vertical thickness. Dielectric-barrier material is laterally adjacent to the first regions. Charge-blocking material is laterally adjacent to the dielectric-barrier material. Charge-storage material is laterally adjacent to the charge-blocking material. Dielectric material is laterally adjacent to the charge storage material. Channel material is laterally adjacent to the dielectric material. | 2022-06-23 |
20220199647 | VERTICAL MEMORY DEVICE - A vertical memory device includes a gate line structure including a cell region in which a vertical channel structure is formed, and a first connection region and a second connection region which are respectively arranged at first and second ends of the cell region in a first direction. Each of the first connection region and the second connection region includes a first protrusion of the first gate line and a second protrusion of the second gate line which are parallel to a top surface of the substrate and arranged as steps in a second direction perpendicular to the first direction. The first protrusion of the second connection region is arranged diagonally from the first protrusion of the first connection region with respect to a center line of the cell region which is parallel to the first direction. | 2022-06-23 |
20220199648 | SET OF INTEGRATED STANDARD CELLS - An integrated circuit includes at least a first standard cell framed by two second standard cells. The three cells are disposed adjacent to each other, and each standard cell includes at least one NMOS transistor and at least one least one PMOS transistor located in and on a silicon-on-insulator substrate. The at least one PMOS transistor of the first standard cell has a channel including silicon and germanium. The at least one PMOS transistor of each second standard cell has a silicon channel and a threshold voltage different in absolute value from the threshold voltage of said at least one PMOS transistor of the first cell. | 2022-06-23 |
20220199649 | ARRAY SUBSTRATE AND DISPLAY PANEL - The present application provides an array substrate and a display panel. The array substrate includes fan-out regions and an inverted region formed between two adjacent fan-out regions. The array substrate includes metal lines and floating metal lines. The metal lines include first metal lines in the fan-out region and second metal lines in the inverted triangle region. The floating metal lines include a first floating metal line arranged between the first metal lines and the second metal lines. The array substrate includes an alignment film arranged on the metal lines and the floating metal lines. | 2022-06-23 |
20220199650 | ARRAY SUBSTRATE, DISPLAY APPARATUS, AND METHOD OF FABRICATING ARRAY SUBSTRATE - An array substrate including a display area having a plurality of subpixels is provided. The plurality of subpixels includes a plurality of first subpixels in a display-bonding sub-area and a plurality of second subpixels in a regular display sub-area. The array substrate includes a plurality of thin film transistors on a first side of the base substrate and respectively in the plurality of subpixels. A respective one of the plurality of first subpixels includes a bonding pad on a second side of a base substrate; a lead line electrically connecting a respective one of a plurality of thin film transistors to the bonding pad; and a via extending through the base substrate. The lead line is unexposed in the array substrate. The lead line extends from the first side to the second side of the base substrate through the via, to connect to the bonding pad. | 2022-06-23 |
20220199651 | DISPLAY PANEL AND CRACK DETECTION METHOD, AND DISPLAY DEVICE - A display panel, a crack detection method and a display device are provided. The display panel includes a substrate, a signal wiring disposed over the substrate, and a test wiring insulated from the signal wiring and disposed on a side of the signal wiring facing away from the substrate. An orthographic projection of the test wiring on the substrate overlaps an orthographic projection of the signal wiring on the substrate. The display panel also includes a first test terminal disposed over the substrate and electrically connected with an end of the test wiring, and a second test terminal disposed over the substrate and electrically connected with another end of the test wiring. | 2022-06-23 |
20220199652 | DISPLAY SUBSTRATE AND DISPLAY DEVICE - The display substrate includes a substrate, multiple sub-pixels, multiple data lines, multiple power lines, multiple data signal input lines, multiple selector switches, a first power bus located in a peripheral area and on a side, facing away from the display area, of the multiple selector switches, and multiple power connection cables located in the peripheral area and between the first power bus and the multiple power lines. The multiple power connection cables are electrically connected with the first power bus and the multiple power lines. | 2022-06-23 |
20220199653 | SEMICONDUCTOR DEVICE AND WIRELESS COMMUNICATION DEVICE WITH THE SEMICONDUCTOR DEVICE - A semiconductor device with a novel structure is provided. The semiconductor device includes an oscillation circuit including a first coil, a second coil, a first capacitor, a second capacitor, a first transistor, and a second transistor and a frequency correction circuit including a third capacitor, a fourth capacitor, a third transistor, a fourth transistor, and a switching circuit. The switching circuit has a function of controlling a conduction state or a non-conduction state of the third transistor and the fourth transistor. The frequency correction circuit is provided above the oscillation circuit and has a function of adjusting an oscillation frequency of the oscillation circuit. The first transistor and the second transistor each include a semiconductor layer containing silicon in a channel formation region. The third transistor and the fourth transistor each include a semiconductor layer containing an oxide semiconductor in a channel formation region. | 2022-06-23 |
20220199654 | LIQUID CRYSTAL DISPLAY DEVICE AND ELECTRONIC DEVICE - To reduce power consumption and suppress display degradation of a liquid crystal display device. To suppress display degradation due to an external factor such as temperature. A transistor whose channel formation region is formed using an oxide semiconductor layer is used for a transistor provided in each pixel. Note that with the use of a high-purity oxide semiconductor layer, off-state current of the transistor at a room temperature can be 10 aA/μm or less and off-state current at 85° C. can be 100 aA/μm or less. Consequently, power consumption of a liquid crystal display device can be reduced and display degradation can be suppressed. Further, as described above, off-state current of the transistor at a temperature as high as 85° C. can be 100 aA/μm or less. Thus, display degradation of a liquid crystal display device due to an external factor such as temperature can be suppressed. | 2022-06-23 |
20220199655 | LIGHT EMITTING DISPLAY APPARATUS - A light emitting display apparatus is provided, which may repair an opened gate line using power supply lines. The light emitting display apparatus comprises a gate line provided along a first direction of a light emitting display panel, a voltage supply line provided in the light emitting display panel along a second direction different from the first direction, at least three pixels provided between two adjacent voltage supply lines and connected to the gate line, a first branch voltage supply line extended from a first voltage supply line of the two voltage supply lines along the first direction and connected to at least one pixel adjacent to the first voltage supply line among the at least three pixels, and a second branch voltage supply line extended from a second voltage supply line of the two voltage supply lines along the first direction and connected with at least one pixel adjacent to the second voltage supply line among the at least three pixels, wherein an end of the first branch voltage supply line and an end of the second branch voltage supply line are adjacent to each other. | 2022-06-23 |
20220199656 | DISPLAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE - The present disclosure provides a display substrate, a manufacturing method thereof and a display device. The display substrate includes a base substrate and a plurality of subpixels arranged in an array form on the base substrate. Each subpixel includes a voltage stabilizing electrode, and a subpixel driving circuitry including a driving transistor, and a first transistor, a first electrode of which is coupled to a second electrode of the driving transistor, and a second electrode of which is coupled to a gate electrode of the driving transistor. An active layer of the first transistor includes a first semiconductor portion and a second semiconductor portion spaced apart from each other, and a conductor portion coupled to thereto. An orthogonal projection of the conductor portion onto the base substrate overlaps an orthogonal projection of voltage stabilizing electrode of a previous subpixel in the first direction onto the base substrate. | 2022-06-23 |
20220199657 | DISPLAY DEVICE - A display device includes: a first gate insulating film; a first interlayer insulating film; a lower metal layer; an oxide semiconductor layer; a second gate insulating film; a second gate electrode; a second interlayer insulating film; and an upper metal layer being sequentially provided on a substrate, wherein the oxide semiconductor layer includes a second channel region and a second conductor region, the second gate insulating film is disposed in alignment with the second gate electrode, a first contact hole is provided in the first gate insulating film and the first interlayer insulating film, the lower metal layer includes a second conductor connection wiring line, a protection layer having an island shape is provided between the second conductor region and the second interlayer insulating film, a second contact hole exposing the second conductor connection wiring line is provided in the protection layer and the second interlayer insulating film. | 2022-06-23 |
20220199658 | SEMICONDUCTOR SUBSTRATE WITH PASSIVATED FULL DEEP-TRENCH ISOLATION AND ASSOCIATED METHODS OF MANUFACTURE - An image sensor with passivated full deep-trench isolation includes a semiconductor substrate, the substrate including a plurality of sidewalls that form a plurality of trenches that separates pixels of a pixel array, and a passivation layer lining the plurality of sidewall surfaces and the back surface of the semiconductor substrate. A method for forming an image sensor with passivated full deep-trench isolation includes forming trenches in a semiconductor substrate, filling the trenches with a sacrificial material, forming a plurality of photodiode regions, forming a circuit layer, thinning the semiconductor substrate, and removing the sacrificial material. A method for reducing noise in an image sensor includes removing material from a semiconductor substrate to form a plurality of trenches that extend from a front surface toward a back surface, and depositing a dielectric material onto the back surface and into the plurality of trenches through a back opening of each trench. | 2022-06-23 |
20220199659 | METHOD FOR MAKING ISOLATION REGION OF CIS DEVICE, AND SEMICONDUCTOR DEVICE STRUCTURE - A method for making an isolation region of a CIS device includes: forming a block layer on a substrate, below the block layer being an oxide layer, below the oxide layer being a silicon nitride layer, and a shallow trench isolation being formed in the substrate; forming a hard mask layer on the surface of the block layer, the material of the hard mask layer is oxide; performing a photolithography process and an etching process to form an isolation region pattern in the hard mask layer; performing an ion implantation process to form an isolation region in the substrate corresponding to the isolation region pattern. | 2022-06-23 |
20220199660 | PIXEL GROUP AND PIXEL ARRAY OF IMAGE SENSOR - A pixel group of an image sensor includes first through fourth unit pixels in a matrix form of two pixels rows and two pixel columns, and a common floating diffusion region in a semiconductor substrate at a center of the pixel group and shared by the first through fourth unit pixels. Each of the first through fourth unit pixels includes a photoelectric conversion element in the semiconductor substrate, and a pair of vertical transfer gates in the semiconductor substrate and extending in a vertical direction perpendicular to a surface of the semiconductor substrate. The pair of vertical transfer gates transfer photo charges collected by the photoelectric conversion element to the common floating diffusion region. Image quality is enhanced by increasing sensing sensitivity of the unit pixel through the shared structure of the floating diffusion region and the symmetric structure of the vertical transfer gates. | 2022-06-23 |
20220199661 | SEMICONDUCTOR IMAGE SENSOR - The semiconductor image sensor of the present invention comprises a light receiving element formed in a silicon substrate under an insulation film of an SOI substrate comprising the silicon substrate, the insulation film formed on the silicon substrate, and a semiconductor layer formed on the insulation film, and composed of a pn junction diode formed in a vertical direction to a main surface of the silicon substrate and having sensitivity to near-infrared light, and a high voltage generating circuit configured to generate an applied voltage for applying a reverse bias voltage to the pn junction diode, and an impurity concentration of the silicon substrate is in a range of 1×10 | 2022-06-23 |
20220199662 | IMAGE SENSOR AND METHOD OF FABRICATING THE SAME - Disclosed are image sensors and methods of fabricating the same. The image sensor includes a semiconductor substrate including a pixel zone and a pad zone and having a first surface and a second surface opposing each other, a first pad separation pattern on the pad zone and extending from the first surface of the semiconductor substrate toward the second surface of the semiconductor substrate, a second pad separation pattern extending from the second surface toward the first surface of the semiconductor substrate on the pad zone the second pad and in contact with the first pad separation pattern, and a pixel separation pattern on the pixel zone and extending from the second surface of the semiconductor substrate toward the first surface of the semiconductor substrate. | 2022-06-23 |
20220199663 | SADDLE-GATE SOURCE FOLLOWER FOR IMAGING PIXELS - A saddle-gate source follower transistor is described, such as for integration with in-pixel circuitry of complementary metal-oxide semiconductor (CMOS) image sensor (CIS) pixels. The saddle-gate source-follower transistor structure can include a channel region having a three-dimensional geometry defined on its axial sides by trenches. A gate oxide layer is formed over the top and axial sides of the channel region, and a saddle-gate structure is formed on the gate oxide layer. As such, the saddle-gate structure includes a seat portion extending over the top of the channel region, and first and second fender portions extending over the first and second axial sides of the channel region, such that the first and second fender portions are buried below an upper surface of the semiconductor substrate (e.g., buried into trenches formed in side isolation regions). | 2022-06-23 |
20220199664 | IMAGE SENSORS - An image sensor for securing an area of a photodiode includes a pixel area and a transistor area adjacent to the pixel area. The pixel area may include a photodiode and a floating diffusion area. The transistor area may include transistors extending along an edge of the pixel area. The transistors in the transistor area may include a reset transistor, one or more source follower transistors, and one or more selection transistors, and the reset transistor and one source follower transistor adjacent to the reset transistor may share a common drain area. The source follower transistors and the selection transistors may each share a common source area or a common drain area between two adjacent transistors thereof. | 2022-06-23 |
20220199665 | FABRICATION PROCESS OF VERTICAL-CHANNEL, SILICON, FIELD-EFFECT TRANSISTORS - A method of fabricating transistors with a vertical gate in trenches includes lithographing to form wide trenches; forming dielectric in the trenches and filling the trenches with flowable material; and lithography to form narrow trenches within the wide trenches thereby exposing well or substrate before epitaxially growing semiconductor strips atop substrate exposed by the narrow trenches; removing the flowable material; growing gate oxide on the semiconductor strip; forming gate conductor over the gate oxide and into gaps between the epitaxially-grown semiconductor strips and the dielectric; masking and etching the gate conductor; and implanting source and drain regions. The transistors formed have semiconductor strips extending from a source region to a drain region, the semiconductor strips within trenches, the trench walls insulated with a dielectric, a gate oxide formed on both vertical walls of the semiconductor strip; and gate material between the dielectric and gate oxide. | 2022-06-23 |
20220199666 | HIGHLY INTEGRATED TRANSMITTER MODULE FOR LIDAR - Embodiments of the disclosure provide an optical sensing system, an integrated transmitter module for the optical sensing system, and an optical sensing method performed using the optical sensing system. The exemplary optical sensing system includes an integrated transmitter module configured to emit an optical signal into an environment surrounding the optical sensing system. The integrated transmitter module includes a laser emitter, one or more driving integrated circuits, and one or more optics integrated into a chamber that is hermetically sealed. The optical sensing system further includes a photodetector configured to receive the optical signal reflected from the environment and convert the received optical signal to an electrical signal. The optical sensing system additionally includes a readout circuit configured to convert the electrical signal to a digital signal. The photodetector and the readout circuit are located outside the chamber enclosing the integrated transmitter module. | 2022-06-23 |
20220199667 | IMAGE SENSING DEVICE - An image sensing device includes a plurality of image pixels, phase detection pixels, a first grid structure, and a second grid structure. The image pixels perform conversion of incident light received through at least one first color filter so as to generate image signals indicative of a target object to be captured. The phase detection pixels perform conversion of incident light received through a second color filter so as to generate a phase signal for calculating a phase difference between images formed by the image signals. The first grid structure is disposed between any two of the first color filters and between any one of the first color filters and any one of the second color filters. The second grid structure is located adjacent to the first grid structure and disposed between any one of the first color filters and any one of the second color filter. | 2022-06-23 |
20220199668 | SOLID-STATE IMAGING DEVICE - The present technology relates to a solid-state imaging device capable of increasing sensitivity while reducing color mixing degradation. A solid-state imaging device includes: a substrate; a plurality of photoelectric conversion regions formed in the substrate; a trench that is formed between the photoelectric conversion regions, and penetrates the substrate; and a recessed region that includes a plurality of concave portions, and is provided above the photoelectric conversion regions and on the side of the light receiving surface of the substrate, in which the substrate includes a III-V semiconductor or polycrystalline SiXGe (1-x) (x=0 to 1). The recessed region is also provided below the photoelectric conversion regions and on the side of a surface of the substrate, the surface facing the light receiving surface. The present technology can be applied to back-illuminated solid-state imaging devices and the like, for example. | 2022-06-23 |
20220199669 | IMAGE SENSING DEVICE - An image sensing device is provided to include a substrate including a first surface and a second surface, a color filter formed over the first surface, a photoelectric conversion element formed in the substrate and arranged to correspond to the color filter, and one or more polarizers formed between the first surface and the photoelectric conversion element and embedded in the substrate. The one or more polarizers are configured to transmit light of polarization oriented in a specific direction and block light of polarization oriented in other directions than the specific direction. | 2022-06-23 |
20220199670 | IMAGE SENSOR - An image sensor includes a sensor chip and a logic chip. The sensor chip includes a first substrate, an upper bonding layer, a first wiring layer, and the logic chip includes a second substrate, a lower bonding layer, a second wiring layer. The upper and lower bonding layers contact each other, with the upper bonding layer including an upper dielectric layer, an upper conductive pad, an upper shield structure, and an upper wiring line, and the lower bonding layer including a lower dielectric layer, a lower conductive pad, a lower shield structure, and a lower wiring line. The upper wiring line, upper conductive pad, and upper shield structure being one body, and the lower wiring line, lower conductive pad, and lower shield structure being one body, the upper and lower conductive pads overlap and contact each other, and the upper and lower wiring lines overlap and contact each other. | 2022-06-23 |
20220199671 | EVENT DRIVEN PIXEL FOR SPATIAL INFORMATION EXTRACTION - An event driven sensor includes an arrangement of photodiodes including an inner portion laterally surrounded by an outer portion. An outer pixel cell circuit is coupled to generate an outer pixel value in response to photocurrent generated by the outer portion. The outer pixel value is a binned signal representative of an average value of brightness of incident light on the arrangement of photodiodes. An inner pixel cell circuit is coupled to the inner portion to generate an inner pixel value in response to photocurrent generated by from the inner portion. An event driven circuit is coupled to the outer pixel cell circuit and the inner pixel cell circuit. The event driven circuit is coupled to generate an output signal responsive to an inner brightness indicated by the inner pixel value relative to an outer brightness indicated by the outer pixel value. | 2022-06-23 |
20220199672 | IMAGE SENSOR AND IMAGE SENSING CIRCUIT - An image sensor, which stores electric charge overflowing from a photoelectric conversion layer, includes: (1) a substrate including a first surface and a second surface, which is opposite to the first surface and upon which light is incident, (2) a photoelectric conversion layer in the substrate, (3) an isolation film disposed on the substrate, along the photoelectric conversion layer, (4) a storage conductive pattern disposed in the isolation film, (5) a transfer gate disposed on a first surface of the substrate, (6) a first impurity-injected area disposed between the photoelectric conversion layer and the isolation film, and (7) a second impurity-injected area disposed on the first surface of the substrate and connected to the transfer gate. The first and second impurity-injected areas are electrically connected. | 2022-06-23 |
20220199673 | MULTISPECTRAL IMAGE SENSOR AND METHOD FOR FABRICATION OF AN IMAGE SENSOR - The present invention relates to a multispectral image sensor having a pixel array for detecting images with light components in different wave-length ranges, comprising a plurality of imaging layers each embedded in a semiconductor substrate, wherein in each of the imaging layers an array of photodetecting regions is provided, wherein the photodetecting regions are configured with different absorption characteristics, wherein the imaging layers are stacked so that the photodetecting regions of the arrays are aligned, wherein the absorption characteristics allow a preferred absorption of light components of at least one predetermined wavelength range. | 2022-06-23 |
20220199674 | LIGHT EMITTING DIODE INTEGRATED WITH TRANSITION METAL DICHALCOGENIDE TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - The inventive concept relates to a light emitting diode integrated with a transition metal dichalcogenide-based transistor and capable of simultaneously fabricating the transistor to have a monolithic integration structure. The transition metal dichalcogenide is formed on the light emitting diode device, thereby providing the light emitting diode integrated with the transistor without affecting the characteristics of the light emitting diode device. | 2022-06-23 |
20220199675 | MANUFACTURING METHOD AND MANUFACTURING MACHINE FOR REDUCING NON-RADIATIVE RECOMBINATION OF MICRO LED - The present disclosure is a manufacturing method for reducing non-radiative recombination of micro LED. At least one etched LED epitaxial wafer includes a plurality of etching grooves and mesas, an etched sidewall of the mesa includes a stack of a first type semiconductor layer, an active layer and a second type semiconductor layer. Two stages of ALD are performed on the etched LED epitaxial wafer with different temperature ranges. The first ALD can be used to repair dangling bonds and defects on the etched side walls of the mesa, and the second ALD can be used to form a passivation layer on the etched side walls of the mesa. By the manufacturing method of the present disclosure, non-radiative recombination of the micro LED can be reduced, and the luminous brightness and luminous efficiency of the micro LED can be improved. | 2022-06-23 |
20220199676 | DISPLAY DEVICE - A display device may include a substrate including pixels; a first bank that defines an emission area of the pixels; a first electrode and a second electrode spaced apart from each other in the emission area; a first insulating layer disposed on the first electrode and the second electrode; light emitting elements disposed on the first insulating layer between the first electrode and the second electrode; a second insulating layer disposed on the first bank; a first opening passing through the first insulating layer; and a second opening passing through the second insulating layer. The first opening and the second opening may overlap the first bank. | 2022-06-23 |
20220199677 | DISPLAY DEVICE - A display device includes a substrate including a display area and a non-display area; pixels disposed in the display area; first scan lines that transmit signals to the pixels, extend in a first direction, and are disposed in a second direction different from the first direction; second scan lines that extend in the second direction and are disposed in the first direction; and a pad part electrically connected to the second scan lines and disposed in the non-display area. Each of the first scan lines is electrically connected to at least one of the second scan lines through a corresponding one of contactors. Each of the pixels is a first pixel, a second pixel, or a third pixel based on whether or not including a contactor. | 2022-06-23 |
20220199678 | DISPLAY PANEL AND DISPLAY DEVICE - A display apparatus includes a display panel on which a plurality of pixels are displayed, a plurality of signal lines to which a signal required to drive the display panel is supplied, and an electrostatic discharge circuit connected between each of the plurality of signal lines and the electrostatic discharge line, and the electrostatic discharge circuit includes first and second current paths between the signal line and the electrostatic discharge line, a first electrostatic discharge circuit connected to the first current path, including a plurality of first thin film transistors having a first gate electrode connected to the second current path and a second gate electrode connected to the first current path, and a second electrostatic discharge circuit connected to the second current path, including at least one second thin film transistor having a first gate electrode connected to the first current path and a second gate electrode connected to the first current path. | 2022-06-23 |
20220199679 | SEMICONDUCTOR LIGHT EMITTING DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor light emitting device is provided. The semiconductor light emitting device includes a plurality of light emitting structures, each of which includes a first surface and a second surface, a plurality of embossed portions provided on the first surface; a partition wall structure provided on the first surface of the plurality of light emitting structures and including a plurality of partition walls which define a plurality of pixel spaces; and a fluorescent layer provided in the plurality of pixel spaces. A bottom surface of the partition wall structure contacts the plurality of embossed portions. | 2022-06-23 |
20220199680 | LIGHT EMITTING DISPLAY APPARATUS - A light emitting display apparatus includes a substrate including a plurality of pixels each including an emission area; a light extraction pattern including a plurality of concave portions in the emission area; and a light emitting portion over the light extraction pattern, wherein at least one of the plurality of concave portions has a curvature of 0.217 μm | 2022-06-23 |
20220199681 | LIGHT-EMITTING DISPLAY DEVICE - A light-emitting display device includes: a substrate, a plurality of pixels on the substrate, each pixel including an opening area, a light extraction pattern disposed in each opening area, the light extraction pattern including: a plurality of concave portions spaced apart from each other, and a protruding portion surrounding each of the plurality of concave portions, and a light-emitting device layer including: a light-emitting layer over the light extraction pattern, and a non-emission area overlapping a top portion of the protruding portion between the two adjacent concave portions. | 2022-06-23 |
20220199682 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - Display device includes a first substrate; an active material layer on the first substrate and including a channel area, a first doped area on one side of the channel area, and a second doped area on another side of the channel area; a gate insulating layer on the active material layer; a first conductive layer on the gate insulating layer and including a gate electrode overlapping the channel area and a signal application electrode; a second conductive layer including a first electrode electrically connected to the first doped area, a second electrode electrically connected to the second doped area, and a third electrode electrically connected to the signal application electrode; a light emitting element; and a third conductive layer on the light emitting element, the third conductive layer including a first contact electrode electrically connected to the second electrode, and a second contact electrode electrically connected to the third electrode. | 2022-06-23 |