25th week of 2011 patent applcation highlights part 19 |
Patent application number | Title | Published |
20110147769 | Organic light emitting display and manufacturing method thereof - An organic light emitting display includes a gate electrode on a substrate, an active layer insulated from the gate electrode, source and drain electrodes that are insulated from the gate electrode and contact the active layer, an insulating layer between the active layer and the source and drain electrodes, a light blocking layer that is on the active layer and that blocks light of a predetermined wavelength from the active layer, and an organic light emitting device that is electrically connected to one of the source and drain electrodes. | 2011-06-23 |
20110147770 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode display includes: a substrate main body having a plurality of pixel regions, each including an opaque region and a transparent region; and organic light emitting diodes, thin film transistors, and conductive lines that are formed in the opaque region of the substrate main body. The transparent region includes a transparent square space that has an area that is at least 15% of the entire area of the pixel region. | 2011-06-23 |
20110147771 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE AND LIGHTING SYSTEM - Disclosed are a light emitting device, a light emitting device package, and a lighting system. The light emitting device includes an oxide including gallium aluminum over a gallium oxide substrate, a nitride including gallium aluminum over the oxide including gallium aluminum, and a light emitting structure over the nitride including gallium aluminum. | 2011-06-23 |
20110147772 | GALLIUM NITRIDE WAFER SUBSTRATE FOR SOLID STATE LIGHTING DEVICES, AND ASSOCIATED SYSTEMS AND METHODS - Gallium nitride wafer substrate for solid state lighting devices, and associated systems and methods. A method for making an SSL device substrate in accordance with one embodiment of the disclosure includes forming multiple crystals carried by a support member, with the crystals having an orientation selected to facilitate formation of gallium nitride. The method can further include forming a volume of gallium nitride carried by the crystals, with the selected orientation of the crystals at least partially controlling a crystal orientation of the gallium nitride, and without bonding the gallium nitride, as a unit, to the support member. In other embodiments, the number of crystals can be increased by a process that includes annealing a region in which the crystals are present, etching the region to remove crystals having an orientation other than the selected orientation, and/or growing the crystals having the selected orientation. | 2011-06-23 |
20110147773 | UTILIZING GRADIENT REFRACTIVE INDEX FILMS FOR LIGHT EXTRACTION AND DISTRIBUTION CONTROL IN OLED - The present invention relates to an electro-optical device, wherein the device is a light source, for example an OLED. The OLED includes at least a substrate, a cathode, an anode, one or more organic light-emissive materials disposed between the cathode and anode, and a gradient refractive index film disposed on an external, light emitting surface of the device, for example on the substrate layer. Alternatively, the device may be constructed with the gradient refractive index film as the substrate, and/or the gradient refractive index film may be applied to more than one light-emitting surface of a device | 2011-06-23 |
20110147774 | WAFER LEVEL LED PACKAGE STRUCTURE FOR INCREASING LIGHT-EMITTING EFFICIENCY AND HEAT-DISSIPATING EFFECT AND METHOD FOR MANUFACTURING THE SAME - A wafer level LED package structure includes a light-emitting unit, a reflecting unit, a first conductive unit and a second conductive unit. The light-emitting unit has a substrate body, a light-emitting body disposed on the substrate body, a positive and a negative conductive layers formed on the light-emitting body, and a light-emitting area formed in the light-emitting body. The reflecting unit has a reflecting layer formed between the positive and the negative conductive layers and on the substrate body for covering external sides of the light-emitting body. The first conductive unit has a first positive conductive layer formed on the positive conductive layer and a first negative conductive layer formed on the negative conductive layer. The second conductive unit has a second positive conductive structure formed on the first positive conductive layer and a second negative conductive structure formed on the first negative conductive layer. | 2011-06-23 |
20110147775 | LIGHT EMITTING DEVICE - According to one embodiment, a light emitting device includes a semiconductor light emitting element to emit a first light, a mounting member, first and second wavelength conversion layers and a transparent layer. The first wavelength conversion layer is provided between the element and the mounting member in contact with the mounting member. The first wavelength conversion layer absorbs the first light and emits a second light having a wavelength longer than a wavelength of the first light. The semiconductor light emitting element is disposed between the second wavelength conversion layer and the first wavelength conversion layer. The second wavelength conversion layer absorbs the first light and emits a third light having a wavelength longer than the wavelength of the first light. The transparent layer is provided between the element and the second wavelength conversion layer. The transparent layer is transparent to the first, second, and third lights. | 2011-06-23 |
20110147776 | LIGHT EMITTING DEVICE - According to one embodiment, a light emitting device includes a semiconductor light emitting element, a mounting member, a first wavelength conversion layer, and a first transparent layer. The semiconductor light emitting element emits a first light. The semiconductor light emitting element is placed on the mounting member. The first wavelength conversion layer is provided between the semiconductor light emitting element and the mounting member in contact with the mounting member. The first wavelength conversion layer absorbs the first light and emits a second light having a wavelength longer than a wavelength of the first light. The first transparent layer is provided between the semiconductor light emitting element and the first wavelength conversion layer in contact with the semiconductor light emitting element and the first wavelength conversion layer. The first transparent layer is transparent to the first light and the second light. | 2011-06-23 |
20110147777 | ORGANIC LIGHT-EMITTING DIODE AND LIGHT SOURCE DEVICE INCLUDING SAME - An organic light-emitting diode in accordance with the present invention includes: a reflective electrode; an organic layer formed on the reflective electrode; a transparent electrode formed on the organic layer; a transparent resin layer formed on the transparent electrode; and an encapsulation glass formed on the transparent resin layer. The organic layer includes a light-emitting point. Cone- or pyramid-shaped transparent resin structures are provided in the transparent resin layer in such a manner that each of the cone- or pyramid-shaped transparent resin structures splays from the transparent resin layer toward the encapsulation glass in a normal direction of the encapsulation glass. A refractive index of the transparent resin layer is 1.3 times or more to 1.6 times or less as high as that of the cone- or pyramid-shaped transparent resin structures. | 2011-06-23 |
20110147778 | LIGHT EMITTING DEVICE - To provide a light emitting device capable of improving both color unevenness and an emission output power. | 2011-06-23 |
20110147779 | LIGHT EMITTING DIODE PACKAGE AND METHOD OF FABRICATING THE SAME - A light emitting diode (LED) package and a method of manufacturing a LED package is provided. The LED package includes a case having first and second lead frames disposed through the case; an LED chip disposed on the case, the LED chip having first and second electrodes directly connected to the first and second lead frames through a eutectic bond, respectively; and a lens disposed over the case covering the LED chip. | 2011-06-23 |
20110147780 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURE - A light emitting device includes a transparent conductive layer formed adjacent one of two semiconductor layers having an active layer therebetween. The transparent conductive layer includes first and second transparent conductive regions with different electrical conductivities. The difference in electrical conductivities controls an amount or flow rate of current into the semiconductor layer adjacent the transparent conductive layer, and an electrode is at least partial aligned with the second transparent conductive region. | 2011-06-23 |
20110147781 | PACKAGE FOR LIGHT EMITTING DEVICE - The present invention discloses a light emitting device package, comprising: a metal base; an electrical circuit layer provided at an upper side of the metal base for providing a conductive path; a light emitting device mounted in a second region having a smaller thickness than a first region on the metal base; an insulating layer sandwiched between the meta base and the electrical circuit layer; an electrode layer provided at an upper side of the electrical circuit layer; and a wire for electrically connecting the electrode layer and the light emitting device. Further, there is provided a light emitting device package which is improved in light emission efficiency since the light emitting device is placed on a small thickness portion of the metal base. | 2011-06-23 |
20110147782 | OPTICAL DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is an optical device which has an increased rate of an area occupied by an effective optical region to an light-transmissive substrate and less noise due to reflection from a peripheral end face of the light-transmissive substrate. The optical device includes a semiconductor substrate in which a light-receiving element is formed and a light-transmissive substrate provided above the semiconductor substrate so as to cover the light-receiving element and fixed to the semiconductor substrate with an adhesive layer. The light-transmissive substrate has, in a peripheral end face, a curved surface which slopes so as to flare from an upper surface toward a lower surface. | 2011-06-23 |
20110147783 | RED PHOSPHOR AND FORMING METHOD THEREOF FOR USE IN SOLID STATE LIGHTING - There are described a red phosphor for use in solid state lighting and a method for preparing the same, which can be excited efficiently with near UV light, blue light and green light. The red phosphor for use in solid state lighting includes a Zn and Ti oxide as a main element and a rare earth element as an additive element. The rare earth element includes a single element or one or more combination thereof selected from a group consisting of Eu, Er, Dy, Sm, Tb, Ce, Gd, Nd, Dy, Ho and the mixture thereof. The Zn and Ti oxide may be one selected from a group consisting of TiZn | 2011-06-23 |
20110147784 | Light emitting device with more uniform current spreading - A nitride light emitting device (LED) according to a non-limiting embodiment of the present invention may include a p-pad and an n-pad, wherein the p-pad and n-pad are disposed on opposite ends of the device. A first p-branch electrode and a second p-branch electrode may extend from the p-pad toward the n-pad, with the first p-branch electrode extending along a length of the device. The second p-branch electrode may have a bent portion so as to extend along a width and length of the device. An n-branch electrode may extend from the n-pad toward the p-pad, wherein a distal end of the n-branch electrode is angled toward the bent portion of the second p-branch electrode. Alternatively, the p-branch and n-branch electrodes may be configured such that a distance between the n-branch electrode and the first and second p-branch electrodes increases with proximity to the n-pad. As a result, the nitride-based LED according to example embodiments may exhibit improved current uniformity, lower forward operating voltage, and higher overall efficiency. | 2011-06-23 |
20110147785 | SURFACE MOUNT LED AND HOLDER - A surface mount LED for attaching an LED to a substrate using a conventional reflow soldering technique. The surface mount LED according to this invention includes an LED and a holder. The LED includes a plurality of leads. The holder supports the LED and includes a plurality of feet arranged at approximately equal intervals around the perimeter of a base of the holder. Each lead is wrapped around a respective foot. The resulting wrapped lead forms a contact point corresponding with a solder pad layout for attaching the surface mount LED to a substrate. | 2011-06-23 |
20110147786 | LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - Disclosed is a light emitting device and a method of manufacturing the same. The light emitting device includes a first conductive semiconductor layer, an active layer over the first conductive semiconductor layer, a second conductive semiconductor layer over the active layer, a current spreading layer over the second conductive semiconductor layer, a first electrode layer over the first conductive semiconductor, and a second electrode layer over the current spreading layer. | 2011-06-23 |
20110147787 | ORGANIC LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - An organic light emitting diode (OLED) and a method for manufacturing the same are provided. In the OLED, patterned metal electrodes are positioned on one or more of upper and lower portions of a light emission layer to allow light generated from the light emission layer to emit to an area between the patterned metal electrodes. | 2011-06-23 |
20110147788 | SEMICONDUCTOR DEVICE WITH A LIGHT EMITTING SEMICONDUCTOR DIE - A semiconductor device includes a light emitting semiconductor die mounted on at least one of first and second electrically conductive bonding pads, which are located on a first major surface of a substrate of the device. The light emitting semiconductor die has an anode and a cathode, which are electrically connected to the first and second electrically conductive bonding pads. The semiconductor device further includes first and second electrically conductive connecting pads, which are located on a second major surface of the substrate. The first and second electrically conductive bonding pads are electrically connected to the first and second electrically conductive connecting pads via first and second electrically conductive edge interconnecting elements. | 2011-06-23 |
20110147789 | ORGANIC LIGHT EMITTING DIODE DEVICE - Disclosed is an organic light emitting diode device including a substrate, an organic light emitting element disposed on the substrate, a polymer resin layer covering the organic light emitting element, and a getter disposed between the organic light emitting element and the polymer resin. The getter may include a moisture absorbing material and a binder having a volatilization degree of about 400 ppm or less when heated at a temperature ranging from about 60° C. to about 120° C. for about 2 hours. | 2011-06-23 |
20110147790 | Light Emitting Diode and Fabricating Method thereof - A light emitting diode and a fabricating method thereof are provided. The method including the steps of sequentially forming a first-type semiconductor layer, a light emitting layer and a second-type semiconductor layer with a first region and a second region on a substrate. Next, an ion implantation process is performed to make the resistance of the first region be larger than of the second region. Afterward, a first electrode is formed above the first region of the second-type semiconductor layer. Since the method uses the ion implantation process to make the inner resistance of the second-type semiconductor layer various, the light emitting intensity and efficiency may both be increased. | 2011-06-23 |
20110147791 | GROWTH OF COINCIDENT SITE LATTICE MATCHED SEMICONDUCTOR LAYERS AND DEVICES ON CRYSTALLINE SUBSTRATES - Methods of fabricating a semiconductor layer or device and said devices are disclosed. The methods include but are not limited to providing a substrate having a crystalline surface with a known lattice parameter (a). The method further includes growing a crystalline semiconductor layer on the crystalline substrate surface by coincident site lattice matched epitaxy, without any buffer layer between the crystalline semiconductor layer and the crystalline surface of the substrate. The crystalline semiconductor layer will be prepared to have a lattice parameter (a′) that is related to the substrate lattice parameter (a). The lattice parameter (a′) maybe related to the lattice parameter (a) by a scaling factor derived from a geometric relationship between the respective crystal lattices. | 2011-06-23 |
20110147792 | Heterocyclic Compound, Light-Emitting Element, Light-Emitting Device, Electronic Device and Lighting Device - Objects of the present invention are to provide the following: a novel heterocyclic compound which can be used as a material in which a light-emitting substance of a light-emitting layer in a light-emitting element is dispersed; a novel heterocyclic compound having a high electron-transport property; a light-emitting element having high current efficiency; and a light-emitting device, an electronic device and a lighting device each having reduced power consumption. Provided are a heterocyclic compound represented by General Formula (G1-1) or (G1-2) below, and a light-emitting element, a light-emitting device, an electronic device and a lighting device each including the heterocyclic compound. Such use of the heterocyclic compound represented by General Formula (G1-1) or (G1-2) makes it possible to provide a light-emitting element having high current efficiency, and a light-emitting device, an electronic device and a lighting device each having reduced power consumption. | 2011-06-23 |
20110147793 | SiGe HETEROJUNCTION BIPOLAR TRANSISTOR MULTI-FINGER STRUCTURE - The present invention provides a multi-finger structure of a SiGe heterojunction bipolar transistor (HBT). It is consisted of plural SiGe HBT single cells. The multi-finger structure is in a form of C/BEBC/BEBC/.../C, wherein, C, B, E respectively stands for collector, base and emitter; CBEBC stands for a SiGe HBT single cell. The collector region is consisted of an n type ion implanted layer inside the active region. The bottom of the implanted layer is connected to two n type pseudo buried layers. The two pseudo buried layers are formed through implantation to the bottom of the shallow trenches that surround the collector active region. Two collectors are picked up by deep trench contact through the field oxide above the two pseudo buried layers. The present invention can reduce junction capacitance, decrease collector electrode output resistance, and improve device frequency characteristics. | 2011-06-23 |
20110147794 | STRUCTURE AND METHOD FOR A SILICON CONTROLLED RECTIFIER (SCR) STRUCTURE FOR SOI TECHNOLOGY - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a P+-N body diode and an N+-P body diode. The P+-N body diode and the N+-P body diode are laterally integrated. | 2011-06-23 |
20110147795 | MATERIALS FOR INTERFACING HIGH-K DIELECTRIC LAYERS WITH III-V SEMICONDUCTORS - A group III chalcogenide layer for interfacing a high-k dielectric to a III-V semiconductor surface and methods of forming the same. A III-V QWFET includes a gate stack which comprises a high-K gate dielectric layer disposed on an interfacial layer comprising a group III chalcogenide. In an embodiment, a III-V semiconductor surface comprising a native oxide is sequentially exposed to TMA and H | 2011-06-23 |
20110147796 | SEMICONDUCTOR DEVICE WITH METAL CARRIER AND MANUFACTURING METHOD - Semiconductor device including a metal carrier substrate. Above the carrier substrate a first semiconductor layer of Al | 2011-06-23 |
20110147797 | STRUCTURE OF A pHEMT TRANSISTOR CAPABLE OF NANOSECOND SWITCHING - A method for fabricating a transistor and the resulting transistor is disclosed. The method generally includes steps (A) to (E). Step (A) may form a high mobility layer. The high mobility layer is generally configured to carry a two-dimensional electron gas. Step (B) may form a planar layer on the high mobility layer. Step (C) may form a barrier layer on the planar layer. Step (D) may form a doped layer on the barrier layer. The doped layer is generally a low bandgap III-V semiconductor. Step (E) may form a gate in contact with the doped layer. The gate may be separated from both a source and a drain by corresponding ungated recess regions. The high mobility layer, the planar layer, the barrier layer, the doped layer, the source, the gate and the drain are generally configured as a pseudomorphic high electron mobility transistor. | 2011-06-23 |
20110147798 | CONDUCTIVITY IMPROVEMENTS FOR III-V SEMICONDUCTOR DEVICES - Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device. | 2011-06-23 |
20110147799 | HIGH ON-STATE BREAKDOWN HETEROJUNCTION BIPOLAR TRANSISTOR - A heterojunction bipolar transistor (HBT) is provided with an improved on-state breakdown voltage V | 2011-06-23 |
20110147800 | SEMICONDUCTOR DEVICE INCLUDING CONDUCTIVE LINES WITH FINE LINE WIDTH AND METHOD OF FABRICATING THE SAME - A semiconductor device comprises a semiconductor substrate including a first core region and a second core region between which a cell array region is interposed, a first conductive line and a second conductive line extending to the first core region across the cell array region, and a third conductive line and a fourth conductive line extending to the second core region across the cell array region, wherein a line width of the first through fourth conductive lines is smaller than a resolution limit in a lithography process. | 2011-06-23 |
20110147801 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds. | 2011-06-23 |
20110147802 | Sensor - A sensor configured to sense an external event including: a first component having a first impedance that changes when the external event occurs and being connected between a reference voltage node and an output node wherein the output node is configured to provide, when the external event occurs, a feedback signal to the first component that further changes the first impedance and wherein the first component is a field effect transistor comprising: a gate formed from a conductive core of a nanowire and connected to the output node; a gate dielectric formed from an insulating shell of the nanowire; a source/drain electrode connected to the output node; a source/drain electrode connected to the reference node; and a channel extending between the source/drain electrodes. | 2011-06-23 |
20110147803 | Gas Sensor And Flip-Chip Method For Its Manufacture - A sensor element is described that includes at least one semiconductor component having a gas-sensitive layer which is attached to a substrate by the flip-chip method, the gas-sensitive layer facing the substrate and a supply arrangement being provided to supply a gas to be examined to the gas-sensitive layer. The semiconductor component is enclosed in a casing. Also described is a method for manufacturing the sensor element, in which a semiconductor component having a gas-sensitive layer is attached by the flip-chip method to a substrate in such a way that the gas-sensitive layer faces the substrate. After that, the casing is applied by a plasma sputtering method, in particular an atmospheric plasma sputtering method. Finally, a use of the sensor element in the exhaust system of an internal combustion engine is also described. | 2011-06-23 |
20110147804 | Drive current enhancement in tri-gate MOSFETS by introduction of compressive metal gate stress using ion implantation - A semiconductor device comprises a fin and a metal gate film. The fin is formed on a surface of a semiconductor material. The metal gate film formed on the fin and comprises ions implanted in the metal gate film to form a compressive stress within the metal gate. In one exemplary embodiment, the surface of the semiconductor material comprises a (100) crystalline lattice orientation, and an orientation of the fin is along a <100> direction with respect to the crystalline lattice of the semiconductor. In another exemplary embodiment, the surface of the semiconductor material comprises a (100) crystalline lattice orientation, and the orientation of the fin is along a <110> direction with respect to the crystalline lattice of the semiconductor. The fin comprises an out-of-plane compression that is generated by the compressive stress within the metal gate film. | 2011-06-23 |
20110147805 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a <110> direction. | 2011-06-23 |
20110147806 | Double-Gated Transistor Memory - Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells may use one, two or three transistors. Single transistor cells are constructed either with or without a bit storage capacitor, and both NAND- and NOR-type Non-Volatile NVRAM cells, as well as Ferroelectric FeRAM cells, are described. For all cells, top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F | 2011-06-23 |
20110147807 | Single Transistor Memory with Immunity to Write Disturb - Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells using one transistor to implement a Ferroelectric FeRAM are described. Top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F | 2011-06-23 |
20110147808 | ASYMMETRIC JUNCTION FIELD EFFECT TRANSISTOR - A junction field effect transistor (JFET) in a semiconductor substrate includes a source region, a drain region, a channel region, an upper gate region, and a lower gate region. The lower gate region is electrically connected to the upper gate region. The upper and lower gate regions control the current flow through the channel region. By performing an ion implantation step that extends the thickness of the source region to a depth greater than the thickness of the drain region, an asymmetric JFET is formed. The extension of depth of the source region relative to the depth of the drain region reduces the length for minority charge carriers to travel through the channel region, reduces the on-resistance of the JFET, and increases the on-current of the JFET, thereby enhancing the overall performance of the JFET without decreasing the allowable Vds or dramatically increasing Voff/Vpinch. | 2011-06-23 |
20110147809 | FORMING A CARBON CONTAINING LAYER TO FACILITATE SILICIDE STABILITY IN A SILICON GERMANIUM MATERIAL - A method includes forming a silicon germanium layer, forming a layer comprising carbon and silicon on a top surface of the silicon germanium layer, forming a metal layer above the layer comprising carbon and silicon, and performing a thermal treatment to convert at least the layer comprising carbon and silicon to form a metal silicide layer. | 2011-06-23 |
20110147810 | METHOD OF FABRICATING STRAINED STRUCTURE IN SEMICONDUCTOR DEVICE - The present disclosure provides a semiconductor device that includes a semiconductor substrate, a gate structure disposed on a portion of the substrate, and strained structures disposed at either side of the portion of the substrate and formed of a semiconductor material different from the semiconductor substrate. The portion of the substrate is T shaped having a horizontal region and a vertical region that extends from the horizontal region in a direction away from a surface of the substrate. | 2011-06-23 |
20110147811 | TWO-DIMENSIONAL CONDENSATION FOR UNIAXIALLY STRAINED SEMICONDUCTOR FINS - Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded. | 2011-06-23 |
20110147812 | POLISH TO REMOVE TOPOGRAPHY IN SACRIFICIAL GATE LAYER PRIOR TO GATE PATTERNING - Techniques are disclosed for fabricating FinFET transistors (e.g., double-gate, trigate, etc). A sacrificial gate material (such as polysilicon or other suitable material) is deposited on fin structure, and polished to remove topography in the sacrificial gate material layer prior to gate patterning. A flat, topography-free surface (e.g., flatness of 50 nm or better, depending on size of minimum feature being formed) enables subsequent gate patterning and sacrificial gate material opening (via polishing) in a FinFET process flow. Use of the techniques described herein may manifest in structural ways. For instance, a top gate surface is relatively flat (e.g., flatness of 5 to 50 nm, depending on minimum gate height or other minimum feature size) as the gate travels over the fin. Also, a top down inspection of gate lines will generally show no or minimal line edge deviation or perturbation as the line runs over a fin. | 2011-06-23 |
20110147813 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes: forming a fin-type semiconductor region on a substrate; and introducing an n-type impurity into at least a side of the fin-type semiconductor region by a plasma doping process, thereby forming an n-type impurity region in the side of the fin-type semiconductor region. In the introducing the n-type impurity, when a source power in the plasma doping process is denoted by a character Y [W], the supply of a gas containing the n-type impurity per unit time and per unit volume is set greater than or equal to 5.1×10 | 2011-06-23 |
20110147814 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device includes a vertical type semiconductor element formed by using a silicon substrate, a P type impurity diffusion layer being formed at a back surface of the silicon substrate. The surface of the P type impurity diffusion layer is wet etched to expose a single silicon crystal surface of the P type impurity diffusion layer, and a metal layer having a work function of 4.5 eV or more is disposed to the single silicon crystal surface so that an ohmic contact is made between the single silicon crystal surface of the P type impurity diffusion layer and the metal layer without making a silicon-metal alloy layer between the P type impurity diffusion layer and the metal layer. | 2011-06-23 |
20110147815 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - Disclosed is a semiconductor device wherein device characteristics are improved by applying a strong stress to a channel region. The semiconductor device includes a semiconductor substrate, a gate insulating film formed over a first plane of the semiconductor substrate, a gate electrode formed over the gate insulating film, a gate sidewall insulating film formed over the sidewall of the gate electrode, source/drain diffusion layer regions into which impurities are implanted, the source/drain diffusion layer regions being adjacent to a channel region formed in the semiconductor substrate below the gate electrode, and a stress applying film formed over the source/drain diffusion layer regions except over the upper part of the gate electrode; and recesses or protrusions are formed in the region where the source/drain diffusion layer regions are formed over the first plane of the semiconductor substrate. | 2011-06-23 |
20110147816 | SPIN TORQUE MAGNETIC INTEGRATED CIRCUITS AND DEVICES THEREFOR - Spin torque magnetic integrated circuits and devices therefor are described. A spin torque magnetic integrated circuit includes a first free ferromagnetic layer disposed above a substrate. A non-magnetic layer is disposed above the first free ferromagnetic layer. A plurality of write pillars and a plurality of read pillars are included, each pillar disposed above the non-magnetic layer and including a fixed ferromagnetic layer. | 2011-06-23 |
20110147817 | SEMICONDUCTOR COMPONENT HAVING AN OXIDE LAYER - Semiconductor component having an oxide layer. One embodiment includes a first semiconductor region and a second semiconductor region. An oxide layer is arranged between the first and second semiconductor region. The first semiconductor region and the oxide layer form a first semiconductor-oxide interface. The second semiconductor region and the oxide layer form a second semiconductor-oxide interface. The oxide layer has a chlorine concentration, the chlorine concentration having a first maximum in the region of the first semiconductor-oxide interface, and having a second maximum in the region of the second semiconductor-oxide interface. | 2011-06-23 |
20110147818 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes: a substrate; a memory multilayer body with a plurality of insulating films and electrode films alternately stacked therein, the memory multilayer body being provided on a memory array region of the substrate; a semiconductor pillar buried in the memory multilayer body and extending in stacking direction of the insulating films and the electrode films; a charge storage film provided between one of the electrode films and the semiconductor pillar; a dummy multilayer body with a plurality of the insulating films and the electrode films alternately stacked therein and a dummy hole formed therein, the dummy multilayer body being provided on a peripheral circuit region of the substrate; an insulating member buried in the dummy hole; and a contact buried in the insulating member and extending in the stacking direction. | 2011-06-23 |
20110147819 | SEMICONDUCTOR DEVICE - p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed. | 2011-06-23 |
20110147820 | Non-Volatile Memory Cell Having a Heating Element and a Substrate-Based Control Gate - The number of times that a non-volatile memory (NVM) can be programmed and erased is substantially increased by utilizing a localized heating element that anneals the oxide that is damaged by tunneling charge carriers when the NVM is programmed and erased. The program and erase voltages are also reduced when heat from the heating element is applied prior to programming and erasing. | 2011-06-23 |
20110147821 | NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT - A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor. | 2011-06-23 |
20110147822 | Semiconductor memory device and method for manufacturing the same - A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a metal oxide layer above the level of the gate insulating film, a second insulating film covering a side of the word line and a surface of the semiconductor substrate between the word lines, and having a film thickness of 15 nm or less, and a third insulating film formed between the word lines adjacent to each other such that a region below the level of the metal oxide layer has a cavity. | 2011-06-23 |
20110147823 | VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a vertical channel type nonvolatile memory device includes forming alternately a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, forming a trench having a plurality of recesses on a surface of the trench by etching the plurality of interlayer dielectric layers and a plurality of conductive layers, wherein the plurality of recesses are formed at a certain interval on the surface of the trench, forming a charge blocking layer over a plurality of surfaces of the plurality of recesses, forming a charge storage layer over the charge blocking layer for filling a plurality of the remaining recesses with a charge storage material, forming a tunnel dielectric layer to cover the charge storage layer, and forming a vertical channel layer by filling the remaining trench. | 2011-06-23 |
20110147824 | SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME - In semiconductor devices and methods of manufacture, a semiconductor device comprises a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers are on the substrate. A plurality of gate patterns are provided, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material is on the substrate and extending in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns. The vertical channel has an outer sidewall, the outer sidewall having a plurality of channel recesses, each channel recess corresponding to a gate pattern of the plurality of gate patterns. The vertical channel has an inner sidewall. An information storage layer is present in the recess between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel. | 2011-06-23 |
20110147825 | NONVOLATILE MEMORY DEVICES INCLUDING DEEP AND HIGH DENSITY TRAPPING LAYERS - A charge trap nonvolatile memory device includes a gate electrode on a substrate; a charge trapping layer between the gate electrode and the substrate, the charge trapping layer having trap sites configured to trap charges; a charge tunneling layer between the trapping layer and the semiconductor substrate; and a charge blocking layer between the gate electrode and the trapping layer. The charge trapping layer comprises a deep trapping layer having a plurality of energy barriers and a high density trapping layer having a trap site density higher than a trap site density of the deep trapping layer. | 2011-06-23 |
20110147826 | Methods Of Forming Memory Cells - Some embodiments include methods of utilizing polysilazane in forming non-volatile memory cells. The memory cells may be multi-level cells (MLCs). The polysilazane may be converted to silicon nitride, silicon dioxide, or silicon oxynitride with thermal processing and exposure to an ambient that contains one or both of oxygen and nitrogen. The methods may include using the polysilazane in forming a charge trapping layer of a non-volatile memory cell. The methods may alternatively, or additionally include using the polysilazane in forming intergate dielectric material of a non-volatile memory cell. Some embodiments include methods of forming memory cells of a NAND memory array. | 2011-06-23 |
20110147827 | Flash memory with partially removed blocking dielectric in the wordline direction - The present disclosure relates generally to the fabrication of non-volatile memory. In at least one embodiment, the present disclosure relates to forming a layered blocking dielectric which has a portion thereof removed in the wordline direction. | 2011-06-23 |
20110147828 | SEMICONDUCTOR DEVICE HAVING DOPED EPITAXIAL REGION AND ITS METHODS OF FABRICATION - Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance. | 2011-06-23 |
20110147829 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - Provided are a semiconductor device which can shorten reverse recovery time without increasing leakage current between the drain and the source, and a fabrication method for such semiconductor device. | 2011-06-23 |
20110147830 | METHOD OF FORMING A SELF-ALIGNED CHARGE BALANCED POWER DMOS - Self-aligned charge balanced semiconductor devices and methods for forming such devices are disclosed. One or more planar gates are formed over a semiconductor substrate of a first conductivity type. One or more deep trenches are etched in the semiconductor self-aligned to the planar gates. The trenches are filled with a semiconductor material of a second conductivity type such that the deep trenches are charge balanced with the adjacent regions of the semiconductor substrate This process can form self-aligned charge balanced devices with a cell pitch less than 12 microns. | 2011-06-23 |
20110147831 | METHOD FOR REPLACEMENT METAL GATE FILL - An exemplary embodiment of a method for forming a gate for a planar-type or a finFET-type transistor comprises forming a gate trench that includes an interior surface. A first work-function metal is formed on the interior surface of the gate trench, and a low-resistivity material is deposited on the first work-function metal using a chemical vapor deposition (CVD) technique, or an atomic layer deposition (ALD) technique, or combinations thereof. Another exemplary embodiment provides that a second work-function metal is formed on the first work-function metal, and then the low-resistivity material is deposited on the first work-function metal using a chemical vapor deposition (CVD) technique, or an atomic layer deposition (ALD) technique, or combinations thereof. | 2011-06-23 |
20110147832 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device, the method comprising: forming a mask pattern over a semiconductor substrate including a device isolation film; etching the semiconductor substrate with the mask pattern as a barrier to form a recess having a semi-circular shape; filling a sacrificial material in the semi-circular shaped recess and between the mask pattern; removing the mask pattern; forming a silicon layer in a portion where the mask pattern is removed; removing the sacrificial material to form a gate region; and providing to gate electrode material in the gate region to form a gate pattern thereby enlarging the radius of curvature of the lower portion of the buried gate to improve a DIBL characteristic and enlarging the area of the part connected to a gate junction to improve contact resistance. | 2011-06-23 |
20110147833 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device includes a semiconductor substrate including an active area defined by an device isolation region, a buried gate formed on both side walls of a trench formed in the semiconductor substrate, and a storage node contact which is buried between the buried gates, and is connected to the active region of a middle portion of the trench and the device isolation region. | 2011-06-23 |
20110147834 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate, an impurity region in the semiconductor substrate, and a conductive layer contacting a top surface of the impurity region and at least a side surface of the impurity region. | 2011-06-23 |
20110147835 | SEMICONDUCTOR DEVICES HAVING REDUCED GATE-DRAIN CAPACITANCE - Embodiments of a semiconductor device include a semiconductor substrate having a first surface and a second surface opposed to the first surface, a trench formed in the semiconductor substrate and extending from the first surface partially through the semiconductor substrate, a gate electrode material deposited in the trench, and a void cavity in the semiconductor substrate between the gate electrode material and the second surface. A portion of the semiconductor substrate is located between the void cavity and the second surface. | 2011-06-23 |
20110147836 | Charged balanced devices with shielded gate trench - This invention discloses a semiconductor power device disposed on a semiconductor substrate includes a plurality of deep trenches with an epitaxial layer filling said deep trenches and a simultaneously grown top epitaxial layer covering areas above a top surface of said deep trenches over the semiconductor substrate. A plurality of trench MOSFET cells disposed in said top epitaxial layer with the top epitaxial layer functioning as the body region and the semiconductor substrate acting as the drain region whereby a super-junction effect is achieved through charge balance between the epitaxial layer in the deep trenches and regions in the semiconductor substrate laterally adjacent to the deep trenches. Each of the trench MOSFET cells further includes a trench gate and a gate-shielding dopant region disposed below and substantially aligned with each of the trench gates for each of the trench MOSFET cells for shielding the trench gate during a voltage breakdown. | 2011-06-23 |
20110147837 | DUAL WORK FUNCTION GATE STRUCTURES - A semiconductor chip having a transistor is described. The transistor having a gate electrode disposed over a gate dielectric. The gate electrode comprised of first gate material disposed on the gate dielectric and second gate material disposed on the gate dielectric. The first gate material being different than the second gate material. The second gate material also located at a source region or drain region of said gate electrode. | 2011-06-23 |
20110147838 | Tunnel Field Effect Transistors - Tunnel field effect devices and methods of fabricating tunnel field effect devices are described. In one embodiment, the semiconductor device includes a first drain region of a first conductivity type disposed in a first region of a substrate, a first source region of a second conductivity type disposed in the substrate, the second conductivity type being opposite the first conductivity type, a first channel region electrically coupled between the first source region and the first drain region, the first source region underlying a least a portion of the first channel region, and a first gate stack overlying the first channel region. | 2011-06-23 |
20110147839 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Multi-gate metal oxide silicon transistors and methods of making multi-gate metal oxide silicon transistors are provided. The multi-gate metal oxide silicon transistor contains a bulk silicon substrate containing one or more convex portions between shallow trench regions; one or more dielectric portions over the convex portions; one or more silicon fins over the dielectric portions; a shallow trench isolation layer in the shallow trench isolation regions; and a gate electrode. The upper surface of the shallow trench isolation layer can be located below the upper surface of the convex portion, or the upper surface of the shallow trench isolation layer can be located between the lower surface and the upper surface of first dielectric layer. The multi-gate metal oxide silicon transistor can contain second spacers adjacent to side surfaces of the convex portions in a source/drain region. | 2011-06-23 |
20110147840 | WRAP-AROUND CONTACTS FOR FINFET AND TRI-GATE DEVICES - A semiconductor device comprises a substrate and a semiconductor body formed on the substrate. The semiconductor body comprises a source region; and a drain region. The source region or the drain region, or combinations thereof, comprises a first side surface, a second side surface, and a top surface. The first side surface is opposite the second side surface, the top surface is opposite the bottom surface. The source region or the drain region, or combinations thereof, comprise a metal layer formed on the substantially all of the first side surface, substantially all of the second side surface, and the top surface. | 2011-06-23 |
20110147841 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device comprises: a channel region of a transistor formed in a predetermined region of silicon layer formed on insulation film; a gate electrode formed on the channel region via gate insulation film; and source/drain regions formed in the silicon layer thicker than said channel region located out of the channel region, wherein the transistor is a memory element constituting the channel region as a floating body cell. | 2011-06-23 |
20110147842 | MULTI-GATE SEMICONDUCTOR DEVICE WITH SELF-ALIGNED EPITAXIAL SOURCE AND DRAIN - A channel strained multi-gate transistor with low parasitic resistance and method of manufacturing the same. A gate stack may be formed over a semiconductor fin having a gate-coupled sidewall height (H | 2011-06-23 |
20110147843 | Semiconductor Component and Method for Producing a Semiconductor Component - A semiconductor component includes at least one field effect transistor disposed along a trench in a semiconductor region and has at least one locally delimited dopant region in the semiconductor region. The at least one locally delimited dopant region extends from or over a pn junction between the source region and the body region of the transistor or between the drain region and the body region of the transistor into the body region as far as the gate electrode, such that a gap between the pn junction and the gate electrode in the body region is bridged by the locally delimited dopant region. | 2011-06-23 |
20110147844 | SEMICONDUCTOR DEVICE WITH REDUCED SURFACE FIELD EFFECT AND METHODS OF FABRICATION THE SAME - Embodiments of the present invention describe a semiconductor device implementing the reduced-surface-field (RESURF) effect. The semiconductor device comprises a source/drain region having a plurality of isolation regions interleaved with source/drain extension regions. A gate electrode is formed on the semiconductor device, where the gate electrode includes gate finger elements formed over the isolation regions to induce capacitive coupling. The gate finger elements enhance the depletion of the source/drain extension regions, thus inducing a higher breakdown voltage. | 2011-06-23 |
20110147845 | Remote Doped High Performance Transistor Having Improved Subthreshold Characteristics - Devices comprising, and a method for fabricating, a remote doped high performance transistor having improved subthreshold characteristics are disclosed. In one embodiment a field-effect transistor includes a channel layer configured to convey between from a source portion and a drain portion of the transistor when the transistor is in an active state. Further, the field-effect transistor includes a barrier layer adjacent to the channel layer. The barrier layer comprises a delta doped layer configured to provide carriers to the channel layer of the transistor, while preferably substantially retaining dopants in said delta-doped layer. | 2011-06-23 |
20110147846 | METHOD FOR INCORPORATING IMPURITY ELEMENT IN EPI SILICON PROCESS - The present disclosure provides a method of fabricating a semiconductor device that includes forming a plurality of fins, the fins being isolated from each other by an isolation structure, forming a gate structure over a portion of each fin; forming spacers on sidewalls of the gate structure, respectively, etching a remaining portion of each fin thereby forming a recess, epitaxially growing silicon to fill the recess including incorporating an impurity element selected from the group consisting of germanium (Ge), indium (In), and carbon (C), and doping the silicon epi with an n-type dopant. | 2011-06-23 |
20110147847 | Methods and apparatus to reduce layout based strain variations in non-planar transistor structures - The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming isolation structures in strained semiconductor bodies of non-planar transistors while maintaining strain in the semiconductor bodies. | 2011-06-23 |
20110147848 | Multiple transistor fin heights - The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming transistor fins of differing heights to obtain a performance improvement for a given type of integrated circuit within the microelectronic device. | 2011-06-23 |
20110147849 | INTEGRATED CIRCUIT WITH ELECTROSTATICALLY COUPLED MOS TRANSISTORS AND METHOD FOR PRODUCING SUCH AN INTEGRATED CIRCUIT - An integrated circuit including:
| 2011-06-23 |
20110147850 | CARBON AND NITROGEN DOPING FOR SELECTED PMOS TRANSISTORS ON AN INTEGRATED CIRCUIT - A method of forming an integrated circuit (IC) including a core and a non-core PMOS transistor includes forming a non-core gate structure including a gate electrode on a gate dielectric and a core gate structure including a gate electrode on a gate dielectric. The gate dielectric for the non-core gate structure is at least 2 Å of equivalent oxide thickness (EOT) thicker as compared to the gate dielectric for the core gate structure. P-type lightly doped drain (PLDD) implantation including boron establishes source/drain extension regions in the substrate. The PLDD implantation includes selective co-implanting of carbon and nitrogen into the source/drain extension region of the non-core gate structure. Source and drain implantation forms source/drain regions for the non-core and core gate structure, wherein the source/drain regions are distanced from the non-core and core gate structures further than their source/drain extension regions. Source/drain annealing is performed after source and drain implantation. | 2011-06-23 |
20110147851 | Method For Depositing Gate Metal For CMOS Devices - A semiconductor device comprises a substrate, a channel region, and a gate formed in association with the channel region. In one exemplary embodiment, the gate comprises a first material that is formed void free on an interior surface of a gate trench of the gate. A width of the gate trench comprises between about 8 nm and about 65 nm. The gate comprises a transition metal alloyed with carbon, aluminum or nitrogen, or combinations thereof, to form a carbide, a nitride, or a carbo-nitride, or combinations thereof, of the transition metal. In another exemplary embodiment, the gate further comprises a second material formed void free on an interior surface of the first material and comprises a transition metal alloyed with carbon, aluminum or nitrogen, or combinations thereof, to form a carbide, a nitride, or a carbo-nitride, or combinations thereof, of the transition metal. | 2011-06-23 |
20110147852 | LOW NOISE AND HIGH PERFORMANCE LSI DEVICE, LAYOUT AND MANUFACTURING METHOD - In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate. For example, mechanical stress can be applied to devices that operate in high-speed digital settings, while devices that operate in analog or RF signal settings, in which electrical noise such as flicker noise that may be introduced by applied stress may degrade performance, have no stress applied. | 2011-06-23 |
20110147853 | Method of Forming an Electrical Fuse and a Metal Gate Transistor and the Related Electrical Fuse - The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor. | 2011-06-23 |
20110147854 | INDIUM, CARBON AND HALOGEN DOPING FOR PMOS TRANSISTORS - A method of forming an integrated circuit (IC) having at least one PMOS transistor includes performing PLDD implantation including co-implanting indium, carbon and a halogen, and a boron specie to establish source/drain extension regions in a substrate having a semiconductor surface on either side of a gate structure including a gate electrode on a gate dielectric formed on the semiconductor surface. Source and drain implantation is performed to establish source/drain regions, wherein the source/drain regions are distanced from the gate structure further than the source/drain extension regions. Source/drain annealing is performed after the source and drain implantation. The co-implants can be selectively provided to only core PMOS transistors, and the method can include a ultra high temperature anneal such as a laser anneal after the PLDD implantation. | 2011-06-23 |
20110147855 | DUAL SILICIDE FLOW FOR CMOS - A method for forming a semiconductor device decouples NMOS and PMOS silicide processing and thereby allows independent optimization of at least one characteristic of both NMOS and PMOS devices, and eliminates constraints of using the same silicide process for both NMOS and PMOS, which limits the degree to which the process can be optimized for either technology. | 2011-06-23 |
20110147856 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A fin-type semiconductor region ( | 2011-06-23 |
20110147857 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode. | 2011-06-23 |
20110147858 | METAL GATE STRUCTURE OF A FIELD EFFECT TRANSISTOR - The invention relates to integrated circuit fabrication, and more particularly to a Field Effect Transistor with a low resistance metal gate electrode. An exemplary structure for a gate electrode for a Field Effect Transistor comprises a lower portion formed of a first metal material having a recess and a first resistance; and an upper portion formed of a second metal material having a protrusion and a second resistance, wherein the protrusion extends into the recess, wherein the second resistance is lower than the first resistance. | 2011-06-23 |
20110147859 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a base substrate made of silicon, a cap substrate and a leading electrode having a metal part. The base substrate has base semiconductor regions being insulated and separated from each other at a predetermined portion of a surface layer thereof. The cap substrate is bonded to the predetermined portion of the surface layer of the base substrate. The leading electrode has a first end connected to one of the plurality of base semiconductor regions of the base substrate and extends through the cap substrate such that a second end of the leading electrode is located adjacent to a surface of the cap substrate for allowing an electrical connection with an external part, the surface being opposite to a bonding surface at which the base substrate and the cap substrate are bonded. The leading electrode defines a groove between an outer surface thereof and the cap substrate. | 2011-06-23 |
20110147860 | MICROMECHANICAL STRUCTURE COMPRISING A MOBILE PART HAVING STOPS FOR OUT-OF-PLANE DISPLACEMENTS OF THE STRUCTURE AND ITS PRODUCTION PROCESS - Process for producing a micromechanical structure comprising a substrate and a stack of at least two layers arranged on the substrate, a mobile part formed in the stack and a fixed part relative to the substrate formed in the stack, and an opposite surface formed between the fixed part and the mobile part, forming for example stop means to limit displacement of the mobile part in a direction substantially perpendicular to the stack, which process using at least one sacrificial layer between the substrate and the stack made of material suitable to be etched selectively relative to the materials of the stack. | 2011-06-23 |
20110147861 | MEMS SWITCH AND FABRICATION METHOD - A MEMS switch ( | 2011-06-23 |
20110147862 | MICROMECHANICAL COMPONENT HAVING AN INCLINED STRUCTURE AND CORRESPONDING MANUFACTURING METHOD - In a micromechanical component having an inclined structure and a corresponding manufacturing method, the component includes a substrate having a surface; a first anchor, which is provided on the surface of the substrate and which extends away from the substrate; and at least one cantilever, which is provided on a lateral surface of the anchor, and which points at an inclination away from the anchor. | 2011-06-23 |
20110147863 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes: a sensor element having a plate shape with a surface and including a sensor structure disposed in a surface portion of the sensor element; and a plate-shaped cap element bonded to the surface of the sensor element. The cap element has a wiring pattern portion facing the sensor element. The wiring pattern portion connects an outer periphery of the surface of the sensor element and the sensor structure so that the sensor structure is electrically coupled with an external element via the outer periphery. The sensor element does not have a complicated multi-layered structure, so that the sensor element is simplified. Further, the dimensions of the device are reduced. | 2011-06-23 |
20110147864 | Method for manufacturing a micromechanical diaphragm structure having access from the rear of the substrate - A method for manufacturing a micromechanical diaphragm structure having access from the rear of the substrate includes: n-doping at least one contiguous lattice-type area of a p-doped silicon substrate surface; porously etching a substrate area beneath the n-doped lattice structure; producing a cavity in this substrate area beneath the n-doped lattice structure; growing a first monocrystalline silicon epitaxial layer on the n-doped lattice structure; at least one opening in the n-doped lattice structure being dimensioned in such a way that it is not closed by the growing first epitaxial layer but instead forms an access opening to the cavity; an oxide layer being created on the cavity wall; a rear access to the cavity being created, the oxide layer on the cavity wall acting as an etch stop layer; and the oxide layer being removed in the area of the cavity. | 2011-06-23 |
20110147865 | INTEGRATED HYBRID HALL EFFECT TRANSDUCER - A Hall effect transducer in a semiconductor wafer comprises a first layer of semiconducting material, a second layer of semiconducting material, and a contact structure configured to provide a path for electrical current to pass through the second layer. The second layer has higher electron hole mobility than the first layer, and is epitaxially grown atop the first layer. | 2011-06-23 |
20110147866 | SPIN-CURRENT SWITCHED MAGNETIC MEMORY ELEMENT SUITABLE FOR CIRCUIT INTEGRATION AND METHOD OF FABRICATING THE MEMORY ELEMENT - A method of fabricating a spin-current switched magnetic memory element includes providing a wafer having a bottom electrode, forming a plurality of layers, such that interfaces between the plurality of layers are formed in situ, in which the plurality of layers includes a plurality of magnetic layers, at least one of the plurality of magnetic layers having a perpendicular magnetic anisotropy component and including a current-switchable magnetic moment, and at least one barrier layer formed adjacent to the plurality of magnetic layers, lithographically defining a pillar structure from the plurality of layers, and forming a top electrode on the pillar structure. | 2011-06-23 |
20110147867 | METHOD OF VERTICALLY MOUNTING AN INTEGRATED CIRCUIT - A method of mounting a first integrated circuit ( | 2011-06-23 |
20110147868 | SEMICONDUCTOR DEVICE - In a multi-core semiconductor device, a data bus between CPUs or the like consumes a larger amount of power. By provision of a plurality of CPUs which transmit data by a backscattering method of a wireless signal, a router circuit which mediates data transmission and reception between the CPUs or the like, and a thread control circuit which has a thread scheduling function, a semiconductor device which consumes less power and has high arithmetic performance can be provided at low cost. | 2011-06-23 |