25th week of 2012 patent applcation highlights part 36 |
Patent application number | Title | Published |
20120155152 | STATIC RANDOM ACCESS MEMORY - In a random access memory, one of a first conductivity type well constituting a first bit in one column group and another first conductivity type well constituting a second bit selected simultaneously to the first bit in an adjacent column group, is isolated from a common well of the first conductivity type by providing a deep well of a second conductivity type, such that the area of the deep well of the second conductivity type does not exceed the area of one column group. | 2012-06-21 |
20120155153 | Scalable Magnetic Memory Cell With Reduced Write Current - A magnetic memory cell comprising a magnetoresistive element including a free layer with a changeable orientation of a magnetization oriented substantially perpendicular to a layer plane in its equilibrium state, a pinned layer with a fixed orientation of a magnetization oriented substantially perpendicular to a layer plane, and a tunnel barrier layer disposed between the free and pinned layers; means for providing a bias magnetic field pulse along magnetic hard axis of both the free and pinned layers, means for providing a spin-polarized current pulse through the magnetoresistive element along magnetic easy axis of both the free layer and the pinned layer, wherein the orientation of magnetization in the free layer will be reversed by a collective effect of the bias magnetic field pulse and the spin-polarizing current pulse; and wherein the magnetoresistive element comprises at least one magnetic layer whose magnetization having a perpendicular orientation in its equilibrium state can be tilted by the bias magnetic field to facilitate the magnetization reversal in the free layer by the spin-polarized current. | 2012-06-21 |
20120155154 | Three-Dimensional Magnetic Random Access Memory With High Speed Writing - A magnetic random access memory with perpendicular magnetization comprising a selection transistor with a gate width, that is formed on a substrate and is electrically connected to a word line; a plurality of memory layers sequentially disposed above the substrate, wherein each of the plurality of the memory layers includes a plurality of magnetoresistive elements with perpendicular magnetization and wherein each of the plurality of the magnetoresistive elements comprises an element width and includes at least a pinned layer comprising a fixed magnetization, a free layer comprising a changeable magnetization, and a tunnel barrier layer residing between the pinned layer and the free layer; a plurality of conductor layers disposed alternately with the memory layers beginning with the memory layer positioned adjacent to the substrate, wherein each of the plurality of the conductor layers comprises a plurality of parallel bit lines intersecting the word line, and wherein the bit line is disposed adjacent to the free layer and is electrically connected with the magnetoresistive element; wherein the gate width is substantially larger than the element width, and wherein the magnetoresistive elements of the memory layer are electrically connected in parallel to the selection transistor. | 2012-06-21 |
20120155155 | GENERATING A TEMPERATURE-COMPENSATED WRITE CURRENT FOR A MAGNETIC MEMORY CELL - This disclosure describes write current temperature compensation techniques for use in programming a data storage device that includes one or more memory cells. The techniques may include programming a programmable magnetization state of a magnetoresistive device included within a resistance network based on a signal indicative of the operating temperature of a magnetic memory cell. The techniques may further include generating a write current having a magnitude that is determined at least in part by the programmable magnetization state of the magnetoresistive device. The techniques may further include supplying the write current to the magnetic memory cell for programming a programmable magnetization state of the magnetic memory cell. | 2012-06-21 |
20120155156 | METHOD AND SYSTEM FOR PROVIDING MAGNETIC TUNNELING JUNCTION ELEMENTS HAVING IMPROVED PERFORMANCE THROUGH CAPPING LAYER INDUCED PERPENDICULAR ANISOTROPY AND MEMORIES USING SUCH MAGNETIC ELEMENTS - A method and system for providing a magnetic element and a magnetic memory utilizing the magnetic element are described. The magnetic element is used in a magnetic device that includes a contact electrically coupled to the magnetic element. The method and system include providing pinned, nonmagnetic spacer, and free layers. The free layer has an out-of-plane demagnetization energy and a perpendicular magnetic anisotropy corresponding to a perpendicular anisotropy energy that is less than the out-of-plane demagnetization energy. The nonmagnetic spacer layer is between the pinned and free layers. The method and system also include providing a perpendicular capping layer adjoining the free layer and the contact. The perpendicular capping layer induces at least part of the perpendicular magnetic anisotropy in the free layer. The magnetic element is configured to allow the free layer to be switched between magnetic states when a write current is passed through the magnetic element. | 2012-06-21 |
20120155157 | MAGNETIC RANDOM ACCESS MEMORY APPARATUS, METHODS FOR PROGRAMMING AND VERIFYING REFERENCE CELLS THEREFOR - A magnetic random access memory apparatus includes a memory cell array including a plurality of magnetic memory cells; a reference cell array including a pair of reference magnetic memory cells; a write driver configured to program data in the memory cell array and the reference cell array; and a first switching unit configured to form a current path which extends from a bit line connected to the write driver via the reference cell array including the pair of reference magnetic memory cells to a source line connected to the write driver or a current path which extends from a source line connected to the write driver via the reference cell array including the pair of reference magnetic memory cells to a bit line connected to the write driver. | 2012-06-21 |
20120155158 | STORAGE DEVICE AND WRITING CONTROL METHOD - A storage device is provided with a plurality of pairs of memory blocks, which have a storage layer which stores information and is configured to have a plurality of storage elements which store the information in the storage layer by the orientation of the magnetization of the storage layer being changed in accordance with the application of a writing voltage and so that selective application of the writing voltage is possible in accordance with input information to one storage element, and writing control sections, which store information which is to be written into each of the storage elements in a shift register, output one piece of information from the shift register, determine whether or not writing of the output information succeeds, and when writing has failed, the same information is output again, and when writing is successful, the next piece of information is output from the shift register. | 2012-06-21 |
20120155159 | MULTIBIT MAGNETIC RANDOM ACCESS MEMORY CELL WITH IMPROVED READ MARGIN - A magnetic random access memory (MRAM) cell including a magnetic tunnel junction including a tunnel barrier layer between a first magnetic layer having a first magnetization direction, and a second magnetic layer having a second adjustable magnetization to vary a junction resistance of the magnetic tunnel junction from a first to a second junction resistance level; said magnetic tunnel junction further including a switching resistant element electrically connected to the magnetic tunnel junction and having a switching resistance switchable from a first to a second switching resistance level when a switching current is passed through the switching resistant element, such that a resistance of the MRAM cell can have at least four different cell resistance levels depending of the resistance level of the junction resistance and the switching resistance. The disclosed MRAM cell achieves improved read margin and allows for writing at least four different cell resistance levels. | 2012-06-21 |
20120155160 | MEMORY CONTROLLER AND METHOD FOR INTERLEAVING DRAM AND MRAM ACCESSES - A memory controller and method for interleaving volatile and non-volatile memory different latencies and page sizes are described wherein a single DDR3 memory controller communicates with a number of memory modules comprising of at least non-volatile memory, e.g., spin torque magnetic random access memory, integrated in a different Rank or Channel with a volatile memory, e.g., dynamic random access memory (DRAM). | 2012-06-21 |
20120155161 | THREE-TERMINAL OVONIC THRESHOLD SWITCH AS A CURRENT DRIVER IN A PHASE CHANGE MEMORY - A three-terminal Ovonic Threshold Switch (OTS) is used to provide current to a Phase Change Memory Switch (PCMS) cross point array. The current is started by sending a small current into the second terminal of the three-terminal OTS allowing a larger current to flow from the first terminal to the third terminal of the three-terminal OTS. A method of making the three-terminal OTS is also presented. | 2012-06-21 |
20120155162 | SEMICONDUCTOR STORAGE APPARATUS OR SEMICONDUCTOR MEMORY MODULE - A semiconductor storage apparatus provides a large capacity phase-change memory possessing high speed operation, low electrical current, and high-reliability. During the period that a read-out start signal is activated in the memory region control circuit and the block of pairs of sense-latch and write driver is performing the verify read in the upper section memory region; the write enable signals in the memory region control circuit are activated and the block of pairs of sense-latch and write driver perform rewrite operation of the data in the lower section memory region. This type of operation allows cancelling out the time required for the verify read and the time required for the time-division write operation by performing the verify read in one memory region, while performing time-division rewrite in other memory region, to achieve both higher reliability rewrite operation along with suppressing the rewrite operation peak electrical current. | 2012-06-21 |
20120155163 | REDUCING PROGRAMMING TIME OF A MEMORY CELL - The present invention provides methods and apparatus for adjusting voltages of bit and word lines to program a two terminal memory cell. The invention may include setting a first line connected to a memory cell to a first voltage from a first line standby voltage, charging a second line connected to the memory cell to a predetermined voltage from a second line standby voltage, and switching the first line from the first voltage to a second voltage. The voltage difference between the first voltage and the predetermined voltage is such that a safe voltage results that does not program the memory cell. A voltage difference between the second voltage and the predetermined voltage is such that a programming voltage operative to program the memory cell results. | 2012-06-21 |
20120155164 | Multibit Cell of Magnetic Random Access Memory With Perpendicular Magnetization - A multi-bit cell of magnetic random access memory comprises a magnetic tunnel junction element including a first and second free layer comprising a changeable magnetization oriented substantially perpendicular to a layer plane in its equilibrium state and a switching current, a first and second tunnel barrier layer, and a pinned layer comprising a fixed magnetization oriented substantially perpendicular to a layer plane, the pinned layer is disposed between the first and second free layers and is separated from the free layers by one of the tunnel barrier layers, a selection transistor electrically connected to a word line, and a bit line intersecting the word line. The magnetic tunnel junction element is disposed between the bit line and the selection transistor and is electrically connected to the bit line and the selection transistor, wherein the first and second free layers have substantially different switching currents. | 2012-06-21 |
20120155165 | MEMORY - An embodiment of the invention relates to a memory comprising a strained double-heterostructure having an inner semiconductor layer which is sandwiched between two outer semiconductor layers, wherein the lattice constant of the inner semiconductor layer differs from the lattice constants of the outer semiconductor layers, the resulting lattice strain in the double-heterostructure inducing the formation of at least one quantum dot inside the inner semiconductor layer, said at least one quantum dot being capable of storing charge carriers therein, and wherein, due to the lattice strain, the at least one quantum dot has an emission barrier of 1.15 eV or higher, and provides an energy state density of at least three energy states per 1000 nm | 2012-06-21 |
20120155166 | Alternate Page By Page Programming Scheme - An alternate page by page scheme for the multi-state programming of data into a non-volatile memory is presented. Pages of data are written a page at a time onto word lines of the memory. After all of the pages of data are written to a first level of resolution onto one word line, the memory goes back to the adjacent word line (on which all of the pages of data have previously been written the first level of resolution) and refines the accuracy with which the data had been written on this preceding word line. This can reduce the effects on the data of capacitive coupling between the word lines. | 2012-06-21 |
20120155167 | NON-VOLATILE STORAGE DEVICE, INFORMATION PROCESSING SYSTEM AND WRITE CONTROL METHOD OF NON-VOLATILE STORAGE DEVICE - A non-volatile storage device has a non-volatile memory, a capacity determination part configured to determine whether data amount stored into the non-volatile memory exceeds a first threshold value, an area dividing determination part configured to provide a first storage area for writing one bit data to one memory cell and a second storage area for writing multiple bit data to one memory cell in storage areas of the non-volatile memory, a first write control part configured to write data into the first storage area by a first writing mode until the capacity determination part determines that the first threshold value has been exceeded, a data selector configured to select data that frequency of access does not reach a predetermined reference value among data stored into the non-volatile memory when the capacity determination part determines that the first threshold value has been exceeded, and a second write control part configured to temporarily save data selected by the data selector from the first storage area to write the saved data to the second storage area by a second writing mode. | 2012-06-21 |
20120155168 | NEGATIVE VOLTAGE GENERATOR, DECODER, NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM USING NEGATIVE VOLTAGE - A negative voltage generator includes a direct current voltage generator configured to generate a direct current voltage, a reference voltage generator configured to generate a reference voltage, an oscillator configured to generate an oscillation clock, a charge pump configured to generate a negative voltage in response to a pump clock, and a voltage detector. The voltage detector is configured to detect the negative voltage by comparing a division voltage, obtained by voltage dividing the direct current voltage, with the reference voltage, and to generate the pump clock corresponding to the detected negative voltage based on the oscillation clock. | 2012-06-21 |
20120155169 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A nonvolatile semiconductor storage device storing plural data bits in one memory cell by assigning multivalued data having a higher-order bit selected from one of a pair of data in a first unit and a lower-order bit selected from the other of the pair of data. In a first write operation processing data in the first unit, logic of one of the higher-order and the lower-order bit is fixed, and two multivalued data that maximize the difference between the threshold voltages are assigned, thereby storing one bit of input data in the memory cell in a pseudo binary state. In a second write operation processing data in a second unit larger than the first unit, plural input data bits in a multivalued state and parity data for error correction in the second unit are stored in the memory cell. | 2012-06-21 |
20120155170 | NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A multi-layered non-volatile memory device and a method of manufacturing the same. The non-volatile memory device may include a plurality of first semiconductor layers having a stack structure. A plurality of control gate electrodes may extend across the first semiconductor layers. A first body contact layer may extend across the first semiconductor layers. A plurality of charge storage layers may be interposed between the control gate electrodes and the first semiconductor layers. | 2012-06-21 |
20120155171 | MEMORY SYSTEM - According to one embodiment, a memory system includes a nonvolatile first memory configured to store a boot program, a volatile second memory, a detection circuit configured to detect a level of a power supply voltage, and to generates an interrupt when the power supply voltage becomes less than a first level, and a state machine configured to execute a sequence including a first read operation for reading the boot program from the first memory and a transfer operation for transferring the read boot program to the second memory at power-on. The state machine includes a waiting state for waiting until the interrupt is deactivated when the interrupt is activated during the first read operation or the transfer operation. | 2012-06-21 |
20120155172 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a first memory and a second memory, a data path between the first memory and the second memory, a register configured to store first data transferred through the data path in a first direction, and a comparison circuit configured to compare second data transferred through the data path in a second direction with the first data stored in the register so as to detect a fault location. | 2012-06-21 |
20120155173 | Universal Timing Waveforms Sets to Improve Random Access Read and Write Speed of Memories - Methods of increasing the speed of random read and write operations of a memory device are provided for improving the performance of volatile and non-volatile memory devices. In contrast to the conventional approach that latches the current memory address right before the currently accessed memory data are outputted, the methods latch the next memory address before the currently accessed memory data are read out. The flow, timing waveforms and control sequences of applying the methods to parallel NOR flash, parallel pSRAM, serial SQI NOR flash and NAND flash are described in detail. The NOR flash device designed with the method can be integrated with a NAND flash device on a same die in a combo flash device packaged in either an ONFI compatible NAND flash package or other standard NAND flash package. | 2012-06-21 |
20120155174 | Use of Alternative Value in Cell Detection - A system and method, including computer software, allows reading data from a flash memory cell. Voltages from a group of memory cells are detected. The group of memory cells have associated metadata for error detection, and each memory cell stores a voltage representing a data value selected from multiple possible data values. Each possible data value corresponds to one range of multiple non-overlapping ranges of analog voltages. Memory cells having uncertain data values are identified based on the detected voltages. Alternative data values for the memory cells having the uncertain data values are determined, and a combination of alternative data values is selected. An error detection test is performed using the metadata associated with the multiple memory cells and the selected combination of alternative data values. | 2012-06-21 |
20120155175 | FLASH MEMORY DEVICE AND OPERATION METHOD THEREOF - A method for operating a flash memory device includes storing a first command and a first address corresponding to a first plane, storing a second command and a second address corresponding to a second plane, and performing a first command operation for the first plane based on the first command and the first address and performing a second command operation for the second plane based on the second command and the second address, wherein the first address includes a first block address for selecting a block in the first plane, and the second address includes a second block address for selecting a block in the second plane. | 2012-06-21 |
20120155176 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a first conductive type well and a second conductive type well disposed on and/or over a semiconductor substrate; a first gate and a second gate disposed on and/or over the first conductive type well and the second conductive type well, respectively; a second conductive type first ion implantation region disposed in the first conductive type well at one side of the first gate and a second conductive type second ion implantation region disposed in the first conductive type well at the other side of the first gate; a first conductive type first ion implantation region disposed in the second conductive type well at one side of the second gate and a first conductive type second ion implantation region disposed in the second conductive type well at the other side of the second gate; and a line electrically connecting the second conductive type second ion implantation region with the first conductive type first ion implantation region. | 2012-06-21 |
20120155177 | STRUCTURES AND METHODS FOR READING OUT NON-VOLATILE MEMORY USING REFERENCING CELLS - The structures and methods of reading out semiconductor Non-Volatile Memory (NVM) using referencing cells are disclosed. The new invented scheme can reduce large current consumption from the direct current biasing in the conventional scheme and achieve a high resolution on the cell threshold voltage with a good sensing speed. | 2012-06-21 |
20120155178 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory, and a data transfer section configured to perform data transfer from and to the memory, and having a first mode to transfer data with a first bit width and a second mode to transfer data with a second bit width. The data transfer section includes a first latch circuit configured to hold first data read from the memory, a second latch circuit configured to hold second data having the first bit width of the first data in the first mode, and to hold third data having the second bit width of the first data in the second mode, and data bus connecting the first latch circuit to the second latch circuit and shared by the first and second modes. | 2012-06-21 |
20120155179 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory cell array having memory cells, word lines connected to the memory cell array, a generation circuit configured to generate voltages required for operations of the memory cell array, selection circuits connected to the word lines, respectively, each of the selection circuits being configured to select a voltage applied to a word line from the voltages, and a transfer unit configured to transfer items of control data for selecting the voltage to the selection circuits, respectively. The transfer unit includes transfer circuits which shift an enable signal in sequence. The transfer circuits include latch circuits which hold the items of control data based on the shifted enable signal, respectively. | 2012-06-21 |
20120155180 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING A NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a memory cell array including a plurality of bitlines, a plurality of wordlines, and a plurality of memory cells. The memory device further includes a plurality of page buffers coupled to the respective bitlines of the memory cell array, each page buffer including a latch configured to store data to be written into and read from a memory cell coupled to a respective bitline of the memory cell array. The memory device further includes a control circuit configured to execute an over-program verify operation which includes detecting an over-programmed memory cell among the plurality of memory cells with reference to pass/fail data stored in the respective latches of the plurality of page buffers, and decreasing a threshold voltage of a detected over-programmed memory cell while maintaining a threshold voltage of memory cells which have not been detected as being over-programmed. | 2012-06-21 |
20120155181 | Method and Apparatus for Reducing Read Disturb in Memory - Various aspects of a NAND memory include have multiple versions of a high threshold voltage distribution—a version with a reduced maximum, and another version. The version with a reduced maximum has a reduced word line pass voltage. | 2012-06-21 |
20120155182 | NON-VOLATILE MEMORY DEVICE AND CACHE PROGRAM METHOD OF THE SAME - A cache programming method for a non-volatile memory device includes programming data for a current programming operation into a memory cell array, determining whether the current programming operation has been performed to a threshold point of program completion, and receiving a data for a next programming operation when the current programming operation has been performed to the threshold point of program completion. | 2012-06-21 |
20120155183 | METHOD OF SOFT PROGRAMMING SEMICONDUCTOR MEMORY DEVICE - An operating method of a semiconductor memory device includes erasing all memory cells of a selected cell block, performing a soft program operation on the erased memory cells by supplying a soft program pulse to word lines of the selected cell block, performing a first verify operation using a first voltage level lower than a target voltage level of the soft program operation, performing a second verify operation using the target voltage level, setting voltages of bit lines, and repeating the soft program operation, the first verify operation, the second verify operation, and an operation of setting the voltages of bit lines while raising the soft program pulse gradually. | 2012-06-21 |
20120155184 | FLASH MEMORY DEVICE HAVING DUMMY CELL - A nonvolatile semiconductor memory device includes a string selection transistor coupled to a bit line. The device also includes a plurality of memory cells coupled in series to the string selection transistor, wherein at least one of the memory cells is configured to be in a programmed state during an erase procedure of the plurality of memory cells. | 2012-06-21 |
20120155185 | MEMORY DEVICE AND CORRESPONDING READING METHOD - An electrically erasable and programmable non-volatile memory device includes memory cells arranged in rows and columns, and each column of memory cells is associated with a respective local bit line. The local bit lines are divided into packets of local bit lines, each packet of local bit lines associated with a respective main bit line. Each local bit line is selectively couplable to the respective main bit line by a corresponding selector. Each local bit line is selectively couplable to a reference terminal, for receiving a reference voltage, by a corresponding discharge selector. Each discharge selector is active when the memory device is in a standby state. The non-volatile memory device further includes biasing circuitry to bias each main bit line to a pre-charge voltage during operation, and reading circuitry to select and access a group of memory cells during reading operations. | 2012-06-21 |
20120155186 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device operate during a program verification operation to apply a read voltage to a word line and a pre-charge voltage to a bit line in order to provide output data. A number of fail cells is determined in view of the output data, wherein the number of fail cells is directly related to an increase in voltage on a common source line (CSL) connected to memory cells providing the output data. During a subsequent program verification operation, the level of at least one of the read voltage and the pre-charge voltage is adjusted in response to the number of fail cells. | 2012-06-21 |
20120155187 | Adaptive Programming for Flash Memories - A method to adjust the programming voltage in flash memory when the programming time exceeds specification. A method to adjust the programming voltage of flash memory after a predetermined number of erase/write cycles. | 2012-06-21 |
20120155188 | REDUCED POWER CONSUMPTION MEMORY CIRCUITRY - In a circuit that reduces power consumption in an array system of memory cells accessible in parallel, a local evaluation circuit is connected to a memory cell and a global bit line of the array system of memory cells. A selection circuitry splits the global bit line into an upper part and a lower part of the global bit line. The selection circuitry is adapted to receive an early set prediction signal and to connect the upper part of the global bit line to the lower part of the global bit line based on the early set prediction signal. The early set prediction signal indicates whether a set of memory cells, which include the memory cell, is being read. The circuit also includes a N:1 multiplexer connected to the lower part of the global bit line to receive the lower part of the global bit line as input. | 2012-06-21 |
20120155189 | System and Method for Level Shifter - In one embodiment, a bit-line interface is disclosed. The bit-line interface has a multiplexer having a plurality of bit-line outputs, and a write path coupled to a multiplexer signal input. The bit-line interface also has a read path coupled to the multiplexer signal input, wherein the read path and the write path share at least one component. | 2012-06-21 |
20120155190 | PAGE BUFFER CIRCUIT - A page buffer circuit includes: a main latch unit configured to have a main latch value which is dependent on a sub latch output signal, and output the main latch value to a first node; a sub latch unit configured to latch a voltage of a second node as a sub latch value in response to a storage enable signal, and generate the sub latch output signal according to the sub latch value when an output enable signal is activated; and a voltage determination unit connected between the first node and the second node, and configured to electrically connect or disconnect the first node to or from the second node in response to the storage enable signal, and determine a voltage level of the second node in response to the storage enable signal. | 2012-06-21 |
20120155191 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a first memory configured to receive a first clock and including a first buffer configured to perform a data input operation and a data output operation, a second memory including a second buffer configured to perform a data input operation and a data output operation, and a data bus configured to connect the first buffer and the second buffer. The first memory transfers a second clock to the second memory using the first clock. The first buffer transfers data to the second memory in response to the first clock. The second buffer receives the data from the first buffer in response to the second clock. | 2012-06-21 |
20120155192 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF TESTING THE SAME - A semiconductor memory device and a method of testing the same are provided. The semiconductor memory device includes a memory cell array including a plurality of memory cells each of which stores at least one bit of data; an output terminal configured to transmit output data; and a data output circuit configured to be connected with the output terminal, to divide a cycle of a clock signal into at least two periods, to transmit the output data to the output terminal only during a particular period among the at least two periods, and to put the output terminal into a state of high impedance during the remaining periods other than the particular period among the at least two periods. | 2012-06-21 |
20120155193 | BURST TERMINATION CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME CROSS-REFERENCES TO RELATED APPLICATION - A semiconductor memory device includes a burst termination control unit and a data output control unit. The burst termination control unit generates a termination control signal, a read command, a write command and a mode resister read command. The data output control unit stops a data output operation in response to the termination control signal. | 2012-06-21 |
20120155194 | Wordline voltage control within a memory - A memory circuit | 2012-06-21 |
20120155195 | OVERLAPPING INTERCONNECT SIGNAL LINES - Described herein are various principles for designing, manufacturing, and operating integrated circuits having functional components and one or more metal interconnect layers, where the dimensions of signal lines of the metal interconnect layers are larger than dimensions of the functional components. In some embodiments, a signal line may have a width greater than a width of a terminal of a functional component to which the signal line is connected. In some embodiments, two functional components formed in a same functional layer of the integrated circuit may be connected to metal signal lines in different metal interconnect layers. Further, the metal signal lines of the different metal interconnect layers may overlap some distance. | 2012-06-21 |
20120155196 | Semiconductor memory and manufacturing method - A semiconductor memory includes a memory cell array that includes data cells of x bits and redundant cells of y bits for each word; a position-data storage unit that stores, for each word, defective-cell position data of defective cells of the data cells and the redundant cells; and a read circuit that reads data from cells of x bits based on the defective-cell position data stored in the position-data storage unit for a specified word of which address is specified as read address, the cells of x bits being formed by the data cells of x bits and the redundant cells of y bits of the specified word other than the defective cells. | 2012-06-21 |
20120155197 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - A semiconductor memory device includes a page buffer configured to store data read from a memory cell, a counter circuit configured to count the number of first data or second data in the read data for every read operation while the read operations are repeated a set number of times, and a control logic configured to determine the number of read operations and determine the read data of the memory cell based on the counted number. | 2012-06-21 |
20120155198 | SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a read bit line is driven based on data read out from a memory cell. A read port drives the read bit line based on data stored in a storage node. A read word line performs row selection via the read port at a time of reading from the memory cell. A coupling driver assists a write operation to the memory cell by controlling a potential of the storage node via the read port. | 2012-06-21 |
20120155199 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus may include a bonding pad; a control signal pad; and an operation mode signal generation unit configured to generate a plurality of operation mode signals in response to a bonding signal inputted through the bonding pad and a control signal inputted through the control signal pad. | 2012-06-21 |
20120155200 | MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND CONTROL METHOD THEREOF - A memory system includes a memory device, a control device configured to control the memory device, a first channel configured to transfer a row command from the control device to the memory device, and a second channel configured to transfer a column command from the control device to the memory device. | 2012-06-21 |
20120155201 | SYSTEM AND METHOD FOR HIDDEN REFRESH RATE MODIFICATION - A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data at a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration. | 2012-06-21 |
20120155202 | DEFECTIVE MEMORY CELL ADDRESS STORAGE CIRCUIT AND REDUNDANCY CONTROL CIRCUIT INCLUDING THE SAME - A fail address storage circuit includes a fail address storage unit configured to store a fail address and a discrimination information storage unit configured to store information indicating whether a value stored in the fail address storage unit is a row address or column address. | 2012-06-21 |
20120155203 | SEMICONDUCTOR MEMORY DEVICE, METHOD OF TESTING THE SAME AND SYSTEM OF TESTING THE SAME - A method of testing a semiconductor memory device comprises receiving a clock, addresses, commands, and data from a test device through channels, generating an internal bank address in response to the addresses and the commands, performing a multi-bit parallel test for each of a plurality of banks based on the addresses, the commands, the data, and the internal bank address, and providing the test device with a test result signal. | 2012-06-21 |
20120155204 | SEMICONDUCTOR MEMORY APPARATUS HAVING A PRE-DISCHARGING FUNCTION, SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME, AND METHOD FOR DRIVING THE SAME - A semiconductor memory apparatus includes a bit line coupled to a plurality of memory cells, a discharge controller configured to generate a bit line discharge signal to pre-discharge the bit line before the memory cells are activated, and a bit line discharge block coupled to the bit line and configured to discharge the bit line in response to the bit line discharge signal. | 2012-06-21 |
20120155205 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor memory apparatus includes a buffer control unit configured to deactivate a buffer control signal in response to an auto-refresh start pulse, and activate the buffer control signal in response to an auto-refresh end pulse, a command buffer configured to buffer an external command and output an internal command when the buffer control signal is activated, an address buffer configured to buffer an external address and output an internal address when the buffer control signal is activated, and a clock buffer configured to buffer an external clock and output an internal clock when the buffer control signal is activated. | 2012-06-21 |
20120155206 | SEMICONDUCTOR DEVICE PERIODICALLY UPDATING DELAY LOCKED LOOP CIRCUIT - Such a device is disclosed that includes a control circuit outputting a first clock signal having a first clock cycle in response to a first command signal and outputting a second clock signal having a second clock cycle in response to a second command signal, a first circuit controlled based on the first clock signal, and a second circuit controlled based on the second clock signal. | 2012-06-21 |
20120155207 | SEMICONDUCTOR DEVICE GENERATING INTERNAL VOLTAGE - Such a device is disclosed that includes an internal voltage generating circuit generating an internal voltage by lowering an external potential and supplying the generated internal voltage to a power supply line, a switch being connected between a grounding wire to which a ground voltage is supplied and the power supply line, and a one-shot signal generating unit controlling turning on and off of the switch, wherein the one-shot signal generating unit brings the switch into conduction synchronously with start of generating the internal voltage by the internal voltage generating circuit. | 2012-06-21 |
20120155208 | NEGATIVE HIGH VOLTAGE GENERATOR AND NON-VOLATILE MEMORY DEVICE INCLUDING NEGATIVE HIGH VOLTAGE GENERATOR - A negative high voltage generator includes a charge providing unit and a voltage conversion unit. The charge providing unit is configured to periodically output a predetermined amount of positive charges received from a supply voltage. The voltage conversion unit is configured to store the positive charges and to discharge the stored positive charges to a ground voltage to generate a negative high voltage having a magnitude larger than a magnitude of the supply voltage. | 2012-06-21 |
20120155209 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is configured to have a first memory cell array having a plurality of blocks (cell arrays corresponded to one I/O bit), each block having a plurality of columns and being corresponding respectively to one of data terminals, wherein the blocks being arranged side by side in the column-wise direction, and a second memory cell array configured similarly to the first memory cell array, and is also configured to assign addresses while classifying the even-number-th memory blocks in the first memory cell array and the odd-number-th memory blocks in the second memory cell array into a first set, whereas the odd-number-th memory blocks in the first memory cell array and the even-number-th memory blocks in the second memory cell array into a second set, so as to output data from every other block in each memory cell array upon being accessed with a certain address. | 2012-06-21 |
20120155210 | PHYSICAL ORGANIZATION OF MEMORY TO REDUCE POWER CONSUMPTION - Controllable arrays in a memory may be activated and deactivated independently. In one embodiment, a processor may include a memory. The memory may be a de-interleaved memory with independently selectable arrays. Based on an address bit of an address used to access data from the memory, a wordline and downstream components may be activated while another wordline and downstream components may be deactivated. | 2012-06-21 |
20120155211 | SEMICONDUCTOR INTEGRATED CIRCUIT - A memory macro includes: a plurality of memory cells arranged in a matrix; a plurality of word lines corresponding to rows of the plurality of memory cells; and a plurality of word line drivers configured to drive the plurality of word lines. The voltage of the word lines in their activated state is set to vary with threshold voltage characteristics of a p-channel transistor and an n-channel transistor. | 2012-06-21 |
20120155212 | SEMICONDUCTOR DEVICE GENERATING A CLOCK SIGNAL WHEN REQUIRED - Such a device is disclosed that includes a clock generation circuit generating a first clock signal and having an output node, and a drive circuit coupled to the output node of the clock generation circuit. The clock generation circuit outputs the first clock signal from the output node to the drive circuit in a clock output mode, fixes a potential of the output node to a first level in a first clock stop mode, and fixes the potential of the output node to a second level that is different from the first level in a second clock stop mode. | 2012-06-21 |
20120155213 | LILAH - This is a mixing device that is used to combine two or more substances to produce a unified mixture. The device has a vertical chamber that can vary in sizes dependent upon the container that it is used in. The vertical chamber has an attached base that is slightly curved upward to allow adequate mixing of the substances. The base is curved only enough to assist the mixtures from settling to the bottom of the container. | 2012-06-21 |
20120155214 | DEVICE TO PREPARE AND ADMINISTER A TWO-COMPONENT MIXTURE - A device to prepare and administer a two-component mixture, including a first chamber in which a container is housed that is hermetically closed for a liquid component, a second chamber containing a powdered component, an opening of the container of the liquid component, a mixing member placed in the second chamber for preparing the mixture and a piston able to move in the second chamber to dispense the mixture. The mixing member includes a stem, passing through an opening for dispensing the mixture in the second chamber, having an outer end equipped with a handle and an inner end provided with a mixing blade connected to the inner end with a releasable connection. | 2012-06-21 |
20120155215 | RING MIXER - Embodiments relate to a mixing device including a mixer body and a mixing bowl. The mixer body has a circular housing defining at least one hole therein and contains a drive assembly. The mixing bowl defines a mixing bowl rotational axis and is removably connected to the mixer body, the mixing bowl is adapted to receive a mixing system defining a mixing system rotational axis and is removably connected to the drive assembly, the drive assembly rotates the mixing system about the mixing bowl rotational axis while simultaneously rotating the mixing system about the mixing system rotational axis. | 2012-06-21 |
20120155216 | DISPOSABLE VORTEX BREAKER - The present invention consists of a closed presterilized bag having a disposable mixing element within it, a drive mechanism outside of the bag for rotating the mixing element without voiding sterility and a vortex breaker in the torm of one or more plastic sheet materials that are attached to various inner surfaces of the bag and disrupt the formation of vortices within the bag. Preferably the sheet(s) are formed of the same material as the bag and are sealed to the bag surfaces. More preferably, the sheet(s) extend across a diameter of the bag. Most preferably, the sheet(s) are perforated with one or more slits or openings to allow for good flow and mixing without a vortex being formed. | 2012-06-21 |
20120155217 | SEISMIC ACQUISITION USING NARROWBAND SEISMIC SOURCES - There is provided herein a system and method of seismic data collection for land and marine data that utilizes narrowband to monochromatic low-frequency non-impulsive sources designed to optimize the ability of migration/inversion algorithms to image the subsurface of the Earth, in particular, full-waveform inversion. | 2012-06-21 |
20120155218 | SEPARATING INTERFERING SIGNALS IN SEISMIC DATA - A method for processing seismic data. The method may include receiving seismic data due to a plurality of seismic sources and applying a first operator to the seismic data in an i | 2012-06-21 |
20120155219 | System and Method for Acoustic Recording in Well Bottomhole Assembly while Firing A Perforating Gun - A sensing and data recording downhole system and method for monitoring of firing of a perforating gun system in a well, including a perforating gun system having charges or bullets for performing well perforation; and one or more downhole recorders and/or one or more fluid detection sensors located above, along, below or in array on the perforating gun system or inside the perforating gun system on a conveyance and configured to at least one of record sound waves generated by explosions of the charges or bullets during the firing of the perforating gun system and detect a presence of fluid within a body of the perforating gun system before and after guns of the perforating gun system are fired. | 2012-06-21 |
20120155220 | SYSTEM FOR TRANSFERRING WIRELESS POWER USING ULTRASONIC WAVE - Disclosed is a system of transferring wireless power using an ultrasonic wave, including: an ultrasonic wave generating device converting and transferring electric energy to an ultrasonic wave; and an ultrasonic wave receiving device receiving the ultrasonic wave to convert the ultrasonic wave to electric energy, wherein the ultrasonic wave generating device includes a radiation plate with a plurality of ultrasonic elements and controls an effective area of the radiation plate by turning on/off the plurality of ultrasonic elements so that the ultrasonic wave receiving device is disposed at a position minimizing dispersion effect due to a circular radiation of the ultrasonic wave. | 2012-06-21 |
20120155221 | ACOUSTIC TRANSMISSION - In apparatus for the acoustic transmission of power or data through a solid barrier such as a ships hull, assembly of an acoustic transducer to the hull is facilitated by bonding it first to an intermediate element by a thin layer of bonding adhesive and then bonding the intermediate element to the barrier using a second bonding layer. Acoustic matching of the transducer to the intermediate element is achieved by the thin layer, and the mechanically more robust base of the intermediate element can be rubbed on the barrier surface to displace or abrade away any unwanted debris or imperfections which might otherwise prevent the achievement of a thin second bonding layer. This makes the mounting and bonding process more tolerant of imperfections in the barrier surface due to either surface defects or particulate contamination. The transmit and receive transducers may be positioned relative to each other so as to suppress or attenuate multiple-transit signals. Thus the intermediate element may be wedge shaped to aid suppression of triple-transit signals. Transmit and receive transducers may have different wedge angles. | 2012-06-21 |
20120155222 | Method and apparatus for terminating rope and its application to seismic streamer strength members - A termination for an end of a braid formed as a flat closed loop of braided strands expandable to an annular cylinder having a selected wall thickness includes a sleeve having a selected internal diameter. Spacers are configured to be applied on the braid such that when in contact with each other form an annular cylinder having an external diameter selected to fit inside the sleeve. The spacers have a bevel at one longitudinal end. A substantially cylindrical insert has a bevel at one longitudinal end at substantially a same bevel angle as on the spacers. A diameter of the insert combined with twice the wall thickness of the braid is larger than an internal diameter the spacers. When axial tension is applied to the braid, the bevel on the insert with braid thereon laterally urges the spacers outward. The sleeve limits lateral outward movement of the spacers. | 2012-06-21 |
20120155223 | INERTIAL MOTION OF A MECHANICAL DISPLAY MEMBER - Coupling device | 2012-06-21 |
20120155224 | WATERPROOF WRIST WORN ELECTRONIC DEVICE - A wrist worn electronic device includes a hollow casing including an internal protruding tab defining a groove. A display panel is arranged within the hollow casing. A touch panel is arranged on the display panel and is larger than the display panel. The touch panel includes a margin portion around the display panel and rests on the protruding tab. The margin portion is connected to the protruding tab by waterproof adhesive. The groove accommodates waterproof adhesive to form a sealing layer to prevent water from entering the casing. | 2012-06-21 |
20120155225 | TIMEPIECE FACEPLATE AND TIMEPIECE - To provide a timepiece faceplate presenting a furred appearance that has been impossible to achieve in the past, and to provide a timepiece provided with the timepiece faceplate. A timepiece faceplate | 2012-06-21 |
20120155226 | GOLFING ACCESSORY TIME PIECE - A golfing time-keeping apparatus is arranged to indicate time of day using a clock face and a movement which has at least a minute hand arranged to complete a revolution of the clock face every hour. The time piece includes means for indicating a plurality of subdivisions of a time period longer than 1 hour and shorter than 5 hours, the means comprising an indicator having a plurality of markings arranged for general visual alignment with the minute hand. The markings include a sequence of indicia circumferentially spaced apart and continuing for more than one but no more than five revolutions wherein some of the later indicia in the sequence are interleaved with some of the earlier indicia. | 2012-06-21 |
20120155227 | WATCH STRIKING MECHANISM - The watch striking mechanism ( | 2012-06-21 |
20120155228 | Manufacturing method of timepiece part and timepiece part - A manufacturing method of a timepiece part which has small variation in hardness and a metallic luster is provided. Configuration includes a heat treatment process that heat-treats a timepiece part and coarsens a plurality of crystals of titanium or the like, a shape processing process that processes the shape of the timepiece part, an etching process that etches titanium or the like, mirror-finishes the surfaces of each crystal, and makes the normal directions of the surfaces of each crystal to be different from one another, and an anodizing process that performs anodizing on the surface of the timepiece part. | 2012-06-21 |
20120155229 | Decorative part, timepiece, and manufacturing method of decorative part - A decorative part, a timepiece, and a manufacturing method of the decorative part capable of stabilizing and improving the aesthetic appearance while using a fixing member are provided. In an oscillating weight which includes a body of an oscillating weight and screws for fixing the body of the oscillating weight to a weight, the body of the oscillating weight and the screws are a member to which an anodizing can be applied. | 2012-06-21 |
20120155230 | Thermal expansion compensator for liquid-filled watches - A watch comprises a case, an electronic movement module inside the case, a piece of closed-cell foam inside the case, and a dielectric liquid filling the remaining voids of the interior of the case. The closed-cell foam compensates for thermal expansion of the dielectric liquid over a wide range of operating temperatures. Upon heating, the liquid expands and the foam is compressed. Upon cooling, the liquid contracts and the foam is decompressed. | 2012-06-21 |
20120155231 | SHOCK ABSORBER BEARING FOR A ROTATING WHEEL SET OF A TIMEPIECE MOVEMENT - The timepiece movement includes a shock absorber bearing ( | 2012-06-21 |
20120155232 | Directional waveguide coupler for ABS reflected light - A waveguide structure for a TAMR head is disclosed wherein at least one detection waveguide is formed parallel to a main waveguide and located a gap distance therefrom. A light source transmits light into the main waveguide and towards an ABS/medium interface. A plasmon generator converts light from the waveguide into plasmon waves that are directed onto a magnetic medium. Back reflected light is captured by the main waveguide, partially diverted into a detection waveguide, and transmitted to a photo detector that measures light intensity (I | 2012-06-21 |
20120155233 | METHOD FOR COPY PROTECTION - A method for copy protection in which an audiovisual or audio data is divided into a plurality of portions. The plurality of portions is at least partly scrambled and prepared so as to be stored on a record carrier in the scrambled order. This is done so that a physical position on the record carrier, e.g., a sector of the record carrier, where a respective portions of the divided data is stored depends on the scrambled order. | 2012-06-21 |
20120155234 | RECORDING METHODS AND DEVICES FOR RECORDING INFORMATION ON DUAL LAYER RECORDABLE DISKS - The invention relates to recording methods for recording information on a dual layer recordable disk, and to corresponding recording devices. In one such method and recording device the OPC-area is variably located on a layer of the disk. In a preferred embodiment the OPC-area is located relative close to the radius where the data stream switches from the first layer to the second layer. This reduced additional time required for jumping to a fixed OPC-area. Furthermore, in another such method and device the information to be recorded is equally divided over both layers of the dual layer disc. This avoids additional time required for finalization. | 2012-06-21 |
20120155235 | METHOD AND DEVICE FOR RETRIEVING INFORMATION FROM AN OPTICAL RECORD CARRIER AT VARIOUS READING SPEEDS - The present invention is related to a method and a reading device ( | 2012-06-21 |
20120155236 | RECORDING AND/OR REPRODUCING APPARATUS, RECORDING AND/OR REPRODUCING METHOD AND INFORMATION STORAGE MEDIUM THEREFOR - A recording and/or reproducing apparatus, a recording and/or reproducing method, and an information storage medium, wherein the recording and/or reproducing apparatus includes: a writing and/or reading unit writing data to or reading data from an information storage medium having one or more information recording layers; and a control unit controlling the writing and/or reading unit to write the data to the information storage medium by referring to one or more disk information structures including recording related parameter information corresponding to recording characteristics of the information storage medium, and recording characteristic information to which the recording related parameters are applied. According to the apparatus and method, parameters of recording characteristics appropriate to a recording and/or reproducing apparatus and compatibility between different specifications can be achieved. | 2012-06-21 |
20120155237 | Optical Information Record/Playback Device - An optical information record/playback device of the present invention includes: a light source; a current driver for supplying current to the light source; an optical system for condensing light from the light source onto a recording medium; a monitoring section for monitoring light emission power of the light source; a current driver control section for controlling output current of the current driver; and an arithmetic/control section for controlling an operation of the current driver control section. Before recording information, the arithmetic/control section sequentially conducts a first test light-emission to cause the light source to emit light by using a closed loop circuit and a second test light-emission to cause the light source to emit light by using an open loop circuit, and compares first and second sampling values, which are respectively obtained by sampling the outputs of the monitoring section during the first and second test light-emissions. | 2012-06-21 |
20120155238 | STORAGE DEVICE AND INFORMATION CORRECTION METHOD - An information correcting method includes: detecting a first pattern in a radial direction and a second pattern formed obliquely to the radial direction on a track traversing the first and second patterns; counting number of the first pattern until the count value reaches number of the first pattern in one round of the track; generating a value incremented up number of the second pattern in the one round every time an interrupt associated with detection of the second pattern is generated as number of the second pattern; calculating an ideal number from a value obtained by multiplying the number of the second pattern until the number is counted by the counted number of the detected first pattern and a number set to the second pattern with reference to the second pattern formed at a present initial position; and correcting the generated number with the ideal number. | 2012-06-21 |
20120155239 | CHANNEL CIRCUIT AND METHOD OF DETECTING DEFECT OF MAGNETIC DISK DRIVE - A channel circuit includes: a detecting module configured to sample a signal amplitude of a reproduced signal of a single-frequency pattern written on a medium, and to detect an amplitude change that is lower or higher than a threshold; and a judgement module configured to judge whether the reproduced signal is decodable by a decoding circuit or not based on a result of detection by the detecting module. | 2012-06-21 |
20120155240 | OPTICAL PICK-UP APPARATUS WITH DIFFRACTIVE OPTICAL ELEMENT AND OPTICAL RECORDING/REPRODUCING APPARATUS HAVING THE SAME - An optical pick-up apparatus for reproducing information recorded on an optical recording medium or recording information on the optical recording medium is provided. The optical pick-up apparatus includes a light source unit which generates beams; a diffraction element which diffracts the generated beams; and an objective lens which focuses a p order diffracted beam which is used for recording and reproducing information among a plurality of diffracted beams which are diffracted by the diffraction element on any one of a plurality of information layers which are formed on an optical recording medium. A p±1 order diffracted beam which is not used for recording and reproducing information is focused away from the plurality of information recording layers and on the surface of the optical recording medium. | 2012-06-21 |
20120155241 | OPTICAL PICKUP APPARATUS AND OBJECTIVE OPTICAL UNIT - An optical pickup apparatus includes: a first light source for emitting a first light flux; a second light source for emitting a second light flux; a third light source for emitting a third light flux; and an objective optical unit having a first optical path difference providing structure and a second optical path difference providing structure. Magnifications of the objective optical unit for the first-third light fluxes have almost same value. The first optical path difference providing structure provides a predefined optical path difference and changes a spherical aberration to be one of under-correction and over-correction for all of the first light flux, the second light flux, and the third light flux. The second optical path difference providing structure provides a predefined optical path difference and changes a spherical aberration to be the other of under-correction and over-correction of the spherical aberration only for the second light flux. | 2012-06-21 |
20120155242 | METHOD FOR HIGH DENSITY DATA STORAGE AND IMAGING - An approach is presented for designing a polymeric layer for nanometer scale thermo-mechanical storage devices. Cross-linked polyimide oligomers are used as the recording layers in atomic force data storage device, giving significantly improved performance when compared to previously reported cross-linked and linear polymers. The cross-linking of the polyimide oligomers may be tuned to match thermal and force parameters required in read-write-erase cycles. Additionally, the cross-linked polyimide oligomers are suitable for use in nano-scale imaging. | 2012-06-21 |
20120155243 | VIBRATION DAMPING DEVICE AND DISC DEVICE HAVING VIBRATION DAMPING DEVICE - As a measure against vibration caused by disturbance due to mass eccentricity of a disc, a conventional disc device has a means to add an auxiliary mass that passively operates. This method has no way to enhance vibration damping effect other than setting the auxiliary mass to be large, and therefore there is a problem that the device becomes large. An auxiliary mass | 2012-06-21 |
20120155244 | INFORMATION RECORDING APPARATUS, INFORMATION RECORDING METHOD, AND INFORMATION RECORDING/PROCESSING PROGRAM - An information recording apparatus recording disc structure definition information defining a structure of an optical disc, in management areas of the optical disc including a data area and the management areas positioned on inner and outer periphery sides of the data area, includes: a memory which stores disc structure definition information of a new version including an invalid mark which cannot be interpreted as the disc structure definition information by an information reproducing apparatus and an information recording/reproducing apparatus being non-adaptive; and a recording control element for, when the disc structure definition information of the new version is recorded in the management areas, controlling recording of the disc structure definition information of the new version so the invalid mark is positioned at a position in the management areas in which all or part of disc structure definition information of an old version without the invalid mark needs to be recorded. | 2012-06-21 |
20120155245 | Method and System for Rebuilding Single Ring Network Topology - The invention provides a method and a system for rebuilding single ring network topology. In the method, each node in the single ring network detects, at a predetermined time interval, whether the link connected with the root port of the present node is failed (S | 2012-06-21 |
20120155246 | Method and System for Blocking Protocol Messages at a Sub-Ring Control Channel without Virtual Channel - The present invention provides a method for blocking a protocol message at a Sub-ring control channel without a virtual channel, for avoiding the problem that the Sub-ring is in a continuous refresh state all the time caused by the existing solution of the Sub-ring control channel without the virtual channel, and the method includes: blocking forwarding of relevant messages when a forced switch is initiated or a failure is detected. | 2012-06-21 |
20120155247 | METHOD AND APPARATUS FOR PROTECTING SUBSCRIBER ACCESS NETWORK - Embodiments of the present disclosure disclose a method and an apparatus for protecting a subscriber access network, and relate to the field of communications. The method includes: connecting a Broadband Network Gateway BNG device and N predetermined Digital Subscriber Line Access Multiplexers DSLAMs to an aggregation device AGG; allocating an active BNG interface for each of the N DSLAMs, allocating a standby BNG interface set for the N DSLAMs to obtain a backup relationship, and sending the backup relationship to the AGG ( | 2012-06-21 |
20120155248 | METHOD AND APPARATUS FOR TRASMITTING GROUP MESSAGE IN UNICAST NETWORK - A method and an apparatus for transmitting a group message in a unicast-based network are provided. A method of a terminal for transmitting a group message in a unicast-based network includes when receiving a session connection request message, transmitting a first group notification message for forming a relay group, to other terminals, receiving a second group notification message from at least one other terminal, forming a relay group with the terminal and at least one other terminal corresponding to the second received group notification message, and determining one of the terminals of the relay group as a relay terminal which relays the group message to other terminals in the relay group. | 2012-06-21 |
20120155249 | TECHNIQUE FOR IDENTIFYING A FAILED NETWORK INTERFACE CARD WITHIN A TEAM OF NETWORK INTERFACE CARDS - A method for identifying a failed network interface card in a system having two NICs configured as a team includes the steps of transmitting a first data packet from the first NIC to a third NIC, wherein the third NIC is not a member of the team, and transmitting a second data packet from the first NIC to the second NIC or from the second NIC to the third NIC, depending on whether the third NIC responds to the transmission of the first data packet. One advantage of the disclosed method is that it specifically identifies which NIC within the team has failed, which is something that cannot be determined by simply exchanging packets between the two NICs. | 2012-06-21 |
20120155250 | METHOD AND SYSTEM OF PROVIDING MICRO-FACILITIES FOR NETWORK RECOVERY - An approach provides micro-facilities for network recovery. An outage condition is detected, and is associated with one of a plurality of service provider facilities forming a service provider network. A router of the service provider network is determined to be capable of reaching the one service provider facility, wherein the provider router is resident within a customer facility. Bandwidth is allocated to one or more links for re-directing traffic over the provider router to the one service provider facility. | 2012-06-21 |
20120155251 | Mobile router network - A method comprises: providing a wireless mobile router in a vehicle. The mobile router is operable to establish a communication link to a network management system. The mobile router collects data independent of the router being coupled to the network management system; stores the data in the router; establishes a first communication link between the router and the network management system upon an occurrence of a first predetermined event; operates the router to upload the data to the network management system upon occurrence of the first predetermined event; and transmits the data to the network management system via the first communication link. | 2012-06-21 |