25th week of 2019 patent applcation highlights part 68 |
Patent application number | Title | Published |
20190189756 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A silicon carbide semiconductor device includes an insulated-gate electrode structure that is formed inside a gate trench that goes through a base region and reaches a upper portion of a current transport layer to control a primary current flowing through the base region; a current suppression layer of the second conductivity type embedded within an upper portion of the current transport layer; a control electrode isolation insulating film filled into a control electrode isolation trench that goes through the base region and reaches an upper portion of the current suppression layer; and a control electrode pad disposed on the control electrode isolation insulating film, wherein an upper portion of the current suppression layer abuts a sidewall of the control electrode isolation insulating film, and a lower portion of the current suppression layer covers at least bottom corners of the control electrode isolation insulating film. | 2019-06-20 |
20190189757 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR, AND HIGH-FREQUENCY AMPLIFIER - A semiconductor device includes a nitride semiconductor stacked structure that includes a channel layer containing GaN and a barrier layer containing In and further includes a cap layer that contains GaN on the outermost surface but does not contain Al. The cap layer has a Ga/N ratio that varies along a thicknesswise direction. | 2019-06-20 |
20190189758 | SEMICONDUCTOR DEVICE, POWER SUPPLY CIRCUIT, AND COMPUTER - A semiconductor device according to an embodiment includes a first nitride semiconductor layer; a second nitride semiconductor layer on the first nitride semiconductor layer; a first electrode and a second electrode disposed on or above the first nitride semiconductor layer; a gate electrode above the first nitride semiconductor layer; and a gate insulating layer, the gate insulating layer including a silicon oxide film and an aluminum oxynitride film, the aluminum oxynitride film disposed between the first nitride semiconductor layer and the silicon oxide film, a first atomic ratio of nitrogen relative to a sum of oxygen and nitrogen at a first position in the aluminum oxynitride film being higher than a second atomic ratio of nitrogen relative to a sum of oxygen and nitrogen at a second position in the aluminum oxynitride film, and the second position being closer to the silicon oxide film than the first position. | 2019-06-20 |
20190189759 | THIN FILM TRANSISTOR AND DISPLAY DEVICE - Disclosed are a thin film transistor and a display device, which can reduce parasitic capacitance between the first metal layer and the second metal layer so as to improve display quality of a liquid crystal display device. The thin film transistor includes a gate electrode, a gate insulation layer covering the gate electrode, a semiconductor layer formed on the gate insulation layer, and a source electrode and a drain electrode formed on the semiconductor layer. The semiconductor layer has an extension portion, a plane projection of which goes beyond a range of the gate electrode, and the drain electrode covers the extension portion. | 2019-06-20 |
20190189760 | STRUCTURE FOR REDUCED SOURCE AND DRAIN CONTACT TO GATE STACK CAPACITANCE - A structure of a semiconductor device is described. A semiconductor device includes a transistor which further includes a gate structure, a source region and a drain region disposed on a first surface of a substrate. A wiring layer of conductive material is disposed over a second surface of the substrate. The second surface of the substrate is located opposite to the first surface of the substrate. A set of contact studs including a first contact stud which extends completely through the source region and through the substrate to a first respective portion of the wiring layer. The set of contact studs also includes a second contact stud which extends completely through the drain region and through the substrate to a second respective portion of the wiring layer. A gate contact stud electrically couples the gate structure and extends completely through the substrate to a third respective portion of the wiring layer disposed over the second surface of the substrate. | 2019-06-20 |
20190189761 | FULLY DEPLETED SOI DEVICE FOR REDUCING PARASITIC BACK GATE CAPACITANCE - A method is presented for forming a semiconductor structure. The method includes forming a bilayer buried insulator over a substrate, forming an extremely thin silicon-on-insulator (ETSOI) over the bilayer buried insulator, forming a dummy gate, and forming a source/drain next to the dummy gate, the source/drain defining a raised source/drain region. The method further includes depositing a dielectric material over the raised source/drain regions, removing the dummy gate to define a recess, implanting a species within a first layer of the bilayer buried insulator, and depositing a gate dielectric and a conducting material within the recess. The method further includes removing the substrate, etching the implanted portion of the first layer of the bilayer buried insulator to expose a surface of a second layer of the bilayer buried insulator, and forming a back gate over the exposed second layer, the back gate self-aligned to the ETSOI channel. | 2019-06-20 |
20190189762 | III-NITRIDE FIELD-EFFECT TRANSISTOR WITH DUAL GATES - A field effect transistor (FET) includes a III-nitride channel layer, a III-nitride barrier layer on the channel layer, a first dielectric on the barrier layer, a first gate trench extending through the first dielectric, and partially or entirely through the barrier layer, a second dielectric on a bottom and walls of the first gate trench, a source electrode on a first side of the first gate trench, a drain electrode on a second side of the first gate trench opposite the first side, a first gate electrode on the second dielectric and filling the first gate trench, a third dielectric between the first gate trench and the drain electrode, a second gate trench extending through the third dielectric and laterally located between the first gate trench and the drain electrode, and a second gate electrode filling the second gate trench. | 2019-06-20 |
20190189763 | SEMICONDUCTOR DEVICE - A semiconductor device including a semiconductor substrate; a conductive film covering a front face of the semiconductor substrate, a front face of the conductive film having plural straight-line shaped concave portions disposed in parallel to each other; and a protecting film covering the front face of the conductive film, the protecting film having an opening that has an edge forming an angle with the plural concave portions of greater than 0° and less than 90°, and that partially exposes the conductive film. | 2019-06-20 |
20190189764 | SEMICONDUCTOR DEVICE - A semiconductor device includes an active layer, source electrodes, drain electrodes, gate electrodes, an insulating layer, gate metal layers, source metal layers, and drain metal layers. The source electrodes, drain electrodes, and gate electrodes are over the active layer, in which each of the gate electrodes includes a plurality of narrow portions and wider portions alternately arranged, and the wider portions of one of the gate electrodes extend toward the source electrode and directly connected to the wider portions of another one of the gate electrodes. The insulating layer is over the source electrodes, the drain electrodes, and the gate electrodes. The gate metal layers are over the gate electrodes and the insulating layer. The source metal layers are over the source electrodes and the insulating layer. The drain metal layers are over the drain electrodes and the insulating layer. | 2019-06-20 |
20190189765 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a first transistor that includes a first gate stack; a second transistor that includes a second gate stack having a narrower width than the first gate stack; and a dummy gate stack disposed around the first gate stack and the second gate stack, wherein the dummy gate stack includes an oxygen sink layer for capturing oxygen atoms that are diffused from an exterior into the first gate stack and the second gate stack. | 2019-06-20 |
20190189766 | PROTECTION OF HIGH-K DIELECTRIC DURING RELIABILITY ANNEAL ON NANOSHEET STRUCTURES - A starting structure for forming a gate-all-around field effect transistor (FET) and a method of fabricating the gate-all-around FET. The method includes forming a stack of silicon nanosheets above a substrate forming an interfacial layer over the nanosheets depositing a high-k dielectric layer conformally on the interfacial layer. The method also includes depositing a layer of silicon nitride (SiN) above the high-k dielectric layer and performing reliability anneal after depositing the layer of SiN to crystalize the high-k dielectric layer. | 2019-06-20 |
20190189767 | SEMICONDUCTOR DEVICES HAVING MULTI-THRESHOLD VOLTAGE - A semiconductor device includes active regions on a semiconductor substrate, gate structures on separate, respective active regions, and source/drain regions in the semiconductor substrate on opposite sides of separate, respective gate structures. Each separate gate structure includes a sequential stack of a high dielectric layer, a first work function metal layer, a second work function metal layer having a lower work function than the first work function metal layer, and a gate metal layer. First work function metal layers of the gate structures have different thicknesses, such that the gate structures include a largest gate structure where the first work function metal layer of the largest gate structure has a largest thickness of the first work function metal layers. The largest gate structure includes a capping layer on the high dielectric layer of the largest gate structure, where the capping layer includes one or more impurity elements. | 2019-06-20 |
20190189768 | Ferroelectric Assemblies - Some embodiments include ferroelectric assemblies. Some embodiments include a capacitor which has ferroelectric insulative material between a first electrode and a second electrode. The capacitor also has a metal oxide between the second electrode and the ferroelectric insulative material. The metal oxide has a thickness of less than or equal to about 30 Å. Some embodiments include a method of forming an assembly. A first capacitor electrode is formed over a semiconductor-containing base. Ferroelectric insulative material is formed over the first electrode. A metal-containing material is formed over the ferroelectric insulative material. The metal-containing material is oxidized to form a metal oxide from the metal-containing material. A second electrode is formed over the metal oxide. | 2019-06-20 |
20190189769 | NANOSHEET DEVICE WITH CLOSE SOURCE DRAIN PROXIMITY - A nanosheet transistor device having reduced access resistance is fabricated by recessing channel nanosheets and replacing the channel material with epitaxially grown doped extension regions. Sacrificial semiconductor layers between the channel nanosheets are selectively removed without damaging source/drain regions epitaxially grown on the extension regions. The sacrificial semiconductor layers are replaced by gate dielectric and gate metal layers. | 2019-06-20 |
20190189770 | GE NANO WIRE TRANSISTOR WITH GAAS AS THE SACRIFICIAL LAYER - An apparatus including a three-dimensional semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the three-dimensional semiconductor body including a plurality of nanowires including a germanium material disposed in respective planes separated in the junction regions by a second material, wherein a lattice constant of the second material is similar to a lattice constant of the germanium material; and a gate stack disposed on the channel region, the gate stack including a gate electrode disposed on a gate dielectric. A method of including forming a plurality of nanowires in separate planes on a substrate, each of the plurality of nanowires including a germanium material and separated from an adjacent nanowire by a sacrificial material; disposing a gate stack on the plurality of nanowires in a designated channel region, the gate stack including a dielectric material and a gate electrode. | 2019-06-20 |
20190189771 | TECHNIQUES FOR FORMING SCHOTTKY DIODES ON SEMIPOLAR PLANES OF GROUP III-N MATERIAL STRUCTURES - Techniques are disclosed for forming Schottky diodes on semipolar planes of group III-nitride (III-N) material structures. A lateral epitaxial overgrowth (LEO) scheme may be used to form the group III-N material structures upon which Schottky diodes can then be formed. The LEO scheme for forming III-N structures may include forming shallow trench isolation (STI) material on a semiconductor substrate, patterning openings in the STI, and growing the III-N material on the semiconductor substrate to form structures that extend through and above the STI openings, for example. A III-N structure may be formed using only a single STI opening, where such a III-N structure may have a triangular prism-like shape above the top plane of the STI layer. Further processing can include forming the gate (e.g., Schottky gate) and tied together source/drain regions on semipolar planes (or sidewalls) of the III-N structure to form a two terminal Schottky diode. | 2019-06-20 |
20190189772 | Semiconductor Device Comprising a Barrier Region - A semiconductor device includes a transistor. The transistor includes a drift region of a first conductivity type in a semiconductor substrate having a first main surface, a body region of a second conductivity type between the drift region and the first main surface, and a plurality of trenches in the first main surface and patterning the semiconductor substrate into a plurality of mesas including a first mesa and a dummy mesa. The plurality of trenches includes at least one active trench. The first mesa is arranged at a first side of the active trench, and the dummy mesa is arranged at a second side of the active trench. A gate electrode is arranged in the active trench, and a source region of the first conductivity type is in the first mesa. A one-sided channel of the transistor is configured to be formed in the first mesa. | 2019-06-20 |
20190189773 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR STRUCTURE - A semiconductor device and a semiconductor structure are disclosed. The semiconductor device includes a substrate, a first III-V compound layer, a second III-V compound layer, a source, a drain and a gate stack structure. The first III-V compound layer is disposed on the substrate. The second III-V compound layer is disposed on the first III-V compound layer. The source and the drain are disposed on opposite sidewall boundaries of the second III-V compound layer. The gate stack structure is disposed on the second III-V compound layer. The gate stack structure includes a first gate and a second gate. The first gate is disposed on the second III-V compound layer. The second gate is disposed on and electrically isolated from the first gate. The second gate is electrically coupled to the source. | 2019-06-20 |
20190189774 | FORMATION OF SELF-ALIGNED BOTTOM SPACER FOR VERTICAL TRANSISTORS - A method of fabricating a semiconductor device includes forming a fin on a substrate. Source/drain regions are arranged on the substrate on opposing sides of the fin. The method includes depositing a semiconductor layer on the source/drain regions. The method includes depositing a germanium containing layer on the fin and the semiconductor layer. The method further includes applying an anneal operation configured to chemically react the semiconductor layer with the germanium containing layer and form a silicon oxide layer. | 2019-06-20 |
20190189775 | VERTICAL FIELD-EFFECT-TRANSISTORS HAVING A SILICON OXIDE LAYER WITH CONTROLLED THICKNESS - A vertical field-effect transistor and a method for fabricating the same. The vertical field-effect transistor includes a substrate and a bottom source/drain region. The vertical field-effect transistor also includes at least one fin structure, and further includes a bottom spacer layer. The bottom spacer layer has a substantially uniform thickness with a thickness variation of less than 3 nm. A gate structure contacts the bottom spacer layer and at least one fin structure. The method includes forming a structure including a substrate, a source/drain region, and one or more fins. A polymer brush spacer is formed in contact with at least sidewalls of the one or more fins. A polymer brush layer is formed in contact with at least the source/drain region and the polymer brush spacer. The polymer brush spacer is removed. Then, the polymer brush layer is reflowed to the sidewalls of the at least one fin. | 2019-06-20 |
20190189776 | LONG CHANNELS FOR TRANSISTORS - A semiconductor device includes a first nanosheet stack, a second nanosheet stack, and a third nanosheet stack arranged on a substrate. The semiconductor device includes a gate arranged on the first nanosheet stack, the second nanosheet stack, and the third nanosheet stack. The semiconductor device includes a channel extending through the gate and from the first nanosheet stack, the second nanosheet stack, and to the third nanosheet stack in a serpentine fashion. The semiconductor device includes a first source/drain and a second source/drain arranged on opposing sides of the gate. | 2019-06-20 |
20190189777 | EFFECTIVE JUNCTION FORMATION IN VERTICAL TRANSISTOR STRUCTURES BY ENGINEERED BOTTOM SOURCE/DRAIN EPITAXY - A vertical transistor structure is provided that includes a bottom source/drain structure that includes a doped semiconductor buffer layer that contains a first dopant species having a first diffusion rate, and an epitaxial doped semiconductor layer that contains a second dopant species that has a second diffusion rate that is less than the first diffusion rate. During a junction anneal, the first dopant species readily diffuses from the doped semiconductor buffer layer into a pillar portion of a base semiconductor substrate to provide the bottom source/drain extension and bottom source/drain junction. No diffusion overrun is observed. During the junction anneal, the second dopant species remains in the epitaxial doped semiconductor layer providing a low resistance contact. The second dopant species does not interfere with the bottom source/drain extension and bottom source/drain junction due to limited diffusion of the second dopant species. | 2019-06-20 |
20190189778 | SEMICONDUCTOR DEVICES HAVING VERTICAL TRANSISTORS WITH ALIGNED GATE ELECTRODES - A semiconductor device includes an active pillar on a substrate. A first source/drain region is disposed at a top end of the active pillar and has a greater width than the active pillar. A first insulating layer is disposed on a sidewall of the active pillar and a second insulating layer is disposed on at least a bottom surface of the first source/drain region. A gate electrode is disposed on the first insulating layer and the second insulating layer. A second source/drain region is disposed in the substrate at a bottom end of the active pillar. Methods of fabrication are also described. | 2019-06-20 |
20190189779 | DUAL GATE LDMOS AND A PROCESS OF FORMING THEREOF - A method for forming a high voltage device is disclosed. The method comprises providing a substrate defined with a high voltage device region. A device well is formed to encompass the high voltage device region. A drift region is formed within the device well. A body well is formed within the device well adjacent to the drift region. A variable thickness gate dielectric is formed on the substrate. Forming the variable thickness gate dielectric comprises patterned a sacrificial polysilicon layer and oxidizing the patterned sacrificial polysilicon layer to define a thick gate oxide having sloped sidewalls. A gate electrode is formed on the variable thickness gate dielectric, wherein the gate electrode partially overlaps the thick gate oxide. A first and a second source/drain (S/D) region is formed adjacent to first and second sides of the variable thickness gate dielectric. | 2019-06-20 |
20190189780 | NANOSHEET WITH CHANGING SiGe PECENTAGE FOR SiGe LATERAL RECESS - A method for manufacturing a semiconductor device includes forming a stacked configuration of a plurality of silicon germanium layers and a plurality of silicon layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a silicon layer stacked on a silicon germanium layer, patterning the stacked configuration into a plurality of patterned stacks spaced apart from each other, and etching exposed sides of the plurality of silicon germanium layers to remove portions of the silicon germanium layers from lateral sides of each of the plurality of silicon germanium layers, wherein a concentration of germanium is varied between each of the plurality of silicon germanium layers to compensate for variations in etching rates between the plurality of silicon germanium layers to result in remaining portions of each of the plurality of silicon germanium layers having the same or substantially the same width as each other. | 2019-06-20 |
20190189781 | NANOSHEET WITH CHANGING SiGe PECENTAGE FOR SiGe LATERAL RECESS - A method for manufacturing a semiconductor device includes forming a stacked configuration of a plurality of silicon germanium layers and a plurality of silicon layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a silicon layer stacked on a silicon germanium layer, patterning the stacked configuration into a plurality of patterned stacks spaced apart from each other, and etching exposed sides of the plurality of silicon germanium layers to remove portions of the silicon germanium layers from lateral sides of each of the plurality of silicon germanium layers, wherein a concentration of germanium is varied between each of the plurality of silicon germanium layers to compensate for variations in etching rates between the plurality of silicon germanium layers to result in remaining portions of each of the plurality of silicon germanium layers having the same or substantially the same width as each other. | 2019-06-20 |
20190189782 | GATE CUT USING SELECTIVE DEPOSITION TO PREVENT OXIDE LOSS - Semiconductor devices and methods of forming the same include forming gate stacks across a semiconductor fin, each gate stack having a gate conductor. An interlayer dielectric is formed between the gate stacks. A protective layer is formed on the interlayer dielectric that leaves the gate stacks exposed. The gate conductor of at least one gate stack is etched away. A dielectric liner is formed in a gap left by the etched gate conductor. | 2019-06-20 |
20190189783 | DOUBLE PATTERNING EPITAXY FIN - A method is provided for use in forming a fin of a FinFET for an integrated circuit. The method comprises the steps of forming a hard mask on a substrate; forming an opening in the hard mask with a portion of the substrate exposed therein; forming a buffer on the exposed substrate within the opening in the hard mask; forming a mandrel at least in part on the buffer within the opening in the hard mask; forming a channel on a top and sides of the mandrel; removing the channel formed on the top of the mandrel without removing the channel formed on the sides of the mandrel; and removing the mandrel without removing the channel formed on the sides of the mandrel. | 2019-06-20 |
20190189784 | FORMING A FIN USING DOUBLE TRENCH EPITAXY - The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a fin using double trench epitaxy. The fin may be composed of a III-V semiconductor material and may be grown on a silicon, silicon germanium, or germanium substrate. A double trench aspect ratio trapping (ART) epitaxy method may trap crystalline defects within a first trench (i.e. a defective region) and may permit formation of a fin free of patterning defects in an upper trench (i.e. a fin mold). Crystalline defects within the defective region may be trapped via conventional aspect ratio trapping or three-sided aspect ratio trapping. Fin patterning defects may be avoided by utilizing a fin mold to grow an epitaxial fin and selectively removing dielectric material adjacent to a fin region. | 2019-06-20 |
20190189785 | TRANSISTORS WITH LATTICE MATCHED GATE STRUCTURE - Integrated circuit transistor structures are disclosed that include a gate structure that is lattice matched to the underlying channel. In particular, the gate dielectric is lattice matched to the underlying semiconductor channel material, and in some embodiments, so is the gate electrode. In an example embodiment, single crystal semiconductor channel material and single crystal gate dielectric material that are sufficiently lattice matched to each other are epitaxially deposited. In some cases, the gate electrode material may also be a single crystal material that is lattice matched to the semiconductor channel material, thereby allowing the gate electrode to impart strain on the channel via the also lattice matched gate dielectric. A gate dielectric material that is lattice matched to the channel material can be used to reduce interface trap density (D | 2019-06-20 |
20190189786 | BIPOLAR TRANSISTOR WITH TRENCH STRUCTURE - The present disclosure relates to a semiconductor structure and a manufacturing process therefor. Provided is a method for manufacturing a bipolar transistor with a trench structure, including providing a semiconductor substrate; fabricating a shallow trench isolation structure to define a device active area; forming an N-type well and a P-type well in the active area to define a first region, a second region and a third region of the bipolar transistor; etching a portion, adjacent to the shallow trench isolation structure, in the first region to form a trench; performing ion implantation to form an emitter, a base and a collector of the bipolar transistor; forming a salicide block structure in the trench; and forming a metal electrode of the bipolar transistor, wherein the emitter is formed in the first region. The present disclosure further provides a bipolar transistor with a trench structure. | 2019-06-20 |
20190189787 | HETEROJUNCTION BIPOLAR TRANSISTOR (HBT) - A heterojunction bipolar transistor (HBT) may include a base contact and emitter mesas on a collector mesa. The HBT may include emitter contacts on the emitter mesas. The HBT may include a first dielectric layer on the collector mesa, sidewalls of the emitter mesas, and the base contact. The HBT may further include a second dielectric layer on the first dielectric layer and on sidewalls of the emitter contacts. The HBT may further include a secondary conductive layer on the first dielectric layer, the second dielectric layer, and the emitter contacts. | 2019-06-20 |
20190189788 | TRANSISTOR DEVICE HAVING A PILLAR STRUCTURE - In at least one general aspect, an apparatus can include a first trench disposed in a semiconductor region and including a gate electrode, and a second trench disposed in the semiconductor region. The apparatus can include a mesa region disposed between the first trench and the second trench, and a source region of a first conductivity type disposed in a top portion of the mesa region. The apparatus can include an epitaxial layer of the first conductivity type, and a body region of a second conductivity type disposed in the mesa region and disposed between the source region and the epitaxial layer of the first conductivity type. The apparatus can include a pillar of the second conductivity type disposed in the mesa region such that a first portion of the source region is disposed lateral to the pillar and a second portion of the source region is disposed above the pillar. | 2019-06-20 |
20190189789 | IGBT with Fully Depletable n- and p-Channel Regions - A power semiconductor device has a semiconductor body coupled to first and second load terminal structures, the semiconductor body configured to conduct a load current during a conducting state of the device and having a drift region. The power semiconductor device includes a plurality of cells, each cell having: a first mesa in a first cell portion, the first mesa including: a first port region, and a first channel region, the first mesa exhibiting a total extension of less than 100 nm in a lateral direction, and a second mesa in a second cell portion including: a second port region, and a second channel region. A trench structure includes a control electrode structure configured to control the load current by inversion or accumulation. A guidance zone of the second conductivity type is below the second channel region and is displaced from the first and the second channel regions. | 2019-06-20 |
20190189790 | METHOD AND STRUCTURE FOR FORMING IMPROVED SINGLE ELECTRON TRANSISTOR WITH GAP TUNNEL BARRIERS - A semiconductor device includes a single electron transistor (SET) having an island region, a bottom source/drain region under the island region, and a top source/drain region over the island region, a first gap between the bottom source/drain region and the island region, a second gap between the top source/drain region and the island region, and a gate structure on a side of the island region. | 2019-06-20 |
20190189791 | LATERAL FIN STATIC INDUCTION TRANSISTOR - Presented is a lateral fin static induction transistor including a semi conductive substrate, source and drain regions extending from an optional buffer layer of same or varied thickness supported by the semi conductive substrate, a semi conductive channel electrically coupling the source region to the drain region of the transistor, a portion of the semi conductive channel being a fin and having a face covered by a gated structure, thereby defining a gated channel within the semi conductive channel, the semi conductive channel further including a drift region electrically coupling the gated channel to the drain region of the transistor. | 2019-06-20 |
20190189792 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD - A compound semiconductor device includes: a compound semiconductor area including, at an upper most portion, a protective layer made of a compound semiconductor; and an ohmic electrode provided on the compound semiconductor area, the ohmic electrode being away from the protective layer in plan view and being not in contact with the protective layer. | 2019-06-20 |
20190189793 | SEMICONDUCTOR STRUCTURE AND ASSOCIATED FABRICATING METHOD - A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed over the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a field plate formed over the substrate between the gate structure and the drain region; wherein the field plate is coupled to the source region or a bulk electrode of the substrate. An associated method for fabricating the semiconductor structure is also disclosed. | 2019-06-20 |
20190189794 | INDIUM-RICH NMOS TRANSISTOR CHANNELS - Techniques are disclosed for forming high mobility NMOS fin-based transistors having an indium-rich channel region electrically isolated from the sub-fin by an aluminum-containing layer. The aluminum aluminum-containing layer may be provisioned within an indium-containing layer that includes the indium-rich channel region, or may be provisioned between the indium-containing layer and the sub-fin. The indium concentration of the indium-containing layer may be graded from an indium-poor concentration near the aluminum-containing barrier layer to an indium-rich concentration at the indium-rich channel layer. The indium-rich channel layer is at or otherwise proximate to the top of the fin, according to some example embodiments. The grading can be intentional and/or due to the effect of reorganization of atoms at the interface of indium-rich channel layer and the aluminum-containing barrier layer. Numerous variations and embodiments will be appreciated in light of this disclosure. | 2019-06-20 |
20190189795 | METHODS AND APPARATUS TO REMOVE EPITAXIAL DEFECTS IN SEMICONDUCTORS - Methods and apparatus to remove epitaxial defects in semiconductors are disclosed. A disclosed example multilayered die structure includes a fin having a first material, where the fin is epitaxially grown from a first substrate layer having a second material, and where a defect portion of the fin is etched or polished. The disclosed example multilayered die structure also includes a second substrate layer having an opening through which the fin extends. | 2019-06-20 |
20190189796 | SCHOTTKY DIODE INTEGRATED INTO SUPERJUNCTION POWER MOSFETS - A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device comprises an active cell area including a plurality of superjunction trench power MOSFETs, and a Schottky diode area including a plurality of Schottky diodes formed in the drift region having the superjunction structure. Each of the integrated Schottky diodes includes a Schottky contact between a lightly doped semiconductor layer and a metallic layer | 2019-06-20 |
20190189797 | Thin Profile Power Semiconductor Device Package Having Face-To-Face Mounted Dice And No Internal Bondwires - A packaged semiconductor device has a thin profile, two face-to-face mounted power semiconductor device dice, and no internal bond wires. A first semiconductor device die is mounted so that a gate pad is bonded to the bottom of a first lead, and so that a source pad is bonded to the bottom of a second lead. A second semiconductor device die identical to the first is mounted so that a gate pad is bonded to the top of the first lead, and so that a source pad is bonded to the top of the second lead. The backside drain electrodes of both dice are electrically coupled to a third lead. The third lead in one example has a forked-shape, and the two dice are disposed entirely between the two tines of the fork. After encapsulation, the three leads extend parallel to each other from a body portion of the package. | 2019-06-20 |
20190189798 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device including a field-effect transistor having source and drain source regions, first and second gate electrodes and a protective diode connected to the transistor. The first gate electrode is formed over a first gate insulating film in a lower part of a trench. The second gate electrode is formed over a second gate insulating film in an upper part of the trench. The first gate electrode includes a first polysilicon film, and the second gate electrode includes a second polysilicon film, wherein an impurity concentration of the first polysilicon film is lower than an impurity concentration of the second polysilicon film. | 2019-06-20 |
20190189799 | SEMICONDUCTOR DEVICE AND METHOD MANUFACTURING THE SAME - A semiconductor device is provided and includes an n− type layer disposed at a substrate first surface. A trench, n type region, and p+ type region are disposed on the n− type layer. A p type region is disposed on the n type region. An n+ type region is disposed on the p type region. A gate insulating layer is disposed in the trench. A gate electrode is disposed on the gate insulating layer. A source electrode is disposed on an insulating layer disposed on the gate electrode, n+ type region, and p+ type region. A drain electrode is disposed at a substrate second surface. The n type region includes a first portion contacting the trench side surface and extending parallel to a substrate upper surface and a second portion contacting the first portion, separated from the trench side surface, and extending vertical to the substrate upper surface. | 2019-06-20 |
20190189800 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The disclosure reduces the risk of collapse of the wall surrounding the trench and suppresses the withstand voltage fluctuation that accompanies the manufacturing variation for a semiconductor device having a super junction structure. The semiconductor device includes a drift layer of a first conductivity type and a plurality of embedded parts embedded in the drift layer. The embedded parts are of a second conductivity type different from the first conductivity type, and the embedded parts are arranged with a first direction as a longitudinal direction and spaced from each other along a second direction that intersects the first direction. A width of each of the embedded parts in the second direction changes continuously along the first direction. | 2019-06-20 |
20190189801 | CAPACITIVE TUNING USING BACKSIDE GATE - A radio frequency (RF) integrated circuit (RFIC) switch multi-finger transistor includes a first dual gate transistor having a first gate with a first gate length on a first side of a substrate, and a second gate with a second gate length on a second side of the substrate. The RFIC also includes a second dual gate transistor having a third gate with a third gate length on the first side of the substrate, and a fourth gate with a fourth gate length on the second side of the substrate. The second gate length is different than the fourth gate length, and the second dual gate transistor is coupled in series with the first dual gate transistor in the RFIC switch multi-finger transistor. | 2019-06-20 |
20190189802 | SEMICONDUCTOR DEVICE WITH FIN AND RELATED METHODS - A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region. | 2019-06-20 |
20190189803 | SELECTIVE DEPOSITION UTILIZING SACRIFICIAL BLOCKING LAYERS FOR SEMICONDUCTOR DEVICES - Methods of selectively depositing high-K gate dielectric on a semiconductor structure are disclosed. The method includes providing a semiconductor structure disposed above a semiconductor substrate. The semiconductor structure is disposed beside an isolation sidewall. A sacrificial blocking layer is then selectively deposited on the isolation sidewall and not on the semiconductor structure. Thereafter, a high-K gate dielectric is deposited on the semiconductor structure, but not on the sacrificial blocking layer. Properties of the sacrificial blocking layer prevent deposition of oxide material on its surface. A thermal treatment is then performed to remove the sacrificial blocking layer, thereby forming a high-K gate dielectric only on the semiconductor structure. | 2019-06-20 |
20190189804 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes first and second fin patterns on a substrate and extending apart from each other, a field insulating film on the substrate and surrounding parts of the first and second fin patterns, a first gate structure on the first fin pattern and intersecting the first fin pattern, a second gate structure on the second fin pattern and intersecting the second fin pattern, and a separating structure protruding from a top surface of the field insulating film and separating the first and second gate structures, the field insulating film and the separating structure including a same insulating material. | 2019-06-20 |
20190189805 | Thin Film Transistor, Method for Manufacturing the Same and Display Device Comprising the Same - A thin film transistor includes an oxide semiconductor layer on a substrate. The oxide semiconductor layer includes a channel portion, a first channel connecting portion connected to a first end of the channel portion, and a second channel connecting portion connected to a second end of the channel portion. A thickness of the second channel connecting portion is different from a thickness of the first channel connecting portion. The first end of the channel portion has a same thickness as the thickness of the first channel connecting portion, and the second end of the channel portion has a same thickness as the thickness of the second channel connecting portion. | 2019-06-20 |
20190189806 | TIGHT PITCH STACK NANOWIRE ISOLATION - Devices and methods for forming a tight pitch stack nanowire without shallow trench isolation including a base nanosheet formed on a substrate. At least one fin are formed, and at least one dummy gate is formed over the at least two fins, on the base nanosheet, the at least two fins including at least two alternating layers of a first material and a second material. The base nanosheet is replaced with a blanket dielectric to form a shallow trench isolation (STI) around the at least one fin and around the at least one dummy gate. A gate replacement is performed to replace the at least one dummy gate and the second material with a gate conductor material and a gate cap to fouls gate structures. | 2019-06-20 |
20190189807 | Transistors Comprising At Least One Of GaP, GaN, and GaAs - A transistor comprises a pair of source/drain regions having a channel region there-between. A transistor gate construction is operatively proximate the channel region. The channel region comprises a direction of current flow there-through between the pair of source/drain regions. The channel region comprises at least one of GaP, GaN, and GaAs extending all along the current-flow direction. Each of the source/drain regions comprises at least one of GaP, GaN, and GaAs extending completely through the respective source/drain region orthogonal to the current-flow direction. The at least one of the GaP, the GaN, and the GaAs of the respective source/drain region is directly against the at least one of the GaP, the GaN, and the GaAs of the channel region. Each of the source/drain regions comprises at least one of elemental silicon and metal material extending completely through the respective source/drain region orthogonal to the current-flow direction. Other embodiments are disclosed. | 2019-06-20 |
20190189808 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device is included a first semiconductor layer with n-type conductivity, containing a gallium nitride-based semiconductor, a second semiconductor layer with p-type conductivity, which is laminated directly on the first semiconductor layer and contains a gallium nitride-based semiconductor added with a p-type impurity at a concentration of 1×10 | 2019-06-20 |
20190189809 | VOLTAGE BREAKDOWN DEVICE FOR SOLAR CELLS - Voltage breakdown devices for solar cells are described. For example, a solar cell includes a semiconductor substrate. A plurality of alternating N-type and P-type semiconductor regions is disposed in or above the substrate. A plurality of conductive contacts is coupled to the plurality of alternating N-type and P-type semiconductor regions. A voltage breakdown device is disposed above the substrate. The voltage breakdown device includes one of the plurality of conductive contacts in electrical contact with one of the N-type semiconductor regions and with one of the P-type semiconductor regions of the plurality of alternating N-type and P-type semiconductor regions disposed in or above the substrate. | 2019-06-20 |
20190189810 | Conductive Paste, Method for Producing Same, and Method for Producing Solar Cell - A conductive paste including: a conductive powder containing silver; an indium powder; a silver-tellurium-coated glass powder; a solvent; and an organic binder, wherein the silver-tellurium-coated glass powder is a silver-tellurium-coated glass powder including a tellurium-based glass powder containing tellurium in an amount of 20% by mass or more, and a coating layer on a surface of the tellurium-based glass powder, the coating layer containing silver and tellurium as a main component. | 2019-06-20 |
20190189811 | PHOTOVOLTAIC DEVICE AND PHOTOVOLTAIC UNIT - A photovoltaic device includes: a p- or n-type semiconductor substrate; a p-type amorphous semiconductor film and an n-type amorphous semiconductor film on a first-face side; p-electrodes on the p-type amorphous semiconductor film; and n-electrodes on the n-type amorphous semiconductor film, wherein: the p-electrodes and the n-electrodes are arranged at intervals; the p-type amorphous semiconductor film surrounds the n-type amorphous semiconductor film in an in-plane direction of the semiconductor substrate; the n-type amorphous semiconductor film has an edge portion providing an overlapping region where the n-type amorphous semiconductor film overlaps the p-type amorphous semiconductor film; and the n-electrodes are disposed in areas of the n-type amorphous semiconductor film that are surrounded by the overlapping region. | 2019-06-20 |
20190189812 | SOLAR CELL AND SOLAR CELL MODULE - A solar cell includes a rectangular-shaped semiconductor substrate having a first principal surface and a second principal surface, and a metal electrode. The second principal surface includes a plurality of band-shaped first conductivity-type regions that comprise a first conductivity-type semiconductor layer and a plurality of band-shaped second conductivity-type regions that comprise a second conductivity-type semiconductor layer. The metal electrode may be disposed on the second principal surface, and no metal electrode may be provided on the first principal surface. The second conductivity-type semiconductor layer may have a conductivity-type different from that of the first conductivity-type semiconductor layer. The semiconductor substrate may include a first direction end portion region at both end portions of the semiconductor substrate in a first direction, and a first direction central region is present between the two first direction end portion regions. | 2019-06-20 |
20190189813 | TRI-LAYER SEMICONDUCTOR STACKS FOR PATTERNING FEATURES ON SOLAR CELLS - Tri-layer semiconductor stacks for patterning features on solar cells, and the resulting solar cells, are described herein. In an example, a solar cell includes a substrate. A semiconductor structure is disposed above the substrate. The semiconductor structure includes a P-type semiconductor layer disposed directly on a first semiconductor layer. A third semiconductor layer is disposed directly on the P-type semiconductor layer. An outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width. An outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the third semiconductor layer to the outermost edge of the third semiconductor layer. A conductive contact structure is electrically connected to the semiconductor structure. | 2019-06-20 |
20190189814 | METHODS FOR PREPARING CIGS THIN FILM SOLAR CELL - This disclosure provides a method for preparing a CIGS thin film solar cell, including placing a substrate formed with a barrier layer into a sputtering chamber, and forming a doping layer on the barrier layer by sputtering, wherein the doping layer is sodium doped a hetero-molybdenum layer; detecting sodium ion content, and introducing water vapor into the sputtering chamber according to the sodium ion content when the doping layer is formed by sputtering. The method for preparing the CIGS thin film solar cell of the present disclosure introduces water vapor into the sputtering chamber according to the content of sodium ions. The water vapor may ensure the stability after sodium ion sputtering, and the content of water vapor is adjusted according to the sodium ion content. | 2019-06-20 |
20190189815 | PHOTOELECTRIC CONVERSION DEVICE INCLUDING QUANTUM DOT LAYERS - A photoelectric conversion device may include a substrate, a photoactive layer disposed on the substrate, and a first electrode and a second electrode respectively connected to corresponding edges of the photoactive layer. The photoactive layer may include a first oxide semiconductor layer on the substrate, and a plurality of quantum dot layers and a plurality of second oxide semiconductor layers that are alternately formed on the first oxide semiconductor layer. | 2019-06-20 |
20190189816 | Complementary Metal-Oxide Semiconductor Compatible Patterning of Superconducting Nanowire Single-Photon Detectors - A device includes a first semiconductor layer; a portion of a second semiconductor layer disposed on the first semiconductor layer; and a third semiconductor layer including a first region disposed on the portion of the second semiconductor layer and a second region disposed on the first semiconductor layer. A thickness of the first region is less than a predefined thickness. The device also includes an etch stop layer disposed on the third semiconductor layer; a plurality of distinct portions of a fourth semiconductor layer disposed on the etch stop layer and exposing one or more distinct portions of the etch stop layer over the portion of the second semiconductor layer; and a plurality of distinct portions of a superconducting layer disposed on the plurality of distinct portions of the fourth semiconductor layer and the exposed one or more distinct portions of the etch stop layer. | 2019-06-20 |
20190189817 | METHOD FOR MAKING CMOS IMAGE SENSOR WITH BURIED SUPERLATTICE LAYER TO REDUCE CROSSTALK - A method for making a CMOS image sensor may include forming a superlattice on a semiconductor substrate having a first conductivity type, with the superlattice including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a plurality of laterally adjacent photodiodes on the superlattice. Each photodiode may include a semiconductor layer on the superlattice and having a first conductivity type dopant and with a lower dopant concentration than the semiconductor substrate, a retrograde well extending downward into the semiconductor layer and having a second conductivity type, a first well around a periphery of the retrograde well having the first conductivity type, and a second well within the retrograde well having the first conductivity type. | 2019-06-20 |
20190189818 | CMOS IMAGE SENSOR INCLUDING PHOTODIODES WITH OVERLYING SUPERLATTICES TO REDUCE CROSSTALK - A CMOS image sensor may include a semiconductor substrate having a first conductivity type, and a plurality of laterally adjacent photodiodes formed in the substrate. Each photodiode may include a retrograde well extending downward into the substrate from a surface thereof and having a second conductivity type, a first well around a periphery of the retrograde well having the second conductivity type, and a second well within the retrograde well having the first conductivity type. Each photodiode may further include first and second superlattices respectively overlying each of the first and second wells. Each of the first and second superlattices may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. | 2019-06-20 |
20190189819 | SHINGLED ARRAY SOLAR CELLS AND METHOD OF MANUFACTURING SOLAR MODULES INCLUDING THE SAME - A solar cell is provided including a substrate having a front and back side, a metallization pattern deposited on the front side, the metallization pattern including a plurality of front side bus bars each including fingers extending therefrom, and a plurality of back side bus bars deposited on the back side. On the front side, one front side bus bar is formed along an edge of the front side of the substrate, and a remainder of the front side bus bars are unequally spaced across the substrate. On the back side of the substrate, only one back side bus bar is formed along an edge of the back side of the substrate, and a remainder of the back side bus bars are unequally spaced across the substrate. | 2019-06-20 |
20190189820 | SOLAR CELL MODULE - A solar cell module having curvature in a vehicle front-rear direction which varies from a vehicle front side towards a vehicle rear side, the solar cell module includes: a sealing layer formed from resin and in which power generating elements are sealed; a front surface layer formed from resin and joined to a light-receiving surface side of the power generating elements in the sealing layer; and a rear surface layer formed from resin and joined to an opposite side from the light-receiving surface side of the power generating elements in the sealing layer, wherein a plate thickness of portions where the front surface layer, the sealing layer, and the rear surface layer are laminated together is formed so as to become proportionately thinner as the curvature in the vehicle front-rear direction increases. | 2019-06-20 |
20190189821 | SOLAR CELL MODULE - A solar cell module includes: a sealing layer in which power generating elements are sealed; a front surface layer formed from resin and joined to a light-receiving surface side of the power generating elements in the sealing layer; and a rear surface layer joined to an opposite side from the light-receiving surface side of the power generating elements in the sealing layer, wherein the front surface layer has a solar cell installation area that forms a portion of a solar cell, and an antenna installation area that extends at a vehicle front side or a vehicle rear side of the solar cell installation area. | 2019-06-20 |
20190189822 | METHOD FOR PREPARING INSULATING LAYER OF FLEXIBLE PHOTOVOLTAIC MODULE AND FLEXIBLE PHOTOVOLTAIC MODULE - The present disclosure discloses a method for preparing an insulating layer of a flexible photovoltaic module. The method includes: placing the flexible photovoltaic module on a spraying device, and using a shielding component to shield both side surfaces of the flexible photovoltaic module; performing a first spraying on the sidewall to be insulated of the flexible photovoltaic module to form an insulating bottom layer; performing a second spraying on the insulating bottom layer to form an insulating top layer such that the insulating bottom layer and the insulating top layer constitute an insulating layer; and drying the insulating layer. | 2019-06-20 |
20190189823 | SOLAR CELL PHOTOVOLTAIC MODULE AND SOLAR CELL PHOTOVOLTAIC ASSEMBLY - The present disclosure relates to a solar cell photovoltaic module and a solar cell photovoltaic assembly. The solar cell photovoltaic module comprises a plurality of matrix-arranged cells, a plurality of main grids and fine grids are distributed on the light receiving surface of the cells, the main grids collect currents on the fine grids connected thereto, the currents collected by the main grids are transmitted through interconnects that connect to the main grids, and the cells are rectangular. The solar cell photovoltaic assembly comprises modules and bus bars, wherein two adjacent modules are connected via a diode or via a virtual conductive wire plus a diode, and the bus bars and the conductive wire are connected with an output via a junction box. | 2019-06-20 |
20190189824 | SOLAR CELL MODULE INCLUDING LIGHT GUIDE MEMBER, AND METHOD OF FABRICATING THE SAME - A solar cell module having a light guide member and a method of fabricating the same are provided. The solar cell module includes a light guide member including a light receiving surface for receiving external light and a side surface formed to be inclined to or perpendicular to the light receiving surface, and at least one solar cell mounted on the side surface, the at least one solar cell being configured to receive the external light through the light guide member and perform photoelectric transformation on the received external light. The light guide member includes a plurality of air pores, and the light guide member guides the received external light to a direction of the side surface. The solar cell module may be configured in various manners according to embodiments. | 2019-06-20 |
20190189825 | OPTICAL VOLTAGE SOURCE - An optical voltage source and decoupling device is provided, wherein the optical voltage source has a number N of series-connected semiconductor diodes, each having a p-n junction, the semiconductor diodes are monolithically integrated and together form a first stack with an upper side and an underside, and the number N of the semiconductor diodes of the first stack is greater than or equal to two, the decoupling device has a further semiconductor diode. The further semiconductor diode has a pin junction and, the further semiconductor diode is anti-serially connected with the semiconductor diodes of the first stack. An underside of the further semiconductor diode is materially connected with the upper side of the first stack and the further semiconductor diode forms a total stack together with the first stack. | 2019-06-20 |
20190189826 | HIGH EFFICIENCY MULTIJUNCTION PHOTOVOLTAIC CELLS - Multijunction photovoltaic cells having at least three subcells are disclosed, in which at least one of the subcells comprises a base layer formed of GaInNAsSb. The GaInNAsSb subcells exhibit high internal quantum efficiencies over a broad range of irradiance energies. | 2019-06-20 |
20190189827 | SOLID-STATE IMAGE SENSOR, IMAGE CAPTURING APPARATUS, AND IMAGE CAPTURING METHOD - A solid-state image sensor comprising one or more processors and/or circuitry which functions as: a pixel portion in which a plurality of pixels are arranged, each pixel being provided with a sensor that includes an avalanche photodiode and a quenching resistor; and a controller that performs setting so that a bias voltage smaller than a breakdown voltage of the avalanche photodiodes is applied across the avalanche photodiode provided in an abnormal pixel among the plurality of pixels. | 2019-06-20 |
20190189828 | METHOD AND DEVICE FOR FILM REMOVING PROCESS - An embodiment of the present disclosure discloses a method and device for film removing process. The device includes: an optical assembly. The optical assembly includes: a laser generator for generating a laser beam; a first scanning mirror for reflecting the laser beam; a second scanning mirror for reflecting the laser beam reflected by the first scanning mirror; and a focusing mirror for focusing the laser beam reflected by the second scanning mirror onto a thin film solar cell for film removing process. The device further includes a processor and a memory in which instructions are stored, and the following steps are implemented when the instructions are executed by the processor: moving the thin film solar cell or the optical assembly to a designated position, and controlling the first scanning mirror and/or the second scanning mirror to be deflected so as to perform a film removing process on the thin film solar cell. The rate of film removing is improved and no chromatic aberrations will be generated according to the embodiments of the present disclosure. | 2019-06-20 |
20190189829 | WASTE LIQUID RECOVERY SYSTEM, CHEMICAL BATH DEPOSITION DEVICE AND DEPOSITION METHOD - The present disclosure provides a waste liquid recovery system, a chemical bath deposition device and a deposition method, the waste liquid recovery system comprises a waste liquid storage tank for storing the waste liquid generated by deposition of a cadmium sulfide deposition tank; a refrigeration device for refrigerating the stored waste liquid; a filtering device for filtering the waste liquid obtained after refrigerating; and a chemical liquid storage tank for storing the filtered waste liquid. The waste liquid recovery system, the chemical bath deposition device and the deposition method provided by the present disclosure provide a chemical liquid having the same concentration as an original liquid by refrigerating and filtering the waste liquid, and then replenishing the chemical raw material, thereby greatly improving the recycling of waste liquid and reducing a production cost. | 2019-06-20 |
20190189830 | SPUTTER COATING DEVICE AND METHOD FOR SOLAR CELL - The present disclosure discloses a sputter coating device and method for a solar cell. The sputter coating device includes a target for sputtering to a substrate, a blocking unit between the target and the substrate, and the orthographic projection of the blocking unit on the substrate partially coincides with the orthographic projection of the target on the substrate. | 2019-06-20 |
20190189831 | PROCESSING METHOD FOR REMOVING FILM AND APPARATUS FOR REMOVING FILM - Embodiments of the present disclosure provide a processing method for removing film and apparatus for removing film. The apparatus for removing film includes an optical component and a processor, in which the optical component includes: a laser generator configured to generate a laser beam; a first scanning galvanometer configured to reflect the laser beam; and a second scanning galvanometer configured to reflect the laser beam reflected by the first scanning galvanometer. The processor is configured to control the laser generator to generate a laser beam, and control the first scanning galvanometer and the second scanning galvanometer to deflect, thereby performing the film removal process on the target object. | 2019-06-20 |
20190189832 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND MANUFACTURING METHOD - The present invention provides a semiconductor light emitting device including a substrate, a first semiconductor layer, a first cladding layer, an active layer, a second cladding layer and a second semiconductor layer, and a manufacturing method. The first semiconductor layer may be an n-type semiconductor including a III-V semiconductor or a II-VI semiconductor. The second semiconductor layer may be a p-type semiconductor including a I-VII semiconductor. The semiconductor light emitting device may further include a third cladding layer between the active layer and the second cladding layer, the third cladding layer including a III-V semiconductor or a II-VI semiconductor. Therefore, by providing the hybrid type semiconductor light emitting device and the manufacturing method thereof, the luminous efficiency limit of the p-type semiconductor can be overcome. | 2019-06-20 |
20190189833 | METHOD OF PREVENTING CONTAMINATION OF LED DIE - A method for allowing a reflective layer to abut against an edge of a metal contact while preventing contamination of a metal contact for an LED die is provided. The method includes encapsulating an electrical contact (i.e. metal contact) via with a barrier layer prior to deposition of a reflective film layer. The barrier layer encapsulates the metal contact by defining a mask pattern with a larger size than the metal contact via, which prevents the metal contact from becoming contaminated by the reflective film. This encapsulation reduces contamination of the metal contact and also reduces the voltage drop during operation of the LED die. | 2019-06-20 |
20190189834 | OPTICAL SEMICONDUCTOR ELEMENT - An optical semiconductor element comprises: an AlN substrate; an n-type semiconductor layer composed of an AlGaN layer, the AlGaN layer being grown on the AlN substrate and being pseudomorphic with the AlN substrate, an Al composition or the AlGaN layer being reduced with an increase in distance from the AlN substrate; an active layer which is grown on the n-type semiconductor layer; and a p-type semiconductor layer which is grown on the active layer. | 2019-06-20 |
20190189835 | METHOD OF MANUFACTURING AN OPTOELECTRONIC DEVICE BY TRANSFERRING A CONVERSION STRUCTURE ONTO AN EMISSION STRUCTURE - The invention relates to a method of manufacturing an optoelectronic device ( | 2019-06-20 |
20190189836 | VERTICAL TYPE LIGHT EMITTING DIODE DIE AND METHOD FOR FABRICATING THE SAME - A vertical type light emitting diode die and a method for fabricating the same is disclosed. A growth substrate is provided and an epitaxial layer is formed on the growth substrate. A metallic combined substrate is connected to the epitaxial layer. Then, the growth substrate is removed. Electrode units are formed on the top surface of the epitaxial layer. The epitaxial layer is divided into epitaxial dies according to the number of the plurality of electrode units. Each vertical type light emitting diode die formed in the abovementioned way includes the metallic combined substrate having a first metal layer and second metal layers. The first metal layer is combined with the two second metal layers by cutting, vacuum heating, and polishing, so as to enable the metallic combined substrate to have a high coefficient of thermal conductivity, a low coefficient of thermal expansion, and initial magnetic permeability. | 2019-06-20 |
20190189837 | VERTICAL TYPE LIGHT EMITTING DIODE DIE AND METHOD FOR FABRICATING THE SAME - A vertical type light emitting diode die and a method for fabricating the same is disclosed. A growth substrate is provided and an epitaxial layer is formed on the growth substrate. A metallic combined substrate is connected to the epitaxial layer. Then, the growth substrate is removed. Electrode units are formed on the top surface of the epitaxial layer. The epitaxial layer is divided into epitaxial dies according to the number of the plurality of electrode units. Each vertical type light emitting diode die formed in the abovementioned way includes the metallic combined substrate having a first metal layer and second metal layers. The first metal layer is combined with the two second metal layers by cutting, vacuum heating, and polishing, so as to enable the metallic combined substrate to have a high coefficient of thermal conductivity, a low coefficient of thermal expansion, and initial magnetic permeability. | 2019-06-20 |
20190189838 | SEMICONDUCTOR LIGHT EMITTING DEVICE INCLUDING A WINDOW LAYER AND A LIGHT-DIRECTING STRUCTURE - A device comprises a window layer and a light-directing structure comprising a porous semiconductor layer formed in an n-type region. The device comprises a semiconductor structure, disposed between the window layer and the light-directing structure, comprising a light emitting layer. An opening is formed in the semiconductor structure. A first metal layer is in direct contact with the light-directing structure. A dielectric layer is disposed over the first metal layer and in the opening. A second metal layer is disposed over the dielectric layer. A transparent conductive oxide is disposed between the p-type region and the window layer and in direct contact with the p-type region. A first hole is formed in the dielectric layer, wherein the first hole exposes the transparent conductive oxide such that the second metal layer is in direct contact with the transparent conductive oxide through the first hole. | 2019-06-20 |
20190189839 | DISPLAY PANEL, METHOD FOR PROCESSING DEFECTIVE PIXELS THEREOF, DISPLAY DEVICE - The present disclosure provides a display panel, a display device comprising such a display panel, and a method for processing defective pixels of such a display panel. The display panel comprises: a substrate; a plurality of pixel units on the substrate and arranged in an array. Each of the pixel units includes a light emitting region and a driving circuit region. In each of the pixel units, the driving circuit region includes a transistor, the light emitting region includes a first electrode, and the first electrode is electrically coupled to a first terminal of the transistor. In a row direction or a column direction of the plurality of pixel units arranged in an array, light emitting regions of two adjacent pixel units are adjacent to each other. | 2019-06-20 |
20190189840 | METHOD OF TRANSFERRING NANOSTRUCTURES AND DEVICE HAVING THE NANOSTRUCTURES - An illustrative method for transferring nanostructures is provided with the steps of: forming a two-dimensional material (2D material) on a first substrate; forming a plurality of nanostructures on the 2D material; bonding a surface of one or more of the plurality of nanostructures with a head or a second substrate, and/or shaking the one or more nanostructures with or without a fluid; and separating the one or more nanostructures from the 2D material. | 2019-06-20 |
20190189841 | ULTRAVIOLET LIGHT EMITTING DEVICES HAVING A DIELECTRIC LAYER AND A TRANSPARENT ELECTRODE LAYER DISPOSED IN BETWEEN PATTERNED NITRIDE SEMICONDUCTOR LAYERS - An ultraviolet light emitting device including a first conductivity-type AlGaN semiconductor layer; an active layer disposed on the first conductivity-type AlGaN semiconductor layer and having an AlGaN semiconductor; a second conductivity-type AlGaN semiconductor layer disposed on the active layer and having an upper surface divided into a first region and a second region; second conductivity-type nitride patterns disposed on the first region of the second conductivity-type AlGaN semiconductor layer and having an energy band gap that is smaller than an energy band gap of the second conductivity-type AlGaN semiconductor layer; a transparent electrode layer covering the second conductivity-type nitride patterns and the second region of the second conductivity-type AlGaN semiconductor layer; a light-transmissive dielectric layer disposed on the transparent electrode layer between the second conductivity-type nitride patterns; and a metal electrode disposed on the transparent electrode layer overlying the second conductivity type nitride patterns and on the light-transmissive dielectric layer. | 2019-06-20 |
20190189842 | PLASMONIC LIGHT EMITTING DIODE - A light emitting diode includes a square quantum well structure, the quantum well structure including III-V materials. A dielectric layer is formed on the quantum well structure. A plasmonic metal is formed on the dielectric layer and is configured to excite surface plasmons in a waveguide mode that is independent of light wavelength generated by the quantum well structure to generate light. | 2019-06-20 |
20190189843 | LIGHT EXTRACTION STRUCTURES FOR SEMICONDUCTOR DEVICES - Aspects of the disclosure provide for mechanisms for fabricating light extraction structures for semiconductor devices (e.g., light-emitting devices). In accordance with some embodiments, a semiconductor device is provided. The semiconductor device may include: a first semiconductor layer including an epitaxial layer of a semiconductor material; a second semiconductor layer comprising an active layer; and a light-reflection layer configured to cause at least a portion of light produced by the active layer to emerge from the semiconductor device via a surface of the second semiconductor layer, wherein the light-reflection layer is positioned between the first semiconductor layer and the second semiconductor layer. In some embodiments, the semiconductor material includes gallium nitride. In some embodiments, the light-reflection layer includes a layer of gallium. | 2019-06-20 |
20190189844 | LIGHT EMITTING DEVICE - A semiconductor light emitting device includes a first light emitting portion including a first semiconductor stack, as well as a first lower dispersion Bragg reflector (DBR) layer and a first upper dispersion Bragg reflector (DBR) layer, disposed above and below the first semiconductor stack, a second light emitting portion including a second semiconductor stack, as well as a second lower dispersion Bragg reflector (DBR) layer and a second upper dispersion Bragg reflector (DBR) layer, disposed above and below the second semiconductor stack, a third light emitting portion including a third semiconductor stack, as well as a third lower dispersion Bragg reflector (DBR) layer and a third upper dispersion Bragg reflector (DBR) layer, disposed above and below the third semiconductor stack, a first bonding layer disposed between the first light emitting portion and the second light emitting portion, and a second bonding layer disposed between the second light emitting portion and the third light emitting portion. | 2019-06-20 |
20190189845 | Semiconductor Stacking Structure, and Method and Apparatus for Separating Nitride Semiconductor Layer Using Same - A semiconductor stacking structure according to the present invention comprises: a monocrystalline substrate which is disparate from a nitride semiconductor; an inorganic thin film which is formed on a substrate to define a cavity between the inorganic thin film and the substrate, wherein at least a portion of the inorganic thin film is crystallized with a crystal structure that is the same as the substrate; and a nitride semiconductor layer which is grown from a crystallized inorganic thin film above the cavity. The method and apparatus for separating a nitride semiconductor layer according the present invention mechanically separate between the substrate and the nitride semiconductor layer. The mechanical separation can be performed by a method of separation of applying a vertical force to the substrate and the nitride semiconductor layer, a method of separation of applying a horizontal force, a method of separation of applying a force of a relative circular motion, and a combination thereof. | 2019-06-20 |
20190189846 | ULTRAVIOLET LIGHT EMITTING DEVICES - An embodiment of the present inventive concept provides an ultraviolet light emitting device comprising: a substrate having a concave or convex edge pattern disposed along an edge of an upper surface thereof; a semiconductor laminate disposed on the substrate and including first and second conductivity-type AlGaN semiconductor layers and an active layer disposed between the first and second conductivity-type AlGaN semiconductor layers and having an AlGaN semiconductor; a plurality of uneven portions extending from the edge pattern along the side surface of the semiconductor laminate in a stacking direction; and first and second electrodes connected to the first and second conductivity-type AlGaN semiconductor layers, respectively. | 2019-06-20 |
20190189847 | SUBSTRATE AND PLANAR ILLUMINATION DEVICE - A substrate according to an embodiment includes a plurality of land portions that are bonded to a plurality of terminals of a light source via solder, respectively, the light source having the terminals on a surface other than a light-emitting surface, each of the land portions having a cutout provided by cutting in accordance with a shape of the corresponding terminal. | 2019-06-20 |
20190189848 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes a light emitting stack including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, a plurality of holes through the second conductive semiconductor layer and the active layer, a trench extending along an edge of the light emitting stack, the trench extending through the second conductive semiconductor layer and the active layer, and a reflective metal layer within the plurality of holes and within the trench. | 2019-06-20 |
20190189849 | AIR VOID STRUCTURES FOR SEMICONDUCTOR FABRICATION - Aspects of the disclosure provide for mechanisms for forming air voids for semiconductor fabrication. In accordance with some embodiments, a method for forming air voids may include forming a first semiconductor layer including a first group III material and a second group III material on a substrate; forming a plurality of air voids in the first semiconductor layer by removing at least a portion of the second group III material from the first semiconductor layer; and forming a second semiconductor layer on the first semiconductor layer. The second semiconductor layer may include an epitaxial layer of a group III-V material. In some embodiments, the first group III material and the second group III material may be gallium and indium, respectively. | 2019-06-20 |
20190189850 | LIGHT-EMITTING DEVICE - A light-emitting device, includes a first semiconductor stack formed on a substrate, including a first semiconductor layer, a second semiconductor layer and an active layer formed therebetween; a first electrode formed on the first semiconductor layer; a second electrode formed on the second semiconductor layer, including a second pad electrode and a second finger electrode extending from the second pad electrode; a second current blocking region formed under the second electrode, including a second core region under the second pad electrode and a extending region under the second finger electrode; and a transparent conductive layer, formed on the second semiconductor layer and covering the extending region; wherein a contour of the second core region has a shape different from that of the second pad electrode; wherein the transparent conductive layer includes a first opening having a width wider than a width of the second pad electrode, wherein the second finger electrode includes a portion extending from the contour of the second pad electrode and having a width wider than other portion of the second finger electrode, and part of the portion is not covered by the transparent conductive layer. | 2019-06-20 |
20190189851 | LIGHT EMITTING DEVICE AND PRODUCTION METHOD THEREOF - A light emitting device includes a substrate, a light emitting unit disposed on the substrate, a metallic electrode unit, a metallic adhesion layer disposed on the first and second electrodes of the electrode unit, and a protective layer disposed on the adhesion layer. The first electrode is disposed on a portion of a first-type semiconductor layer of the light emitting unit. The second electrode is disposed on a second-type semiconductor layer of the light emitting unit disposed on a separated portion of the first-type semiconductor layer. The first and second electrodes are partially exposed by the protective layer and the adhesion layer that is partially exposed by the protective layer. A production method for the light emitting device is also disclosed. | 2019-06-20 |
20190189852 | OPTOELECTRONIC SEMICONDUCTOR DEVICE - An optoelectronic semiconductor device includes a semiconductor layer sequence having an active zone that generates radiation, a first electrode that supplies current directly to a bottom side of the semiconductor layer sequence, and a second electrode that supplies current and extends from the bottom side to a top side of the semiconductor layer sequence opposite the bottom side, wherein the second electrode includes at least one current distribution structure on the top side, and the current distribution structure is impermeable to the generated radiation and electrically connected in a plurality of contact regions to at least one further component of the second electrode and configured for lateral current distribution starting from the contact regions. | 2019-06-20 |
20190189853 | LIGHT EMITTING DEVICE PACKAGE - A light emitting device package comprises a light emitting cell array including a first light emitting cell, a second light emitting cell, and a third light emitting cell, and including a first surface, and a second surface, disposed to oppose the first surface; a plurality of metal pillars disposed on the first surface of the light emitting cell array and electrically connected to the first light emitting cell, the second light emitting cell, and the third light emitting cell; and a molding portion encapsulating the light emitting cell array and the plurality of metal pillars, wherein the plurality of metal pillars include a conductive layer and a bonding layer disposed below the conductive layer, and an interface between the bonding layer and the conductive layer is higher than a lower surface of the molding portion. | 2019-06-20 |
20190189854 | SEMICONDUCTOR DEVICE, LIGHT-EMITTING DEVICE CHIP, OPTICAL PRINT HEAD, AND IMAGE FORMING DEVICE - A semiconductor device includes a light-emitting thyristor, including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, and a fourth semiconductor layer of the second conductivity type, and first to third electrodes. The first semiconductor layer includes a first layer, a second layer having a band gap wider than band gaps of the second semiconductor layer and the third semiconductor layer, and a third layer having an impurity concentration higher than impurity concentrations of the second semiconductor layer and the third semiconductor layer and having a band gap narrower than or equal to the band gaps of the second semiconductor layer and the third semiconductor layer. | 2019-06-20 |
20190189855 | OPTOELECTRONIC DEVICE AND PROCESS OF PRODUCING AN OPTOELECTRONIC DEVICE - An optoelectronic device includes an active layer stack that generates or detects radiation, a radiation entrance or radiation exit surface including an inorganic material, and a protective layer disposed over the radiation entrance or radiation exit surface and including chemical compounds each containing an anchor group and a head group, wherein the anchor group is bonded to the inorganic material, and an encapsulation laterally surrounding at least the active layer stack or at least the active layer stack and the protective layer. | 2019-06-20 |