25th week of 2014 patent applcation highlights part 19 |
Patent application number | Title | Published |
20140167054 | THIN FILM TRANSISTOR ARRAY PANEL INCLUDING LAYERED LINE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu). | 2014-06-19 |
20140167055 | METHOD OF PROCESSING A SILICON WAFER AND A SILICON INTEGRATED CIRCUIT - Methods and systems for processing a silicon wafer are disclosed. A method includes providing a flash memory region in the silicon wafer and providing a bipolar transistor with a polysilicon external base in the silicon wafer. The flash memory region and the bipolar transistor are formed by depositing a single polysilicon layer common to both the flash memory region and the bipolar transistor. | 2014-06-19 |
20140167056 | SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - A voltage equal to the threshold value of a TFT ( | 2014-06-19 |
20140167057 | REO/ALO/AlN TEMPLATE FOR III-N MATERIAL GROWTH ON SILICON - A method of forming a template on a silicon substrate includes providing a single crystal silicon substrate. The method further includes epitaxially depositing a layer of rare earth oxide on the surface of the silicon substrate. The rare earth oxide being substantially crystal lattice matched to the surface of the silicon substrate. The method further includes forming an aluminum oxide layer on the rare earth oxide, the aluminum oxide being substantially crystal lattice matched to the surface of the rare earth oxide and epitaxially depositing a layer of aluminum nitride (AlN) on the aluminum oxide layer substantially crystal lattice matched to the surface of the aluminum oxide. | 2014-06-19 |
20140167058 | COMPOSITIONALLY GRADED NITRIDE-BASED HIGH ELECTRON MOBILITY TRANSISTOR - An epitaxial structure on a substrate includes a gallium nitride buffer layer over the substrate and a graded channel layer over the gallium nitride layer. The graded channel layer consists essentially of In | 2014-06-19 |
20140167059 | PEC ETCHING OF (20-2-1) SEMIPOLAR GALLIUM NITRIDE FOR EXTERNAL EFFICIENCY ENHANCEMENT IN LIGHT EMITTING DIODE APPLICATIONS - A method of performing a photoelectrochemical (PEC) etch on an exposed surface of a semipolar {20-2-1} III-nitride semiconductor, for improving light extraction from and for enhancing external efficiency of one or more active layers formed on or above the semipolar {20-2-1} III-nitride semiconductor. | 2014-06-19 |
20140167060 | NORMALLY OFF POWER ELECTRONIC COMPONENT - An electronic power component including a normally on high-voltage transistor and a normally off low-voltage transistor. The normally on transistor and the normally off transistor are coupled in cascode configuration and are housed in a single package. The normally off transistor is of the bottom-source type. | 2014-06-19 |
20140167061 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a p-type semiconductor layer; an n-type semiconductor layer connected with the p-type semiconductor layer; a first electrode layer formed on the n-type semiconductor layer; and a second electrode layer formed on the p-type semiconductor layer. The first electrode layer and the second electrode layer are electrically connected such as to each operate at an identical potential. The second electrode layer is connected with at least a part of a surface of the first electrode layer which is opposite to a surface of the first electrode layer that is in contact with the n-type semiconductor layer. | 2014-06-19 |
20140167062 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device includes the steps of: forming a first electrode layer on a n-type semiconductor layer; forming a second electrode layer on a p-type semiconductor layer; and performing heat treatment for the first electrode layer and the second electrode layer formed on the semiconductor layers. Temperature of the heat treatment is not lower than 400 degrees centigrade and not higher than 650 degrees centigrade. | 2014-06-19 |
20140167063 | LED CHIP PACKAGING STRUCTURE, ITS MANUFACTURING METHOD, AND DISPLAY DEVICE - A LED chip packaging structure, its manufacturing method, and a display device are disclosed. A conductive unit is formed at two opposite sides of a LED chip unit, and comprises a first conductive layer formed at a side of, and electrically connected to, a first electrode, a second conductive layer formed at a side of, and electrically connected to, a second electrode, and an intermediate isolation layer formed at a side of a GaN layer. The LED chip unit and the conductive unit are connected laterally to form an electrical-connection channel as a whole, without welding a gold wire for the conductive channel as in a traditional LED. Thus, the method is able to reduce the total thickness of the LED chip device, increase the thermal conductivity effect of the LED chip and the overall stability, and improve the light-extraction effect of the surface of the LED chip. | 2014-06-19 |
20140167064 | GaN HEMTs AND GaN DIODES - A GaN hetereojunction structure has a three-layer dielectric structure. The lowermost and middle portions of the gate electrode together define the gate foot, and this is associated with two dielectric layers. A thinner first dielectric layer is adjacent the gate edge at the bottom of the gate electrode. The second dielectric layer corresponds to the layer in the conventional structure, and it is level with the main portion of the gate foot. | 2014-06-19 |
20140167065 | LED STRUCTURE WITH ENHANCED MIRROR REFLECTIVITY - Embodiments of the present invention are generally related to LED chips having improved overall emission by reducing the light-absorbing effects of barrier layers adjacent mirror contacts. In one embodiment, a LED chip comprises one or more LEDs, with each LED having an active region, a first contact under the active region having a highly reflective mirror, and a barrier layer adjacent the mirror. The barrier layer is smaller than the mirror, such that it does not extend beyond the periphery of the mirror. In another possible embodiment, an insulator is further provided, with the insulator adjacent the barrier layer and adjacent portions of the mirror not contacted by the active region or by the barrier layer. In yet another embodiment, a second contact is provided on the active region. In a further embodiment, the barrier layer is smaller than the mirror such that the periphery of the mirror is at least 40% free of the barrier layer, and the second contact is below the first contact and accessible from the bottom of the chip. | 2014-06-19 |
20140167066 | LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING SAME - A semiconductor light emitting element including, in a light extraction layer thereof, a photonic crystal periodic structure including two systems (structures) with different refractive indices. An interface between the two systems (structures) satisfies Bragg scattering conditions, and the photonic crystal periodic structure has a photonic band gap. | 2014-06-19 |
20140167067 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT HAVING SUPERIOR LEAKAGE CURRENT BLOCKING EFFECT AND METHOD FOR MANUFACTURING SAME - Disclosed are a nitride semiconductor light-emitting element and a method for manufacturing the same. The nitride semiconductor light-emitting element according to the present invention comprises: a current blocking part disposed between a substrate and an n-type nitride layer; an activation layer disposed on the top surface of the n-type nitride layer; and a p-type nitride layer disposed on the top surface of the activation layer, wherein the current blocking part is an Al | 2014-06-19 |
20140167068 | SYSTEMS AND METHODS FOR OHMIC CONTACTS IN SILICON CARBIDE DEVICES - A silicon carbide device is presented that includes a gate electrode disposed over a portion of a silicon carbide substrate as well as a dielectric film disposed over the gate electrode. The device has a contact region disposed near the gate electrode and has a layer disposed over the dielectric film and over the contact region. The layer includes nickel in portions disposed over the dielectric film and includes nickel silicide in portions disposed over the contact region. The nickel silicide layer is configured to provide an ohmic contact to the contact region of the silicon carbide device. | 2014-06-19 |
20140167069 | SYSTEMS AND METHODS FOR INTEGRATING BOOTSTRAP CIRCUIT ELEMENTS IN POWER TRANSISTORS AND OTHER DEVICES - Embodiments relate to bootstrap circuits integrated with at least one other device, such as a power transistor or other semiconductor device. In embodiments, the bootstrap circuit can comprise a bootstrap capacitor and a bootstrap diode, or the bootstrap circuit can comprise a bootstrap capacitor and a bootstrap transistor. The bootstrap capacitor comprises a semiconductor-based capacitor, as opposed to an electrolytic, ceramic or other capacitor, in embodiments. The integration of the bootstrap circuit with another circuit or device, such as a power transistor device in one embodiment, is at a silicon-level in embodiments, rather than as a module-like system-in-package of conventional approaches. In other words, the combination of the bootstrap circuit elements and power transistor or other device forms a system-on-silicon, or an integrated circuit, in embodiments, and additionally can be arranged in a single package. | 2014-06-19 |
20140167070 | ELECTRONIC CHIP AND METHOD OF FABRICATING THE SAME - Provided are an electronic chip and a method of fabricating the same. The semiconductor chip may include a substrate, an active device integrated on the substrate, a lower interlayered insulating layer covering the resulting structure provided with the active device, a passive device provided on the lower interlayered insulating layer, an upper interlayered insulating layer covering the resulting structure provided with the passive device, and a ground electrode provided on the upper interlayered insulating layer. The upper interlayered insulating layer may be formed of a material, whose dielectric constant may be higher than that of the lower interlayered insulating layer. | 2014-06-19 |
20140167071 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a plurality of n type pillar regions and an n− type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate; a p type epitaxial layer and an n+ region disposed on the plurality of n type pillar regions and the n− type epitaxial layer; a trench penetrating the n+ region and the p type epitaxial layer and disposed on the plurality of n type pillar regions and the n− type epitaxial layer; a gate insulating film disposed within the trench; a gate electrode disposed on the gate insulating film; an oxide film disposed on the gate electrode; a source electrode disposed on the p type epitaxial layer, the n+ region, and the oxide film; and a drain electrode disposed on a second surface of the n+ type silicon carbide substrate, wherein each corner portion of the trench is in contact with a corresponding n type pillar region. | 2014-06-19 |
20140167072 | SCHOTTKY BARRIER DIODE AND METHOD OF MANUFACTURING THE SAME - A schottky barrier diode includes an n− type epitaxial layer disposed at a first surface of an n+ type silicon carbide substrate, a plurality of n type pillar areas disposed in the n− type epitaxial layer at a first portion of a first surface of the n+ type silicon carbide substrate, a plurality of p+ areas disposed at a surface of the n− type epitaxial layer and separated from the n type pillar area, a schottky electrode disposed on the n− type epitaxial layer and the p+ area, and an ohmic electrode disposed at a second surface of the n+ type silicon carbide substrate. A doping density of the n type pillar area is larger than a doping density of the n− type epitaxial layer. | 2014-06-19 |
20140167073 | SILICON CARBIDE SEMICONDUCTOR DEVICES HAVING NITROGEN-DOPED INTERFACE - Methods, systems, and devices are disclosed for implementing high power circuits and semiconductor devices. In one aspect, a method for fabricating a silicon carbide semiconductor device includes forming a thin epitaxial layer of a nitrogen doped SiC material on a SiC epitaxial layer formed on a SiC substrate, and thermally growing an oxide layer to form an insulator material on the nitrogen doped SiC epitaxial layer, in which the thermally grown oxide layer results in at least partially consuming the nitrogen doped SiC epitaxial layer in the oxide layer to produce an interface including nitrogen between the SiC epitaxial layer and the oxide layer. | 2014-06-19 |
20140167074 | Intensity Scattering LED Apparatus - An Intensity Scattering LED apparatus which comprises an uneven surface on the tip of the epoxy encapsulation layer of the LED to act as a scattering lens such that the light beam on the normal line, relative to the light source, is scattered and the intensity to the human eye or human body is decreased. Simultaneously, the light beams that are not on the normal line are unchanged, and moreover, the total intensity and the brightness of the LED remain unchanged. In the instant invention, no reductions in driving current or additional diffusing agents are needed to decrease the intensity and the brightness of the LED and may be structured as Pin Packaging having two or more supporting legs and/or SMD (Surface Mount Device) Packaging having no supporting leg but having two or more connecting pads. | 2014-06-19 |
20140167075 | PHOSPHOR CAP FOR LED DIE TOP AND LATERAL SURFACES - A method for depositing a layer of phosphor-containing material on a plurality of LED dies includes disposing a template with a plurality of openings on an adhesive tape and disposing each of a plurality of LED dies in one of the plurality of openings of the template. The method also includes forming a patterned dry film photoresist layer over the template and the plurality of LED dies. The photoresist layer has a plurality of openings configured to expose a top surface and side surfaces of each of the LED dies. Next, a phosphor-containing material is disposed on the exposed top surface of each the LED dies. The method further includes removing the photoresist layer and the template. | 2014-06-19 |
20140167076 | LED MODULE WITH SEPARATE HEAT-DISSIPATION AND ELECTRICAL CONDUCTION PATHS, AND RELATED HEAT DISSIPATION BOARD - A LED module with separate heat-dissipation and electrical conduction paths is disclosed, having a metal substrate; a plastic layer, comprising one or more hollow regions, and attached to the metal substrate; one or more conducting elements attached to the plastic layer; one or more LED chips positioned in the one or more hollow regions of the plastic layer and directly attached to the metal substrate; and a plurality of conducting wires for electrically connecting the one or more conducting elements and the one or more LED chips; wherein inner sides of the one or more hollow regions comprise one or more inclined surfaces each having an included angle with an upper surface of the metal substrate, and the included angle is between 90-180 degrees. | 2014-06-19 |
20140167077 | LIGHT SOURCE MODULE - A light source module includes a substrate, at least two light emitting diode (LED) chips and at least one dummy chip. The LED chips are disposed on the substrate. The dummy chip is disposed on the substrate and located between the LED chips. The LED chips, the dummy chip and the substrate are electrically connected to one another. The dummy chip is used to redirect a lateral light emitted from the LED chips. | 2014-06-19 |
20140167078 | LEAD FRAME AND LIGHT EMITTING DIODE PACKAGE HAVING THE SAME - An exemplary lead frame includes a substrate and a bonding electrode, a first connecting electrode, and a second connecting electrode embedded in the substrate. A top surface of the bonding electrode includes a first bonding surface and a second bonding surface spaced from the first bonding surface. A top surface of the first connecting electrode includes a first connecting surface and a second connecting surface spaced from the first connecting surface. Top surfaces of the bonding electrode, the first connecting electrode and the second connecting electrode are exposed out of the substrate to support and electrically connect with light emitting chips. Light emitting chips can be mounted on the lead frame and electrically connect with each other in parallel or in series; thus, the light emitting chips can be connected with each in a versatile way. | 2014-06-19 |
20140167079 | ARRAY SUBSTRATE, METHOD FOR FABRICATING THE SAME AND DISPLAY DEVICE - An array substrate, a method for fabricating the same and a display device are disclosed. The array substrate comprises a display region, at least two common electrode blocks are disposed at a periphery of the display region and conducted via a pixel electrode bridge line pattern. | 2014-06-19 |
20140167080 | LIGHT EMITTING DEVICE - A light emitting device includes a substrate, light emitting units, an insulation layer, a current distribution layer and a reflective layer. The substrate has an upper surface. The light emitting units are disposed on the upper surface and include at least one first light emitting diode (LED) and at least one second LED. A first side wall of the first LED is adjacent to a second side wall of the second LED so as to define a concave portion exposing a portion of the upper surface. The insulation layer at least covers the first side wall and the second side wall. The current distribution layer covers the concave portion and at least covers a portion of the second LED. The reflective layer covers the current distribution layer and is electrically connected to the first LED and the second LED. | 2014-06-19 |
20140167081 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a substrate; a semiconductor layer composed of GaN-based compound semiconductor on the substrate; a source electrode, a gate electrode, and a drain electrode on the substrate; and an additive substance added to the semiconductor layer. The additive substance serves as a luminescent center within the semiconductor layer. Charge trapped at an energy level in the semiconductor layer is released and recombined by light generated from the luminescent center. | 2014-06-19 |
20140167082 | GaN LEDs WITH IMPROVED AREA AND METHOD FOR MAKING THE SAME - Enlightening device and method for making the same are disclosed. Individual light emitting devices such as LEDs are separated to form individual dies by process in which a first narrow trench cuts the light emitting portion of the device and a second trench cuts the substrate to which the light emitting portion is attached. The first trench can be less than 10 μm. Hence, a semiconductor area that would normally be devoted to dicing streets on the wafer is substantially reduced thereby increasing the yield of devices. The devices generated by this method can also include base members that are electrically conducting as well as heat conducting in which the base member is directly bonded to the light emitting layers thereby providing improved heat conduction. | 2014-06-19 |
20140167083 | LED PACKAGE WITH INTEGRATED REFLECTIVE SHIELD ON ZENER DIODE - A lighting package is disclosed. The lighting package is disclosed as including a primary light source, such as a Light Emitting Diode, and an additional electrical component that protects the primary light source from electrostatic discharge, for example. The additional electrical component may correspond to a Zener diode and may be treated with at least one material that helps reduce the light absorption of the Zener diode. | 2014-06-19 |
20140167084 | PHOSPHOR, METHOD FOR PRODUCING THE SAME, AND LUMINESCENT DEVICE USING THE SAME - A blue phosphor having an emission peak wavelength different from that of conventional blue phosphors, a method for producing the same, and a high-intensity luminescent device using the phosphor are provided. The phosphor of the present invention is represented by a general formula Me | 2014-06-19 |
20140167085 | LIGHT EMITTING DEVICE HAVING IMPROVED LIGHT EXTRACTION EFFICIENCY - According to example embodiments, a light emitting device includes a transparent substrate, a transparent electrode on a transparent substrate, a transparent light extraction layer at least partially on the transparent electrode, a light emitting layer on the transparent electrode, and a reflective electrode on the light extraction layer and the light emitting layer. The light extraction layer and the light emitting layer may be alternately and repeatedly arranged between the transparent electrode and the reflective electrode. | 2014-06-19 |
20140167086 | EPITAXIAL LAYER WAFER HAVING VOID FOR SEPARATING GROWTH SUBSTRATE THEREFROM AND SEMICONDUCTOR DEVICE FABRICATED USING THE SAME - An epitaxial wafer having a void for separation of a substrate and a semiconductor device fabricated using the same. The epitaxial wafer includes a substrate, a mask pattern disposed on the substrate and comprising a masking region and an opening region, and an epitaxial layer covering the mask pattern. The epitaxial layer includes a void disposed on the masking region. | 2014-06-19 |
20140167087 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD FOR THE SAME - The present invention provides a light emitting device, which includes a light emitting diode (LED) chip, a wavelength conversion plate including a fluorescent substance and disposed on a light output surface side of the LED chip, and a sub heat radiation path formed to radiate heat of the wavelength conversion plate. The sub heat radiation path includes a transparent heat-conductive film provided on a surface of the wavelength conversion plate, a heat radiator provided in the vicinity of the LED chip, and a thermal connection member that thermally connects the transparent heat-conductive film to the heat radiator. | 2014-06-19 |
20140167088 | Molded Reflectors for Light-Emitting Diode Assemblies - Polymer compositions are described that are well suited for producing reflectors for light-emitting devices, such as light-emitting diodes. In one particular embodiment, the polymer composition contains a polymer resin, a white pigment, a silicone compound, and a nucleating agent. The polymer resin may comprise, for instance, a poly(1,4-cyclohexanedimethanol terephthalate). In accordance with the present disclosure, the composition also contains at least one silicone compound and at least one nucleating agent. The silicone compound and nucleating agent have been found to improve the molding processability and reflectance stability of the polymer composition. | 2014-06-19 |
20140167089 | HIGH EFFICIENCY GROUP III NITRIDE LED WITH LENTICULAR SURFACE - A high efficiency Group III nitride light emitting diode is disclosed. The diode includes a Group III nitride-based light emitting region including a plurality of Group III nitride-based layers. A lenticular surface directly contacts one of the Group III nitride-based layers of the light emitting region. The lenticular surface includes a transparent material that is different from the Group III nitride-based layer of the light emitting region that the lenticular surface directly contacts. | 2014-06-19 |
20140167090 | OPTOELECTRONIC TRANSMISSION SYSTEM AND METHOD - An optoelectronic transmission system has a photoemitter semiconductor component and a photodetector semiconductor component. The photoemitter semiconductor component has a radiation source for converting a first electrical signal into a first electromagnetic radiation and a first polarization filter having a first polarization direction for filtering the first electromagnetic radiation. The photodetector semiconductor component has a second polarization filter having a second polarization direction for filtering a second electromagnetic radiation and a sensor element for converting a second electromagnetic radiation which has been polarized by the polarization filter into a second electrical signal. In this case, the first polarization direction of the first polarization filter is identical to the second polarization direction of the second polarization filter. | 2014-06-19 |
20140167091 | THERMOPLASTIC RESIN COMPOSITION FOR REFLECTIVE MATERIAL, REFLECTIVE PLATE, AND LIGHT-EMITTING DIODE ELEMENT - The purpose of the present invention is to provide a thermoplastic resin composition for a reflective material which has excellent mechanical strength, excellent heat resistance, excellent high reflectance, and excellent moldability, and which makes it possible to obtain a reflective plate with little decline in reflectance caused by heating. A first embodiment of this thermoplastic resin composition for a reflective material includes: a polyester resin (A) that has a melting point or glass transition temperature of 250° C. or higher and includes an alicyclic hydrocarbon structure; a thermoplastic resin (B) that has a polyolefin backbone and a functional group; a white pigment (C); and an inorganic filler (D); the thermoplastic resin (B) either including 0.1 to 1.8 wt % of a functional group unit (B1) that further includes a heteroatom, or further including an aromatic hydrocarbon structure (B2), and the limiting viscosity [η] being 0.04 to 1.0 dl/g. | 2014-06-19 |
20140167092 | OPTOELECTRONIC ASSEMBLY AND METHOD FOR PRODUCING AN OPTOELECTRONIC ASSEMBLY - An optoelectronic assembly includes a carrier, an optoelectronic component arranged on the carrier, wherein the optoelectronic component includes a substrate and a light-emitting layer arranged on the substrate, and a light-reflecting first encapsulation at least locally covers a region of the carrier surrounding the optoelectronic component and side surfaces of the optoelectronic component. | 2014-06-19 |
20140167093 | LIGHT EMITTING DIODE HAVING A PLURALITY OF HEAT CONDUCTIVE COLUMNS - An LED (light emitting diode) includes a substrate, a first electrode and a second electrode located on the substrate, and an LED chip electrically connected to the first electrode and the second electrode. The substrate includes a ceramic plate and a plurality of metallic heat conductive columns inserted in an interior of the plate. The plurality of heat conductive columns is spaced from each other and all located rightly underneath the LED chip. The LED chip is thermally connected to the plurality of heat conductive columns. | 2014-06-19 |
20140167094 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes an electrode layer, a first semiconductor layer, a first elongated electrode, a second semiconductor layer, and a light emitting layer. The first semiconductor layer includes a crystal having a cleavage plane. The first semiconductor layer includes a first thin film portion and a thick film portion. The first thin film portion extends in a first direction perpendicular to a stacking direction from the electrode layer toward the first semiconductor layer. The first thin film portion has a first thickness. The thick film portion is arranged with the first thin film portion in a plane perpendicular to the stacking direction. An angle between the first direction and the cleavage plane is not less than 3 degrees and not more than 27 degrees. The first elongated electrode extends in the first direction in contact with the first thin film portion. | 2014-06-19 |
20140167095 | LIGHT EMITTING DEVICE PACKAGE - Disclosed is a light emitting device package including a package body including at least one electrode pad disposed on a surface thereof, a light emitting device disposed on the package body, the light emitting device being electrically connected to the electrode pad through a wire, and a via hole electrode passing through the package body, wherein the wire forms a stitch on at least one of the light emitting device and the electrode pad, the light emitting device package further includes a bonding ball disposed on the stitch, and the via hole electrode non-overlaps the stitch and the bonding ball in a vertical direction. | 2014-06-19 |
20140167096 | LIGHT EMITTING DEVICE AND METHODS FOR FORMING THE SAME - The present invention provides a light emitting device, which comprises an epitaxial stack structure, a II/V group compound contact layer directly formed on the epitaxial stack structure, a protrusion or recess type structure directly formed on the II/V group compound contact layer, and a conductive layer covering the protrusion or recess type structure. | 2014-06-19 |
20140167097 | OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method of fabricating an optoelectronic device comprising, providing a substrate, wherein the substrate comprises a first major surface and a second major surface opposite to the first major surface; forming a semiconductor epitaxial stack on the first major surface including a first conductive-type semiconductor layer having a first doping concentration, an active layer, and a second conductive-type semiconductor layer wherein the semiconductor epitaxial stack having four boundaries and a geometric center; and forming a plurality of the hollow components in the first conductive-type semiconductor layer wherein the plurality of the hollow components is formed from the boundary of the semiconductor epitaxial stack to the geometric center of the semiconductor epitaxial stack. | 2014-06-19 |
20140167098 | Quantum Tunneling Devices and Circuits with Lattice-Mismatched Semiconductor Structures - Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials. | 2014-06-19 |
20140167099 | INTEGRATED CIRCUIT INCLUDING SILICON CONTROLLED RECTIFIER - An integrated circuit includes a protected circuit. The integrated circuit further includes a silicon controlled rectifier including a sequence of a first p-type region, a second n-type region, a third p-type region and a fourth n-type region. The first n-type region is electrically coupled to the protected circuit. The integrated circuit further includes a first pn junction diode including a first semiconductor zone and one of the group including the second n-type region and the third p-type region as a second semiconductor zone. A conductivity type of the first semiconductor zone is opposite to the conductivity type of the second semiconductor zone. The integrated circuit further includes a first trigger circuit electrically coupled to the first semiconductor zone. | 2014-06-19 |
20140167100 | CASCODE CIRCUIT DEVICE WITH IMPROVED REVERSE RECOVERY CHARACTERISTIC - A semiconductor device including: an FET; a MOSFET having a drain thereof connected with a source of the FET; a resistor having one end thereof connected with a gate of the FET and having the other end thereof connected with a source of the MOSFET; and a diode having an anode thereof connected with the gate of the FET and having a cathode thereof connected with the source of the MOSFET. | 2014-06-19 |
20140167101 | TVS WITH LOW CAPACITANCE & FORWARD VOLTAGE DROP WITH DEPLETED SCR AS STEERING DIODE - A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate of a first conductivity type. The TVS includes a buried dopant region of a second conductivity type disposed and encompassed in an epitaxial layer of the first conductivity type wherein the buried dopant region extends laterally and has an extended bottom junction area interfacing with the underlying portion of the epitaxial layer thus constituting a Zener diode for the TVS device. The TVS device further includes a region above the buried dopant region further comprising a top dopant layer of a second conductivity type and a top contact region of a second conductivity type which act in combination with the epitaxial layer and the buried dopant region to form a plurality of interfacing PN junctions constituting a SCR acting as a steering diode to function with the Zener diode for suppressing a transient voltage. | 2014-06-19 |
20140167102 | SEMICONDUCTOR DEVICE WITH SINGLE-EVENT LATCH-UP PREVENTION CIRCUITRY - A semiconductor device includes a parasitic silicon-controlled rectifier (SCR) and a first transistor. The parasitic SCR includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The first transistor is coupled between a first power supply node and an emitter of the parasitic pnp BJT. The first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor is not positioned between a base of the pnp BJT and the first power supply node. The first transistor limits current conducted by the parasitic pnp BJT following a single-event latch-up (SEL) event. | 2014-06-19 |
20140167103 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a semiconductor device including a semiconductor substrate, a collector layer formed under the semiconductor substrate, a base layer formed on the semiconductor substrate, an emitter layer formed on the base layer, one or more trench barriers vertically penetrating the base layer and the emitter layer, a first gate insulating layer formed on the trench barriers and the emitter layer such that an upper portion of the emitter layer is partially exposed, a gate formed on the first gate insulating layer, a second gate insulating layer formed to cover the gate, and an emitter metal layer formed on an upper portion of the emitter layer exposed by the first gate insulating layer. | 2014-06-19 |
20140167104 | INTERFACE PROTECTION DEVICE WITH INTEGRATED SUPPLY CLAMP AND METHOD OF FORMING THE SAME - Protection circuit architectures with integrated supply clamps and methods of forming the same are provided herein. In certain implementation, an integrated circuit interface protection device includes a first diode protection structure and a first thyristor protection structure electrically connected in parallel between a signal pin a power high supply. Additionally, the protection device includes a second diode protection structure and a second thyristor protection structure electrically connected in parallel between the signal pin and a power low supply. Furthermore, the protection device includes a third diode protection structure and a third thyristor protection structure electrically connected in parallel between the power high supply and the power low supply. The third thyristor protection structure and the third diode protection structure are synthesized as part of the integrated circuit interface and can share at least a portion of the wells and/or diffusion regions associated with the first and second thyristor protection structures. | 2014-06-19 |
20140167105 | DEVICES FOR MONOLITHIC DATA CONVERSION INTERFACE PROTECTION AND METHODS OF FORMING THE SAME - Apparatus and methods for monolithic data conversion interface protection are provided herein. In certain implementations, a protection device includes a first silicon controlled rectifier (SCR) and a first diode for providing protection between a signal node and a power high supply node, a second SCR and a second diode for providing protection between the signal node and a power low supply node, and a third SCR and a third diode for providing protection between the power high supply node and the power low supply node. The SCR and diode structures are integrated in a common circuit layout, such that certain wells and active regions are shared between structures. Configuring the protection device in this manner enables in-suit input/output interface protection using a single cell. The protection device is suitable for monolithic data conversion interface protection in sub 3V operation. | 2014-06-19 |
20140167106 | INTERFACE PROTECTION DEVICE WITH INTEGRATED SUPPLY CLAMP AND METHOD OF FORMING THE SAME - Protection circuit architectures with integrated supply clamps and methods of forming the same are provided herein. In certain implementation, an integrated circuit interface protection device includes a first diode protection structure and a first thyristor protection structure electrically connected in parallel between a signal pin a power high supply. Additionally, the protection device includes a second diode protection structure and a second thyristor protection structure electrically connected in parallel between the signal pin and a power low supply. Furthermore, the protection device includes a third diode protection structure and a third thyristor protection structure electrically connected in parallel between the power high supply and the power low supply. The third thyristor protection structure and the third diode protection structure are synthesized as part of the integrated circuit interface and can share at least a portion of the wells and/or diffusion regions associated with the first and second thyristor protection structures. | 2014-06-19 |
20140167107 | SEMICONDUCTOR LIGHT RECEIVING DEVICE AND LIGHT RECEIVING APPARATUS - A semiconductor light receiving device includes a substrate having an incident surface receiving light incident on the semiconductor light receiving device and a principal surface opposite to the incident surface; a first semiconductor layer disposed on the principal surface of the substrate, the first semiconductor layer defining one of a cathode region and an anode region; a light absorbing region disposed on the first semiconductor layer; and a second semiconductor layer disposed on the light absorbing region, the second semiconductor layer defining the other of the cathode region and the anode region and forming a junction with the light absorbing region. The light absorbing region includes a semiconductor layer having a conductivity type opposite to the conductivity type of the first semiconductor layer. The semiconductor layer of the light absorbing region forms a p-n junction with the first semiconductor layer. | 2014-06-19 |
20140167108 | SEMICONDUCTOR DEVICES WITH GERMANIUM-RICH ACTIVE LAYERS & DOPED TRANSITION LAYERS - Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers. | 2014-06-19 |
20140167109 | CONTINUOUS METAL SEMICONDUCTOR ALLOY VIA FOR INTERCONNECTS - A contact structure is disclosed in which a continuous metal semiconductor alloy is located within a via contained within a dielectric material. The continuous semiconductor metal alloy is in direct contact with an upper metal line of a first metal level located atop the continuous semiconductor metal alloy and at least a surface of each source and drain diffusion region located beneath the continuous metal semiconductor alloy. The continuous metal semiconductor alloy includes a lower portion that is contained within an upper surface of each source and drain region, and a vertical pillar portion extending upward from the lower portion. | 2014-06-19 |
20140167110 | PARTIAL POLY AMORPHIZATION FOR CHANNELING PREVENTION - Semiconductor devices are formed without zipper defects or channeling and through-implantation and with different silicide thicknesses in the gates and source/drain regions, Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region in the substrate on each side of the gate, forming a wet cap fill layer on the source/drain region on each side of the gate, removing the nitride cap from the gate, and forming an amorphized layer in a top portion of the gate. Embodiments include forming the amorphized layer by implanting low energy ions. | 2014-06-19 |
20140167111 | TRANSISTOR AND METHOD OF FABRICATING THE SAME - A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion. The foot portion of an end part of the gate electrode has a width less than a width of the head portion of another part of the gate electrode and greater than a width of the foot portion of the another part of the gate electrode. The foot portion of the end part of the gate electrode further penetrates the active layer so as to be adjacent to the substrate. | 2014-06-19 |
20140167112 | Cascode Circuit Integration of Group III-N and Group IV Devices - In an exemplary implementation, an integrated assembly includes a printed circuit board, and a depletion mode III-Nitride transistor die and a group IV transistor die coupled to the printed circuit board. The depletion mode III-Nitride transistor die is situated on one side of the printed circuit board and the group IV transistor die is situated on an opposing side of the printed circuit board. At least one via in the printed circuit board electrically connects the depletion mode III-Nitride transistor die to the group IV transistor die. In some implementations, the depletion mode III-Nitride transistor die is in cascode with the group IV transistor die. Furthermore, the depletion mode III-Nitride transistor die can he situated over the group IV transistor die. | 2014-06-19 |
20140167113 | GALLIUM NITRIDE BASED SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - Gallium nitride (GaN) based semiconductor devices and methods of manufacturing the same. The GaN-based semiconductor device may include a heat dissipation substrate (that is, a thermal conductive substrate); a GaN-based multi-layer arranged on the heat dissipation substrate and having N-face polarity; and a heterostructure field effect transistor (HFET) or a Schottky electrode arranged on the GaN-based multi-layer. The HFET device may include a gate having a double recess structure. While such a GaN-based semiconductor device is being manufactured, a wafer bonding process and a laser lift-off process may be used. | 2014-06-19 |
20140167114 | Method for Growing III-V Epitaxial Layers - Disclosed are methods of growing III-V epitaxial layers on a substrate, semiconductor structures thus obtained, and devices comprising such semiconductor structures. An example semiconductor substrate includes a substrate and a buffer layer on top of the substrate, where a conductive path is present between the substrate and buffer layer. A conductive path may be present in the conductive interface, and the conductive path may be interrupted by one or more local electrical isolations. The local electrical isolation(s) may be positioned with the device such that at least one of the local electrical isolation(s) is located between a high voltage terminal and a low voltage terminal of the device. | 2014-06-19 |
20140167115 | HETEROJUNCTION BIPOLAR TRANSISTOR, POWER AMPLIFIER INCLUDING THE SAME, AND METHOD FOR FABRICATING HETEROJUNCTION BIPOLAR TRANSISTOR - A heterojunction bipolar transistor includes a ballast resistor layer of which resistance increases with an increase in temperature. The ballast resistor layer includes a first ballast resistor sub-layer having a positive temperature coefficient of resistivity in a first temperature range and a second temperature range and a second ballast resistor sub-layer having a negative temperature coefficient of resistivity in the first temperature range and a positive temperature coefficient of resistivity in the second temperature range. | 2014-06-19 |
20140167116 | HETEROJUNCTION BIPOLAR TRANSISTOR - The present disclosure is directed to a method that includes exposing a surface of a silicon substrate in a first region between first and second isolation trenches, etching the silicon substrate in the first region to form a recess between the first and second isolation trenches,=; and forming a base of a heterojunction bipolar transistor by selective epitaxial growth of a film comprising SiGe in the recess. | 2014-06-19 |
20140167117 | Methods for Cell Boundary Encroachment and Layouts Implementing the Same - A semiconductor device is disclosed to include a plurality of cells. Each of the cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner. Also, each of the cells includes circuitry for performing one or more logic functions. This circuitry includes a plurality of conductive features defined in one or more levels of the cell. One or more of the conductive features in at least one level of a given cell is an encroaching feature positioned to encroach by an encroachment distance into an exclusion zone. The exclusion zone occupies an area within the cell defined by an exclusion distance extending perpendicularly inward into the given cell from a first segment of the outer cell boundary. The exclusion distance is based on a design rule distance representing a minimum separation distance required between conductive features in adjacently placed cells on the semiconductor device. | 2014-06-19 |
20140167118 | CROSSTALK IMPROVEMENT THROUGH P ON N STRUCTURE FOR IMAGE SENSOR - The present disclosure provides an image sensor semiconductor device. The semiconductor device includes a semiconductor substrate having a first type of dopant; a semiconductor layer having a second type of dopant different from the first type of dopant and disposed on the semiconductor substrate; and an image sensor formed in the semiconductor layer. | 2014-06-19 |
20140167119 | METHODS OF FORMING A SIDEWALL SPACER HAVING A GENERALLY TRIANGULAR SHAPE AND A SEMICONDUCTOR DEVICE HAVING SUCH A SPACER - A method of forming a spacer is disclosed that involves forming a layer of spacer material above an etch stop layer, performing a first main etching process on the layer of spacer material to remove some of material, stopping the etching process prior to exposing the etch stop layer and performing a second over-etch process on the layer of spacer material, using the following parameters: an inert gas flow rate of about 50-200 sscm, a reactive gas flow rate of about 3-20 sscm, a passivating gas flow rate of about 3-20 sscm, a processing pressure about 5-15 mT, a power level of about 200-500 W for ion generation and a bias voltage of about 300-500 V. A device includes a gate structure positioned above a semiconducting substrate, a substantially triangular-shaped sidewall spacer positioned proximate the gate structure and an etch stop layer positioned between the spacer and the gate structure. | 2014-06-19 |
20140167120 | METHODS OF FORMING A FINFET SEMICONDUCTOR DEVICE BY PERFORMING AN EPITAXIAL GROWTH PROCESS - A method of forming a FinFET device involves performing an epitaxial growth process to form a layer of semiconducting material on a semiconducting substrate, wherein a first portion of the layer of semiconducting material will become a fin structure for the FinFET device and wherein a plurality of second portions of the layer of semiconducting material will become source/drain structures of the FinFET device, forming a gate insulation layer around at least a portion of the fin structure and forming a gate electrode above the gate insulation layer. | 2014-06-19 |
20140167121 | FILAMENT FREE SILICIDE FORMATION - A device and methods for forming the device are disclosed. The method includes providing a substrate. A gate having a gate electrode and sidewall spacers are formed adjacent to sidewalls of the gate. A height H | 2014-06-19 |
20140167122 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and method of manufacturing the semiconductor device are disclosed. The semiconductor device includes: a substrate including an active region and at least one groove isolation region formed on the substrate, wherein the at least one groove isolation region is formed adjoining the active region, a gate structure formed on a first portion of the active region, and at least one local interconnection layer formed on a portion of the substrate, wherein the at least one local interconnection layer is located on a side of the gate structure, and covers at least a second portion of the active region and a portion of the groove isolation region adjoining the active region. | 2014-06-19 |
20140167123 | POWER SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - There is provided a power semiconductor device including: a body region having a first conductivity; a well formed in an upper portion of the body region and having a second conductivity; and a conductive via formed in the body region while traversing the well. | 2014-06-19 |
20140167124 | SOLID-STATE IMAGING APPARATUS, METHOD OF MANUFACTURING SOLID-STATE IMAGING APPARATUS, AND ELECTRONIC APPARATUS - A solid-state imaging apparatus includes a transfer gate electrode formed on a semiconductor substrate; a photoelectric conversion unit including an electric charge storage area that is formed from a surface side of the semiconductor substrate in a depth direction, a transfer auxiliary area formed of a second conductive type impurity area that is formed in such a manner as to partially overlap the transfer gate electrode, and a dark current suppression area that is a first dark current suppression area formed in an upper layer of the transfer auxiliary and formed so as to have positional alignment in such a manner that the end portion of the transfer auxiliary area on the transfer gate electrode side is at the same position as the end portion of the transfer auxiliary area; and a signal processing circuit configured to process an output signal output from the solid-state imaging apparatus. | 2014-06-19 |
20140167125 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device capable of increasing ON current while reducing channel resistance and allowing transistors to operate independently and stably, having a fin formed to protrude from the bottom of a gate electrode trench, a gate insulating film covering the surfaces of the gate electrode trench and the fin, a gate electrode embedded in a lower part of the gate electrode trench and formed to stride over the fin via the gate insulating film, a first impurity diffusion region arranged on a first side face, and a second impurity diffusion region arranged on a second side face. | 2014-06-19 |
20140167126 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate and a PIP capacitor located. The PIP capacitor includes a first polysilicon layer, a metallic silicide layer, a protective layer, a dielectric layer, and a second polysilicon layer, which have a lower conductive plate pattern and are successively arranged. The method includes: providing a substrate; successively forming a first polysilicon layer, a metallic silicide, and a protective layer on the substrate; transferring a lower conductive plate pattern into the first polysilicon layer, the metallic silicide layer, and the protective layer, thus forming the first polysilicon layer, the metallic silicide layer, and the protective layer having the lower conductive plate pattern; successively forming a dielectric layer and a second polysilicon layer having a lower conductive plate pattern on the protective layer. The capacitance and reliability of the PIP capacitor are improved. | 2014-06-19 |
20140167127 | Memory Devices and Methods of Manufacture Thereof - Memory devices and methods of manufacture thereof are disclosed. In one embodiment, a memory device includes a transistor having a gate disposed over a workpiece. The transistor includes a source region and a drain region disposed in the workpiece proximate the gate. The memory device includes an erase gate having a tip portion that extends towards the workpiece. The erase gate is coupled to the gate of the transistor. | 2014-06-19 |
20140167128 | Memory Gate Landing Pad Made From Dummy Features - Embodiments described herein generally relate to landing gate pads for contacts and manufacturing methods therefor. A bridge is formed between two features to allow a contact to be disposed, at least partially, on the bridge. Landing the contact on the bridge avoids additional manufacturing steps to create a target for a contact. | 2014-06-19 |
20140167129 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a bit line and a common source line formed on a cell array region of a substrate, a first channel layer coupled to the common source line and extending higher than the common source line, a second channel layer coupled to the bit line and extending higher than the bit line, and a coupling pattern coupling a top of the first channel layer opposite to the common source line and a top of the second channel layer opposite to the bit line. | 2014-06-19 |
20140167130 | EEPROM CORE STRUCTURE EMBEDDED INTO BCD PROCESS AND FORMING METHOD THEREOF - The present invention provides an EEPROM core structure embedded into BCD process and forming method thereof. The EEPROM core structure embedded into BCD process comprises a selection transistor and a storage transistor connected in series, wherein the selection transistor is an LDNMOS transistor. The present invention may embed the procedure for forming the EEPROM core structure into the BCD process, which is favorable to reduce the complexity of the process. | 2014-06-19 |
20140167131 | THREE DIMENSIONAL MEMORY - A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer. | 2014-06-19 |
20140167132 | SEMICONDUCTOR DEVICE - A semiconductor device including a nonvolatile memory cell with a high performance and also a high reliability is provided. | 2014-06-19 |
20140167133 | NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory according to an embodiment includes: a semiconductor region; a first insulating film formed on the semiconductor region; a charge storage film formed on the first insulating film; a hydrogen diffusion preventing film formed on the charge storage film; a second insulating film formed on the hydrogen diffusion preventing film; a control gate electrode formed on the second insulating film; a hydrogen discharge film formed on the control gate electrode; and a sidewall formed on a side surface of a multilayer structure including the first insulating film, the charge storage film, the hydrogen diffusion preventing film, the second insulating film, and the control gate electrode, the sidewall containing a material for preventing hydrogen from diffusing. | 2014-06-19 |
20140167134 | SELF-ALIGNED VERTICAL NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - The present invention belongs to the technical field of semiconductor memory devices and specifically relates to a self-aligned vertical nonvolatile semiconductor memory device, Including: a semiconductor substrate, a drain region of a first doping type, two source regions of a second doping type, a stacked gate used to capture electrons; wherein the drain region, the two source regions and the stacked gate form two tunneling field effect transistors (TFETs) sharing one gate and one drain, the drain region current of each of the TFET is affected by the quantity and distribution of the charges in the stacked gate used to capture electrons, the drain is buried in the semiconductor substrate, the source regions above the drain region are separated from the drain through a channel and separated form each other through a region of the first doping type. The semiconductor memory device of the present invention features small unit area and simple manufacturing process. The memory chip using the present invention is of low manufacturing cost and high storage density. | 2014-06-19 |
20140167135 | Process Charging Protection for Split Gate Charge Trapping Flash - A semiconductor device and method of making such device is presented herein. The semiconductor device includes a plurality of memory cells, a plurality of p-n junctions, and a metal trace of a first metal layer. Each of the plurality of memory cells includes a first gate disposed over a first dielectric, a second gate disposed over a second dielectric and adjacent to a sidewall of the first gate, a first doped region in the substrate adjacent to the first gate, and a second doped region in the substrate adjacent to the second gate. The plurality of p-n junctions are electrically isolated from the doped regions of each memory cell. The metal trace extends along a single plane between a via to the second gate of at least one memory cell in the plurality of memory cells, and a via to a p-n junction within the plurality of p-n junctions. | 2014-06-19 |
20140167136 | Charge Trapping Device with Improved Select Gate to Memory Gate Isoloation - Embodiments described herein generally relate to charge-trapping memory with improved isolation between a select gate and a memory gate. The isolation is improved because the charge trapping layer is not present in the junction between the select gate and the memory gate. The methods described herein additionally allow insulation to be disposed between the select gate and the memory gate. | 2014-06-19 |
20140167137 | High Voltage Gate Formation - Embodiments described herein generally relate to methods of manufacturing charge-trapping memory by patterning the high voltage gates before other gates are formed. One advantage of such an approach is that a thin poly layer may be used to form memory and low voltage gates while protecting high voltage gates from implant penetration. One approach to accomplishing this is to dispose the layer of poly, and then dispose a mask and a thick resist to pattern the high voltage gates. In this manner, the high voltage gates are formed before either the low voltage gates or the memory cells. | 2014-06-19 |
20140167138 | HTO OFFSET FOR LONG LEFFECTIVE, BETTER DEVICE PERFORMANCE - Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions. | 2014-06-19 |
20140167139 | Integrated Circuits With Non-Volatile Memory and Methods for Manufacture - Semiconductor devices and the manufacture of such semiconductor devices are described. According to various aspects of the disclosure, a semiconductor device can include a memory region, a first logic region, and a second logic region. A select gate can be formed in the memory region of the device and a first logic gate formed in the logic region. A charge trapping dielectric can then be disposed and removed from a second logic region. A gate conductor layer can then be disposed on the device and etched to define a memory gate on the sidewall of the select gate and a second logic gate in the second logic region. | 2014-06-19 |
20140167140 | Memory First Process Flow and Device - Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, a semiconductor device includes a memory gate disposed in a first region of the semiconductor device. The memory gate may include a first gate conductor layer disposed over a charge trapping dielectric. A select gate may be disposed in the first region of the semiconductor device adjacent to a sidewall of the memory gate. A sidewall dielectric may be disposed between the sidewall of the memory gate and the select gate. Additionally, the device may include a logic gate disposed in a second region of the semiconductor device that comprises the first gate conductor layer. | 2014-06-19 |
20140167141 | Charge Trapping Split Gate Embedded Flash Memory and Associated Methods - Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, the semiconductor device can be made by forming an dielectric layer at a first region and at a second region of a semiconductor substrate. A gate conductor layer is disposed over the dielectric formed in the first and the second regions of the semiconductor substrate, and the second region is masked. A split gate memory cell is formed in the first region of the semiconductor substrate with a first gate length. The first region is then masked, and the second region is etched to define a logic gate that has a second gate length. The first and second gate lengths can be different. | 2014-06-19 |
20140167142 | Use Disposable Gate Cap to Form Transistors, and Split Gate Charge Trapping Memory Cells - A semiconductor device and method of making such device is presented herein. The method includes disposing a gate layer over a dielectric layer on a substrate and further disposing a cap layer over the gate layer. A first transistor gate is defined having an initial thickness substantially equal to a combined thickness of the cap layer and the gate layer. A first doped region is formed in the substrate adjacent to the first transistor gate. The cap layer is subsequently removed and a second transistor gate is defined having a thickness substantially equal to the thickness of the gate layer. Afterwards, a second doped region is formed in the substrate adjacent to the second transistor gate. The first doped region extends deeper in the substrate than the second doped region, and a final thickness of the first transistor gate is substantially equal to the thickness of the second transistor gate. | 2014-06-19 |
20140167143 | Semiconductor Device with Step-Shaped Edge Termination, and Method for Manufacturing a Semiconductor Device - A semiconductor body has a first side, second side, lateral edge, active area, edge termination between the active area and the lateral edge, and drift region of a first conductivity type. The edge termination includes a step formed in the semiconductor body between the first side and the lateral edge. The step includes a lateral surface extending up to the first side and a bottom surface extending up to the lateral edge. A first doping zone of a second conductivity type is formed in the semiconductor body along the lateral surface of the step and forms a pn-junction with the drift region. A second doping zone of the first conductivity type is formed in the semiconductor body at least along a part of the bottom surface of the step and extends up to the lateral edge, wherein the second doping zone is in contact with the drift region. | 2014-06-19 |
20140167144 | VERTICAL DMOS TRANSISTOR - A transistor includes a semiconductor body; a body region of a first conductivity type formed in the semiconductor body; a gate electrode formed partially overlapping the body region and insulated from the semiconductor body by a gate dielectric layer; a source diffusion region of a second conductivity type formed in the body region on a first side of the gate electrode; a trench formed in the semiconductor body on a second side, opposite the first side, of the gate electrode, the trench being lined with a sidewall dielectric layer; and a doped sidewall region of the second conductivity type formed in the semiconductor body along the sidewall of the trench where the doped sidewall region forms a vertical drain current path for the transistor. | 2014-06-19 |
20140167145 | SEMICONDUCTOR DEVICE - According to one embodiment, the semiconductor device is provided with a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a pair of first conductors, a pair of second conductors, first wiring layers, and second wiring layers. Each pair of first and second conductors is formed in first and second trenches via the first and second insulating films and is opposite to the first semiconductor layer and the second semiconductor layer. The first wiring layers have main body parts and plural convex parts. Plural convex parts extend from the main body parts and are electrically connected with the first conductors via a first opening part of a first interlayer insulating film. The second wiring layers are electrically connected with the second conductors via a second opening part of the first interlayer insulating film. | 2014-06-19 |
20140167146 | TUNNELING FIELD EFFECT TRANSISTOR AND FABRICATION METHOD THEREOF - A tunneling field effect transistor (FET) and a method of fabricating the same are provided. The tunneling FET includes a first electrode formed on a substrate, a second electrode disposed over the first electrode with respect to the substrate, a channel layer which connects the first electrode and the second electrode, and a plurality of third electrodes formed on sidewalls of the channel layer, wherein the channel layer is higher than the third electrodes in the criteria of the substrate. | 2014-06-19 |
20140167147 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a p-type semiconductor layer; an n-type semiconductor layer connected with the p-type semiconductor layer; a first electrode layer formed on the n-type semiconductor layer; and a second electrode layer formed on the p-type semiconductor layer. The first electrode layer and the second electrode layer are electrically connected such as to each operate at an identical potential. The first electrode layer is connected with a connection line which is a part of a peripheral line of a joint interface between the p-type semiconductor layer and the n-type semiconductor layer on an interface side between the second electrode layer and the p-type semiconductor layer, with a surface of the p-type semiconductor layer and with at least a part of a surface of the second electrode layer which is opposite to a surface of the second electrode layer that is in contact with the p-type semiconductor layer. | 2014-06-19 |
20140167148 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a p-type semiconductor layer; an n-type semiconductor layer; a first electrode layer; a second electrode layer; and a control electrode layer. The first and second electrode layers are electrically connected such as to each operate at an identical potential. The first electrode layer is connected with a part of a surface of the second electrode layer which is opposite to a surface of the second electrode layer that is in contact with the p-type semiconductor layer. The second electrode layer is connected with a connection line which is a part of a peripheral line of a joint interface between the p-type semiconductor layer and the n-type semiconductor layer on an interface side between the second electrode layer and the p-type semiconductor layer, and is formed to be extended to a position on a control electrode layer side of the connection line. | 2014-06-19 |
20140167149 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device includes a gate electrode formed on a sidewall of a structure extending from a semiconductor substrate. A junction region is form in the structure to a first depth from a top of the structure and formed to overlap the gate electrode. A protection layer is formed between an outer wall of the structure and the gate electrode to a second depth less than the first depth from the top of the structure. | 2014-06-19 |
20140167150 | POWER SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - There is provided a power semiconductor device including a contact formed in an active region, a trench gate extendedly formed from the first region into a first termination region and formed alternately with the contact, a first conductive well formed between the contact of the active region and the trench gate, a first conductive well extending portion formed in the first termination region and a part of a second termination region, and a first conductive field limiting ring formed in the second termination region and contacting the well extending portion. | 2014-06-19 |
20140167151 | STEPPED TRENCH MOSFET AND METHOD OF FABRICATING THE SAME - A step trench metal-oxide-semiconductor field-effect transistor comprises a drift layer, a first semiconductor region, a stepped gate and a floating region. The drift layer is of a first conductivity type. The first semiconductor region is of a second conductivity type and located on the drift layer, wherein the drift layer and the first semiconductor region have a stepped gate trench therein. The stepped gate trench at least comprises a first recess located in the first semiconductor region and extending into the drift layer and a second recess located below a bottom of the first recess, wherein a width of the second recess is smaller than a width of the first recess. A floating region is of the second conductivity type and located in the drift layer below the second recess. | 2014-06-19 |
20140167152 | Reduced Gate Charge Trench Field-Effect Transistor - In one implementation, a trench field-effect transistor (trench FET) can include a semiconductor substrate including a drain region, a drift zone over the drain region, and first and second gate trenches including a gate dielectric and respective gate electrodes disposed therein, also over the drain region. The trench FET can further include a depletion trench situated between the first and second gate trenches, the depletion trench including a trench insulator. The trench insulator adjoins the gate electrodes and the gate dielectric so as to reduce a gate charge of the trench FET. | 2014-06-19 |
20140167153 | Trench Fet Having Merged Gate Dielectric - In one implementation, a trench field-effect transistor (trench FET) includes a semiconductor substrate having a drain region, a drift zone over the drain region, and depletion trenches formed over the drain region. Each depletion trench includes a depletion trench dielectric and a depletion electrode. The trench FET can further include a respective bordering gate trench situated alongside each depletion trench, each bordering gate trench having a gate electrode and a gate dielectric. The gate dielectric is merged with the depletion trench dielectric between the depletion electrode and the gate electrode. | 2014-06-19 |