24th week of 2021 patent applcation highlights part 72 |
Patent application number | Title | Published |
20210184032 | HIGH VOLTAGE EXTENDED-DRAIN MOS (EDMOS) NANOWIRE TRANSISTORS - Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment a semiconductor device comprises a substrate, a source region over the substrate, a drain region over the substrate, and a semiconductor body extending from the source region to the drain region. In an embodiment, the semiconductor body has a first region with a first conductivity type and a second region with a second conductivity type. In an embodiment, the semiconductor device further comprises a gate structure over the first region of the semiconductor body, where the gate structure is closer to the source region than the drain region. | 2021-06-17 |
20210184033 | HIGH VOLTAGE DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR - A modified structure of an n-channel lateral double-diffused metal oxide semiconductor (LDMOS) transistor is provided to suppress the rupturing of the gate-oxide which can occur during the operation of the LDMOS transistor. The LDMOS transistor comprises a dielectric isolation structure which physically isolates the region comprising a parasitic NPN transistor from the region generating a hole current due to weak-impact ionization, e.g., the extended drain region of the LDMOS transistor. According to an embodiment of the disclosure, this can be achieved using a vertical trench between the two regions. Further embodiments are also proposed to enable a reduction in the gain of the parasitic NPN transistor and in the backgate resistance in order to further improve the robustness of the LDMOS transistor. | 2021-06-17 |
20210184034 | TRANSISTOR WITH EXTENDED DRAIN REGION - A transistor device having a channel region including a portion located in a sidewall of semiconductor material of a trench and an extended drain region including a portion located in a lower portion of the semiconductor material of the trench. In one embodiment, a control terminal of the transistor device is formed by patterning a layer of control terminal material to form a sidewall in the trench and a field plate for the transistor device is formed by forming a conductive sidewall spacer structure along the sidewall of the control terminal material. | 2021-06-17 |
20210184035 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate and a resistance element provided above the semiconductor substrate, the resistance element includes a conductive pattern using a gate electrode film formed simultaneously with a gate electrode film arranged on a side surface of a semiconductor nanowire of a VNW transistor, and there is fabricated the semiconductor device that includes the VNW transistor having the semiconductor nanowire and the resistance element having sufficient electrical resistance. | 2021-06-17 |
20210184036 | Transistor with Asymmetric Source and Drain Regions - Semiconductor structures and methods for forming a semiconductor structure are provided. An active semiconductor region is disposed in a substrate. A gate is formed over the substrate. Source and drain regions of a transistor are formed in the active semiconductor region on opposite sides of the gate. The drain region has a first width, and the source region has a second width that is not equal to the first width. | 2021-06-17 |
20210184037 | MOS Devices Having Epitaxy Regions with Reduced Facets - An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region. | 2021-06-17 |
20210184038 | SEMICONDUCTOR DEVICES - A semiconductor device includes first and second active patterns, a first gate structure, first and second channels, and first and second source/drain layers. The first and second active patterns extend in a first direction, and are spaced apart in a second direction. The first gate structure extends in the second direction on the first and second active patterns. The first channels are spaced apart in a third direction on the first active pattern. The second channels are spaced apart in the third direction on the second active pattern. The first source/drain layer having a first conductivity type is formed at a side of the first gate structure to contact the first channels. The second source/drain layer having a second conductivity type is formed at a side of the first gate structure to contact the second channels. Widths in the second direction of the first and second channels are different. | 2021-06-17 |
20210184039 | THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor and a method for manufacturing the same are disclosed. The thin film transistor includes a substrate, a gate, an insulation layer, a first active layer, a second active layer, a source, a drain, and a protection layer. The gate is disposed on the substrate. The insulation layer covers the gate. The first active layer is disposed on the insulation layer and above the gate. The second active layer is disposed on the first active layer, wherein a material of the second active layer is a metal oxide in which oxygen vacancies are filled with nitrogen. The source is disposed on the second active layer. The drain is disposed on the second active layer, wherein the source and the drain are above two opposite sides of the gate. The protection layer covers the first active layer, the second active layer, the source, and drain. | 2021-06-17 |
20210184040 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - To reduce defects in an oxide semiconductor film in a semiconductor device. To improve electrical characteristics of and reliability in the semiconductor device including an oxide semiconductor film. A method for manufacturing a semiconductor device includes the steps of forming a gate electrode and a gate insulating film over a substrate, forming an oxide semiconductor film over the gate insulating film, forming a pair of electrodes over the oxide semiconductor film, forming a first oxide insulating film over the oxide semiconductor film and the pair of electrodes by a plasma CVD method in which a film formation temperature is 280° C. or higher and 400° C. or lower, forming a second oxide insulating film over the first oxide insulating film, and performing heat treatment at a temperature of 150° C. to 400° C. inclusive, preferably 300° C. to 400° C. inclusive, further preferably 320° C. to 370° C. inclusive. | 2021-06-17 |
20210184041 | SEMICONDUCTOR DEVICE - Provided is a structure of a transistor, which enables a so-called normally-off switching element, and a manufacturing method thereof. Provided is a structure of a semiconductor device which achieves high-speed response and high-speed operation by improving on characteristics of a transistor, and a manufacturing method thereof. Provided is a highly reliable semiconductor device. In the transistor in which a semiconductor layer, source and drain electrode layers, a gate insulating layer, and a gate electrode layer are stacked in that order. As the semiconductor layer, an oxide semiconductor layer which contains at least four kinds of elements of indium, gallium, zinc, and oxygen, and has a composition ratio (atomic percentage) of indium as twice or more as a composition ratio of gallium and a composition ratio of zinc, is used. | 2021-06-17 |
20210184042 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A transistor with stable electrical characteristics. A semiconductor device includes a first insulator over a substrate, a second insulator over the first insulator, an oxide semiconductor in contact with at least part of a top surface of the second insulator, a third insulator in contact with at least part of a top surface of the oxide semiconductor, a first conductor and a second conductor electrically connected to the oxide semiconductor, a fourth insulator over the third insulator, a third conductor which is over the fourth insulator and at least part of which is between the first conductor and the second conductor, and a fifth insulator over the third conductor. The first insulator contains a halogen element. | 2021-06-17 |
20210184043 | SIDEWALL SPACER STRUCTURE TO INCREASE SWITCHING PERFORMANCE OF FERROELECTRIC MEMORY DEVICE - Various embodiments of the present disclosure are directed towards an integrated chip including a ferroelectric structure overlying a substrate. A pair of source/drain regions are disposed in the substrate. A gate dielectric layer overlies the substrate and is spaced laterally between the pair of source/drain regions. The ferroelectric structure overlies the gate dielectric layer. The ferroelectric structure includes a ferroelectric layer and a sidewall spacer structure, where the sidewall spacer structure continuously laterally wraps around the ferroelectric layer. The ferroelectric layer comprises a first metal oxide and the sidewall spacer structure comprises a second metal oxide different than the first metal oxide. | 2021-06-17 |
20210184044 | Programmable Charge-Storage Transistor, An Array Of Elevationally-Extending Strings Of Memory Cells, And A Method Of Forming An Array Of Elevationally-Extending Strings Of Memory Cells - A programmable charge-storage transistor comprises channel material, insulative charge-passage material, charge-storage material, a control gate, and charge-blocking material between the charge-storage material and the control gate. The charge-blocking material comprises a non-ferroelectric insulator material and a ferroelectric insulator material. Arrays of elevationally-extending strings of memory cells of memory cells are disclosed, including methods of forming such. Other embodiments, including method, are disclosed. | 2021-06-17 |
20210184045 | HIGH VOLTAGE ULTRA-LOW POWER THICK GATE NANORIBBON TRANSISTORS FOR SOC APPLICATIONS - Embodiments disclosed herein include nanoribbon and nanowire semiconductor devices. In an embodiment, the semiconductor device comprises a nanowire disposed above a substrate. In an embodiment, the nanowire has a first dopant concentration, and the nanowire comprises a pair of tip regions on opposite ends of the nanowire. In an embodiment, the tip regions comprise a second dopant concentration that is greater than the first dopant concentration. In an embodiment, the semiconductor device further comprises a gate structure over the nanowire. In an embodiment, the gate structure is wrapped around the nanowire, and the gate structure defines a channel region of the device. In an embodiment, a pair of source/drain regions are on opposite sides of the gate structure, and both source/drain regions contact the nanowire. | 2021-06-17 |
20210184046 | LOW NOISE AMPLIFIER TRANSISTORS WITH DECREASED NOISE FIGURE AND LEAKAGE IN SILICON-ON-INSULATOR TECHNOLOGY - A metal oxide semiconductor field effect transistor preferably fabricated with a silicon-on-insulator process has a first semiconductor region and a second semiconductor region in a spaced relationship thereto A body structure is defined by a channel segment between the first semiconductor region and the second semiconductor region, and a first extension segment structurally contiguous with the channel segment. A shallow trench isolation structure surrounds the first semiconductor region, the second semiconductor region, and the body structure, with a first extension interface being defined between the shallow trench isolation structure and the first extension segment of the body structure to reduce leakage current flowing from the second semiconductor region to the first semiconductor region through a parasitic path of the body structure. | 2021-06-17 |
20210184047 | THIN-FILM TRANSISTOR AND DISPLAY PANEL - The present invention provides a thin-film transistor and a display panel. The thin-film transistor includes a substrate, an active layer, an insulating layer, a metal layer, a dielectric layer, a source electrode, a drain electrode, a first through hole, a second through hole, a third through hole, and a fourth through hole. A first contact portion in a first metal layer is connected to the active layer via the first through hole, and a second contact portion is connected to the active layer via a second through hole. The source electrode is connected to the first contact portion via the third through hole, and the drain electrode is connected to the second contact portion via the fourth through hole. | 2021-06-17 |
20210184048 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer. The source electrode and the drain electrode include an oxide region formed by oxidizing a side surface thereof. Note that the oxide region of the source electrode and the drain electrode is preferably formed by plasma treatment with a high frequency power of 300 MHz to 300 GHz and a mixed gas of oxygen and argon. | 2021-06-17 |
20210184049 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The stability of steps of processing a wiring formed using copper or the like is increased. The concentration of impurities in a semiconductor film is reduced. Electrical characteristics of a semiconductor device are improved. A semiconductor device includes a semiconductor film, a pair of first protective films in contact with the semiconductor film, a pair of conductive films containing copper or the like in contact with the pair of first protective films, a pair of second protective films in contact with the pair of conductive films on the side opposite the pair of first protective films, a gate insulating film in contact with the semiconductor film, and a gate electrode overlapping with the semiconductor film with the gate insulating film therebetween. In a cross section, side surfaces of the pair of second protective films are located on the outer side of side surfaces of the pair of conductive films. | 2021-06-17 |
20210184050 | LOW TEMPERATURE POLYSILICON LAYER, THIN FILM TRANSISTOR, AND METHOD FOR MANUFACTURING SAME - A low temperature polysilicon layer, a thin film transistor, and a method for manufacturing same are provided. The low temperature polysilicon layer includes a substrate, at least one buffer layer, and a polysilicon layer. The polysilicon layer is disposed on the at least one buffer layer. The polysilicon layer includes a channel region, two low doped regions disposed on two sides of the channel region, and two high doped regions disposed on an outer side of the low doped regions. Thicknesses of an edge of the channel region and at least one portion of the low doped regions are less than a thickness of another position of the polysilicon layer. | 2021-06-17 |
20210184051 | CO-INTEGRATED HIGH PERFORMANCE NANORIBBON TRANSISTORS WITH HIGH VOLTAGE THICK GATE FINFET DEVICES - Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a substrate, a first transistor over the substrate, where the first transistor comprises a vertical stack of first semiconductor channels, and a first gate dielectric surrounding each of the first semiconductor channels. The first gate dielectric has a first thickness. In an embodiment, the semiconductor device further comprises a second transistor over the substrate, where the second transistor comprises a second semiconductor channel. The second semiconductor channel comprises pair of sidewalls and a top surface. In an embodiment, a second gate dielectric is over the pair of sidewalls and the top surface of the fin, where the second gate dielectric has a second thickness that is greater than the first thickness. | 2021-06-17 |
20210184052 | THREE-DIMENSIONAL NANORIBBON-BASED LOGIC - Described herein are three-dimensional nanoribbon-based logic ICs that include one of more of 1) individual gate control in a vertical stack of nanoribbons, 2) inter-ribbon interconnects in a vertical stack of nanoribbons, and 3) both P- and N-type nanoribbons in a vertical stack of nanoribbons. Using one or more of these features may help realize unique monolithic 3D logic architectures that were not possible with conventional logic circuits and may allow realizing logic devices with favorable metrics in terms of power and performance while preserving the substrate area and cost. | 2021-06-17 |
20210184053 | Nanopore FET Sensor with Non-Linear Potential Profile - In a first aspect, the present invention relates to a nanopore field-effect transistor sensor ( | 2021-06-17 |
20210184054 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - A gallium oxide diode includes: a gallium oxide substrate having an n-type gallium oxide drift layer; an anode electrode of a metal film formed over a front surface of the n-type gallium oxide drift layer; a cathode electrode formed over a rear surface of the gallium oxide substrate; and a reaction layer of a metal oxide film of p-type conductivity formed between the anode electrode and the n-type gallium oxide drift layer. Further, a manufacturing method of a gallium oxide diode includes steps of forming an anode electrode of a metal film over an n-type gallium oxide drift layer formed over a gallium oxide substrate; and forming a reaction layer between the anode electrode and the n-type gallium oxide drift layer by performing a heat treatment to the gallium oxide substrate after forming the anode electrode, the reaction layer being made of a metal oxide film with p-type conductivity. | 2021-06-17 |
20210184055 | CAPACITOR STRUCTURE HAVING VERTICAL DIFFUSION PLATES - A capacitor structure includes a semiconductor substrate, a first vertical diffusion plate in the semiconductor substrate, a first STI structure in the semiconductor substrate and surrounding the first vertical diffusion plate, a second vertical diffusion plate in the semiconductor substrate and surrounding the first STI structure, and an ion well in the semiconductor substrate. The ion well is disposed directly under the first vertical diffusion plate, the first STI structure and the second vertical diffusion plate. The second vertical diffusion plate is electrically coupled to an anode of the capacitor structure. The first vertical diffusion plate is electrically coupled to a cathode of the capacitor structure. | 2021-06-17 |
20210184056 | OPTICAL MODULE - An optical module includes: a thermoelectric cooler with an upper surface and a lower surface, the lower surface fixed to the first surface of the conductive block, the thermoelectric cooler having a Peltier device therein configured to transfer heat between the upper surface and the lower surface; a metal layer laminated on the upper surface of the thermoelectric cooler; a ground wire connecting the first surface of the conductive block and the metal layer; a photoelectric device adapted to convert an optical signal and an electrical signal at least from one to another; a mounting substrate on which the photoelectric device is mounted, the mounting substrate fixed to the upper surface of the thermoelectric cooler with at least the metal layer interposed therebetween, the mounting substrate having a first wiring pattern electrically connected to the photoelectric device. | 2021-06-17 |
20210184057 | TRANSACTION CARD FOR TRANSFERRING SOLAR POWER - A transaction card is provided for communicating data relating to a transaction. The transaction card includes a solar layer, a transaction card layer, and a power transfer layer. The solar layer includes at least one solar panel capable of converting light into electricity, the transaction card layer supports the solar layer and includes a magnetic strip, and the power transfer layer includes circuitry capable of receiving electricity from the solar layer. | 2021-06-17 |
20210184058 | IMAGING PANEL - An imaging panel includes an imaging element that is formed on a substrate. The imaging element includes a gate line, a source line, a switching element, a photoelectric conversion element, and a bias line. The gate line and the source line are formed in a layer in which a part of the switching element is formed, a layer in which a part of the photoelectric conversion element is formed, or a layer in which the bias line is formed. | 2021-06-17 |
20210184059 | SENSORS HAVING RESISTIVE ELEMENTS - A sensor is provided, which includes a semiconductor substrate, a photodiode region, and a multi-layered resistive element. The photodiode region is arranged in the semiconductor substrate. The multi-layered resistive element is arranged over the semiconductor substrate and is coupled with the photodiode region. | 2021-06-17 |
20210184060 | SOLID STATE IMAGING APPARATUS, PRODUCTION METHOD THEREOF AND ELECTRONIC DEVICE - A solid state imaging apparatus includes an insulation structure formed of an insulation substance penetrating through at least a silicon layer at a light receiving surface side, the insulation structure having a forward tapered shape where a top diameter at an upper portion of the light receiving surface side of the silicon layer is greater than a bottom diameter at a bottom portion of the silicon layer. Also, there are provided a method of producing the solid state imaging apparatus and an electronic device including the solid state imaging apparatus. | 2021-06-17 |
20210184061 | CAPACITORS IN GROOVES - An energy storage device comprising a substrate comprising a series of grooves. Each groove having a first and a second face. Wherein there is a capacitor material in each groove of the series of grooves. | 2021-06-17 |
20210184062 | AUTOMOTIVE SOLAR CELL ROOF PANEL USING LAMINATED GLASS - Disclosed herein is an automotive solar cell roof panel which may be manufactured by adjusting the width and number of cells according to a transparent part and an opaque part in one solar cell module, thus improving output and simplifying a structure. The first and second solar cells include a plurality of transparent-part cells and a plurality of opaque-part cells whose widths and numbers are adjusted according to a current density and a voltage ratio. As such, it is unnecessary to array different kinds of solar cells with different voltage or current ranges, thus maximizing output in one solar cell module, and an additional wiring structure for individually controlling output power, an additional converter, and additional control for voltage matching may not be required, thus simplifying a process. | 2021-06-17 |
20210184063 | Light Trapping Dynamic Photovoltaic Module - There is provided a light trapping dynamic photovoltaic module having a module surface configured to be exposed to solar rays, including a plurality of photovoltaic cell stacks configured adjacent to each other throughout the module surface, wherein each photovoltaic cell stack comprises a plurality of photovoltaic cells. Further, a plurality of reflective strips are placed in between each of the photovoltaic cell stacks for continuously reflecting incident solar rays from one reflective strip to another until absorbed by a photovoltaic cell among said plurality of photovoltaic cells, wherein the incident solar rays are continuously reflected through a mirror phenomenon, wherein the incident solar rays are additionally reflected by front and back panels of the dynamic photovoltaic module, thereby trapping incident solar rays within boundaries of the dynamic photovoltaic module for conversion into electrical energy. Also disclosed is a method of manufacturing the light trapping photovoltaic module. | 2021-06-17 |
20210184064 | PHOTOELECTRIC CONVERSION LAYER, SOLAR CELL, MULTI-JUNCTION SOLAR CELL, SOLAR CELL MODULE, AND PHOTOVOLTAIC POWER SYSTEM - The photoelectric conversion layer of an embodiment is based on Cu | 2021-06-17 |
20210184065 | Electrically Controllable and Tunable Electromagnetic-Field Absorber/Emitter using Graphene/2D Material Multilayer Nanostructures - An electrically controllable and tunable electromagnetic-field absorber/thermal emitter is invented using graphene/two-dimensional materials based multilayer nanostructures that have the absorption efficiency of unity at mid-infrared wavelengths. Alternating layers of graphene and hexagonal boron nitride are deposited between support materials and grown on a substrate. Tungsten may be used as the substrate, and silicon carbide as the support material; or, silicon may be used as the substrate and tungsten disulfide as the support material depending on the operating frequencies and ambient temperature. The invention demonstrates a selectable, tunable and switchable electromagnetic-field absorption or thermal emission by changing a DC bias that alters the chemical potential of the graphene layers and thereby the optical response of the multilayer nanostructures. | 2021-06-17 |
20210184066 | SOLAR CELL, LAMINATED BODY, MULTI-JUNCTION SOLAR CELL, SOLAR CELL MODULE, AND SOLAR POWER GENERATION SYSTEM - A solar cell according to an embodiment includes a first electrode being transparent, a first semiconductor layer on the first electrode, a second semiconductor layer on the first semiconductor layer, and a second electrode being transparent on the second semiconductor layer, wherein grooves exist regularly on a surface of the first semiconductor layer facing a side of the second semiconductor layer. | 2021-06-17 |
20210184067 | LIGHT DETECTION DEVICE AND METHOD FOR MANUFACTURING LIGHT DETECTION DEVICE - A method for producing a light detection device includes preparing a back-illuminated light receiving element that includes a plurality of light receiving sections and a trench which is open to a first main surface so as to isolate the adjacent light receiving sections from each other; disposing the light receiving element on a wiring substrate such that the first main surface of the light receiving element faces the wiring substrate; forming a resin mold, which reaches at least a position that is further away from the wiring substrate than an end portion on a second main surface side of the trench in a thickness direction of the wiring substrate, on the wiring substrate so as to surround an entire side surface of the light receiving element; polishing the light receiving element and the resin mold from the second main surface side of the light receiving element. | 2021-06-17 |
20210184068 | METHOD FOR MANUFACTURING MONOCRYSTALLINE SILICON CELL AND MONOCRYSTALLINE SILICON WAFER, AND PHOTOVOLTAIC MODULE - Provided is a method for manufacturing at least one solar cell, a method for manufacturing a monocrystalline silicon wafer and a photovoltaic module. The method for manufacturing a monocrystalline silicon wafer includes: providing a monocrystalline silicon rod; squaring the monocrystalline silicon rod to form a quasi-square silicon rod with quasi-square cross-section having an arc, a length of the arc being not less than 15 mm; slicing the quasi-square silicon rod to form at least one quasi-square silicon wafer having the arc. The method for manufacturing at least one solar cell includes: using the method described above to obtain a quasi-square silicon wafer having an arc; forming a first solar cell by processing the quasi-square silicon wafer; scribing the first solar cell to obtain a square-shaped sub-solar cell and at least one strip-shaped sub-solar cell. The above methods improve the utilization rate of the monocrystalline silicon rod and reduce production cost. | 2021-06-17 |
20210184069 | METHOD FOR FABRICATING A DETECTION DEVICE COMPRISING A STEP OF DIRECT BONDING OF A THIN SEALING LAYER PROVIDED WITH A GETTER MATERIAL - The invention relates to a method for fabricating a thermal detector ( | 2021-06-17 |
20210184070 | METHOD OF ALIGNING MICRO LEDs AND METHOD OF MANUFACTURING MICRO LED DISPLAY USING THE SAME - A method of aligning micro LEDs and a method of manufacturing a micro LED display using the same are provided. The method of aligning micro LEDs includes providing micro LEDs, each having a first surface that has a first maximum width and a second surface opposite to the first surface and has a second maximum width that is greater than the first maximum width, providing a transfer substrate including a transfer mold that has an array of openings, each of the openings being configured to accommodate the first surface of a corresponding micro LED and not accommodate the second surface of the corresponding micro LED and aligning the micro LEDs in one direction in the openings of the transfer mold by inserting the micro LEDs into the openings of the transfer mold so that the first surface of each of the micro LEDs is positioned within a corresponding opening. | 2021-06-17 |
20210184071 | III-NITRIDE SEMICONDUCTOR DEVICES - A method of making a semiconductor device, comprising: forming a plurality of semiconductor seeds of a first III-nitride material through a mask provided over a substrate; growing a second III-nitride semiconductor material; planarizing the grown second semiconductor material to form a plurality of discrete base elements having a substantially planar upper surface. Preferably the step of planarizing involves performing atomic distribution of III type atoms of the grown second semiconductor material under heating to form the planar upper surface, and without supply of III type atoms is carried out during the step of planarization. | 2021-06-17 |
20210184072 | PARTIAL LASER LIFTOFF PROCESS DURING DIE TRANSFER AND STRUCTURES FORMED BY THE SAME - A transfer method includes providing a first light emitting diode on a first substrate, performing a partial laser liftoff of the first light emitting diode from the first substrate, laser bonding the first light emitting diode to the backplane after performing the partial laser liftoff, and separating the first substrate from the first light emitting diode after the laser bonding. | 2021-06-17 |
20210184073 | DOPED SEMICONDUCTOR LAYER FORMING METHOD - A method of obtaining a doped semiconductor layer, including the successive steps of: a) performing, in a first single-crystal layer made of a semiconductor alloy of at least a first element A | 2021-06-17 |
20210184074 | DISPLAY DEVICE - Provided is a display device containing quantum dots. A display device includes a display area. The display area has a light emitting device in which a first electrode, a layer between the first electrode and an emitting layer, the emitting layer, a layer between the emitting layer and a second electrode, and the second electrode are stacked in this order on a substrate. The emitting layer is formed of an inorganic layer containing quantum dots, and the light emitting device is a bottom emission device. All the layers from the first electrode to the second electrode are preferably each formed of the inorganic layer. | 2021-06-17 |
20210184075 | SEMICONDUCTOR STACKING STRUCTURE, AND METHOD AND APPARATUS FOR SEPARATING NITRIDE SEMICONDUCTOR LAYER USING SAME - A semiconductor stacking structure according to the present invention comprises: a monocrystalline substrate which is disparate from a nitride semiconductor; an inorganic thin film which is formed on a substrate to define a cavity between the inorganic thin film and the substrate, wherein at least a portion of the inorganic thin film is crystallized with a crystal structure that is the same as the substrate; and a nitride semiconductor layer which is grown from a crystallized inorganic thin film above the cavity. The method and apparatus for separating a nitride semiconductor layer according the present invention mechanically separate between the substrate and the nitride semiconductor layer. The mechanical separation can be performed by a method of separation of applying a vertical force to the substrate and the nitride semiconductor layer, a method of separation of applying a horizontal force, a method of separation of applying a force of a relative circular motion, and a combination thereof. | 2021-06-17 |
20210184076 | PIXEL OF MICRO DISPLAY HAVING VERTICALLY STACKED SUB-PIXELS AND COMMON ELECTRODE - Disclosed is a unit pixel of a microdisplay. In the unit pixel, sub-pixels which respectively form blue, green, and red light are vertically stacked on a growth substrate. Accordingly, the overall area of the unit pixel is reduced, and a transfer process is easily performed. | 2021-06-17 |
20210184077 | LIGHT-EMITTING DEVICE - An optical element driving system is provided. The optical element driving system includes an optical element driving mechanism and a control assembly. The optical element driving mechanism includes a movable portion, a fixed portion, a driving assembly, and a position sensing assembly. The movable portion connects to an optical element. The movable portion is movable relative to the fixed portion. The movable portion is in an accommodating space in the fixed portion. The driving assembly is used for driving the movable portion to move relative to the fixed portion. The control assembly provides a driving signal to the driving assembly to control the driving assembly. The position sensing assembly is used for detecting the movement of the movable portion relation to the fixed portion and providing a motion sensing signal to the control assembly. | 2021-06-17 |
20210184078 | METHOD FOR PRODUCING A PATTERNED LAYER OF MATERIAL - Method for producing a patterned layer of material, comprising;
| 2021-06-17 |
20210184079 | LIGHT EMITTING DIODES AND ASSOCIATED METHODS OF MANUFACTURING - Light emitting diodes and associated methods of manufacturing are disclosed herein. In one embodiment, a light emitting diode (LED) includes a substrate, a semiconductor material carried by the substrate, and an active region proximate to the semiconductor material. The semiconductor material has a first surface proximate to the substrate and a second surface opposite the first surface. The second surface of the semiconductor material is generally non-planar, and the active region generally conforms to the non-planar second surface of the semiconductor material. | 2021-06-17 |
20210184080 | GROUP-III NITRIDE LAMINATED SUBSTRATE AND SEMICONDUCTOR ELEMENT - Provided is a technology capable of improving the quality of a GaN layer that is formed on an underlying substrate. A group III-nitride laminated substrate includes an underlying substrate, a first layer that is formed on the underlying substrate and is made of aluminum nitride, and a second layer that is formed on the first layer and is made of gallium nitride. The second layer has a thickness of 10 μm or less. A half-value width of (0002) diffraction determined through X-ray rocking curve analysis is 100 seconds or less, and a half-value width of (10-12) diffraction determined through X-ray rocking curve analysis is 200 seconds or less. | 2021-06-17 |
20210184081 | LIGHT-EMITTING DEVICE WITH INTERNAL NON-SPECULAR LIGHT REDIRECTION AND ANTI-REFLECTIVE EXIT SURFACE - A light-emitting device includes a semiconductor diode structure with one or more light-emitting active layers, an anti-reflection coating on its front surface, and a redirection layer on its back surface. Active-layer output light propagates within the diode structure. The anti-reflection coating on the front surface increases transmission of active-layer output light incident below the critical angle Θ | 2021-06-17 |
20210184082 | RADIATION-EMITTING OPTOELECTRONIC COMPONENT - A radiation-emitting optoelectronic component may include a semiconductor chip or a semiconductor laser which, in operation of the component, emits a primary radiation in the UV region or in the blue region of the electromagnetic spectrum. The optoelectronic component may further include a conversion element comprising a first phosphor configured to convert the primary radiation at least partly to a first secondary radiation having a peak wavelength in the green region of the electromagnetic spectrum between 475 nm and 500 nm inclusive. The first phosphor may be or include BaSi | 2021-06-17 |
20210184083 | LIGHT EMITTING DIODES WITH REFLECTIVE SIDEWALLS COMPRISING POROUS PARTICLES - Sidewall reflectors disposed on the sidewalls of an LED or pcLED comprise porous (for example, hollow) high refractive index light scattering particles dispersed in a transparent binder. The porous particles exhibit a high refractive index contrast and corresponding strong scattering at the interfaces between the porous particle material and one or more air-filled voids in each particle. These sidewall reflectors can provide light confinement with thin reflector structures, allowing close spacing between LEDs and pcLEDs, and may be advantageously employed in microLED arrays. | 2021-06-17 |
20210184084 | PHOSPHOR DEPOSITION SYSTEM FOR LEDS - A method to produce a light-emitting device package includes mounting junctions on pads of a metalized substrate, where the junctions are at least partially electrically insulated from each other, and forming wavelength converters, where each wavelength converter is located over a different junction and separated by a gap from neighboring wavelength converters. | 2021-06-17 |
20210184085 | SIDEWALL SCATTERING FOR RADIATION PATTERN CONTROL OF LEDS - Sidewall reflector structures disposed on the sidewalls of an LED or pcLED comprise a thin specular reflection layer and a light scattering layer disposed between the sidewall and the specular reflection layer. These sidewall reflector structures are more diffusively reflective than a specular reflector, yet maintain high reflectivity. | 2021-06-17 |
20210184086 | LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A light-emitting device 100 includes: a light-emitting element; a light-transmissive member covering the light-emitting element; and a light-diffusing agent contained in the light-transmissive member and comprising hollow particles. The light-transmissive member has a first surface having irregularities according to the light-diffusing agent. The first surface of the light-transmissive member has a convex shape with a height gradually increased from a peripheral portion of the first surface toward a central portion of the first surface. | 2021-06-17 |
20210184087 | PACKAGED ULTRAVIOLET LIGHT-EMITTING DEVICE AND PRODUCTION METHOD THEREOF - A packaged ultraviolet light-emitting device includes a support member, at least one ultraviolet light-emitting chip, and an encapsulating cover. The support member has opposite top and bottom surfaces, a side surface interconnecting the top and bottom surfaces, and at least one indentation. The ultraviolet light-emitting chip is disposed on the top surface of the support member. The encapsulating cover is made from a fluorine-containing resin, and is disposed over and in contact with the ultraviolet light-emitting chip and the top surface and the indentation of the support member. The encapsulating cover extends into the indentation. A production method of the packaged ultraviolet light-emitting device is also disclosed. | 2021-06-17 |
20210184088 | DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF - A display apparatus includes a substrate; a light-emitting diode on the substrate; a pixel separating layer surrounding the light-emitting diode; and a light dispersion layer on the light-emitting diode and the pixel separating layer. | 2021-06-17 |
20210184089 | LIGHT BAR AND EXTERIOR LIGHTING ASSEMBLY FOR AN AUTOMOTIVE VEHICLE COMPRISING THE SAME - A light emitting diode (LED) having a uniform optimal luminance pattern includes an outer cylindrical section, an inner cone shape section completely contained inside the outer section, and a top section having a plurality of micro-lenses covering the top surface of the outer cylindrical section. | 2021-06-17 |
20210184090 | LIGHT EMITTING DEVICE PACKAGE AND LIGHT SOURCE DEVICE - The light emitting device package disclosed in the embodiment includes a first frame having a first through hole; a second frame having a second through hole; a body disposed between the first and second frames; and light emitting devices disposed on the first and second frames, wherein the first and second through holes have an area of a lower surface larger than an area of the upper surface, and centers of the upper and lower surfaces of the first through hole may be offset from each other in the vertical direction, and centers of the upper and lower surfaces of the second through hole may be offset from each other in the vertical direction. | 2021-06-17 |
20210184091 | DISPLAY MODULE ADJUSTMENT METHOD OF MOBILE DEVICE AND LIGHT-EMITTING DIODE ARRAY DRIVING SYSTEM - A light-emitting diode array driving system and a display module adjustment method are provided. The light-emitting diode array driving system includes a driving module, and a light-emitting diode array. The driving module includes a plurality of driving units electrically connected to signal driving lines. The light-emitting diode array includes a plurality of light-emitting diode modules. The plurality of light-emitting diode modules are arranged in a matrix. The light-emitting diode modules arranged in the same row or the light-emitting diode modules arranged in the same column are electrically connected to one of the plurality of signal driving lines. The driving units respectively provide a driving signal to the plurality of signal driving lines. The light-emitting diode modules connected to the same signal driving line respectively extract, based on a sequence, a driving unit signal of the driving signal. | 2021-06-17 |
20210184092 | OPTOELECTRONIC COMPONENT, OPTOELECTRONIC MODULE, AND METHOD OF PRODUCING AN OPTOELECTRONIC COMPONENT - An optoelectronic component includes a radiation side, a contact side opposite the radiation side having at least two electrically conductive contact elements, and a semiconductor layer sequence having an active layer that emits or absorbs the electromagnetic radiation, wherein the at least two electrically conductive contact elements have different polarities, are spaced apart from each other and are completely or partially exposed at the contact side in an unmounted state of the optoelectronic component, a region of the contact side is partially or completely covered with an electrically insulating, contiguously formed cooling element, the cooling element is in direct contact with the contact side and has a thermal conductivity of at least 30 W/(m·K), and in a plan view of the contact side, the cooling element partially covers one or both of the at least two electrically conductive contact elements. | 2021-06-17 |
20210184093 | BREATHABLE MICRO LIGHT EMITTING DIODE DISPLAY - A micro light emitting diode display includes a substrate, an electrode layer and a micro light emitting diode device. The substrate has a first surface, a second surface opposite to the first surface, and at least one air passage extending from the first surface to the second surface. The electrode layer is disposed on and in contact with the first surface of the substrate. The air passage has an opening on the first surface of the substrate, and the electrode layer is spaced apart from the opening. The micro light emitting diode device is disposed on the electrode layer and has a light emitting area that is less than or equal to 2500 μm | 2021-06-17 |
20210184094 | JOSEPHSON MAGNETIC MEMORY WITH A SEMICONDUCTOR-BASED MAGNETIC SPIN VALVE - Josephson magnetic memory cells with a semiconductor-based magnetic spin valve are described. An example memory cell includes a first superconducting electrode, a second superconducting electrode, and a semiconductor-based magnetic spin valve arranged between the two superconducting electrodes. The semiconductor-based magnetic spin valve includes a semiconductor layer and a first ferromagnetic insulator arranged near the semiconductor layer, arranged on a first side of the semiconductor layer, configured to provide a fixed magnetization oriented in a first direction. The semiconductor-based magnetic spin valve further includes a second ferromagnetic insulator, arranged on a second side, opposite to the first side, of the semiconductor layer, configured to provide a free magnetization oriented in the first direction or a second direction, opposite to the first direction, in order to control a parameter associated with a flow of current from the first superconducting electrode to the second superconducting electrode through the semiconductor layer. | 2021-06-17 |
20210184095 | SINGLE PHOTON DETECTOR FOR REGULATING SUPERCONDUCTING NANO WIRE AND PREPARATION METHOD THEREFOR - The present disclosure provides a method for making a single photon detector with a modified superconducting nanowire. The method includes: preparing a substrate; modifying a superconducting nanowire with stress on a surface of the substrate; and fabricating a superconducting nanowire single photon detector based on the superconducting nanowire with stress. Based on the above technical solution, in the superconducting nanowire single photon detector provided by the present disclosure, the device material layer film has a certain thickness, the critical temperature of the device material can be reduced, the uniformity of the device material and small superconducting transition width are ensured, thereby improving the detection efficiency of the device. | 2021-06-17 |
20210184096 | FABRICATION OF SUPERCONDUCTOR WIRE - A 2nd generation high temperature superconductor wire that prevents mechanical destruction from the wire edge due to slitting. A 2G HTS wire according to embodiments of the present invention has a structure that prevents mechanical destruction from the wire edge. This can be accomplished by forming a striation at or near the edge of the wire where the buffer and superconducting layers are removed to prevent any propagation of edge cracks from damaging the HTS wire. | 2021-06-17 |
20210184097 | Superconducting Current Limiter With Electroconductive Spacer - A superconducting current limiter having at least one superconducting conductor ( | 2021-06-17 |
20210184098 | METHOD FOR CREATING HIGH-RESOLUTION MICRO- TO NANO-SCALE STRUCTURES ON FLEXIBLE SUBSTRATES - A method includes providing a film of a high-temperature superconductor compound on a flexible substrate, where a portion of the film has a first oxygen state, and exposing a portion of the film to a focused ion beam to create a structure within the film. The structure may result from the portion of the film being partially or completely removed. The structure may be a trench along the length or width of the film. The method may include annealing the exposed portion of the film to a second oxygen state. The oxygen content of the second oxygen state may be greater or less than the oxygen content of the first oxygen state. | 2021-06-17 |
20210184099 | Piezoelectric Element, Piezoelectric Actuator, Ultrasonic Probe, Ultrasonic Apparatus, Electronic Apparatus, Liquid Jet Head, And Liquid Jet Apparatus - A piezoelectric element includes a first electrode layer, a piezoelectric layer, and a second electrode layer. The first electrode layer, the piezoelectric layer, and the second electrode layer are stacked in sequence on one another. The first electrode layer has a first part overlapping the piezoelectric layer in a plan view, and a second part at least partially separated from the first part and not overlapping the piezoelectric layer in the plan view. The second electrode layer has a third part overlapping the piezoelectric layer in the plan view, and a fourth part separated from the third part. The fourth part is in contact with the first part and the second part. | 2021-06-17 |
20210184100 | ELECTRET - An electret includes a substrate and an electret layer formed above a surface of the substrate. The electret layer is a composite metal compound containing two or more different metal elements, and is obtained by subjecting a thin film mainly composed of an inorganic dielectric material having a bandgap energy of 4 eV or more to a polarization treatment. | 2021-06-17 |
20210184101 | ELECTRONIC DEVICE - An electronic device may include a semiconductor memory, and the semiconductor memory may include a multilayer synthetic anti-ferromagnetic (Multi SAF) structure including a first ferromagnetic layer, a second ferromagnetic layer, and a spacer layer interposed between the first ferromagnetic layer and the second ferromagnetic layer, wherein the spacer layer may include n non-magnetic layers and n−1 magnetic layers that are disposed such that each of the n non-magnetic layers and each of the n−1 magnetic layers are alternately stacked, wherein n indicates an odd number equal to or greater than 3, wherein the n−1 magnetic layers and n non-magnetic layers may be configured to effectuate an antiferromagnetic exchange coupling with at least one of the first ferromagnetic layer and the second ferromagnetic layer. | 2021-06-17 |
20210184102 | ELECTRONIC DEVICE - An electronic device may include a semiconductor memory, and the semiconductor memory may include a magnetic tunnel junction (MTJ) structure including a free layer, a pinned layer, and a tunnel barrier layer, the free layer having a variable magnetization direction, the pinned layer having a fixed magnetization direction, the tunnel barrier layer being interposed between the free layer and the pinned layer; and a thermal stability enhanced layer (TSEL) including a homogeneous material having an Fe—O bond. | 2021-06-17 |
20210184103 | MAGNETORESISTIVE EFFECT ELEMENT - The magnetoresistive effect element includes a first ferromagnetic layer, a second ferromagnetic layer, and a nonmagnetic layer positioned between the first ferromagnetic layer and the second ferromagnetic layer, and at least one of the first ferromagnetic layer and the second ferromagnetic layer includes a Heusler alloy layer including a crystal region and an amorphous region. | 2021-06-17 |
20210184104 | MAGNETORESISTIVE RANDOM ACCESS MEMORY - A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction. | 2021-06-17 |
20210184105 | SPIN-ORBIT TORQUE MAGNETORESISTANCE EFFECT ELEMENT AND MAGNETIC MEMORY - A spin-orbit torque magnetoresistance effect element includes an element part including a first ferromagnetic layer, a second ferromagnetic layer, and a nonmagnetic layer positioned between the first ferromagnetic layer and the second ferromagnetic layer, a spin-orbit torque wiring positioned in a first direction with respect to the element part, facing the first ferromagnetic layer of the element part, and extending in a second direction, a first conductive part and a second conductive part facing the spin-orbit torque wiring at positions sandwiching the element part when viewed from the first direction, and a gate part including a gate insulating layer and a gate electrode in order from a position near the spin-orbit torque wiring, in which the spin-orbit torque wiring includes a semiconductor to which a scattering element is added. | 2021-06-17 |
20210184106 | MAGNETORESISTIVE EFFECT ELEMENT, MAGNETIC MEMORY, MAGNETIZATION ROTATION METHOD, AND SPIN CURRENT MAGNETIZATION ROTATIONAL ELEMENT - This spin current magnetization rotational type magnetoresistive element includes a magnetoresistive effect element having a first ferromagnetic metal layer having a fixed magnetization orientation, a second ferromagnetic metal layer having a variable magnetization orientation, and a non-magnetic layer sandwiched between the first ferromagnetic metal layer and the second ferromagnetic metal layer, and spin-orbit torque wiring which extends in a direction that intersects the stacking direction of the magnetoresistive effect element, and is connected to the second ferromagnetic metal layer, wherein the electric current that flows through the magnetoresistive effect element and the electric current that flows through the spin-orbit torque wiring merge or are distributed in the portion where the magnetoresistive effect element and the spin-orbit torque wiring are connected. | 2021-06-17 |
20210184107 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - Semiconductor structure and fabrication method are provided. The semiconductor structure includes: a substrate and a magnetic tunnel junction on the substrate. The magnetic tunnel junction includes: a bottom electromagnetic structure on the substrate, an insulating layer on the bottom electromagnetic structure, and a top electromagnetic structure on the insulating layer. The semiconductor structure further includes a sidewall tunneling layer on sidewall surfaces of the magnetic tunnel junction. | 2021-06-17 |
20210184108 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - Semiconductor structure and fabrication method are provided. The fabrication method includes: providing a substrate; forming a bottom electromagnetic material film on the substrate; forming a precursor film on the bottom electromagnetic material film; forming a first insulating film on the precursor film; and performing an annealing treatment to form the precursor film into a second insulating film. The performance of the semiconductor structure is improved. | 2021-06-17 |
20210184109 | SEMICONDUCTOR STRUCTURE AND FORMATION METHOD THEREOF - A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a substrate, and a conductive layer in the substrate and having a surface exposed by the substrate. A groove is formed in the substrate and adjacent to the conductive layer, and a sidewall of the groove exposes a portion of a sidewall surface of the conductive layer. The semiconductor structure also includes a lower electrode layer located in the groove and on a top surface of the conductive layer. The lower electrode layer covers the top surface and the portion of the sidewall surface of the conductive layer. | 2021-06-17 |
20210184110 | MANUFACTURING TECHNIQUES AND CORRESPONDING DEVICES FOR MAGNETIC TUNNEL JUNCTION DEVICES - Some embodiments relate to a magnetoresistive random-access memory (MRAM) cell. The cell includes a bottom electrode having a central bottom electrode portion surrounded by a peripheral bottom electrode portion. Step regions of the conductive bottom electrode couple the central and peripheral bottom electrode portions to one another such that an upper surface of the central portion is recessed relative to an upper surface of the peripheral portion. A magnetic tunneling junction (MTJ) has MTJ outer sidewalls which are disposed over the bottom central electrode portion and which are arranged between the step regions. A top electrode is disposed over an upper surface of the MTJ. Other devices and methods are also disclosed. | 2021-06-17 |
20210184111 | RESISTIVE MEMORY DEVICES USING A CARBON-BASED CONDUCTOR LINE AND METHODS FOR FORMING THE SAME - An array of rail structures is formed over a substrate. Each rail structure includes at least one bit line. Dielectric isolation structures straddling the array of rail structures are formed. Line trenches are provided between neighboring pairs of the dielectric isolation structures. A layer stack of a resistive memory material layer and a selector material layer is formed within each of the line trenches. A word line is formed on each of the layer stacks within unfilled volumes of the line trenches. The word lines or at least a subset of the bit lines includes a carbon-based conductive material containing hybridized carbon atoms in a hexagonal arrangement to provide a low resistivity conductive structure. An array of resistive memory elements is formed over the substrate. A plurality of arrays of resistive memory elements may be formed at different levels over the substrate. | 2021-06-17 |
20210184112 | CAsSeGe OVONIC MATERIALS FOR SELECTOR DEVICES AND MEMORY DEVICES USING SAME - A voltage sensitive switching device has a first electrode, a second electrode, and a switching layer between the first and second electrodes, comprising a composition of carbon C, arsenic As, selenium Se and germanium Ge thermally stable to temperatures over 400° C. The switching device is used in 3D crosspoint memory. | 2021-06-17 |
20210184113 | Conductive Oxide Diffusion Barrier for Laser Crystallization - A cross-point memory semiconductor structure and a method of creating the same are provided. There is a first electrode layer on top of the substrate. A conductive oxide diffusion barrier layer is on top of the first electrode. A polycrystalline silicon diode is on top of the conductive oxide diffusion barrier. A phase change material (PCM) layer is on top of the polycrystalline silicon diode. A second electrode is on top of the PCM layer. | 2021-06-17 |
20210184114 | RRAM WITH A BARRIER LAYER - Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell comprising a barrier layer to constrain the movement of metal cations during operation of the RRAM cell. In some embodiments, the RRAM cell further comprises a bottom electrode, a top electrode, a switching layer, and an active metal layer. The switching layer, the barrier layer, and the active metal layer are stacked between the bottom and top electrodes, and the barrier layer is between the switching and active metal layers. The barrier layer is conductive and between has a lattice constant less than that of the active metal layer. | 2021-06-17 |
20210184115 | MULTIPLE GERMANIUM ATOM QUANTUM DOT AND DEVICES INCLUSIVE THEREOF - A multiple-atom germanium quantum dot is provided that includes multiple dangling bonds on an otherwise H-terminated germanium surface, each dangling bonds having one of three ionization states of +1, 0 or −1 and corresponding respectively to 0, 1, or 2 electrons in a dangling bond state. The dangling bonds together in close proximity and having the dangling bond states energetically in the germanium band gap with selective control of the ionization state of one of the dangling bonds. A new class of electronics elements is provided through the inclusion of at least one input and at least one output to the multiple dangling bonds. Selective modification or creation of a dangling bond is also detailed. | 2021-06-17 |
20210184116 | SEMICONDUCTOR DEVICE INCLUDING VARIABLE RESISTANCE ELEMENT - A semiconductor device including a variable resistance device is provided. A variable resistance element according to one embodiment of the present disclosure includes: an ion-receiving layer having a top, a bottom and a sidewall connecting the top to the bottom; an ion supply layer having an inner sidewall connected to at least a portion of the sidewall of the ion-receiving layer; a gate pattern connected to an outer sidewall of the ion supply layer; and a source pattern connected to one of the top or bottom of the ion-receiving layer, and a drain pattern connected to the other one of the top or bottom of the ion-receiving layer, wherein a resistance of the ion-receiving layer varies depending on an amount of ions supplied from the ion supply layer based on a voltage applied to the gate pattern. | 2021-06-17 |
20210184117 | ELEMENTARY CELL COMPRISING A RESISTIVE MEMORY AND ASSOCIATED METHOD OF INITIALISATION - An aspect of the invention relates to an elementary cell that includes a breakdown layer made of dielectric having a thickness that depends on a breakdown voltage, a device and a non-volatile resistive memory mounted in series, the device including an upper selector electrode, a lower selector electrode, a layer made in a first active material, referred to as active selector layer, the device being intended to form a volatile selector; the memory including an upper memory electrode, a lower memory electrode, a layer made in at least one second active material, referred to as active memory layer. | 2021-06-17 |
20210184118 | PHASE-CHANGE MEMORY WITH NO DRIFT - A bottom electrode is deposited on top of a substrate. A dielectric material layer is deposited on top of the bottom electrode. A hole is created in the dielectric material layer. A lift off layer is spun on and baked on the dielectric material layer. A photoresist layer is spun on and baked on the lift off layer. UV lithography is performed to create an opening above the hole in the dielectric material layer. An Ag layer is deposited on top of the remaining patterned dielectric material layer and the photoresist layer. A Germanium Antimony Telluride (GST) layer is deposited on top of the Ag layer. A top electrode is deposited on top of the GST layer. The Ag layer, the GST layer, and the top electrode located on top of the photoresist layer along with the photoresist layer and the lift off layer are removed. | 2021-06-17 |
20210184119 | ORGANIC LIGHT-EMITTING DEVICE - An organic light-emitting device including: a first electrode; a second electrode facing the first electrode; and an organic layer between the first electrode and the second electrode, the organic layer including an emission layer. The organic layer includes a first compound and the emission layer includes a second compound and a third compound. The second compound is a fluorescent host, the third compound is a fluorescent dopant, and the first compound, the second compound, and the third compound each independently includes at least one selected from moieties represented by Formulae A to D: | 2021-06-17 |
20210184120 | FUNCTIONAL LAYER FORMING INK AND SELF-LUMINOUS ELEMENT MANUFACTURING METHOD - An ink used in forming a functional layer of a self-luminous element by a printing method, the ink including a functional material and a mixed solvent. The mixed solvent includes solvents each having different vapor pressures. The functional material is dissolved or dispersed in the mixed solvent. A solvent that has a lowest vapor pressure among the solvents has a viscosity of at least 53 mPa·s, and a viscosity of the mixed solvent is 15 mPa·s or less. | 2021-06-17 |
20210184121 | HETEROCYCLIC COMPOUND AND ORGANIC LIGHT-EMITTING DEVICE COMPRISING SAME - Provided is a heterocyclic compound of Chemical Formula 1: | 2021-06-17 |
20210184122 | COMPOUND, DISPLAY PANEL, AND DISPLAY APPARATUS - The present disclosure provides a boron heterocyclic compound having a structure represented by a chemical formula 1, wherein L | 2021-06-17 |
20210184123 | ORGANIC ELECTROLUMINESCENCE DEVICE AND FUSED POLYCYCLIC COMPOUND FOR ORGANIC ELECTROLUMINESCENCE DEVICE - An organic electroluminescence device of an embodiment includes a first electrode, an oppositely disposed second electrode, and a plurality of organic layers disposed between the first electrode and the second electrode, wherein at least one of the plurality of organic layers includes a fused polycyclic compound represented by Formula 1 and has an improved emission efficiency and long device life span: | 2021-06-17 |
20210184124 | Organic Electronic Device - The present invention relates to an organic electronic device, comprising a first electrode, a second electrode, and a substantially organic layer comprising a compound according to formula (I) between the first and the second electrode: | 2021-06-17 |
20210184125 | MASK ASSEMBLY AND METHOD OF PATTERNING SEMICONDUCTOR FILM USING THEREOF - A mask assembly and a method of patterning a semiconductor film using the mask assembly. A first mask comprises a plurality of first light shielding regions, a plurality of first light transmissive regions, and at least one first light shielding island; a boundary of a first light shielding island is not connected to a boundary of the first mask; a second mask comprises a plurality of second light shielding regions, a plurality of second light transmissive regions, and at least one second light shielding island; a boundary of the second light shielding island is not connected to a boundary of the second mask; the first light shielding region and the second light shielding region are complementarily arranged, the first light transmissive region and the second light transmissive region are complementarily disposed. | 2021-06-17 |
20210184126 | LIGHT-EMITTING COMPONENT, MANUFACTURING METHOD THEREFOR, MASK, AND DISPLAY DEVICE - A method for manufacturing a light-emitting component, including forming an auxiliary electrode and a first electrode arranged at an interval on a base substrate; depositing, by means of a mask with a hollow area, a light-emitting layer on the base substrate on which the auxiliary electrode and the first electrode are formed; and forming a second electrode on the base substrate on which the light-emitting layer is formed. The light-emitting layer covers at least part of the first electrode, and at least a partial area of the auxiliary electrode is exposed outside the light-emitting layer. The second electrode covers at least part of the light-emitting layer and the at least partial area of the auxiliary electrode, and the second electrode is connected to the at least partial area of the auxiliary electrode. | 2021-06-17 |
20210184127 | PROCESS FOR PRODUCING ELECTRODE AND PROCESS FOR PRODUCING PHOTOELECTRIC CONVERSION DEVICE - The embodiments provide a process for easily producing an electrode having low resistance, easily subjected to post-process and hardly impairing the device; and also provide, as its application, a production process for a photoelectric conversion device. The process comprises the steps of:
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20210184128 | COMPOUND FOR ORGANIC OPTOELECTRONIC DEVICE, COMPOSITION FOR ORGANIC OPTOELECTRONIC DEVICE, ORGANIC OPTOELECTRONIC DEVICE, AND DISPLAY DEVICE - The present invention is related to a first compound for an organic optoelectronic device represented by Chemical Formula 1, a composition for an organic optoelectronic device including the same, an organic optoelectronic device, and a display device. | 2021-06-17 |
20210184129 | COMPOUND FOR ORGANIC ELECTRONIC ELEMENT, ORGANIC ELECTRONIC ELEMENT USING SAME AND ELECTRONIC DEVICE THEREOF - Provided is a novel mixture capable of improving luminous efficiency, stability, and lifespan of an element, an organic electric element using the same, and an electronic device therefor. | 2021-06-17 |
20210184130 | ORGANIC COMPOUND, LIGHT-EMITTING DEVICE, OPTICAL DEVICE, LIGHT-EMITTING APPARATUS, ELECTRONIC DEVICE, AND LIGHTING DEVICE - A novel organic compound with favorable thermophysical properties is provided. An organic compound represented by General Formula (G1) is provided. At least one of X | 2021-06-17 |
20210184131 | NOVEL COMPOUND AND ORGANIC LIGHT EMITTING DEVICE COMPRISING THE SAME - A novel compound of the following Chemical Formula 1, and an organic light emitting device including the same. | 2021-06-17 |