24th week of 2021 patent applcation highlights part 70 |
Patent application number | Title | Published |
20210183832 | METHODS AND APPARATUSES FOR PACKAGING ULTRASOUND-ON-CHIP DEVICES - Aspects of the technology described herein related to an ultrasound device including a first integrated circuit substrate having first integrated ultrasound circuitry and a second integrated circuit substrate having second integrated ultrasound circuitry. The first and second integrated circuit substrates are arranged in a vertical stack. A first conductive pillar is electrically coupled, through a first redistribution layer, to the first integrated circuit substrate, and a second conductive pillar is electrically coupled, through the first and second redistribution layers, to the second integrated circuit substrate. | 2021-06-17 |
20210183833 | ELECTRONIC DEVICE - An electronic device is provided. The electronic device includes a plurality of light-emitting elements and a first thin-film transistor array. The first thin-film transistor array is used to drive at least a portion of the plurality of light-emitting elements, and the plurality of light-emitting elements and the first thin-film transistor array are disposed on different substrates. | 2021-06-17 |
20210183834 | COMPONENT ASSEMBLY AND METHOD FOR PRODUCING COMPONENTS - A component assembly includes an intermediate carrier, a plurality of components and a plurality of anchoring elements. The components have at least two electrical devices and an insulating layer. At least one of the electrical devices is an optoelectronic semiconductor chip. The insulating layer is between the electrical devices of a same component. The at least two electrical devices of the same component are arranged next to one another and enclosed laterally by the insulating layer. The at least two electrical devices and the insulating layer of the same component are integral parts of a self-supporting and mechanically stable unit. The self-supporting and mechanically stable unit and the anchoring elements fix the positions of the components on the intermediate carrier. The components that are self-supporting and mechanically stable units are detachable from the intermediate carrier, and the anchoring elements release the components under mechanical load when the latter are removed. | 2021-06-17 |
20210183835 | DISPLAY PANEL COMPRISING MICRO LIGHT-EMITTING DIODES AND METHOD FOR MAKING SAME - A micro LED display panel includes a substrate, a plurality of first metal electrodes and a plurality of metal pads on a surface of the substrate, a connection layer on the substrate, a plurality of micro LEDs on a side of the connection layer away from the substrate. The connection layer includes conductive particles. Each of the micro LEDs is coupled to at least one of the first metal electrode. A side of each of the metal pads away from the substrate is coupled to some of the conductive particles in the connection layer to form a metal retaining wall. The metal retaining walls enhance structural strength of the micro LED display panel and avoid breakage of any of the micro LEDs. | 2021-06-17 |
20210183836 | SEMICONDUCTOR ELEMENT PACKAGE AND LIGHT-EMITTING DEVICE COMPRISING SAME - An embodiment discloses a semiconductor element package and a light-emitting device comprising same. The semiconductor element package comprises: a body comprising a cavity; a first electrode and a second electrode arranged on the bottom surface of the cavity; a semiconductor element arranged on the first electrode; a protective element arranged on the first electrode and spaced apart from the semiconductor element; a first wire electrically connecting the semiconductor element and the second electrode; and a second wire electrically connecting the protective element and the second electrode. The second electrode is arranged to be spaced apart from the first electrode in a first direction. The second electrode overlaps the semiconductor element in the first direction. The protective element is arranged to deviate from the semiconductor element in a second direction that is perpendicular to the first direction. The first electrode comprises a groove arranged between the semiconductor element and the protective element. | 2021-06-17 |
20210183837 | DISPLAY APPARATUS HAVING DISPLAY MODULE AND METHOD OF MANUFACTURING THE SAME - A display module may include: (1) a substrate including a mounting surface on which a thin film transistor (TFT) layer is formed, a side surface, and a chamfer portion formed between the mounting surface and the side surface; (2) a plurality of inorganic light emitting diodes (LEDs) disposed on the TFT layer, each of the plurality of inorganic LEDs including a pair of electrodes electrically connected to the TFT layer and disposed to face the mounting surface, and a light emitting surface configured to emit light in a first direction opposite to a second direction that extends from the plurality of inorganic LEDs to the mounting surface of the substrate; and (3) a molding provided to cover the plurality of inorganic LEDs, the chamfer portion of the substrate, and the side surface of the substrate. | 2021-06-17 |
20210183838 | STRETCHABLE DISPLAY DEVICE - The present disclosure provides a stretchable display device. The stretchable display device includes a lower substrate made of a stretchable insulating material and having an active area and a non-active area adjacent to the active area, a plurality of individual substrates spaced apart from each other and disposed in the active area of the lower substrate, pixels disposed on the plurality of individual substrates respectively, and a plurality of connecting lines disposed between the plurality of individual substrates on the lower substrate, and electrically connecting corresponding pads disposed within the plurality of individual substrates respectively. The modulus of the plurality of individual substrates is higher than the lower substrate. | 2021-06-17 |
20210183839 | SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - An optical module includes a carrier, a light emitter disposed on the carrier, a light detector disposed on the carrier, and a housing disposed on the carrier. The housing defines a first opening that exposes the light emitter and a second opening that exposes the light detector. The optical module further includes a first light transmission element disposed on the first opening and a second light transmission element disposed on the second opening. A first opaque layer is disposed on the first light transmission element, the first opaque layer defining a first aperture, and a second opaque layer disposed on the second light transmission element, the second opaque layer defining a second aperture. | 2021-06-17 |
20210183840 | BENDABLE PANEL AND METHOD OF FABRICATING SAME - A bendable panel and a method of fabricating same are provided. The bendable panel improves a current display panel to provide better support and impact resistance to a bent region of a display panel. In addition, a protection performance, such as corrosion resistance, on a line in the bent region is improved. | 2021-06-17 |
20210183841 | SEMICONDUCTOR DEVICE MODULE AND METHOD OF ASSEMBLY - A semiconductor device module. The semiconductor device module may include a first substrate; and a semiconductor die assembly, disposed on the first substrate. The semiconductor die assembly may include a first semiconductor die, bonded to the first substrate; a second semiconductor die, disposed over the first semiconductor die; and an electrical connector, disposed between the first semiconductor die and the second semiconductor die, wherein the semiconductor die assembly comprises an insulated gate bipolar transistor (IGBT) die and a freewheeling diode die. | 2021-06-17 |
20210183842 | STACKED INTERPOSER STRUCTURES, MICROELECTRONIC DEVICE ASSEMBLIES INCLUDING SAME, AND METHODS OF FABRICATION, AND RELATED ELECTRONIC SYSTEMS - An interposer comprises a semiconductor material and includes cache memory under a location on the interposer for a host device. Memory interface circuitry may also be located under one or more locations on the interposer for memory devices. Microelectronic device assemblies incorporating such an interposer and comprising a host device and multiple memory devices are also disclosed, as are methods of fabricating such microelectronic device assemblies. | 2021-06-17 |
20210183843 | SEMICONDUCTOR DEVICES, SEMICONDUCTOR DEVICE PACKAGES, ELECTRONIC SYSTEMS INCLUDING SAME, AND RELATED METHODS - Semiconductor devices and semiconductor device packages may include at least one first semiconductor die supported on a first side of a substrate. The at least one first semiconductor die may include a first active surface. A second semiconductor die may be supported on a second, opposite side of the substrate. The second semiconductor die may include a second active surface located on a side of the second semiconductor die facing the substrate. The second semiconductor die may be configured to have higher median power consumption than the at least one first semiconductor die during operation. An electronic system incorporating a semiconductor device package is disclosed, as are related methods. | 2021-06-17 |
20210183844 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor device, at least one second semiconductor device, at least one dummy die, an encapsulant and a redistribution structure. The first semiconductor device, the at least one second semiconductor device and at least one dummy die are laterally separated from one another, and laterally encapsulated by the encapsulant. A Young's modulus of the at least one dummy die is greater than a Young's modulus of the encapsulant. A sidewall of the at least one dummy die is substantially coplanar with a sidewall of the encapsulant. The redistribution structure is disposed over the encapsulant, and electrically connected to the first semiconductor device and the at least one second semiconductor device. | 2021-06-17 |
20210183845 | DISPLAY DEVICE - A display device including a lower substrate, a display structure, pad electrodes, and a driver integrated circuit. The lower substrate has a display area and a pad area. The display structure is disposed in the display area on the lower substrate. The pad electrodes are disposed in the pad area on the lower substrate while being spaced apart from each other in a first direction. The driver integrated circuit is spaced apart from the pad electrodes in the second direction in the pad area on the lower substrate, and includes a circuit portion and a first blocking portion spaced apart from the circuit portion in a second direction perpendicular to the first direction. | 2021-06-17 |
20210183846 | ENHANCED INTEGRATED CIRCUIT COMPONENT POWER DELIVERY - A processor module comprises an integrated circuit component attached to a power interposer. One or more voltage regulator modules attach to the power interposer via interconnect sockets and the power interposer routes regulated power signals generated by the voltage regulator modules to the integrated circuit component. Input power signals are provided to the voltage regulator from the system board via straight pins, a cable connector, or another type of connector. The integrated circuit component's I/O signals are routed through the power interposer to a system board via a socket located between the power interposer and the socket. Not having to route regulated power signals from a system board through a socket to an integrated circuit component can result in a system board with fewer layers, which can reduce overall system cost, as well as creating more area available in the remaining layers for I/O signal entry to the socket. | 2021-06-17 |
20210183847 | STACKED DIES AND METHODS FOR FORMING BONDED STRUCTURES - In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive. | 2021-06-17 |
20210183848 | Electrostatic Protection Device and Manufacturing Method Thereof and Array Substrate - An electrostatic protection device ( | 2021-06-17 |
20210183849 | POWER MOS DEVICE HAVING AN INTEGRATED CURRENT SENSOR AND MANUFACTURING PROCESS THEREOF - Power MOS device, in which a power MOS transistor has a drain terminal that is coupled to a power supply node, a gate terminal that is coupled to a drive node and a source terminal that is coupled to a load node. A detection MOS transistor has a drain terminal that is coupled to a detection node, a gate terminal that is coupled to the drive node and a source terminal that is coupled to the load node. A detection resistor has a first terminal coupled to the power supply node and a second terminal coupled to the detection node. | 2021-06-17 |
20210183850 | ESD DIODE SOLUTION FOR NANORIBBON ARCHITECTURES - Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a semiconductor substrate and a source. The source has a first conductivity type and a first insulator separates the source from the semiconductor substrate. The semiconductor device further comprises a drain. The drain has a second conductivity type that is opposite from the first conductivity type, and a second insulator separates the drain from the semiconductor substrate. In an embodiment, the semiconductor further comprises a semiconductor body between the source and the drain, where the semiconductor body is spaced away from the semiconductor substrate. | 2021-06-17 |
20210183851 | APPARATUS WITH VOLTAGE PROTECTION MECHANISM - An apparatus includes a protection circuit electrically connected to first and second voltage domains. The protection circuit includes a first silicon-controlled rectifier (SCR) and a second SCR connected in anti-parallel configuration. The first SCR is configured to connect the first voltage domain and the second voltage domain based on detection of a first triggering condition. The second SCR is configured to connect the second voltage domain and the first voltage domain based on detection of a second triggering condition. The protection circuit is configured to isolate the first and second voltage domains without the triggering conditions. | 2021-06-17 |
20210183852 | NANOSHEET (NS) AND FIN FIELD-EFFECT TRANSISTOR (FINFET) HYBRID INTEGRATION - Certain aspects of the present disclosure are directed to a semiconductor device. The semiconductor device generally includes a substrate, at least one silicon-on-insulator (SOI) transistor disposed above the substrate, a gate-all-around (GAA) transistor disposed above the substrate, and a fin field-effect transistor (FinFET) disposed above the substrate. | 2021-06-17 |
20210183853 | MONOLITHIC ELECTRONIC DEVICE AND METHOD OF MANUFACTURE - A monolithic electronic device includes a plurality of rigid portions arranged in a polyhedron shape and a plurality of in-plane and out-of-plane deformable portions connecting the plurality of rigid portions to each other. Each of the plurality of rigid portions has an outer side and an opposing inner side. The inner of each of the plurality of rigid portions face an inside of the polyhedron shape. At least some of the plurality of rigid portions include semiconductor devices on both the outer and inner sides. The plurality of rigid portions and the plurality of in-plane and out-of-plane deformable portions are monolithic. | 2021-06-17 |
20210183854 | SEMICONDUCTOR DEVICE HAVING A PLURALITY OF BIPOLAR TRANSISTORS WITH DIFFERENT HEIGHTS BETWEEN THEIR RESPECTIVE EMITTER LAYERS AND EMITTER ELECTRODES - A semiconductor device has a semiconductor substrate, and multiple first bipolar transistors on the first primary surface side of the semiconductor substrate. The first bipolar transistors have a first height between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. The semiconductor device further has at least one second bipolar transistor on the first primary surface side of the semiconductor substrate. The second bipolar transistor have a second height, greater than the first height, between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. Also, the semiconductor has a first bump stretching over the multiple first bipolar transistors and the at least one second bipolar transistor. | 2021-06-17 |
20210183855 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure is provided. The semiconductor structure includes a first gate-all-around FET over a substrate, and the first gate-all-around FET includes first nanostructures and a first gate stack surrounding the first nanostructures. The semiconductor structure also includes a first FinFET adjacent to the first gate-all-around FET, and the first FinFET includes a first fin structure and a second gate stack over the first fin structure. The semiconductor structure also includes a gate-cut feature interposing the first gate stack of the first gate-all-around FET and the second gate stack of the first FinFET | 2021-06-17 |
20210183856 | MINIMIZING SHORTING BETWEEN FINFET EPITAXIAL REGIONS - The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another. | 2021-06-17 |
20210183857 | NANORIBBON THICK GATE DEVICE WITH HYBRID DIELECTRIC TUNING FOR HIGH BREAKDOWN AND VT MODULATION - Embodiments disclosed herein include semiconductor devices and methods of forming such semiconductor devices. In an embodiment, the semiconductor device comprises a substrate, and a first transistor over the substrate. In an embodiment, the first transistor comprises a first semiconductor channel above the substrate, a first gate dielectric surrounding the first semiconductor channel, and a first gate electrode over the first gate dielectric. In an embodiment, the semiconductor device further comprises a second transistor over the substrate. In an embodiment, the second transistor comprises a second semiconductor channel above the substrate, a second gate dielectric surrounding the second semiconductor channel, where the second gate dielectric is different than the first gate dielectric, and a second gate electrode over the second gate dielectric, where the first gate electrode and the second gate electrode comprise the same material. | 2021-06-17 |
20210183858 | Low Resistance Fill Metal Layer Material as Stressor in Metal Gates - An Integrated Circuit (IC) device includes a first plurality of semiconductor layers over a substrate, a first gate dielectric layer and a first gate electrode. The first gate electrode includes a first fill metal layer and a work function metal layer disposed between the first gate dielectric layer and the first fill metal layer. The IC device further includes a second plurality of semiconductor layers over the substrate, a second gate dielectric layer and a second gate electrode. The second gate electrode includes a second fill metal layer directly contacting the second gate dielectric layer. A top surface of the second fill metal layer extends above a topmost layer of the second plurality of semiconductor layers. The material of the semiconductor layers has a midgap. The work function metal layer has a work function lower than the midgap. The fill metal layer has a work function higher than the midgap. | 2021-06-17 |
20210183859 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a substrate, and a standard cell on the substrate. The standard cell includes a first wiring structure electrically connecting a first gate pattern to a fourth gate pattern, and a second wiring structure electrically connecting a second gate pattern to a third gate pattern. The first wiring structure includes a first lower wiring layer, a second lower wiring layer, first and second intermediate wiring layers, and a first upper wiring layer. The second wiring structure includes a third lower wiring layer, a fourth lower wiring layer, third and fourth intermediate wiring layers, and a second upper wiring layer. | 2021-06-17 |
20210183860 | MEMORY DEVICE AND ELECTRONIC DEVICE - A novel semiconductor device is provided. A semiconductor device includes a plurality of cell arrays and a plurality of peripheral circuits. The cell array includes a plurality of memory cells. The peripheral circuit includes a first driver circuit, a second driver circuit, a first amplifier circuit, a second amplifier circuit, a third amplifier circuit, and a fourth amplifier circuit. The first driver circuit and the second driver circuit each have a function of supplying a selection signal to the cell array. The first amplifier circuit and the second amplifier circuit each have a function of amplifying a potential input from the cell array. The third amplifier circuit and the fourth amplifier circuit each have a function of amplifying a potential input from the first amplifier circuit or the second amplifier circuit. The first driver circuit, the second driver circuit, the first amplifier circuit, the second amplifier circuit, the third amplifier circuit, and the fourth amplifier circuit have a region overlapping with the cell array. A transistor included in the memory cell includes a metal oxide in a channel formation region. | 2021-06-17 |
20210183861 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE - A three-dimensional semiconductor device includes a first channel pattern on and spaced apart from a substrate, the first channel pattern having a first end and a second end that are spaced apart from each other in a first direction parallel to a top surface of the substrate, and a first sidewall and a second sidewall connecting between the first end and the second end, the first and second sidewalls being spaced apart from each other in a second direction parallel to the top surface of the substrate, the second direction intersecting the first direction, a bit line in contact with the first end of the first channel pattern, the bit line extending in a third direction perpendicular to the top surface of the substrate, and a first gate electrode adjacent to the first sidewall of the first channel pattern. | 2021-06-17 |
20210183862 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device includes a stack structure comprising a plurality of layers vertically stacked on a substrate, each layer including a semiconductor pattern, a gate electrode extending in a first direction on the semiconductor pattern, and a data storage element electrically connected to the semiconductor pattern, a plurality of vertical insulators penetrating the stack structure, the vertical insulators arranged in the first direction, and a bit line provided at a side of the stack structure and extending vertically. The bit line electrically connects the semiconductor patterns which are stacked. Each of the vertical insulators includes first and second vertical insulators adjacent to each other. The gate electrode includes a connection portion disposed between the first and second vertical insulators. | 2021-06-17 |
20210183863 | MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A memory device and its manufacturing method are provided, including: a semiconductor substrate, including a shallow trench isolation structure and an active area positioned at one side of the shallow trench isolation structure; two buried word lines and a first dielectric layer, wherein the buried word lines are disposed in the semiconductor substrate and separated from each other, the first dielectric layer is disposed on the semiconductor substrate and corresponds to the two buried word lines; a contact plug disposed on the semiconductor substrate and within the active area, including a conductive layer and an epitaxial layer, the conductive layer is disposed on the sidewalls of the first dielectric layer, the epitaxial layer is disposed on the sidewalls of the conductive layer and extends into the semiconductor substrate; a second dielectric layer disposed over the semiconductor substrate, covering the contact plug and the shallow trench isolation structure. | 2021-06-17 |
20210183864 | Transistors, Arrays Of Transistors, Arrays Of Memory Cells Individually Comprising A Capacitor And An Elevationally-Extending Transistor, And Methods Of Forming An Array Of Transistors - A transistor comprises semiconductor material that is generally L-shaped or generally mirror L-shaped in at least one straight-line vertical cross-section thereby having an elevationally-extending stem and a base extending horizontally from a lateral side of the stem above a bottom of the stem. The semiconductor material of the stem comprises an upper source/drain region and a channel region there-below. The transistor comprises at least one of (a) and (b), where (a): the semiconductor material of the stem comprises a lower source/drain region below the channel region, and (b): the semiconductor material of the base comprises a lower source/drain region. A gate is operatively laterally adjacent the channel region of the stem. Other embodiments are disclosed, including arrays of memory cells individually comprising a capacitor and an elevationally-extending transistor. Methods are disclosed. | 2021-06-17 |
20210183865 | SEMICONDUCTOR STRUCTURE FORMATION - Systems, apparatuses, and methods related to semiconductor structure formation are described. An example apparatus includes a first trench and a second trench formed in a semiconductor substrate material, where the first and second trenches are adjacent and separated by the semiconductor substrate material. The apparatus includes a metallic material formed to a first height in the first trench that is less than, relative to the semiconductor substrate material, a second height of the metallic material formed in the second trench and a polysilicon material formed over the metallic material in the first trench to a first depth greater than, relative to the semiconductor substrate material, a second depth of the polysilicon material formed over the metallic material in the second trench. The greater first depth of the polysilicon material formed in the first trench reduces transfer of charge by way of the metallic material in the first trench. | 2021-06-17 |
20210183866 | SEMICONDUCTOR STRUCTURE FORMATION - An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate. The first source/drain region and the second source/drain region are separated by the channel. The example apparatus further includes a gate separated from the channel by a dielectric material and an access line formed in a high aspect ratio trench connected to the gate. The access line includes a first titanium nitride (TiN) material formed in the trench, a metal material formed over the first TiN material, and a second TiN material formed over the metal material. The example apparatus further includes a sense line coupled to the first source/drain region and a storage node coupled to the second source/drain region. | 2021-06-17 |
20210183867 | SEMICONDUCTOR MEMORY DEVICE WITH SHALLOW BURIED CAPACITOR AND FABRICATION METHOD THEREOF - A semiconductor device includes a bottle-shaped capacitor cavity extends through a silicon device layer and a buried oxide layer of a substrate. The bottle-shaped capacitor cavity includes an upper portion in the silicon device layer and a widened bottom burrow in the buried oxide layer and underneath the silicon device layer. The widened bottom burrow is wider than the upper portion. A buried capacitor is disposed in the bottle-shaped capacitor cavity. The buried capacitor includes an inner electrode and an outer electrode with the capacitor dielectric layer therebetween. A transistor is disposed on the substrate. The transistor includes a source region and a drain region, a channel region between the source region and the drain region, and a gate over the channel region. The source region is electrically connected to the inner electrode. | 2021-06-17 |
20210183868 | SEMICONDUCTOR MEMORY DEVICE WITH BURIED CAPACITOR AND FIN-LIKE ELECTRODES, AND FABRICATION METHOD THEREOF - A semiconductor device includes a substrate having a semiconductor substrate, an insulator layer on the semiconductor substrate, and a silicon device layer on the insulator layer. At least one capacitor cavity with corrugated sidewall surface is disposed within the insulator layer between the semiconductor substrate and the silicon device layer. At least one buried capacitor is provided in the at least one capacitor cavity. The at least one buried capacitor includes an inner electrode and an outer electrode with a capacitor dielectric layer therebetween. | 2021-06-17 |
20210183869 | FIN FIELD-EFFECT TRANSISTOR (FINFET) STATIC RANDOM ACCESS MEMORY (SRAM) - Certain aspects are directed to a static random access memory (SRAM) including an SRAM cell with a pass-gate (PG) transistor having increased threshold voltage to improve the read margin of the SRAM cell. The SRAM generally includes a first SRAM cell having a pull-down (PD) transistor and a PG transistor coupled to the PD transistor. In certain aspects, the SRAM includes a second SRAM cell, the second SRAM cell being adjacent to the first SRAM cell and having a PD transistor and a PG transistor coupled to the PD transistor of the second SRAM cell. The SRAM may also include a gate contact region coupled to a gate region of the PG transistor of the first SRAM cell, wherein at least a portion of the gate contact region is offset from a midpoint between the first SRAM cell and the second SRAM cell. | 2021-06-17 |
20210183870 | EIGHT-TRANSISTOR STATIC RANDOM ACCESS MEMORY, LAYOUT THEREOF, AND METHOD FOR MANUFACTURING THE SAME - A Static Random Access Memory (SRAM) cell includes a write port including a first inverter including a first pull-up transistor and a first pull-down transistor, and a second inverter including a second pull-up transistor and a second pull-down transistor and cross-coupled with the first inverter; and a read port including a read pass-gate transistor and a read pull-down transistor serially connected to each. A first doped concentration of impurities doped in channel regions of the second pull-down transistor and the read pull-down transistor is greater than a second doped concentration of the impurities doped in a channel region of the first pull-down transistor, or the impurities are doped in the channel regions of the second pull-down transistor and the read pull-down transistor and are not doped in the channel region of the first pull-down transistor. | 2021-06-17 |
20210183871 | SEMICONDUCTOR DEVICE INCLUDING ANTI-FUSE CELL - A structure includes anti-fuse cells. The anti-fuse cells include a first active area, a first gate, a second gate, at least one first gate via, and at least one second gate via. The first gate and the second gate are separate from each other. The first gate and the second gate extend to cross over the first active area. The at least one first gate via is coupled to the first gate and disposed directly above the first active area. The at least one second gate via is coupled to the second gate. The first gate is coupled through the at least one first gate via to a first word line for receiving a first programming voltage, and the second gate is coupled through the at least one second gate via to a second word line for receiving a first reading voltage. | 2021-06-17 |
20210183872 | VERTICAL FUSE MEMORY IN ONE-TIME PROGRAM MEMORY CELLS - In some embodiments, the present disclosure relates to a one-time program memory device that includes a source-line arranged over a bottom dielectric layer. Further, a bit-line is arranged directly over the source-line in a first direction. A channel isolation structure is arranged between the source-line and the bit-line. A channel structure is also arranged between the source-line and the bit-line and is arranged beside the channel isolation structure in a second direction perpendicular to the first direction. A vertical gate electrode extends in the first direction from the bottom dielectric layer to the bit-line and is arranged beside the channel isolation structure in the second direction. The one-time program memory device further includes a gate dielectric layer arranged between the vertical gate electrode and the bit-line, the source-line, and the channel structure. | 2021-06-17 |
20210183873 | Memory Devices and Methods of Forming Memory Devices - Some embodiments include an integrated assembly having bottom electrodes coupled with electrical nodes. Each of the bottom electrodes has a first leg electrically coupled with an associated one of the electrical nodes, and has a second leg joining to the first leg. First gaps are between some of the bottom electrodes, and second gaps are between others of the bottom electrodes. The first gaps alternate with the second gaps. Insulative material and conductive-plate-material are within the first gaps. Scaffold structures are within the second gaps and not within the first gaps. Capacitors include the bottom electrodes, regions of the insulative material and regions of the conductive-plate-material. The capacitors may be ferroelectric capacitors or non-ferroelectric capacitors. Some embodiments include methods of forming integrated assemblies. | 2021-06-17 |
20210183874 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate, a plurality of floating gates, a tunneling dielectric layer, a plurality of control gates, and an ONO layer. The floating gates are located on the substrate, and the tunneling dielectric layer is located between the substrate and each of the floating gates. The control gates are located on the floating gates, and the ONO layer is located on two sidewalls of each of the control gates and between each of the control gates and each of the floating gates. | 2021-06-17 |
20210183875 | STRAP-CELL ARCHITECTURE FOR EMBEDDED MEMORY - Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced. | 2021-06-17 |
20210183876 | ERASABLE PROGRAMMABLE NON-VOLATILE MEMORY - An erasable programmable non-volatile memory includes a first-type well region, three doped regions, two gate structures, a blocking layer and an erase line. The first doped region is connected with a source line. The third doped region is connected with a bit line. The first gate structure is spanned over an area between the first doped region and the second doped region. A first polysilicon gate of the first gate structure is connected with a select gate line. The second gate structure is spanned over an area between the second doped region and the third doped region. The second gate structure includes a floating gate and the floating gate is covered by the blocking layer. The erase line is contacted with the blocking layer. The erase line is located above an edge or a corner of the floating gate. | 2021-06-17 |
20210183877 | MEMORY SYSTEM - According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation. | 2021-06-17 |
20210183878 | THREE-DIMENSIONAL MEMORY DEVICE WITH SOURCE STRUCTURE AND METHODS FOR FORMING THE SAME - Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a method for forming a 3D memory device includes the following operations. A cut structure is first formed in a stack structure. The stack structure includes interleaved initial sacrificial layers and initial insulating layers. A patterned cap material layer is formed over the stack structure. The patterned cap material layer includes an opening over the cut structure. Portions of the stack structure and the patterned cap material layer adjacent to the opening are removed to form a slit structure and an initial support structure. The initial support structure divides the slit structure into slit openings. Conductor portions are formed through the plurality of slit openings to form a support structure. A source contact is formed in each slit opening. A connection layer is formed over the source contact in each slit opening and over the support structure. | 2021-06-17 |
20210183879 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a logic circuit disposed on a substrate having a cell region and a peripheral region outside the cell region; a source plate defined over the logic circuit; a slit separating the source plate into a cell source plate in the cell region and a dummy source plate in the peripheral region; and a memory cell array defined on the cell source plate. The dummy source plate is maintained at a constant voltage independent of operations of the memory cell array and the logic circuit. | 2021-06-17 |
20210183880 | HIGH VOLTAGE CMOS WITH CO-PLANAR UPPER GATE SURFACES FOR EMBEDDED NON-VOLATILE MEMORY - The present disclosure relates to an integrated circuit that includes a semiconductor substrate having a periphery region and memory cell region separated by a boundary region. A pair of split gate flash memory cells are disposed on the memory cell region and include a first select gate and a first memory gate. A first gate electrode is disposed over a first gate dielectric layer on the periphery region. A second gate electrode is disposed over a second gate dielectric layer on the periphery region at a position between the boundary region and the first gate electrode. The second dielectric layer is thicker than the first gate dielectric layer. The first select gate and the first memory gate have upper surfaces that are co-planar or level with the upper surface of the second gate electrode. | 2021-06-17 |
20210183881 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a stacked body, memory pillars, first and second insulation layers and an isolation region. The stacked body above a substrate includes conductive layers isolated from each other and stacked along a first direction crossing the substrate surface. The memory pillars extend through the stacked body along the first direction. The first insulation layer is provided above the memory pillars. The isolation region is provided higher than upper surfaces of the memory pillars in the stacked body along the first direction, and isolates the stacked body in a second direction crossing the first direction. The second insulation layer is provided on the first insulation layer and a side wall of the isolation region. | 2021-06-17 |
20210183882 | THREE-DIMENSIONAL MEMORY DEVICE CONTAINING PLURAL WORK FUNCTION WORD LINES AND METHODS OF FORMING THE SAME - A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory stack structures extending through the alternating stack. Each of the memory stack structures contains a memory film and a vertical semiconductor channel. At least one of the electrically conductive layers contains a first conductive material portion having a respective inner sidewall that contacts a respective one of the memory films at a vertical interface, and a second conductive material portion that has a different composition from the first conductive material portion, and contacting the first electrically conductive material portion. The first conductive material portion has a lower work function than the second conductive material portion. | 2021-06-17 |
20210183883 | THREE-DIMENSIONAL MEMORY DEVICE CONTAINING PLURAL WORK FUNCTION WORD LINES AND METHODS OF FORMING THE SAME - A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory stack structures extending through the alternating stack. Each of the memory stack structures contains a memory film and a vertical semiconductor channel. At least one of the electrically conductive layers contains a first conductive material portion having a respective inner sidewall that contacts a respective one of the memory films at a vertical interface, and a second conductive material portion that has a different composition from the first conductive material portion, and contacting the first electrically conductive material portion. The first conductive material portion has a lower work function than the second conductive material portion. | 2021-06-17 |
20210183884 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: an alternating stack of conductive layers and dielectric layers disposed over a substrate; a channel layer disposed in a through portion, penetrating through the alternating stack; a blocking layer disposed in the through portion, surrounding an outer wall of the channel layer; and a continuous etch stop layer disposed in the through portion, surrounding an outer wall of the blocking layer. | 2021-06-17 |
20210183885 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes: a first gate stack including a plurality of first gate electrodes; a second gate stack arranged on the first gate stack and including a plurality of second gate electrodes; and a plurality of channel structures arranged in a plurality of channel holes penetrating the first gate stack and the second gate stack. Each of the channel holes includes a first channel hole portion penetrating the first gate stack and a second channel hole portion penetrating the second gate stack, and a ratio of a second width in the second direction to a first width in the first direction of an upper end of the first channel hole portion is less than a ratio of a fourth width in the second direction to a third width in the first direction of an upper end of the second channel hole portion. | 2021-06-17 |
20210183886 | MEMORY DEVICE BASED ON IGO CHANNEL LAYER AND METHOD OF FABRICATING THE SAME - Disclosed are a memory device based on an IGO channel layer and a method of fabricating the same. More particularly, the memory device according to an embodiment includes multilayers including at least one transition metal; and a channel layer formed adjacent to the multilayers and configured to include an indium gallium oxide (IGO) material. | 2021-06-17 |
20210183887 | THREE DIMENSIONAL MEMORY AND METHODS OF FORMING THE SAME - Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described. | 2021-06-17 |
20210183888 | SEMICONDUCTOR DEVICE - According to one embodiment, the semiconductor body of the first portion includes a first semiconductor part and a second semiconductor part. The first semiconductor part extends in the stacking direction. The second semiconductor part is provided between the first semiconductor part and the first electrode layer, and has an end located closer to the first electrode layer side than the first semiconductor part. The first insulating film of the second portion includes a first insulating part and a second insulating part. The first insulating part extends in the stacking direction. The second insulating part is provided between the first insulating part and the second electrode layer, and has an end located closer to the second electrode layer side than the first insulating part. | 2021-06-17 |
20210183889 | GRID STRUCTURE TO REDUCE DOMAIN SIZE IN FERROELECTRIC MEMORY DEVICE - Various embodiments of the present disclosure are directed towards an integrated chip including a pair of source/drain regions disposed in a substrate. A gate dielectric layer overlies the substrate and is spaced laterally between the pair of source/drain regions. A ferroelectric structure overlies the gate dielectric layer. The ferroelectric structure includes a ferroelectric layer and a grid structure. The ferroelectric layer includes a plurality of segments laterally offset from one another, and the grid structure laterally encloses each segment of the ferroelectric layer. | 2021-06-17 |
20210183890 | METHOD OF FABRICATING VERTICAL MEMORY DEVICE - In a method, a stack structure including a plurality of first interlayer sacrificial layers and a plurality of second interlayer sacrificial layers that are alternately stacked is formed over a substrate. A trench penetrating the stack structure is formed. A channel layer covering a sidewall surface of the trench is formed. The plurality of first interlayer sacrificial layers are selectively removed to form a plurality of first recesses. The plurality of first recesses are filled with a conductive material to form a plurality of channel contact electrode layers. The plurality of second interlayer sacrificial layers are selectively removed to form a plurality of second recesses. A plurality of interfacial insulation layers, a plurality of ferroelectric layers and a plurality of gate electrode layers are formed in the plurality of second recesses. | 2021-06-17 |
20210183891 | ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE - An embodiment of the present disclosure provides an array substrate, a display panel, and a display device, relating to the field of display technology. The array substrate includes a plurality of sub-pixel regions. The sub-pixel regions include at least one white sub-pixel region and a sub-pixel region adjacent to the white sub-pixel region. A signal line is disposed between the white sub-pixel region and the sub-pixel region adjacent thereto. At most a first data line is disposed between the white sub-pixel region and the adjacent sub-pixel region. The first data line is used to provide a data signal to a sub-pixel electrode in the white sub-pixel region. The signal line transmits a signal of a different type than the data signal. | 2021-06-17 |
20210183892 | ARRAY SUBSTRATE AND DISPLAY DEVICE - An array substrate and a display device are provided. The array substrate is provided with a display area and a non-display area, and the array substrate further includes a plurality of thin film transistors, a driving circuit, a plurality of polysilicon resistors, and a plurality of fan-out wires. The thin film transistor array is arranged in the display area, and each thin film transistor is provided with an input end. The driving circuit corresponds to the non-display area, and the driving circuit is provided with an output end. The polysilicon resistors and the fanout wires correspond to the non-display area. Two ends of each polysilicon resistor are respectively connected to the input end of a corresponding thin film transistor and the output end of the driving circuit through a corresponding fanout wire. | 2021-06-17 |
20210183893 | ARRAY SUBSTRATE - An array substrate including a substrate, a plurality of fan-out traces and a plurality of bonding terminals. The substrate includes a display area and a non-display area surrounding the display area. The fan-out traces and the bonding terminals are disposed in the non-display area. The bonding terminals are spaced apart from each other. First ends of the fan-out traces are respectively electrically connected to the bonding terminals. Second ends of the fan-out traces are electrically connected to the display area. The fan-out traces include a plurality of first fan-out traces and a plurality of second fan-out traces. The first fan-out traces are formed by a first metal layer. The second fan-out traces are formed by a second metal layer. An insulating layer is provided between the first metal layer and the second metal layer. The first fan-out traces and the second fan-out traces are partially overlapped. | 2021-06-17 |
20210183894 | DISPLAY PANEL AND METHOD OF FABRICATING SAME - A display panel and a method of fabricating the same are provided. The display panel has an active region and a non-active region. The display panel has a plurality of data lines, wherein a height difference is defined between neighboring data lines in the non-active region. The display panel can reduce an area of the non-active region by switching layers of the data lines in the non-active region. | 2021-06-17 |
20210183895 | ELECTRONIC DEVICE - An electronic device includes a substrate and transistors disposed on the substrate. At least one of the transistors includes a semiconductor layer, a gate insulating layer, a gate electrode, a first electrode, and a second electrode. The gate insulating layer includes first contact holes and second contact holes. The gate electrode is disposed on the gate insulating layer. The first electrode is disposed on the gate electrode, has a first side away from the gate electrode, and contacts the semiconductor layer through the first contact holes. The second electrode is disposed on the gate electrode, has a second side away from the gate electrode, and contacts the semiconductor layer through the second contact holes. The first contact holes have first edges away from the gate electrode. A minimum distance between the first side and the gate electrode is less than a minimum distance between the first edge of one of the first contact holes and the gate electrode. | 2021-06-17 |
20210183896 | ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, AND DISPLAY APPARATUS - An array substrate includes a base, a plurality of thin film transistors, a passivation layer, at least one reflective electrode, and at least one first connecting electrode. The array substrate has a display area. The thin film transistors are disposed in the display area on the base. The passivation layer covers the thin film transistors, and has at least one first via hole in the display area. The reflective electrode is disposed on a surface of the passivation layer facing away from the base, and is disposed in the display area and uncovers the first via hole. The first connecting electrode is disposed on a side of the reflective electrode away from the base. Each first connecting electrode is connected to a corresponding reflective electrode, and is connected to a source or a drain of a corresponding thin film transistor through a corresponding first via hole. | 2021-06-17 |
20210183897 | SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, DISPLAY PANEL, AND DISPLAY APPARATUS - A substrate includes a driving backplane, a plurality of first connecting lines and a plurality of second connecting lines. The driving backplane includes a base substrate, at least one first lead group and at least one second lead group. Each first lead group includes a plurality of first leads, and each second lead group includes a plurality of second leads. A first lead group and a corresponding second lead group is disposed in a peripheral region. The plurality of first connecting lines are disposed on at least one side face of the driving backplane, each first connecting line is electrically connected to at least one first lead. The plurality of second connecting lines are disposed on the at least one side face of the driving backplane, each second connecting line is electrically connected to at least one second lead, and is in contact with a corresponding first connecting line. | 2021-06-17 |
20210183898 | Transistor Array Substrate and Electronic Device Including Same - Provided are a transistor array substrate and an electronic device. A first active layer includes a first area, a second area spaced apart from the first area, and a channel area provided between the first area and the second area. A gate insulating film is disposed on the first active layer. A gate electrode is disposed on the gate insulating film to overlap a portion of the channel area of the first active layer. The gate electrode overlaps a portion of at least one area of the first and second areas of the first active layer. Deteriorations in the channel area are prevented. | 2021-06-17 |
20210183899 | ACTIVE MATRIX SUBSTRATE AND METHOD FOR MANUFACTURING SAME - An active matrix substrate includes a plurality of source bus lines, a lower insulating layer covering the source bus lines, a plurality of gate bus lines formed above the lower insulating layer, and an oxide semiconductor TFT disposed to correspond to each pixel area. The oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, and a gate electrode disposed above the oxide semiconductor layer. The gate electrode is formed in a different layer from the gate bus lines, and is disposed to be separated from another gate electrode disposed in an adjacent pixel area. The gate electrode is covered by an interlayer insulating layer. The gate bus line is disposed on the interlayer insulating layer and in a gate contact hole formed in the interlayer insulating layer, and is connected to the gate electrode in the gate contact hole. | 2021-06-17 |
20210183900 | LIGHT EMITTING DISPLAY APPARATUS - A light emitting display apparatus includes a substrate, a first metal line and a second metal line spaced apart from each other along a first direction on the substrate and disposed along a second direction crossing the first direction, and a subpixel overlapped with at least one of the first metal line and the second metal line. The subpixel includes a first light emission portion between the first metal line and the second metal line, and a second light emission portion overlapped with at least one of the first metal line and the second metal line. | 2021-06-17 |
20210183901 | DISPLAY DEVICE - In a display device, the display device includes a substrate, a first conductive layer, a second conductive layer, a semiconductor layer, an opposite substrate and a display medium layer. The first conductive layer is disposed on the substrate and includes a trace portion extending along a first direction and a protrusive portion extending from the trace portion. The second conductive layer is disposed on the first conductive layer and includes a wiring portion extending along a second direction. The semiconductor layer is disposed on the substrate. When viewed in a third direction perpendicular to the first direction and the second direction, an interface disposes between the trace portion and the protrusive portion, a virtual extending line overlaps the second edge and the interface, and the semiconductor layer extends beyond the virtual extending line. The display medium layer is disposed between the substrate and the opposite substrate. | 2021-06-17 |
20210183902 | THIN FILM TRANSISTOR ARRAY - A thin film transistor array includes column wirings and row wirings formed on an insulating substrate and extending perpendicularly to each other, and pixels formed at crossing points of the column and row wirings. Each of the pixels includes a pixel electrode and a thin film transistor that includes a gate electrode, a source electrode, a drain electrode, and a semiconductor pattern. The source electrode has a linear shape having a constant width in a plan view, the drain electrode includes a U-shaped portion positioned around the source electrode such that a gap is formed between the U-shaped portion and the source electrode in the plan view, the semiconductor pattern connects at least the source electrode and the drain electrode such that a channel region is formed, and the gate electrode overlaps the channel region via a gate insulating film and includes the channel region in the plan view. | 2021-06-17 |
20210183903 | THIN FILM TRANSISTOR ARRAY - A thin film transistor array includes column wirings extending in a first direction, row wirings extending in a second direction, capacitor wirings, and pixels formed in a matrix. Each pixel includes a thin film transistor, a pixel electrode, and a capacitor electrode. The pixels form a rectangular effective region of an M column by N row matrix structure in which N pixels are formed in the first direction and M pixels are formed in the second direction, where M and N are natural numbers, the row wirings each have a length extending across the M pixels formed in the second direction in the effective region, the column wirings each have a length extending across the N/2 pixels formed in the first direction in the effective region, and the capacitor wirings each have a length which extends across the N pixels formed in the first direction in the effective region. | 2021-06-17 |
20210183904 | POLYIMIDE SUBSTRATE AND DISPLAY DEVICE - Embodiments of the disclosure are related to polyimide substrates and display devices, a plurality of intaglio patterns are formed on at least a portion of one surface of a polyimide substrate, a high transmissive filling is disposed inside the intaglio pattern, thus an overall transmittance of the polyimide substrate is enhanced. Furthermore, the filling having a certain range of a coefficient of thermal expansion is disposed in the intaglio pattern to maintain a heat resistance of the polyimide substrate, an element being required a high temperature process could be disposed on the polyimide substrate having an enhanced transmittance. | 2021-06-17 |
20210183905 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - The invention provides an array substrate and a manufacturing method thereof. The array substrate includes a display area and a non-display area. The non-display area has a bonding area and a fan-out area, and the fan-out area is disposed between the display area and the bonding area. The array substrate further includes a thin-film transistor structure layer, including a gate layer and a source-drain electrode layer. A material of the gate layer and the source-drain electrode layer includes at least one of titanium, aluminum, or titanium aluminum alloy. | 2021-06-17 |
20210183906 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A highly reliable semiconductor device having a high on-state current is provided. The semiconductor device includes a first insulator, a second insulator over the first insulator, a first oxide over the first insulator, a second oxide over the first oxide, a first conductor and a second conductor over the second oxide, a third insulator over the first conductor, a fourth insulator over the second conductor, a third oxide over the second oxide, a fifth insulator over the third oxide, a third conductor that is positioned over the fifth insulator and overlaps with the third oxide, a sixth insulator covering the first to fifth insulators, the first oxide, the second oxide, and the first to third conductors, and a seventh insulator over the sixth insulator. | 2021-06-17 |
20210183907 | SEMICONDUCTOR DEVICES - A device comprising a stack of layers defining one or more electronic elements, wherein the stack comprises at least: one or more semiconductor channels; a dielectric; a first conductor pattern defining one or more coupling conductors, wherein the one or more coupling conductors are capacitively coupled to the one or one or more semiconductor channels via the dielectric; a planarisation layer; a second conductor pattern defining one or more routing conductors, wherein the second conductor pattern is in contact with the first conductor pattern via through holes in at least the planarisation layer, and wherein the semiconductor channel regions are at least partly outside the through hole regions. | 2021-06-17 |
20210183908 | CHIP - A chip is provided. The chip includes a flexible substrate, a plurality of thin-film transistors, a redistribution layer, a first power rail layer, and a second power rail layer. The plurality of thin-film transistors are disposed on the flexible substrate. The redistribution layer is disposed above the plurality of thin-film transistors. The first power rail layer is disposed above the redistribution layer. The first power rail layer provides a first voltage to the plurality of thin-film transistors. The second power rail layer is disposed above the first power rail layer. The second power rail layer provides a second voltage to the plurality of thin-film transistors, wherein the second power rail layer is disposed in a grid shape. | 2021-06-17 |
20210183909 | DISPLAY DEVICE - To make the dimension of an electrostatic protection circuit small with the same maintained high in sensitivity. The electrostatic protection circuit is of the configuration that a first diode and a second diode are connected in series, wherein a semiconductor layer owned by each diode is configured to be sandwiched between a gate electrode and a conductive light shielding film. The light shielding film is formed to overlap with the semiconductor layer and has a wider area than the semiconductor layer. This results in having a gate covering the semiconductor layer from an upper side and a back gate covering the semiconductor layer from a lower side, so that the sensitivity can be maintained high irrespective of decreasing the electrostatic protection circuit in dimension. | 2021-06-17 |
20210183910 | FOLDALBE DISPLAY SCREEN AND METHOD FOR MANUFACTURING SAME - The present disclosure provides a foldable display screen and a method for manufacturing same. The foldable display screen includes a substrate; a plurality of inorganic layers disposed on the substrate; a patterned metal layer sandwiched between any two of the inorganic layers; a first through-hole and a second through-hole disposed in the inorganic layers, wherein the first through-hole is disposed on the patterned metal layer, the second through-hole is positioned between two adjacent patterned metal layers, and a footprint of the first through-hole is smaller than a footprint of the patterned metal layer; and a patterned organic layer disposed on the inorganic layers to fill up the first through-hole and the second through-hole. | 2021-06-17 |
20210183911 | DISPLAY PANEL, MANUFACTURING METHOD THEREOF AND DISPLAY MODULE - The present application proposes a display panel, a manufacturing method for the display panel, and a display module. The display panel includes an array substrate. The array substrate includes a substrate and a thin film transistor and a storage capacitor on the substrate. The storage capacitor includes a first electrode on the substrate, a first insulating layer on the first electrode, a second electrode on the first insulating layer, a second insulating layer on the second electrode, and a third electrode on the second insulating layer. An orthogonal projection of the second electrode on the second insulating layer is on the second insulating layer. | 2021-06-17 |
20210183912 | MANUFACTURING METHOD OF TFT ARRAY SUBSTRATE - The invention provides a manufacturing method of the TFT array substrate. Compared to existing 4M process, the invention changes the structural design of the semi-transmissive mask for the photoresist layer for patterning the source/drain metal layer and the semiconductor layer. The edge forms a reduced thickness edge portion, so that the edge of the photoresist layer is thinned, and thereby the width of the photoresist layer is easily reduced in subsequent processes, and the semiconductor layer at the edge of the metal wire structure is easily etched during dry etching, reducing the tailing problem of the active layer at edges of source/drain to achieve finer metal wire structure, and improve optical stability, electrical performance, aperture ratio, reliability, power consumption, and the overall performance of the TFT array substrate. The residual problem of amorphous and heavily doped silicon on source/drain edge in original process is solved or reduced. | 2021-06-17 |
20210183913 | METHOD FOR FABRICATING TFT ARRAY SUBSTRATE - A method of fabricating a thin-film transistor (TFT) array substrate including forming a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming a semiconductor layer on the gate insulating layer, forming an ohmic contact layer on the semiconductor layer, and forming a source electrode and a drain electrode comprising a plurality of metal layer patterns on the ohmic contact layer, in which the semiconductor layer, the ohmic contact layer, the source electrode and the drain electrode are formed through a single mask process, and one of the plurality of metal layer patterns is etched through a polishing process to form the source electrode and the drain electrode. | 2021-06-17 |
20210183914 | DISPLAY APPARATUS COMPRISING THIN FILM TRANSISTOR - A display apparatus comprises a first signal line on a substrate, a second signal line intersecting with the first signal line, a first gate electrode, a first source electrode, a first drain electrode, and a second gate electrode disposed on the same layer as that of the first signal line, a first active layer spaced apart from the first gate electrode and partially overlapped with the first gate electrode, a second active layer spaced apart from the second gate electrode and partially overlapped with the second gate electrode, and a first electrode of a display device connected with the second active layer. | 2021-06-17 |
20210183915 | Optical Sensor with Trench Etched Through Dielectric Over Silicon - In described examples an integrated circuit (IC) has multiple layers of dielectric material overlying at least a portion of a surface of a substrate. A trench is etched through the layers of dielectric material to expose a portion the substrate to form a trench floor, the trench being surrounded by a trench wall formed by the layers of dielectric material. A metal perimeter band surrounds the trench adjacent the trench wall, the perimeter band being embedded in one of the layers of the dielectric material. | 2021-06-17 |
20210183916 | IMAGING ELEMENT, METHOD FOR MANUFACTURING IMAGING ELEMENT, AND ELECTRONIC DEVICE - A photoelectric conversion unit that outputs an image signal according to received light and a bonding pad section are disposed on one surface side of the substrate, and the bonding pad section has at least: a first opening provided to expose a pad electrode at a bottom; and a second opening that is arranged to surround the first opening and that is shallower than the first opening. The surface of a terrace in the bonding pad section is formed such that multiple types of materials are exposed. | 2021-06-17 |
20210183917 | LIGHT DETECTING ELEMENT AND METHOD OF MANUFACTURING SAME - The present technology relates to a light detecting element and a method of manufacturing the same that make it possible to reduce pixel size. The light detecting element includes a plurality of pixels arranged in the form of a matrix. Each of the pixels includes a first semiconductor layer of a first conductivity type formed in an outer peripheral portion in the vicinity of a pixel boundary, and a second semiconductor layer of a second conductivity type opposite from the first conductivity type formed on the inside of the first semiconductor layer as viewed in plan. A high field region formed by the first semiconductor layer and the second semiconductor layer when a reverse bias voltage is applied is configured to be formed in a depth direction of a substrate. The present technology is, for example, applicable to a photon counter or the like. | 2021-06-17 |
20210183918 | TRENCH-BASED PHOTODIODES - Structures including a photodiode and methods of fabricating such structures. A trench extends from a top surface of a substrate to a depth into the substrate. The photodiode includes an active layer positioned in the trench. Trench isolation regions, which are located in the substrate, are arranged to surround the trench. A portion of the substrate is positioned in a surrounding relationship about the active layer and between the active layer and the trench isolation regions. | 2021-06-17 |
20210183919 | IMAGE SENSING DEVICE - An image sensing device is disclosed. The image sensing device includes a semiconductor substrate configured to generate charge carriers in response to light incident, a plurality of control regions supported by the semiconductor substrate and configured to cause majority carrier currents in the semiconductor substrate to control movement of minority carriers, and a plurality of detection regions formed adjacent to the control regions and configured to capture the minority carriers moving in the semiconductor substrate. Each of the control regions includes an upper portion, a lower portion, and a middle portion disposed between the upper portion and the lower portion. The middle portion has a smaller horizontal cross-sectional profile than each of the upper portion and the lower portion. | 2021-06-17 |
20210183920 | IMAGE SENSOR - An image sensor includes a semiconductor substrate having a first surface and a second surface with a pixel region having photoelectric conversion regions, a gate electrode disposed on the pixel region and adjacent to the first surface, a first isolation structure extending from the first surface toward the second surface, the first isolation structure comprising a first pixel isolation pattern enclosing the pixel region, and a first inner isolation pattern spaced apart from the first pixel isolation pattern and positioned between the photoelectric conversion regions, and a second isolation structure extending from the second surface toward the first surface with a top surface vertically spaced apart from at least a portion of a bottom surface of the first isolation structure. The bottom surface of the first isolation structure is closer to the second surface of the semiconductor substrate than to the first surface thereof. | 2021-06-17 |
20210183921 | IMAGE SENSOR HAVING IMPROVED FULL WELL CAPACITY AND RELATED METHOD OF FORMATION - In some embodiments, a method is provided. The method includes forming a plurality of trenches in a semiconductor substrate, where the trenches extend into the semiconductor substrate from a back-side of the semiconductor substrate. An epitaxial layer comprising a dopant is formed on lower surfaces of the trenches, sidewalls of the trenches, and the back-side of the semiconductor substrate, where the dopant has a first doping type. The dopant is driven into the semiconductor substrate to form a first doped region having the first doping type along the epitaxial layer, where the first doped region separates a second doped region having a second doping type opposite the first doping type from the sidewalls of the trenches and from the back-side of the semiconductor substrate. A dielectric layer is formed over the back-side of the semiconductor substrate, where the dielectric layer fill the trenches to form back-side deep trench isolation structures. | 2021-06-17 |
20210183922 | IMAGE SENSOR WITH IMPROVED NEAR-INFRARED (NIR) RADIATION PHASE-DETECTION AUTOFOCUS (PDAF) PERFORMANCE - Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a first phase detection autofocus (PDAF) photodetector and a second PDAF photodetector in a substrate. A first electromagnetic radiation (EMR) diffuser is disposed along a back-side of the substrate and within a perimeter of the first PDAF photodetector. The first EMR diffuser is spaced a first distance from a first side of the first PDAF photodetector and a second distance less than the first distance from a second side of the first PDAF photodetector. A second EMR diffuser is disposed along the back-side of the substrate and within a perimeter of the second PDAF photodetector. The second EMR diffuser is spaced a third distance from a first side of the second PDAF photodetector and a fourth distance less than the third distance from a second side of the second PDAF photodetector. | 2021-06-17 |
20210183923 | GLOBAL SHUTTER PIXEL CIRCUIT AND METHOD FOR COMPUTER VISION APPLICATIONS - An image sensor device includes a plurality of pixel cells arranged in a pixel array, a control circuit for controlling an exposure phase and a sampling phase of the image sensor device. Each of the plurality of pixel cells includes a photodiode, a storage diode, and a floating diffusion region. The control circuit is configured to activate the photodiode in a plurality of time windows to sense light reflected from a target as a result of a corresponding plurality of emitted light pulses, with a pre-determined delay time between each time window and a corresponding emitted light pulse. The photodiode can be activated using a plurality of bias voltage pulses or a plurality of global shutter signal pulses. | 2021-06-17 |
20210183924 | LIGHT-RECEIVING DEVICE, IMAGING DEVICE, AND ELECTRONIC APPARATUS - A light-receiving device includes at least one pixel. The at least one pixel includes a first electrode; a second electrode; and a photoelectric conversion layer between the first electrode and the second electrode. The photoelectric conversion layer is configured to convert incident infrared light into electric charge. The photoelectric conversion layer has a first section and a second section. The first section is closer to the first electrode than the second section, and the second section is closer to the second electrode than the first section. At least one of the first section and the second section have a plurality of surfaces. | 2021-06-17 |
20210183925 | SOLID-STATE IMAGING DEVICE AND CAMERA SYSTEM - The present invention provides a solid-state imaging device and a camera system capable of recording a still image without using a recording medium. Each pixel P of an image sensor is provided with a photodiode, a transfer transistor, a reset transistor, and an amplifying transistor, as well as a memory element that has functions of a select transistor. The memory element has a structure integrating a drain side select transistor, a source side select transistor, and a memory transistor. By applying a program voltage to a memory gate electrode as a gate voltage, the memory transistor stores charge of an amount corresponding to an amount of light received by the photodiode in a charge storage layer. | 2021-06-17 |
20210183926 | MULTI-GATE LATERAL OVERFLOW INTEGRATION CAPACITOR SENSOR - A pixel circuit includes a photodiode, a floating diffusion, and a conduction gate channel of a multi-gate transfer block disposed in a semiconductor material layer. The multi-gate transfer block is coupled to the photodiode, the floating diffusion, and an overflow capacitor. The multi-gate transfer block also includes first, second, and third gates that are disposed proximate to the single conduction gate channel region. The conduction gate channel is a single region shared among the first, second, and third gates. Overflow image charge generated in the photodiode leaks from the photodiode into the conduction gate channel to the overflow capacitor in response to the first gate, which is coupled between the photodiode and the conduction gate channel, receiving a first gate OFF signal and the second gate, which is coupled between the conduction gate channel and the overflow capacitor, receiving a second gate ON signal. | 2021-06-17 |
20210183927 | IMAGE SENSOR, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - An image sensor that includes a sensor substrate provided with a sensor surface on which a photodiode is arranged in a planar manner, a sealing resin applied to a side of the sensor surface of the sensor substrate, sealing glass bonded to the sensor substrate via the sealing resin, and a reinforcing resin made of a resin material having higher rigidity than the sealing resin and formed on an outer periphery of the sealing resin to bond the sensor substrate and the sealing glass. The sealing resin is formed to have a smaller area than each of the sensor substrate and the sealing glass, so that the reinforcing resin is formed to fill a gap provided on the outer periphery of the sealing resin, the sensor substrate and the sealing glass facing each other through the gap. | 2021-06-17 |
20210183928 | IMAGING ELEMENT, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPLIANCE - The present technology relates to an imaging element, a method of manufacturing the same, and an electronic appliance capable of reducing false signal output caused by reflected light of incident light. An imaging element includes: a semiconductor substrate including a photoelectric conversion unit for each pixel, the photoelectric conversion unit photoelectrically converting incident light; a color filter layer that is formed on the semiconductor substrate and that passes the incident light of a predetermined wavelength; a light-shielding wall that is formed at a pixel boundary on the semiconductor substrate so as to have a height greater than a height of the color filter layer; and a protective substrate that is disposed via a seal resin and that protects an upper-surface side of the color filter layer. The present technology can be applied to, for example, an imaging element having a CSP structure and the like. | 2021-06-17 |
20210183929 | IMAGE SENSING DEVICE - The image sensing device includes a pixel array that includes a plurality of unit pixels for converting incident light into an electrical signal in response to the incident light is arranged. The pixel array includes a plurality of color filters placed relative to the plurality of unit pixels and configured to filter the incident light to transmit light at predetermined wavelengths to be received by the plurality of unit pixels, a plurality of grid structures disposed between the plurality of color filters to prevent optical crosstalk from occurring between adjacent color filters, and a lens layer disposed over the color filters and the grid structure to direct the incident light to converge upon the plurality of color filters. | 2021-06-17 |
20210183930 | SOLID-STATE IMAGING DEVICE, DISTANCE MEASUREMENT DEVICE, AND MANUFACTURING METHOD - The present technology relates to a solid-state imaging device, a distance measurement device, and a manufacturing method that make it possible to improve condensing efficiency. Provided is a solid-state imaging device including: a pixel unit in which a plurality of pixels each having a light detection unit are arranged; a micro lens formed on a light incident surface side of the light detection unit for each of the pixels; and a light-shielding unit that is formed around the micro lens and shields light, wherein the micro lens is formed inside an opening part provided in the light-shielding part. The present technology is applicable to, for example, CMOS image sensors. | 2021-06-17 |
20210183931 | SOLID-STATE IMAGING ELEMENT, MANUFACTURING METHOD, AND ELECTRONIC APPARATUS - The present disclosure relates to a solid-state imaging element, a manufacturing method, and an electronic apparatus which are capable of further improving a light-blocking effect. The solid-state imaging element having a laminated structure in which a memory substrate, a logic substrate, and a sensor substrate are laminated includes: a through electrode that connects the memory substrate and the sensor substrate in a manner passing through a semiconductor layer of the logic substrate; a light-blocking metal film arranged in a wiring layer included in the logic substrate and provided on the sensor substrate side, and the light-blocking metal film having an opening opened so as to allow the through electrode to pass through; and a contact electrode formed on a bonded surface between the logic substrate and the sensor substrate and used to connect the through electrode to the sensor substrate side. The present technology is applicable to, for example, a laminated solid-state imaging element in which three layers of substrates are laminated. | 2021-06-17 |