24th week of 2022 patent applcation highlights part 70 |
Patent application number | Title | Published |
20220190110 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - The HEMT includes a channel layer, a barrier layer, a drain, and a gate conductor. The barrier layer is disposed on the channel layer. The drain is disposed on the barrier layer. The gate conductor is disposed on the barrier layer. The channel layer includes a doped semiconductor structure overlapping with a top surface of the channel layer and having a bottom-most border that is located over a bottom-most surface of the channel layer and is spaced apart from the bottom-most surface of the channel layer. The doped semiconductor structure is located between the drain and the gate conductor. | 2022-06-16 |
20220190111 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - The HEMT includes a channel layer, a barrier layer, a drain, and a gate conductor. The barrier layer is disposed on the channel layer. The drain is disposed on the barrier layer. The gate conductor is disposed on the barrier layer. The barrier layer comprises a doped semiconductor region extending from a top surface to a bottom surface of the barrier layer and located between the drain and the gate conductor. | 2022-06-16 |
20220190112 | SEMICONDUCTOR DEVICE - A semiconductor device including a substrate including an active pattern; a gate electrode crossing the active pattern; a source/drain pattern adjacent to one side of the gate electrode and on an upper portion of the active pattern; an active contact electrically connected to the source/drain pattern; and a silicide layer between the source/drain pattern and the active contact, the source/drain pattern including a body part including a plurality of semiconductor patterns; and a capping pattern on the body part, the body part has a first facet, a second facet on the first facet, and a corner edge defined where the first facet meets the second facet, the corner edge extending parallel to the substrate, the capping pattern covers the second facet of the body part and exposes the corner edge, and the silicide layer covers a top surface of the body part and a top surface of the capping pattern. | 2022-06-16 |
20220190113 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A compound semiconductor layer in a semiconductor device includes a drift region of a first conductivity type, a JFET region of the first conductivity type disposed above the drift region, a body region of a second conductivity type disposed above the drift region and adjacent to the JFET region, and a JFET embedded region of the second conductivity type or i-type disposed in the JFET region. The JFET region has a bottom surface portion adjacent to the drift region, a side surface portion adjacent to the body region, and an inside portion adjacent to the JFET embedded region, and further has a high concentration portion at the bottom surface portion and the side surface portion. The high concentration portion has an impurity concentration higher than an impurity concentration of the inside portion. | 2022-06-16 |
20220190114 | VERTICAL MOSFET HAVING TRENCH GATE STRUCTURE CONTAINING SILICON CARBIDE - A vertical metal oxide semiconductor field effect transistor, including a starting substrate of a first conductivity type, a second first-conductivity-type epitaxial layer provided on a first surface of the starting substrate via a first first-conductivity-type epitaxial layer, a first semiconductor region of the first conductivity type provided as a portion of the second first-conductivity-type epitaxial layer, a second-conductivity-type epitaxial layer forming a pn junction interface with the second first-conductivity-type epitaxial layer and supplying a minority carrier to the second first-conductivity-type epitaxial layer, a plurality of second semiconductor regions of the first conductivity type selectively provided in the second-conductivity-type epitaxial layer, a plurality of trenches penetrating through the second semiconductor regions and the second-conductivity-type epitaxial layer, and a plurality of gate electrodes provided in the trenches via gate insulating films. A lifetime of the minority carrier of the first semiconductor region is shorter than that of the rest of the second first-conductivity-type epitaxial layer. | 2022-06-16 |
20220190115 | METHOD AND SYSTEM OF OPERATING A BI-DIRECTIONAL DOUBLE-BASE BIPOLAR JUNCTION TRANSISTOR (B-TRAN) - Operating a bi-directional double-base bipolar junction transistor (B-TRAN). One example is a method comprising: conducting a first load current from an upper terminal of the power module to an upper collector-emitter of the transistor, through the transistor, and from a lower collector-emitter to a lower terminal of the power module; and then responsive assertion of a first interrupt signal, interrupting the first load current from the lower collector-emitter to the lower terminal by opening a lower-main FET and thereby commutating a first shutoff current through a lower base of the transistor to the lower terminal; and blocking current from the upper terminal to the lower terminal by the transistor. | 2022-06-16 |
20220190116 | INTEGRATED CIRCUIT (IC) STRUCTURE WITH BODY CONTACT TO WELL WITH MULTIPLE DIODE JUNCTIONS - The disclosure provides an integrated circuit (IC) structure with a body contact to a well with multiple diode junctions. A first doped well is in a substrate. A transistor is on the first doped well. A trench isolation (TI) is adjacent a portion of the first doped well. A second doped well within the substrate has a bottom surface beneath a bottom surface of the first doped well. A sidewall of the TI horizontally abuts the second doped well. A first diode junction is between the second doped well and the first doped well. A second diode junction is between the second doped well and the substrate. A body contact is on the second doped well. | 2022-06-16 |
20220190117 | SILICON CARBIDE SEMICONDUCTOR DEVICE - The invention provides a silicon carbide semiconductor device, in particular to a monolithically integrated trench Metal-Oxide-Semiconductor Field-Effect Transistor with segmentally surrounded trench Schottky diode, which comprises a semiconductor substrate, a trench Metal-Oxide-Semiconductor Field-Effect Transistor and a trench Schottky diode. The trench Schottky diode has a perpendicularly disposed trench extending in a first horizontal direction, a metal electrode filled into the trench, and a plurality of doped regions disposed segmentally and extending in a second horizontal direction around the trench. The first horizontal direction is substantially orthogonal to the second horizontal direction, a side wall and a bottom wall of the metal electrode in the trench forms a Schottky junction, and the current flowing from the metal electrode is restricted between adjacent doped regions. | 2022-06-16 |
20220190118 | SEMICONDUCTOR DEVICE - A semiconductor device of embodiments includes a first gate electrode, a second gate electrode, a third gate electrode extending in a first direction, and a gate wiring line extending in a second direction crossing the first direction and to which the first to the third gate electrodes are connected. Assuming distance between the first and the second gate electrode in the second direction in a first region is S1, distance between the first and the second gate electrode in the second direction in a second region closer to the gate wiring line than the first region is S2, distance between the second and the third gate electrode in the second direction in the first region is S3, and distance between the second and the third gate electrode in the second direction in the second region is S4, following Expressions are satisfied, | 2022-06-16 |
20220190119 | NITRIDE SEMICONDUCTOR, WAFER, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE NITRIDE SEMICONDUCTOR - According to one embodiment, a nitride semiconductor includes a nitride member. The nitride member includes a first nitride region including Al | 2022-06-16 |
20220190120 | Alignment-Tolerant Gallium Oxide Device - A gallium oxide field effect transistor that is built on a base layer. A doped gallium oxide channel layer is disposed on top of the base layer, and a dielectric barrier layer is disposed on top of the gallium oxide channel layer. Source contacts and drain contacts are disposed on top of the dielectric barrier layer, with one each of the drain contacts disposed in an interdigitated manner between one each of the source contacts. The interdigitated source contacts and drain contacts thereby define channels between them, where alternating ones of the channels are defined as odd channels, with even channels disposed therebetween. Gate contacts are disposed on top of the dielectric barrier layer in only one of the odd channels and the even channels. | 2022-06-16 |
20220190121 | TRANSISTOR CHANNEL MATERIALS - Disclosed herein are transistor channel materials, and related methods and devices. For example, in some embodiments, a transistor may include a channel material including a semiconductor material having a first conductivity type, and the channel material may further include a dopant including (1) an insulating material and/or (2) a material having a second conductivity type opposite to the first conductivity type. | 2022-06-16 |
20220190122 | MULTI-LAYER DIFFUSION BARRIER AND METHOD OF MAKING THE SAME - A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide. | 2022-06-16 |
20220190123 | Miniature Field Plate T-Gate and Method of Fabricating the Same - A method of fabricating a gate with a mini field plate includes forming a dielectric passivation layer over an epitaxy layer on a substrate, coating the dielectric passivation layer with a first resist layer, etching the first resist layer and the dielectric passivation layer to form a first opening in the dielectric passivation layer, removing the first resist layer; and forming a tri-layer gate having a gate foot in the first opening, the gate foot having a first width, a gate neck extending from the gate foot and extending for a length over the dielectric passivation layer on both sides of the first opening, the gate neck having a second width wider than the first width of the gate foot, and a gate head extending from the gate neck, the gate head having a third width wider than the second width of the gate neck. | 2022-06-16 |
20220190124 | POWER AMPLIFIER - A power amplifier that includes a substrate, and an emitter layer, a base layer, and a collector layer laminated in this order on a major surface of the substrate includes an electrical insulator provided adjacent to the emitter layer, an emitter electrode provided between the substrate and both the emitter layer and the electrical insulator, a base electrode electrically connected to the base layer, and a collector electrode electrically connected to the collector layer. The emitter electrode, the electrical insulator, and the base layer are provided between the substrate and the base electrode in a direction perpendicular to the major surface of the substrate. | 2022-06-16 |
20220190125 | VFET CONTACT FORMATION - An embodiment of the invention may include a Vertical Field Effect Transistor (VFET) structure, and method of making that structure, having a first VFET and a second VFET. The first VFET may include a single liner between a first source/drain epi and a contact. The second VFET may include two liners between a second source/drain epi and a contact. This may enable proper contact liner matching for differing VFET devices. | 2022-06-16 |
20220190126 | SEMICONDUCTOR DEVICE WITH A CROSSING REGION - A semiconductor device includes a semiconductor substrate, a first current-carrying electrode, a second current-carrying electrode, a first control electrode disposed between the first current-carrying electrode and the second current-carrying electrode, a third current-carrying electrode electrically coupled to the first current-carrying electrode, and a fourth current-carrying electrode adjacent the third current-carrying electrode. The third current-carrying electrode and the fourth current-carrying electrode are configured to support current flow from the third current-carrying electrode to the fourth current-carrying electrode parallel to a second direction. The fourth current-carrying element is electrically coupled to the second current-carrying electrode and a second control electrode. The second control electrode is electrically coupled to the first control electrode. A first crossing region is electrically coupled to the first control electrode and a second crossing region is electrically coupled to the fourth current-carrying electrode, wherein the second crossing region crosses a portion of the first crossing region. | 2022-06-16 |
20220190127 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided. The semiconductor structure includes a gate structure, a source/drain structure, a barrier layer, and a glue layer. The gate structure is over a fin structure. The source/drain structure is in the fin structure and adjacent to the gate structure. The barrier layer is over the source/drain structure. The glue layer is adjacent to the barrier layer. The glue layer has an extending portion in direct contact with the gate structure. | 2022-06-16 |
20220190128 | CONTACT OVER ACTIVE GATE STRUCTURES WITH TAPERED GATE OR TRENCH CONTACT FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION - Contact over active gate (COAG) structures with a tapered gate or trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, wherein individual ones of the plurality gate of structures have thereon a conductive cap between sidewall spacers. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, wherein individual ones of the plurality of conductive trench contact structures have thereon a conductive cap between sidewall spacers. A conductive structure is in direct contact with the conductive cap and sidewall spacers on one of the plurality of gate structures or with the conductive cap and sidewall spacers on one of the plurality of conductive trench contact structures. | 2022-06-16 |
20220190129 | TRANSISTOR ARRANGEMENTS WITH STACKED TRENCH CONTACTS AND GATE STRAPS - Disclosed herein are transistor arrangements with trench contacts that have two parts—a first trench contact and a second trench contact—stacked over one another. Such transistor arrangements may be fabricated by forming a first trench contact over a source or drain contact of a transistor, recessing the first trench contact, forming the second trench contact over the first trench contact, and, finally, forming a gate contact that is electrically isolated from, while being self-aligned to, the second trench contact. Such a fabrication process may provide improvements in terms of increased edge placement error margin, cost-efficiency, and device performance, compared to conventional approaches to forming trench and gate contacts. The conductive material of the first trench contact may also be deposited over the gate electrodes of transistors, forming a gate strap, to advantageously reduce gate resistance. | 2022-06-16 |
20220190130 | SEMICONDUCTOR DEVICE, INVERTER CIRCUIT, DRIVE DEVICE, VEHICLE, AND ELEVATOR - A semiconductor device according to an embodiment includes: a silicon carbide layer having a first plane parallel to a first direction and a second direction orthogonal to the first direction, and a second plane facing the first plane, the silicon carbide layer including a first trench and a second trench extending in the first direction; a gate electrode in the first trench and the second trench; a gate insulating layer; a gate wiring extending in the second direction, intersecting with the first trench and the second trench, connected to the gate electrode; a first electrode; a second electrode; and an interlayer insulating layer provided between the gate electrode and the first electrode. Neither the gate electrode nor the gate wiring is present between an end of the first trench in the first direction and the interlayer insulating layer. | 2022-06-16 |
20220190131 | NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY SYSTEM INCLUDING THE SAME - A nonvolatile memory device includes a peripheral logic structure including a peripheral circuit on a substrate, a horizontal semiconductor layer extending along an upper surface of the peripheral logic structure, stacked structures arranged in a first direction on the horizontal semiconductor layer and including interlayer insulating films and conductive films alternately stacked in a direction perpendicular to the substrate, a first opening disposed between the stacked structures and included in the horizontal semiconductor layer to expose a part of the peripheral logic structure and a second opening arranged in a second direction, which differs from the first direction, from the first opening, included in the horizontal semiconductor layer, and disposed adjacent to the first opening. The peripheral logic structure includes a control transistor overlapping the second opening in a plan view and controlling operation of the plurality of stacked structures. | 2022-06-16 |
20220190132 | SEMICONDUCTOR DEVICE - A semiconductor device includes a gate stack including a gate insulating layer and a gate electrode on the gate insulating layer. The gate insulating layer includes a first dielectric layer and a second dielectric layer on the first dielectric layer, and a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer. The semiconductor device also includes a first spacer on a side surface of the gate stack, and a second spacer on the first spacer, wherein the second spacer includes a protruding portion extending from a level lower than a lower surface of the first spacer towards the first dielectric layer, and a dielectric constant of the second spacer is greater than the dielectric constant of the first dielectric layer and less than a dielectric constant of the first spacer. | 2022-06-16 |
20220190133 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a substrate and a gate structure. The substrate includes a source region and a drain region. The source region is located in a first area of the substrate. The drain region is located in a second area of the substrate. The gate structure includes a first gate region and a second gate region. The first gate region is disposed above the first area of the substrate or disposed above the second area of the substrate. The second gate region is disposed above a third area of the substrate. A second height of the second gate region is higher than a first height of the first gate region. | 2022-06-16 |
20220190134 | SEMICONDUCTOR DEVICE - A semiconductor device includes an active pattern including a lower pattern and a plurality of sheet patterns; a gate structure disposed on the lower pattern and surrounding the plurality of sheet patterns; and a source/drain pattern filling a source/drain recess formed on one side of the gate structure. The source/drain pattern includes a first semiconductor pattern extending along the source/drain recess and contacting the lower pattern, a second and third semiconductor patterns sequentially disposed on the first semiconductor pattern, a lower surface of the third semiconductor pattern is disposed below a lower surface of a lowermost sheet pattern, a side surface of the third semiconductor pattern includes a planar portion, and a thickness of the second semiconductor pattern on the lower surface of the third semiconductor pattern is different from a thickness of the second semiconductor pattern on the planar portion of the side surface of the third semiconductor pattern. | 2022-06-16 |
20220190135 | LATERAL GATE MATERIAL ARRANGEMENTS FOR QUANTUM DOT DEVICES - Disclosed herein are lateral gate material arrangements for quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; and a gate above the quantum well stack, wherein the gate includes a gate electrode, the gate electrode includes a first material proximate to side faces of the gate and a second material proximate to a center of the gate, and the first material has a different material composition than the second material. | 2022-06-16 |
20220190136 | SEMICONDUCTOR DEVICES - Semiconductor devices and methods of forming the same are provided. The semiconductor devices may include a substrate, a pair of semiconductor patterns adjacent to each other on the substrate, a gate electrode on the pair of semiconductor patterns, a source/drain pattern connected to the pair of semiconductor patterns, and a ferroelectric pattern on surfaces of the pair of semiconductor patterns. The surfaces of the pair of semiconductor patterns may face each other, and the ferroelectric pattern may define a first space between the pair of semiconductor patterns. The gate electrode may include a work function metal pattern that is in the first space. | 2022-06-16 |
20220190137 | SPACER STRUCTURE FOR SEMICONDUCTOR DEVICE - The present disclosure describes an inner spacer structure for a semiconductor device and a method for forming the same. The method for forming the inner spacer structure in the semiconductor device can include forming a vertical structure over a substrate, forming a gate structure over a portion of the vertical structure, exposing sidewalls of the portion of the vertical structure, forming multiple spacers over the sidewalls of the portion of the vertical structure, and forming a void in each of the multiple spacers. | 2022-06-16 |
20220190138 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING THE SAME - Semiconductor structure and fabrication method are provided. The semiconductor structure includes a substrate, including a first region and a second region; a plurality of fins, formed on the first region of the substrate; a first isolation structure, formed on the first region between adjacent fins and on the second region of the substrate; a second isolation structure, formed in each fin and in the first isolation structure, over the first region of the substrate; and a power rail, formed in the isolation structure and partially in the substrate of the second region. | 2022-06-16 |
20220190139 | METHOD FOR FORMING SEMICONDUCTOR STRUCTURE - A method for forming a semiconductor structure includes forming a gate structure over a substrate. The method also includes forming a spacer on a sidewall of the gate structure. The method also includes forming a source/drain recess beside the spacer. The method also includes treating the source/drain recess and partially removing the spacers in a first cleaning process. The method also includes treating the source/drain recess with a plasma process after performing the first cleaning process. The method also includes treating the source/drain recess in a second cleaning process after treating the source/drain recess with the plasma process. The method also includes forming a source/drain structure in the source/drain recess after performing the second cleaning process. | 2022-06-16 |
20220190140 | BIPOLAR TRANSISTOR - A bipolar transistor includes a collector. The collector is formed by: a first portion of the collector which extends under an insulating trench, and a second portion of the collector which crosses through the insulating trench. The first and second portions of the collector are in physical contact. | 2022-06-16 |
20220190141 | ION IMPLANTATION TO FORM STEP-OXIDE TRENCH MOSFET - Disclosed herein are methods for forming MOSFETs. In some embodiments, a method may include providing a device structure including a plurality of trenches, forming a gate spacer layer over the device structure, and removing the gate spacer layer from a top surface of the device structure and from a first section of each of the plurality of trenches, wherein a portion of the gate spacer layer remains along a second section of each of the plurality of trenches. The method may further include forming a gate oxide layer along the first section of each of the plurality of trenches and along the portion of the gate spacer layer. | 2022-06-16 |
20220190142 | METHOD OF MANUFACTURING TRANSISTOR - A method of manufacturing transistor may include forming an active layer on a base substrate, forming a sacrificial layer on the active layer, doping a first dopant ion in the active layer through a first ion implantation process, removing the sacrificial layer, forming a gate insulating layer; and forming a gate electrode on the gate insulating layer. | 2022-06-16 |
20220190143 | SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF - A semiconductor structure and a forming method thereof are provided. In one form, a forming method includes: providing a base, including a device region and a zero mark region; forming a zero mark trench inside the base in the zero mark region; filling the zero mark trench, to form a dielectric layer; forming a fin mask material layer covering the base and the dielectric layer; forming a mandrel layer on the fin mask material layer above the dielectric layer and the base in the device region, where the mandrel layer covers a top portion of the dielectric layer; forming a mask spacer on a side wall of the mandrel layer; removing the mandrel layer; etching the fin mask material layer by using the mask spacer as a mask after the mandrel layer is removed, to form a fin mask layer; and etching a partial thickness of the base using the fin mask layer as a mask, where the remaining base after etching is used as a substrate, and a protrusion located over the substrate in the device region is used as a fin, and etching a partial thickness of the dielectric layer during the etching of the base. In the present disclosure, after a fin is formed by filling a zero mark trench with a dielectric layer, a probability that a residue defect or a peeling defect occurs is relatively low. | 2022-06-16 |
20220190144 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - Present disclosure provides a method for forming a semiconductor structure, including forming a dielectric layer over a semiconductor substrate, patterning an insulator stripe over the semiconductor substrate, including forming an insulator layer over the semiconductor substrate and at a bottom of the insulator stripe, depositing a semiconductor capping layer continuously over the insulator stripe, wherein the semiconductor capping layer includes crystalline materials, wherein the semiconductor capping layer is free from being in direct contact with the semiconductor substrate, and cutting off the semiconductor capping layer between the insulator stripes, forming a gate, wherein the gate is in direct contact with the semiconductor capping layer, a first portion of the semiconductor capping layer covered by the gate is configured as a channel structure, and forming a conductible region at a portion of the insulator stripe not covered by the gate stripe by a regrowth operation. | 2022-06-16 |
20220190145 | HETEROJUNCTION BIPOLAR TRANSISTORS WITH UNDERCUT EXTRINSIC BASE REGIONS - Device structures and fabrication methods for heterojunction bipolar transistors. Trench isolation regions are positioned in a semiconductor substrate to define active regions. A base layer includes first sections that are respectively positioned over the active regions and second sections that are respectively positioned over the trench isolation regions. Emitter fingers are respectively positioned on the first sections of the base layer. The first sections of the base layer include single-crystal semiconductor material, and the second sections of the base layer include polycrystalline semiconductor material. The second sections of the base layer are spaced in a vertical direction from the trench isolation regions to define a first cavity that extends about a perimeter of the base layer and second cavities that are connected to the first cavity. | 2022-06-16 |
20220190146 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first contact layer connected to a lower portion of a first trench contact portion and a second contact layer connected to a lower portion of a second trench contact portion. The distance between a first side portion of a first trench and the first trench contact portion is larger than that between a second side portion of the first trench and the second trench contact portion in a plan view, and the first contact layer is separated from the first side portion and the second contact layer is connected to the second side portion in a cross section. With this structure, it is possible to provide a technique for achieving an appropriate channel region. | 2022-06-16 |
20220190147 | POWER SEMICONDUCTOR DEVICE AND POWER SEMICONDUCTOR CHIP - A power semiconductor device includes a semiconductor layer, first trenches recessed into the semiconductor layer from a surface of the semiconductor layer, a drift region, having a first conductivity type, disposed in the semiconductor layer to extend from a lower side the first trenches to between the first trenches such that a vertical charge transport path is provided, a well region disposed in the semiconductor layer on the drift region between the first trenches and having a second conductivity type, an emitter region disposed on the well region and having the first conductivity type, a floating electrode layer disposed in each of the first trenches, a second trench extending through the well region to be in contact with the drift region, and a gate electrode layer disposed in the second trench. | 2022-06-16 |
20220190148 | P TYPE GALLIUM NITRIDE CONFORMAL EPITAXIAL STRUCTURE OVER THICK BUFFER LAYER - A semiconductor device includes a GaN FET on a silicon substrate and a buffer layer of III-N semiconductor material, with a columnar region, a transition region surrounding the columnar region, and an inter-columnar region around the transition region. The columnar region is higher than the inter-columnar region. The GaN FET includes a gate of III-N semiconductor material with a thickness greater than twice the vertical range of the top surface of the buffer layer in the columnar region. A difference between the gate thickness over the columnar region and over the transition region is less than half of the vertical range of the top surface of the buffer layer in the columnar surface. The semiconductor device may be formed by forming a gate layer of III-N semiconductor material over the barrier layer by a gate MOVPE process using a carrier gas that includes zero to 40 percent hydrogen gas. | 2022-06-16 |
20220190149 | HEMT AND METHOD OF FABRICATING THE SAME - An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from the composition of the second III-V compound layer. A third III-V compound layer is disposed on the second III-V compound layer. The first III-V compound layer and the third III-V compound layer are composed of the same group III-V elements. The third III-V compound layer includes a body and numerous finger parts. Each of the finger parts is connected to the body. All finger parts are parallel to each other and do not contact each other. A source electrode, a drain electrode and a gate electrode are disposed on the first III-V compound layer. | 2022-06-16 |
20220190150 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes first, second, third electrodes, a semiconductor member, and a first compound member. The third electrode is between the first and second electrodes in a first direction from the first to second electrodes. The semiconductor member includes first and second semiconductor regions. The first semiconductor region includes first, second, third, fourth, and fifth partial regions. A second direction from the first partial region to the first electrode crosses the first direction. The fourth partial region is between the first and third partial regions in the first direction. The fifth partial region is between the third and second partial regions in the first direction. The second semiconductor region includes first and second semiconductor portions. The first compound member includes first, second and third compound regions. | 2022-06-16 |
20220190151 | SEMICONDUCTOR DEVICE AND PRODUCING METHOD THEREOF - A semiconductor device is provided. In particular, a semiconductor device is disclosed as including an electron transit layer; an electron supply layer disposed on or above the electron transit layer, the electron supply layer inducing a two-dimensional electron gas in the electron transit layer; a source electrode disposed on or above the electron supply layer; a drain electrode disposed on or above the electron supply layer; a gate electrode between the source electrode and the drain electrode; and an insulating film that is disposed in a region between the gate electrode and the drain electrode, and the region being closer to the gate electrode than to the drain electrode. The insulating film includes a nitrosyl group. | 2022-06-16 |
20220190152 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a substrate; a channel layer constituted of a single nitride semiconductor on the substrate; a first barrier layer which is a nitride semiconductor on a part of an upper surface of the channel layer and having a band gap larger than that of the channel layer; a gate layer which is a nitride semiconductor on and in contact with the first barrier layer; a second barrier layer which is a nitride semiconductor in contact with the first barrier layer in an area where the gate layer is not disposed above the channel layer, and having a band gap larger than that of the channel layer and having a thickness or a band gap independent from the first barrier layer; a gate electrode on the gate layer; and a source electrode and a drain electrode spaced apart from the gate layer and on the second barrier layer. | 2022-06-16 |
20220190153 | METAL GATE STRUCTURES OF SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor device includes forming first and second nanostructured layers arranged in an alternating configuration on a substrate, forming first and second nanostructured channel regions in the first nanostructured layers, forming first and second gate-all-around structures wrapped around each of the first and second nanostructured channel regions. The forming the GAA structures includes depositing first and second gate barrier layers having similar material compositions and work function values on the first and second gate dielectric layers, forming first and second diffusion barrier layers on the first and second gate barrier layers, and doping the first and second gate barrier layers from a dopant source layer through the first and second diffusion barrier layers. The first diffusion barrier layer is thicker than the second diffusion barrier layer and the doped first and second gate barrier layers have work function values and doping concentrations different from each other. | 2022-06-16 |
20220190154 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes first to third electrodes, a first conductive member, a semiconductor member, and a first insulating member. The third electrode includes a third electrode end portion and a third electrode other-end portion. The first conductive member includes a first conductive member end portion and a first conductive member other-end portion. The first conductive member is electrically connected with one of the second electrode or the third electrode. The semiconductor member includes first to fourth semiconductor regions. The first semiconductor region includes first and second partial regions. The third semiconductor region is electrically connected with the second electrode. The fourth semiconductor region is electrically connected with the first electrode. At least a portion of the first insulating member is between the semiconductor member and the third electrode and between the semiconductor member and the first conductive member. | 2022-06-16 |
20220190155 | SEMICONDUCTOR DEVICE - A semiconductor device includes a source electrode, a drain electrode and a gate. The gate controls a current flowing between the source electrode and the drain electrode. Capacitance between the gate and the drain electrode is first capacitance. Capacitance between the gate and the source electrode is second capacitance. A sum of the first capacitance and the second capacitance is equal to third capacitance. Total switching loss is a sum of first switching loss and second switching loss. The first switching loss is defined by a current variation rate, and the second switching loss is defined by a voltage variation rate. A capacitance ratio of the first capacitance to the third capacitance is set to a ratio to satisfying a relationship that the total switching loss is smaller than a predetermined value. | 2022-06-16 |
20220190156 | LDMOS Architecture and Method for Forming - A method for forming a semiconductor device involves providing a semiconductor wafer having an active layer of a first conductivity type. First and second gates having first and second gate polysilicon are formed on the active layer. A first mask region is formed on the active layer. Between the first and second gates, using the first mask region, the first gate polysilicon, and the second gate polysilicon as a mask, a deep well of a second conductivity type, a shallow well of the second conductivity type, a source region of the first conductivity type, and first and second channel regions of the second conductivity type, are formed. In the active layer, using one or more second mask regions, first and second drift regions of the first conductivity type, first and second drain regions of the first conductivity type, and a source connection region of the second conductivity type, are formed. | 2022-06-16 |
20220190157 | REDUCTION OF BOTTOM EPITAXY PARASITICS FOR VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS - A semiconductor device structure comprises at least one semiconductor fin for a vertical transport field effect transistor, a bottosource/drain layer, and an insulating layer underlying the bottom source/drain layer. A method of forming the structure comprises forming a sacrificial layer within a lower portion of a source/drain region for a vertical transport field effect transistor structure. The sacrificial layer being formed adjacent to at least one semiconductor fin and in contact with a substrate. A source/drain layer is formed within an upper portion of the source/drain region above the sacrificial layer. The sacrificial layer is removed thereby forming a cavity between the substrate and the source/drain layer. An insulating layer is formed within the cavity. | 2022-06-16 |
20220190158 | DRAIN-EXTENDED TRANSISTOR - Described examples include an integrated circuit having a semiconductor substrate. The integrated circuit has a transistor that includes a buried layer having within the substrate, the buried layer defining a drift region between the buried layer and the top surface and a body region in the substrate extending from the buried layer to the surface of the substrate. The transistor also having a source formed in the body region, a drain extending from the buried layer to the surface of the substrate, a drift well extending from the buried layer toward the top surface and extending from the body region to the drain, a drift surface layer located between the drift well and the top, and a gate proximate to the surface of the substrate at the body region. | 2022-06-16 |
20220190159 | INTEGRATED CIRCUIT STRUCTURES HAVING GESNB SOURCE OR DRAIN STRUCTURES - Integrated circuit structures having GeSnB source or drain structures, and methods of fabricating integrated circuit structures having GeSnB source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include germanium, tin and boron. | 2022-06-16 |
20220190160 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes the steps of first forming a gate structure on a substrate, forming a first spacer adjacent to the gate structure, forming a second spacer adjacent to the first spacer, forming an epitaxial layer adjacent to the second spacer, forming a second cap layer on the epitaxial layer, and then forming a first cap layer on the second cap layer. Preferably, a top surface of the first cap layer includes a V-shape and the first cap layer and the second cap layer are made of different materials. | 2022-06-16 |
20220190161 | WRAP-AROUND CONTACTS INCLUDING LOCALIZED METAL SILICIDE - A conformally deposited metal liner used for forming discrete, wrap-around contact structures is localized between pairs of gate structures and below the tops of the gate structures. Block mask patterning is employed to protect transistors over active regions of a substrate while portions of the metal liner between active regions are removed. A chamfering technique is employed to selectively remove further portions of the metal liner within the active regions. Metal silicide liners formed on the source/drain regions using the conformally deposited metal liner are electrically connected to source/drain contact metal following the deposition and patterning of a dielectric layer and subsequent metallization. | 2022-06-16 |
20220190162 | SEMICONDUCTOR DEVICE STRUCTURE WITH INNER SPACER - A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin over the base. The semiconductor device structure also includes a first nanostructure over the fin and a second nanostructure over the first nanostructure. The semiconductor device structure further includes a gate stack wrapping around an upper portion of the fin, the first nanostructure, and the second nanostructure. In addition, the semiconductor device structure includes a first inner spacer between the fin and the first nanostructure and a second inner spacer between the first nanostructure and the second nanostructure. The semiconductor device structure includes a first low dielectric constant structure in the first inner spacer and a second low dielectric constant structure in the second inner spacer. The first low dielectric constant structure is larger than the second low dielectric constant structure. | 2022-06-16 |
20220190163 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first insulating layer, an oxide semiconductor disposed on the first insulating layer, a second insulating layer which covers the oxide semiconductor and a gate electrode disposed on the second insulating layer and overlapping the oxide semiconductor. The oxide semiconductor includes a first region overlapping the gate electrode and a second region not overlapping the gate electrode. The first insulating layer, the second region and the second insulating layer contain impurities of a same type. The impurities contained in a region directly below the second region in the first insulating layer are more than the impurities contained in the second region. | 2022-06-16 |
20220190164 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes an oxide semiconductor. The oxide semiconductor includes a first edge portion and a second edge portion intersecting a gate electrode, a first area overlapping the gate electrode, a second area along the first edge portion, a third area along the second edge portion, a fourth area the first edge portion, a fifth area along the second edge portion, a sixth area surrounded by the first area, the second area and the third area, and a seventh area surrounded by the first area, the fourth area and the fifth area. The first area, the second area and the third area, the fourth area and the fifth area have a higher resistivity than those of the sixth area and the seventh area. | 2022-06-16 |
20220190165 | DISPLAY DEVICE - A display device includes a first transistor including a gate electrode, a second transistor including a lower gate electrode, an upper gate electrode, and a first end portion electrically connected to an end portion of the first transistor, a lower gate signal line extending in a first direction, an upper gate signal line disposed on the lower gate signal line and extending in a first direction, and a first connection pattern disposed on the upper gate signal line, electrically connecting the gate electrode and a second end portion of the second transistor, and intersecting the lower gate signal line and the upper gate signal line. An entirety of the upper gate signal line overlaps a part of the lower gate signal line in an overlapping area in which the lower gate signal line or the upper gate signal line overlaps the first connection pattern. | 2022-06-16 |
20220190166 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - It is an object to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a semiconductor device including an inverted staggered thin film transistor whose semiconductor layer is an oxide semiconductor layer, a buffer layer is provided over the oxide semiconductor layer. The buffer layer is in contact with a channel formation region of the semiconductor layer and source and drain electrode layers. A film of the buffer layer has resistance distribution. A region provided over the channel formation region of the semiconductor layer has lower electrical conductivity than the channel formation region of the semiconductor layer, and a region in contact with the source and drain electrode layers has higher electrical conductivity than the channel formation region of the semiconductor layer. | 2022-06-16 |
20220190167 | NCFETS WITH COMPLIMENTARY CAPACITANCE MATCHING USING STACKED N-TYPE AND P-TYPE NANOSHEETS - A negative capacitance field effect transistor (NCFET) device is provided. The NCFET device includes a substrate, and a transistor stack structure formed on the substrate. The nanosheet stack structure includes a PFET region and an NFET region, the PFET region including a pWF metal layer stack and the NFET region including a nWF metal layer stack. The NCFET device also includes a dielectric interfacial layer formed on the transistor stack structure, the dielectric interfacial layer including metal induced oxygen vacancies, and the dielectric interfacial layer formed on a portion of the transistor stack structure. The NCFET device also includes a top electrode formed on the dielectric interfacial layer. | 2022-06-16 |
20220190168 | SEMICONDUCTOR DEVICES - A semiconductor device includes a multi-channel active pattern, a plurality of gate structures on the multi-channel active pattern and spaced apart from each other in a first direction, the plurality of gate structures including a gate electrode that extends in a second direction different from the first direction, a source/drain recess between the adjacent gate structures, and a source/drain pattern on the multi-channel active pattern in the source/drain recess, wherein the source/drain pattern includes: a semiconductor liner layer including silicon-germanium and extending along the source/drain recess, a semiconductor filling layer including silicon-germanium on the semiconductor liner layer, and at least one or more semiconductor insertion layers between the semiconductor liner layer and the semiconductor filling layer, and wherein the at least one or more semiconductor insertion layers have a saddle structure. | 2022-06-16 |
20220190169 | STRAINED VERTICAL CHANNEL SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS INCLUDING THE SAME - A strained vertical channel semiconductor device, a method of manufacturing the same, and an electronic apparatus including the same are provided. The method includes: providing a vertical channel layer on a substrate, wherein the vertical channel layer is held by a first supporting layer on a first side in a lateral direction, and is held by a second supporting layer on a second side opposite to the first side; replacing the first supporting layer with a first gate stack while the vertical channel layer is held by the second supporting layer; and replacing the second supporting layer with a second gate stack while the vertical channel layer is held by the first gate stack. | 2022-06-16 |
20220190170 | Thin Film Transistor and Display Apparatus Comprising the Same - One embodiment of the present disclosure provides a thin film transistor comprising an auxiliary electrode, a gate electrode and an active layer disposed between the auxiliary electrode and the gate electrode, wherein the active layer includes a channel portion overlapped with the gate electrode, a first connection portion disposed at one side of the channel portion, and a second connection portion disposed at the other side of the channel portion, and the channel portion includes a first portion overlapped with the auxiliary electrode and a second portion not overlapped with the auxiliary electrode. One embodiment of the present disclosure also provides a display apparatus comprising the thin film transistor. | 2022-06-16 |
20220190171 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor base body of a first conductivity-type; a first electrode electrically connected to the semiconductor base body; a first semiconductor region of a second conductivity-type provided at an upper part of the semiconductor base body; a second semiconductor region of the first conductivity-type provided at an upper part of the first semiconductor region; a second electrode electrically connected to the first semiconductor region; an insulating film provided on a top surface of the second semiconductor region; and a passive element provided on a top surface of the insulating film. | 2022-06-16 |
20220190172 | LASER-TEXTURED THIN-FILM SEMICONDUCTORS BY MELTING AND ABLATION - A photovoltaic device and a method of making the photovoltaic device are disclosed. The photovoltaic device may include a semiconductor layer epitaxially grown using a compound semiconductor material, such as a group III-V semiconductor material, wherein a surface of the semiconductor layer is textured via one or more laser pulses of a laser. The photovoltaic device may also include a dielectric layer deposited over the textured surface of the semiconductor layer, and a back metal reflector provided on the dielectric layer. The textured surface extends a path of light traveling through the photovoltaic device to increase absorption of the light within the photovoltaic device. | 2022-06-16 |
20220190173 | METHOD FOR FABRICATION OF COPPER-INDIUM GALLIUM OXIDE AND CHALCOGENIDE THIN FILMS - A composition of matter having a coated silicon substrate with multiple alternating layers of polydopamine and polyallylamine bound copper-indium-gallium oxide (CIGO) nanoparticles on the substrate. A related composition of matter having polyallylamine bound to CIGO nanoparticles to form PAH-coated CIGO nanoparticles. A related CIGO thin film made via conversion of layer-by-layer assembled CIGO nanoparticles and polyelectrolytes. CIGO nanoparticles are created via a flame-spray pyrolysis method using metal nitrate precursors, subsequently coated with polyallylamine (PAH), and dispersed in aqueous solution. Multilayer films are assembled by alternately dipping a substrate into a solution of either polydopamine or polystyrenesulfonate and then in the CIGO-PAH dispersion to fabricate CIGO films as thick as 1-2 microns. | 2022-06-16 |
20220190174 | SILICON-BASED SPIN-QUBIT QUANTUM MAGNETOMETER AND RADAR SYSTEM WITH ALL ELECTRICAL CONTROL - The present invention relates to a spin-qubit quantum magnetometer anti radar system entirely implemented in silicon and with full electrical control. By default, each detection clement of the silicon-based spin-qubit quantum magnetometer and radar system of the invention is built around a Field Effect Transistor (PET) on silicon over insulator with a back-gate as well as two front gates, which can be adjacent to one another along the Drain-Source FET channel or alternatively placed across that same channel and facing each other as corner gates. The silicon-based spin-qubit quantum magnetometer and radar system of the invention is particularly well-suited for any type of extremely-sensitive radar applications but but can also be applied for mineral/mining prospecting, discovery of distant astronomical objects, mine and metal detectors, tomography/MRI (Magnetic Resonance Imaging). | 2022-06-16 |
20220190175 | Ultraviolet Detector and Preparation Method Therefor - A ultraviolet detector includes a substrate; a first epitaxial layer that is a heavily doped epitaxial layer and located on the substrate, a second epitaxial layer located on the first epitaxial layer, where the second epitaxial layer is a lightly doped epitaxial layer, or a double-layer or multi-layer structure composed of at least one lightly doped epitaxial layer and at least one heavily doped epitaxial layer; an ohmic contact layer located on the second epitaxial layer or formed in the second epitaxial layer, where the ohmic contact layer is a graphical heavily doped layer; and a first metal electrode layer located on the ohmic contact layer. | 2022-06-16 |
20220190176 | Configurable Solar Cells - A photovoltaic cell may include a substrate configured as a single light absorption region. The cell may include at least one first semiconductor region and at least one second semiconductor region arranged on or in the substrate. The cell may include a plurality of first conductive contacts arranged on the substrate and physically separated from one another and a plurality of second conductive contacts arranged on the substrate and physically separated from one another. Each first conductive contact may be configured to facilitate electrical connection with the at least one first semiconductor region. Each second semiconductor conductive contact may be configured to facilitate electrical connection with the at least one second semiconductor region. Each of the first conductive contacts may form at least one separate cell partition with at least one of the second conductive contacts, thereby forming a plurality of cell partitions on or in the substrate. | 2022-06-16 |
20220190177 | FLEXIBLE SOLAR-POWERED WIRELESS COMMUNICATION DEVICE - A solar-powered wireless communication device a flexible circuit, a device layer positioned adjacent to the flexible circuit and having a plurality of electronic components coupled to the flexible circuit, a flexible cover positioned over the device layer, a flexible substrate coupled with a second side of the flexible circuit, opposite the first side, by a first adhesive layer, and a solar panel positioned at a surface of the solar-powered tape node and coupling with the flexible circuit. The solar panel has a light-receiving surface facing away from the flexible circuit and is operable to generate electrical power when light is incident on the light-receiving surface. The solar-powered wireless communication device being operable to determine that power available to the solar-powered wireless communication device is below a first threshold and delegate at least one task of the solar-powered wireless communication device to another node of a network communications environment. | 2022-06-16 |
20220190178 | SOLAR CELL MODULE HAVING EXCELLENT VISIBILITY - Provided, according to the present invention, is a solar cell module having excellent visibility, the solar cell module comprising: a transparent substrate; and a solar cell which is installed inside the transparent substrate and converts sunlight into photoelectricity, wherein the solar cell is installed so as to be horizontally arrayed in the transparent substrate. | 2022-06-16 |
20220190179 | WIRE-BASED METALLIZATION AND STRINGING FOR SOLAR CELLS - Wire-based metallization and stringing techniques for solar cells, and the resulting solar cells, modules, and equipment, are described. In an example, a substrate has a surface. A plurality of N-type and P-type semiconductor regions is disposed in or above the surface of the substrate. A conductive contact structure is disposed on the plurality of N-type and P-type semiconductor regions. The conductive contact structure includes a plurality of conductive wires, each conductive wire of the plurality of conductive wires essentially continuously bonded directly to a corresponding one of the N-type and P-type semiconductor regions. | 2022-06-16 |
20220190180 | METHOD OF MAKING LIGHT CONVERTING SYSTEMS USING THIN LIGHT ABSORBING AND LIGHT TRAPPING STRUCTURES - A method of making a light converting optical system comprising providing a first optical layer, a thin sheet of reflective light scattering material, a light source, a second optical layer approximately coextensive with the first optical layer, a continuous broad-area photoabsorptive film layer approximately coextensive with the first optical layer, positioning the thin sheet of reflective light scattering material parallel to the first optical layer, positioning the continuous broad-area photoabsorptive film layer between and parallel to the first optical layer and the thin sheet of reflective material, and positioning the second optical layer on a light path between the light source and the continuous broad-area photoabsorptive film layer. The first optical layer has a microstructured broad-area front surface comprising an array of linear grooves disposed side by side and extending along a straight line between two edges of the layer. | 2022-06-16 |
20220190181 | MULTIJUNCTION METAMORPHIC SOLAR CELLS - A multijunction solar cell including a growth substrate; a graded interlayer disposed over the growth substrate, a plurality of subcells disposed over the graded interlayer including a second solar subcell disposed over and lattice mismatched with respect to the growth substrate, and at least a third solar subcell disposed over the second subcell; the grading interlayer including a plurality of N step-graded sublayers (where N is an integer and the value of N is 12022-06-16 | |
20220190182 | INDIRECT BANDGAP, PEROVSKITE-BASED X-RAY DETECTOR AND METHOD - An X-ray system includes an X-ray generation unit configured to generate X-rays; an X-ray detection unit including at least one X-ray sensor that includes an indirect bandgap, perovskite semiconductor material, the X-ray sensor being configured to record the X-rays; and a control unit that controls a generation of the X-rays and a detection of the X-rays at the X-ray detection unit. | 2022-06-16 |
20220190183 | AVALANCHE PHOTODETECTOR (VARIANTS) AND METHOD FOR MANUFACTURING THE SAME (VARIANTS) - Method for manufacturing avalanche photodetector, including forming multiplication layer on wafer; etching closed groove on surface of the multiplication layer, so that depth of the closed groove is greater than or equal to thickness of the multiplication layer, but less than total thickness of the wafer and multiplication layer combined; filling the groove with highly-doped polycrystalline silicon of same conductivity type as multiplication layer; forming, on upper surface of multiplication layer, inside groove, avalanche amplifier as mesa structure, by forming contact layer on multiplication layer, while simultaneously forming photoconverter outside contact layer, and etching away portion of multiplication layer in the photoconverter to depth less than thickness of the multiplication layer; forming dielectric layer on multiplication layer where etching took place, its thickness equal to the depth of multiplication layer that was etched away; forming first electrode of transparent material on surfaces of contact and dielectric layers; forming second electrode. | 2022-06-16 |
20220190184 | INTEGRATED CIRCUIT COMPRISING A SINGLE PHOTON AVALANCHE DIODE AND CORRESPONDING MANUFACTURING METHOD - A single photon avalanche diode (SPAD) includes a PN junction in a semiconductor well doped with a first type of dopant. The PN junction is formed between a first region doped with the first type of dopant and a second region doped with a second type of dopant opposite to the first type of dopant. The first doped region is shaped so as to incorporate local variations in concentration of dopants that are configured, in response to a voltage between the second doped region and the semiconductor well that is greater than or equal to a level of a breakdown voltage of the PN junction, to generate a monotonic variation in the electrostatic potential between the first doped region and the semiconductor well. | 2022-06-16 |
20220190185 | POSITIVE-INTRINSIC-NEGATIVE (PIN) PHOTOSENSITIVE DEVICE, MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL - A positive-intrinsic-negative (PIN) photosensitive device is provided. A p-type semiconductor layer composed of molybdenum oxide and having valence band energy between valence band energy of an intrinsic semiconductor layer and an upper electrode is used to replace a p-type semiconductor layer used in a conventional PIN photodiode, so that the PIN photodiode may be prepared without using borane gas. More, a difference between valence band energy of the p-type semiconductor layer and the intrinsic semiconductor layer is used to transport holes located in a valence band, so that it is unnecessary to use an active layer of a thin film transistor, so that the PIN photosensitive device may be stacked on the thin film transistor to reduce aperture ratio loss of a display panel. | 2022-06-16 |
20220190186 | OPTOELECTRONIC MODULE - We disclose an optoelectronic module comprising an optoelectronic device operable to emit or detect a wavelength of radiation, an optical element arranged on the optoelectronic device, the optical element being transparent to the wavelength of radiation capable of being emitted or detected by the optoelectronic device, and a wall configured to laterally enclose the optoelectronic device and the optical element, the wall being opaque to the wavelength of radiation capable of being emitted or detected by the optoelectronic device. | 2022-06-16 |
20220190187 | MONOLITHIC ELECTRICAL POWER CONVERTER FORMED WITH LAYERS - An electrical power converter can include a plurality of layers disposed on a substrate. An emitter, including a first semiconductor junction that is formed at an interface between a first pair of adjacent layers, can produce light in response to a first electrical signal. An absorber, including a second semiconductor junction that is formed at an interface between a second pair of adjacent layers, can absorb at least some of the light. Circuitry can produce a second electrical signal in response to the absorbed light. The second electrical signal can be substantially proportional to the first electrical signal and can be electrically isolated from the first electrical signal. Because the light can remain within the layers during use, the electrical power converter can have a higher efficiency than a comparable device that propagates the light through at least one interface between air and a semiconductor material. | 2022-06-16 |
20220190188 | ELECTRO-OPTICAL PHYSIOLOGIC SENSOR - An electro-optical physiologic sensor comprises a printed circuit board (PCB) and a light emitter and a photodetector respectively mounted to the PCB. A first sensor element is disposed on the PCB and comprises a first electrode configured to contact tissue of a subject and a first light channel co-located with the first electrode, the first light channel optically coupled to the light emitter and configured to direct light into the subject's tissue. A second sensor element is disposed on the PCB and comprises a second electrode configured to contact the subject's tissue and a second light channel co-located with the second electrode, the second light channel optically coupled to the photodetector and configured to receive light from the tissue of the subject resulting from the light generated by the light emitter. | 2022-06-16 |
20220190189 | METHOD FOR MANUFACTURING SOLAR CELL - A manufacturing method of an embodiment according to the present invention may comprise the steps of: locating a solar cell, including a semiconductor substrate and a semiconductor layer which has an absorption coefficient higher than that of the semiconductor substrate and is formed on at least one side of the semiconductor substrate, such that the semiconductor layer is oriented toward a laser; emitting a laser beam toward the semiconductor layer to form a groove on the solar cell; and dividing the solar cell along the groove into a plurality of pieces. | 2022-06-16 |
20220190190 | SOLAR CELL WAFER WIRE BONDING SYSTEM AND METHOD - A wire bonding system attaches wires to a solar cell wafer. The wire bonding system includes a feed tube through which a wire is drawn. Rollers contact the wire through openings in the feed tube to facilitate movement of the wire. The wire bonding system includes a soldering heater tip and a wire cutter. The solar cell wafer is placed on a platform, which moves the solar cell wafer. The system has multiple lanes for attaching multiple wires to the solar cell wafer at the same time in parallel operations. | 2022-06-16 |
20220190191 | CdSeTe PHOTOVOLTAIC DEVICES WITH INTERDIGITATED BACK CONTACT ARCHITECTURE - Disclosed herein are CdSeTe photovoltaic devices having interdigitated back contact architecture for use in polycrystalline thin films in photovoltaic devices. | 2022-06-16 |
20220190192 | METHOD OF MANUFACTURING MICRO-LED DISPLAY - Provided is a method of manufacturing a display, the method including a first operation of transferring a plurality of micro light emitting diodes (LEDs) to a plurality of wells of an interposer through a fluidic self assembly (FSA) process, a second operation of aligning a driving substrate on the interposer, a third operation of injecting a penetrating solvent between the interposer and the driving substrate, such that the penetrating solvent penetrates between the plurality of micro LEDs and the plurality of wells, and a fourth operation of transferring the plurality of micro LEDs to the driving substrate by radiating light to the interposer to vaporize the penetrating solvent. | 2022-06-16 |
20220190193 | DISPLAY TRANSFER STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A display transfer structure includes a base layer, a flexible barrier rib positioned on the base layer and having a plurality of holes therein, and a plurality of micro light emitting diodes (LEDs) positioned respectively in the plurality of holes. A method of manufacturing the display transfer structure includes forming a flexible barrier rib having holes on a base layer, supplying liquid to the holes, supplying micro LEDs to the liquid, and scanning the flexible barrier rib with an absorber capable of absorbing the liquid to align each of the micro LEDs in a respective hole such that electrodes of the micro LEDs face an outside of the holes. | 2022-06-16 |
20220190194 | AN OPTOELECTRONIC DEVICE - In some embodiments, a semiconductor structure includes a first conductivity type region comprising a first superlattice, and an i-type active region adjacent to the first conductivity type region comprising an i-type superlattice. The first conductivity type region can be a p-type region or an n-type region. The first superlattice can be comprised of a plurality of first unit cells comprising a first set of single crystal layers, and the i-type superlattice can be comprised of a plurality of i-type unit cells comprising a second set of single crystal layers. An average alloy content of the plurality of the first unit cells and the i-type unit cells can be constant along a growth direction. A combined thickness of the second set single crystal layers can be thicker than a combined thickness of the first set of single crystal layers. | 2022-06-16 |
20220190195 | Laser Removal of Defects in a Dielectric for Modulating an Adjoining Atomically Two-Dimensional Material - A method removes defects in a dielectric layer, such as during fabrication of a device that emits light from hot electrons injected into an atomically two-dimensional material. An atomically two-dimensional material and the dielectric layer are adjoined. The dielectric layer is adapted to convey a variable electric field for modulating a wavelength of photons electronically emitted across a band structure of the atomically two-dimensional material. Laser pulses are strobed into the dielectric layer with sufficient cumulative energy to remove a majority of the defects in the dielectric layer without altering the atomically two-dimensional material. | 2022-06-16 |
20220190196 | ALIGNMENT MODULE FOR TRANSFERRING A MAGNETIC LIGHT-EMITTING DIE AND ALIGNMENT METHOD THEREOF - An alignment module and alignment method for transferring magnetic light-emitting die are provided, including a backplane having at least one cavity, a magnetic pull device and magnetic light-emitting die. The magnetic pull device is located below the cavity and disposed correspondingly to the cavity. The magnetic light-emitting die includes a magnetic metallic substrate and a peripheral electrode formed on the magnetic metallic substrate. The peripheral electrode is surrounding on the magnetic metallic substrate and formed adjacent to an inner edge of the magnetic metallic substrate. Depth of the cavity is designed as equal to a thickness of the magnetic metallic substrate such that the die is accommodated and aligning transferred to the backplane by using the cavity and magnetic pull device. By employing the proposed die alignment techniques, accurate alignment result is achieved and thereby the present invention is applied perfectly for industrial mass transfer technology. | 2022-06-16 |
20220190197 | MICRO LIGHT EMITTING DIODES WITH NANOSTRUCTURES - A light emitting diode may include a light emission layer and a charge transport layer disposed on the light emission layer. One or more nanostructures may be formed by removing a portion of the charge transport layer and/or the light emission layer and depositing a plasmonic metamaterial on a remaining portion of the charge transport layer and/or the light emission layer. The one or more nanostructures may include the plasmonic metamaterial deposited inside the recesses formed by the remaining portion of the charge transport layer and/or the light emission layer, with an additional portion of the charge transport layer disposed on top. A material composition, shape, dimension, placement, and/or distribution of the one or more nanostructures may be configured to maximize the quantum efficiency of the light emitting diode, especially at a microscale of less than 100 microns. | 2022-06-16 |
20220190198 | Light Emitting Diode Device - Described are light emitting diode (LED) devices including a combination of electroluminescent quantum wells and photo-luminescent active regions in the same wafer. A first group of QWs with shortest emission wavelength is placed between the p- and n-layers of a p-n junction. Other groups of QWs with longer wavelengths are placed outside the p-n junction in a part of the LED structure where electrical injection of minority carriers does not occur. Electroluminescence emitted by the first group of QWs is absorbed by other group(s) and re-emitted as longer wavelength light. The color of an individual die made on the wafer can be controlled by either etching away unwanted groups of longer-wavelength QWs at the position of that die, or keeping them intact. Wavelength-selective mirrors that increase down conversion efficiency may be selectively applied to die where longer wavelength emission is desired. The use of tunnel junction contacts facilitates integration of wavelength selective mirrors to external surfaces of the die and avoids problems of conductivity type conversion on etched p-GaN layers. | 2022-06-16 |
20220190199 | POINT SOURCE TYPE LIGHT-EMITTING DIODE AND MANUFACTURING METHOD THEREOF - The present disclosure provides a point source type light-emitting diode and a manufacturing method thereof, which simplify a manufacturing process and have superior temperature-dependent characteristic. A point source type light-emitting diode includes a support substrate, a metal layer having a light reflecting surface, a current narrowing layer, a III-V compound semiconductor laminate sequentially having a p-type semiconductor layer, an active layer, and an n-type semiconductor layer, and a top electrode. The top electrode has an opening for ejecting light emitted by the active layer. The current narrowing layer includes a dielectric layer having a through hole and an intermediate electrode. In a projection plane in which the current narrowing layer including the intermediate electrode is projected vertically onto the top electrode, the opening encloses the intermediate electrode, and the dielectric layer encloses the top electrode. The thickness of the p-type semiconductor layer is between 0.5 μm and 3.0 μm inclusive. | 2022-06-16 |
20220190200 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel includes a first substrate, a second substrate, a plurality of light-emitting elements, a plurality of baffle wall structures, and a plurality of first auxiliary structures. The plurality of light-emitting elements and the plurality of baffle wall structures are located between the first substrate and the second substrate. The plurality of light-emitting elements are disposed on the first substrate, the plurality of baffle wall structures are disposed on the second substrate, and a baffle wall structure is located between adjacent light-emitting elements. The plurality of first auxiliary structures are disposed between at least a part of the plurality of light-emitting elements and the first substrate. The first auxiliary structures and gaps are alternated in a direction which is parallel to the first substrate, and the gap is a space between the baffle wall structure and the first substrate. | 2022-06-16 |
20220190201 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE INCLUDING THE SAME - A semiconductor light emitting device is provided. The semiconductor light emitting device includes: a substrate structure; a light emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer sequentially provided on the substrate structure, wherein a hole penetrates through the first conductivity-type semiconductor layer and the active layer to expose the second conductivity-type semiconductor layer, and uneven portions are provided on a surface of the second conductivity-type semiconductor layer; a dam structure provided adjacent a portion of the light emitting structure on the substrate structure; a first electrode provided between the substrate structure and the light emitting structure, and connected to the first conductivity-type semiconductor layer; and a second electrode provided in the hole between the substrate structure and the light emitting structure, and connected to the second conductivity-type semiconductor layer. The first conductivity-type semiconductor layer extends through the light emitting structure and the dam structure. | 2022-06-16 |
20220190202 | LIGHT-EMITTING ELEMENT AND METHOD FOR MANUFACTURING THE SAME - A light-emitting element includes an n-type contact layer which includes AlGaN and in which a Fermi level and a conduction band are in degeneracy, and a light-emitting layer including AlGaN and being stacked on the n-type contact layer. An Al composition x of the n-type contact layer is not less than 0.1 greater than an Al composition x of the light-emitting layer. The n-type contact layer has an effective donor concentration that is a concentration to cause the degeneracy and that is not more than 4.0×10 | 2022-06-16 |
20220190203 | DISPLAY DEVICE AND METHOD OF REPAIRING DISPLAY DEVICE - A display device includes a first electrode and a second electrode which are disposed on a substrate and face each other. Light-emitting elements are disposed between the first electrode and the second electrode. Markings are formed on the first electrode in a first extending direction of the first electrode in a plan view. | 2022-06-16 |
20220190204 | LIGHT-EMITTING ELEMENT, METHOD OF MANUFACTURING LIGHT-EMITTING ELEMENT, AND DISPLAY DEVICE INCLUDING LIGHT-EMITTING ELEMENT - A light-emitting element includes: a first semiconductor layer including a first type semiconductor; a second semiconductor layer including a second type semiconductor different from the first type semiconductor; an active layer between one surface of the first semiconductor layer and one surface of the second semiconductor layer; a first electrode layer on another surface of the second semiconductor layer and having a first cross-sectional area; and a second electrode layer on another surface of the first semiconductor layer and having a second cross-sectional area smaller than the first cross-sectional area. A side surface of the light-emitting element defined by the first semiconductor layer, the active layer, the second semiconductor layer, and the second electrode layer is perpendicular to a main surface of the first electrode layer. | 2022-06-16 |
20220190205 | Emission of Electromagnetic Radiation and Control of the Properties of the Emitted Electromagnetic Radiation - Provided is a device for emitting electromagnetic radiation. The device includes a first electrode, a second electrode, and an exciton recombination layer extending from the first electrode to the second electrode. The device is configured to relocate a recombination zone in the exciton recombination layer by changing an electric field between the first electrode and the second electrode, or to emit electromagnetic radiation through a transparent substrate. | 2022-06-16 |
20220190206 | ARRAY SUBSTRATE AND DISPLAY DEVICE - An array substrate and a display panel are provided, the array substrate is disposed on the base substrate, and a passivation layer is formed on a side of the array substrate layer away from the base substrate. The passivation layer includes a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked in sequence, the first dielectric layer is disposed close to the array layer and the third dielectric layer is disposed away from the array layer, a refractive index of the first dielectric layer is different from a refractive index of the second dielectric layer, and the refractive index of the second dielectric layer is different from a refractive index of the third dielectric layer. | 2022-06-16 |
20220190207 | SEMICONDUCTOR LIGHT-EMITTING DEVICE INCLUDING A REFLECTOR LAYER HAVING A MULTI-LAYERED STRUCTURE - A semiconductor light-emitting device includes a light-emitting structure including a first semiconductor layer, an active layer, and a second semiconductor layer which are sequentially stacked, a first insulating layer on the second semiconductor layer with a plurality of first openings having first widths and a plurality of second openings having second widths different from the first widths, a first electrode electrically connected to the first semiconductor layer through the first openings, a first sub-electrode layer between the second semiconductor layer and the first insulating layer, the first sub-electrode layer being exposed through the second openings, and a second sub-electrode layer on the first insulating layer, the second sub-electrode layer being connected to the first sub-electrode layer through the second openings, wherein a first distance between the first openings closest to each other is different from a second distance between the second openings closest to each other. | 2022-06-16 |
20220190208 | SUPPORT STRUCTURES FOR LIGHT EMITTING DIODE PACKAGES - Solid-state lighting devices including light-emitting diodes (LEDs), and more particularly support structures for LED packages are disclosed. Support structure arrangements are provided for LED packages with increased reflectivity. Support structures may include patterned electrically conductive materials that provide electrical connections and bonding surfaces for LED chips within the package, and bonding surfaces for cover structures in certain arrangements. Depending on the wavelengths of light emitted by the LED package, light reflectivity tradeoffs can exist for conductive materials that provide suitable electrical connections and bonding surfaces. Additional patterned layers with increased reflectivity may be provided on underlying patterned electrically conductive materials. The patterned layers with increased reflectivity may be arranged in areas of the LED package where light may impinge surfaces of the LED package that are outside of one or more of a die attach area and a cover structure mounting area for the LED package. | 2022-06-16 |
20220190209 | OPTOELECTRONIC COMPONENT WITH A LUMINESCENCE CONVERSION LAYER - An optoelectronic component may include at least one light-emitting semiconductor layer sequence and at least one luminescence conversion layer having a transparent conductive oxide and at least one dopant for forming luminescence centers. | 2022-06-16 |