24th week of 2012 patent applcation highlights part 16 |
Patent application number | Title | Published |
20120146043 | SEMICONDUCTOR DEVICE, ACTIVE MATRIX SUBSTRATE, AND DISPLAY DEVICE - Provided are a semiconductor device that can be fabricated easily and can achieve leakage current reduction, without its structure becoming complex or the device becoming bulky; an active matrix substrate in which the device is used; and a display device in which the device is used. A switching portion ( | 2012-06-14 |
20120146044 | Optoelectronic Semiconductor Chip and Method for Producing an Optoelectronic Semiconductor Chip - In at least one embodiment of the optoelectronic semiconductor chip ( | 2012-06-14 |
20120146045 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a light emitting layer, a light transmitting layer and a first semiconductor layer. The light transmitting layer is transmittable with respect to light emitted from the light emitting layer. The first semiconductor layer contacts the light transmitting layer between the light emitting layer and the light transmitting layer. The light transmitting layer has a thermal expansion coefficient larger than a thermal expansion coefficient of the light transmitting layer, has a lattice constant smaller than a lattice constant of the active layer, and has a tensile stress in an in-plane direction. | 2012-06-14 |
20120146046 | SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer, a gate recess formed by removing at least a portion of the second semiconductor layer, an insulation film formed on the gate recess and the second semiconductor layer, a gate electrode formed on the gate recess via the insulation film, source and drain electrodes formed on one of the first and the second semiconductor layers, and a fluorine containing region formed in at least one of a part of the first semiconductor layer corresponding to a region in which the gate recess is formed and a part of the second semiconductor layer corresponding to the region in which the gate recess is formed. | 2012-06-14 |
20120146047 | P-CONTACT AND LIGHT-EMITTING DIODE FOR THE ULTRAVIOLET SPECTRAL RANGE - The present invention relates to a p-doped contact for use in a light-emitting diode for the ultraviolet spectral range, comprising a p-contact layer having a first surface for contacting a radiation zone and a second surface comprising, on the side facing away from the first surface: a) a coating, which directly contacts 5%-99.99% of the second surface of the p-contact layer and contains or consists of a material having a maximum reflectivity of at least 60% for light with a wavelength of 200 nm to 400 nm; b) a plurality of p-injectors, which are disposed directly on the second surface of the p-contact layer. | 2012-06-14 |
20120146048 | GALLIUM NITRIDE COMPOUND SEMICONDUCTOR LIGHT-EMITTING DEVICE - Provided is a gallium nitride-based compound semiconductor light-emitting element, in which the concentration of Mg which is a p-type dopant in a p-GaN layer in which the (10-10) m-plane of a hexagonal wurtzite structure grows is adjusted in a range from 1.0×10 | 2012-06-14 |
20120146049 | JFET DEVICES WITH INCREASED BARRIER HEIGHT AND METHODS OF MAKING THE SAME - Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a doped silicon-carbide gate, while other embodiments include a JFET with a metal gate. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET. | 2012-06-14 |
20120146050 | MEASUREMENT OF CMOS DEVICE CHANNEL STRAIN BY X-RAY DIFFRACTION - A direct measurement of lattice spacing by X-ray diffraction is performed on a periodic array of unit structures provided on a substrate including semiconductor devices. Each unit structure includes a single crystalline strained material region and at least one stress-generating material region. For example, the single crystalline strained material region may be a structure simulating a channel of a field effect transistor, and the at least one stress-generating material region may be a single crystalline semiconductor region in epitaxial alignment with the single crystalline strained material region. The direct measurement can be performed in-situ at various processing states to provide in-line monitoring of the strain in field effect transistors in actual semiconductor devices. | 2012-06-14 |
20120146051 | NITRIDE BASED SEMICONDUCTOR DEVICE - Disclosed herein is a nitride based semiconductor device. There is provided a nitride based semiconductor device including a base substrate; a semiconductor layer disposed on the base substrate; and an electrode structure disposed on the semiconductor layer, wherein the electrode structure includes: a first ohmic electrode ohmic-contacting the semiconductor layer; a second ohmic electrode ohmic-contacting the semiconductor layer and spaced apart from the first ohmic electrode; and a schottky electrode unit schottky-contacting the semiconductor layer and covering the second ohmic electrode. | 2012-06-14 |
20120146052 | NITRIDE BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein is a nitride based semiconductor device. There is provided a nitride based semiconductor device including: a base substrate; an epitaxial growth layer disposed on the base substrate and generating 2-dimensional electron gas (2DEG) therein; and an electrode structure disposed on the epitaxial growth layer and having an extension extending into the epitaxial growth layer, wherein the epitaxial growth layer includes a depressing part depressed thereinto from the surface of the epitaxial growth layer, and the depressing part includes: a first area in which the extension is disposed; and a second area that is an area other than the first area. | 2012-06-14 |
20120146053 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, first gate sidewalls formed on both sides of the gate electrode, and a source/drain semiconductor layer formed on the semiconductor substrate to sandwich the first gate sidewalls with the gate electrode. Further, second gate sidewalls are provided on the first gate sidewalls and the source/drain semiconductor layer at both sides of the gate electrode, wherein the boundary of each of the second gate sidewalls with each of the first gate sidewalls is terminated at the side surface of the gate electrode, and each of the second gate sidewalls has a smaller Young's modulus and a lower dielectric constant than each of the first gate sidewalls. | 2012-06-14 |
20120146054 | MOSFET WITH SOURCE SIDE ONLY STRESS - An integrated circuit contains a transistor with a stress enhancement region on the source side only. In a DeMOS transistor, forming the stress enhancement region on the source side only and not forming a stress enhancement region in the drain extension increases the resistance of the drain extension region enabling formation of a DeMOS transistor with reduced area. In a MOS transistor, by forming the stress enhancement region on the source side only and eliminating the stress enhancement region from the drain side, transistor leakage is reduced and CHC reliability improved. | 2012-06-14 |
20120146055 | SiC SEMICONDUCTOR DEVICE - A SiC semiconductor device includes a SiC semiconductor layer having a first-conductivity-type impurity, a field insulation film formed on a front surface of the SiC semiconductor layer and provided with an opening for exposing therethrough the front surface of the SiC semiconductor layer, an electrode connected to the SiC semiconductor layer through the opening of the field insulation film, and a guard ring having a second-conductivity-type impurity and being formed in a surface layer portion of the SiC semiconductor layer to make contact with a terminal end portion of the electrode connected to the SiC semiconductor layer. A second-conductivity-type impurity concentration in a surface layer portion of the guard ring making contact with the electrode is smaller than a first-conductivity-type impurity concentration in the SiC semiconductor layer. | 2012-06-14 |
20120146056 | SILICON CARBIDE EPITAXIAL WAFER AND MANUFACTURING METHOD THEREFOR - Provided is a silicon carbide epitaxial wafer, the entire surface of which is free of step bunching. Also provided is a method for manufacturing said silicon carbide epitaxial wafer. The provided method for manufacturing a silicon carbide semiconductor device includes: a step wherein a 4H—SiC single-crystal substrate having an off-axis angle of 5° or less is polished until the lattice disorder layer on the surface of the substrate is 3 nm or less; a step wherein, in a hydrogen atmosphere, the polished substrate is brought to a temperature between 1400° C. and 1600° C. and the surface of the substrate is cleaned; a step wherein silicon carbide is epitaxially grown on the surface of the cleaned substrate as the amounts of SiH | 2012-06-14 |
20120146057 | METHOD OF FABRICATING SPACERS IN A STRAINED SEMICONDUCTOR DEVICE - The present disclosure provides a method for fabricating a semiconductor device that includes forming a gate stack over a silicon substrate, forming dummy spacers on sidewalls of the gate stack, isotropically etching the silicon substrate to form recess regions on either side of the gate stack, forming a semiconductor material in the recess regions, the semiconductor material being different from the silicon substrate, removing the dummy spacers, forming spacer layers having an oxide-nitride-oxide configuration over the gate stack and the semiconductor material, and etching the spacer layers to form gate spacers on the sidewalls of the gate stack. | 2012-06-14 |
20120146058 | LIGHT EMITTING DIODE MODULE PROVIDING STABLE COLOR TEMPERATURE - A light emitting diode module providing stable color temperature includes a plurality of light emitting diodes, at least one color sensor and a controller. The plurality of light emitting diodes can emit light with different wavelengths. The light emitting diode module providing stable color temperature includes a reflection region at the path of the light emitting from half peak angle of each light emitting diode. The color sensor detects the light having different wavelengths reflected from the reflection region. The controller adjusts driving currents of the light emitting diodes according to the luminous intensities of the light of the light emitting diodes reflected by the reflection region and detected by the color sensor. | 2012-06-14 |
20120146059 | Organic light emitting diode display - An organic light emitting diode (OLED) display includes: a substrate; an organic light emitting diode disposed on the substrate; a sealing member sealed with the substrate, interposing the organic light emitting diode therebetween; a pad portion disposed on the substrate, corresponding to an edge of the sealing member, and electrically connected with the organic light emitting diode; a conductive line portion formed on the sealing member and/or on the substrate, and applied with driving power supplied to the organic light emitting diode; and a conductive connection portion directly connecting the pad portion and the conductive line portion. | 2012-06-14 |
20120146060 | Organic Light Emitting Display Device and Manufacturing Method for the Same - An organic light emitting display device may comprises a thin film transistor including an active layer, a gate electrode including a gate lower electrode and a gate upper electrode, a source electrode, a drain electrode, and an organic light emitting device electrically connected to the thin film transistor. A pixel electrode formed of the same material and in the same layer as the gate lower electrode, an intermediate layer including a light emitting layer, and an opposed electrode are sequentially deposited. A first pad electrode is formed in the same layer as the gate lower electrode, a second pad electrode is formed on at least a part of the first pad electrode and in the same layer as the gate upper electrode, and a third pad electrode contacts at least a part of the second pad electrode and is formed in the same layer as the source electrode. | 2012-06-14 |
20120146061 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND MANUFACTURING METHOD THEREOF - A large size organic light emitting diode (OLED) display and manufacturing method thereof are disclosed. In one embodiment, the method includes i) forming a display unit including a plurality of pixels on a substrate, ii) forming a getter layer, a bonding layer and a conductive contact layer around the display unit and iii) manufacturing a sealing member including a flexible polymer film and a metal layer formed on at least one side of the polymer film. The method may further include laminating the sealing member on the substrate using a roll lamination process such that the metal layer contacts the conductive contact layer and curing the contact layer and the conductive contact layer. | 2012-06-14 |
20120146062 | LIGHT EMITTING DEVICE, DISPLAY APPARATUS, AND ELECTRONIC APPARATUS - In a display panel, a first electron injection layer is formed between an anode and a light-emitting functional layer, and a hole injection layer is formed between the anode and the first electron injection layer. In other words, the hole injection layer, the first electron injection layer, and the light-emitting functional layer are configured to be laminated on the anode in this order. An electron injection material used for the first electron injection layer is diffused into the hole injection layer, and the diffused electron injection material inhibits or promotes hole transportation of the hole injection layer, so that the amount of holes transported to a light-emitting functional layer is adjusted. As a result, the carrier balance is improved. | 2012-06-14 |
20120146063 | LIGHT EMITTING DIODE LAMP - An LED lamp comprises a front cover comprising an upper plate, a first sidewall perpendicular to the upper plate, a through hole in a central portion of the upper plate; a rear cover comprising a bottom plate, a second sidewall perpendicular from the bottom plate to engage the front and rear covers by sleeving over the first sidewall; a lamp body comprising a first and second substrates, a third sidewall interconnecting the first and second substrates, the third sidewall penetrating through the through hole and is between the upper and bottom plates; a first LED unit on the first substrate, facing the second substrate; a second LED unit on the second substrate, facing away the first substrate, wherein the LED lamp is configure to direct light from the first LED units via the third sidewall, and light from the second LED units along a direction away from the first substrate. | 2012-06-14 |
20120146064 | DEPOSITION MASK AND METHOD OF MANUFACTURING ORGANIC EL DISPLAY PANEL INCORPORATING DEPOSITION MASK - A deposition mask used in the manufacture of an organic EL display panel. A sheet of mask foil provided with a plurality of slit-shaped openings is fixed to a mask frame. Ends of successively arranged at least three openings are displaced from one another along the longitudinal direction of the openings. | 2012-06-14 |
20120146065 | LIGHTING EMITTING DEVICE, MANUFACTURING METHOD OF THE SAME, ELECTRONIC DEVICE HAVING THE SAME - One pixel is divided into a first region including a first light emitting element and a second region including a second light emitting element, wherein the first region emits light in one direction and the second region emits light in the direction opposite to that of the first region. Independently driving the first light emitting element and the second light emitting element allows images to be displayed independently on the surface. | 2012-06-14 |
20120146066 | HIGH EFFICIENCY LEDS AND LED LAMPS - The present invention relates to a light emitting device comprising a plurality of electrically coupled light emitting elements, wherein each light emitting element has a luminous efficacy vs. current characteristic, wherein said luminous efficacy vs. current characteristic has a maximum luminous efficacy value and wherein at least one of said light emitting devices is operated at a current corresponding to a luminous efficacy value that is within 10% of said maximum luminous efficacy value. The present invention also relates to methods of making said light emitting device, to lamps comprising said light emitting device and to methods of operating said light emitting device. | 2012-06-14 |
20120146067 | LIGHT EMITTING DEVICE - A light emitting device includes a supporting substrate, a first conductivity type layer of a first conductivity type provided on the supporting substrate, an active layer provided on the first conductivity type layer, a second conductivity type layer of a second conductivity type provided on the active layer, a first electrode being in contact with a part of the surface of the first conductivity type layer, and a second electrode being in contact with a part of the surface of the second conductivity type layer. The first electrode is in contact with a surface of the first conductivity type layer, and the surface is different from a surface of the first conductivity type layer corresponding to a region located directly above or below the active layer. | 2012-06-14 |
20120146068 | Semiconductor Light Source and Method of Fabrication Thereof - Embodiments of the present invention provided a method of fabricating a semiconductor light source structure. The method comprises providing a GaAs substrate; forming a lower cladding layer above the substrate, the lower cladding layer comprising an AI | 2012-06-14 |
20120146069 | Oxide Based LED BEOL Integration - A light emitting diode (LED) structure and method for making a light emitting diode are disclosed. The structure comprises deep trench metal electrodes between which electroluminescent material is disposed on the sidewalls of the electrodes, forming a series of luminescent diode elements stacked horizontally on a substrate. | 2012-06-14 |
20120146070 | LIGHT EMITTING CHIP AND METHOD FOR MANUFACTURING THE SAME - A light emitting chip includes a substrate, a heat conducting layer formed on the substrate, a protective layer formed on the heat conducting layer, a light emitting structure and a connecting layer connecting the protective layer with the light emitting structure. The heat conducting layer includes a plurality of horizontally grown carbon nanotube islands. The light emitting structure includes a first semiconductor layer, a light emitting layer and a second semiconductor layer. A first transparent conductive layer and a current conducting layer are sandwiched between the first semiconductor layer and the connecting layer. A second transparent conductive layer is formed on the second semiconductor layer. | 2012-06-14 |
20120146071 | LIGHT EMITTING CHIP AND METHOD FOR MANUFACTURING THE SAME - A light emitting chip includes a substrate, a heat conducting layer formed on the substrate, a light emitting structure and a connecting layer connecting the heat conducting layer with the light emitting structure. The heat conducting layer includes a plurality of spaced catalyst areas on the substrate and a plurality of carbon nanotube islands vertically grown from the catalyst areas. The light emitting structure includes a first semiconductor layer, a light emitting layer and a second semiconductor layer. A first transparent conductive layer and a current conducting layer are sandwiched between the first semiconductor layer and the connecting layer. A second transparent conductive layer is formed on the second semiconductor layer. | 2012-06-14 |
20120146072 | SEMICONDUCTOR LIGHT EMITTING ELEMENT - According to one embodiment, a semiconductor light emitting element includes a light emitting layer, a current spreading layer of a first conductivity type, and a pad electrode. The light emitting layer is capable of emitting light. The current spreading layer has a first surface and a second surface. The light emitting layer is disposed on a side of the first surface. A light extraction surface having convex structures of triangle cross-sectional shape and a flat surface which is a crystal growth plane are included in the second surface. The pad electrode is provided on the flat surface. One base angle of the convex structure is 90 degrees or more. | 2012-06-14 |
20120146073 | NIGHT VISION IMAGING SYSTEM (NVIS) COMPATIBLE LIGHT EMITTING DIODE - The present disclosure is directed to a LED assembly that is compatible for use with a night vision imaging system. Such LEDs may emit energy between 400 and 600 nm of the electromagnetic spectrum while limiting energy emissions between 600 and 1200 nanometers. Near infrared photochemistry is incorporated directly into the lens or encapsulant of an LED with an opaque package that limits transmission of visible and near infrared energy. | 2012-06-14 |
20120146074 | OPTICAL DEVICE - According to one embodiment, an optical device includes a lead, an optical element, and a sealing layer. The optical element is provided on the lead. The sealing layer is provided so as to cover the optical element. An upper surface of the sealing layer has a central portion including an optical axis of the optical element, a protrusion including an inner side surface surrounding the central portion and an outer side surface facing outward, and a connecting portion provided below the inner side surface and between the inner side surface and the central portion. The connecting portion includes a rounded portion on at least one of the inner side surface side and the central portion side. The outer side surface of the protrusion has average value of gradient angle larger than average value of gradient angle of a surface of the central portion. | 2012-06-14 |
20120146075 | Semiconductor light emitting element - A semiconductor light emitting element includes a semiconductor multilayer structure including a first conductive type layer, a second conductive type layer and a light emitting layer sandwiched between the first conductive type layer and the second conductive type layer, a first transparent electrode formed on the second conductive type layer, a reflecting layer formed on the first transparent electrode, and including a smaller area than the first transparent electrode, a second transparent electrode formed on the first transparent electrode so as to cover the reflecting layer, and a pad electrode formed on the second transparent electrode and in a region above the reflecting layer. | 2012-06-14 |
20120146076 | CONVERSION MEDIUM BODY, OPTOELECTRONIC SEMICONDUCTOR CHIP AND METHOD OF PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR CHIP - A method of producing an optoelectronic semiconductor chip includes providing a semiconductor layer sequence with at least one active layer, providing a one-piece conversion medium body, wherein a matrix material is incompletely crosslinked and/or cured, and wherein the conversion medium body exhibits at room temperature a hardness of Shore A 0 to Shore A 35 and/or a viscosity of 10 Pa·s to 150 Pa·s, placing the conversion medium body onto the semiconductor layer sequence such that they are in direct contact with one another, and curing the conversion medium body wherein after curing the hardness of the conversion medium body is Shore A 30 to Shore D 80. | 2012-06-14 |
20120146077 | LIGHT EMITTING DEVICE - A light emitting device | 2012-06-14 |
20120146078 | High Efficiency Conversion LED - A conversion LED with a chip which emits primary blue radiation, and a layer containing luminescent substance upstream of the chip which converts at least part of the primary radiation of the chip into secondary radiation, wherein a first garnet A3B5O12:Ce yellow-green emitting luminescent substance and a second nitride silicate M2X5Y8:D orange-red emitting luminescent substance is used, wherein the peak wavelength of the primary radiation is in the range of 430 to 450 nm, in particular of up to 445 nm, while the first luminescent substance is a garnet with the cation A=Lu or a mixture of Lu, Y with up a Y fraction of up to 30%, and wherein B has fractions of both Al and Ga, while the second luminescent substance is a nitride silicate which contains both Ba and Sr as cation M, and in which the doping consists of Eu, wherein the second luminescent substance contains 35 to 75 mol.-% Ba for the component M, remainder is Sr, where X=Si and Y=N. | 2012-06-14 |
20120146079 | Conversion LED with High Color Rendition Index - A conversion LED comprising a chip which emits primary radiation and, positioned upstream of the chip, a luminescent substance-containing layer which converts at least some of the primary radiation of the chip into secondary radiation, wherein a first yellow-green emitting luminescent substance of the A3B5O12:Ce garnet type and a second orange-red emitting luminescent substance of the MAlSiN3:Eu calsine type is used, wherein the peak wavelength of the primary radiation lies in the 435 to 455 nm range, the first luminescent substance being a garnet having essentially the cation A=Lu or Lu in combination with Y, and B simultaneously having fractions of Al and Ga, while the second luminescent substance is of the basic MAlSiN3:Eu type containing Ca as M with a fraction of at least 80%, in particular at least 90%, preferably at least 95%, where M is Ca alone or predominantly Ca and the remainder of M may be Sr, Ba, Mg, Li or Cu, in each case alone or in combination, and wherein some of the Al up to 20%, preferably at most 5%, can be replaced by B, O, F, Cl, alone or in combination. | 2012-06-14 |
20120146080 | LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - A light emitting device package includes substrate; first and second conduction members on the substrate; a light emitting diode on the substrate, the light emitting diode being electrically connected with the first and second conduction members; and a phosphor layer on the light emitting diode. | 2012-06-14 |
20120146081 | GaN COMPOUND SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a gallium nitride (GaN) compound semiconductor light emitting element (LED) and a method of manufacturing the same. The present invention provides a vertical GaN LED capable of improving the characteristics of a horizontal LED by means of a metallic protective film layer and a metallic support layer. According to the present invention, a metallic protective film layer with a thickness of at least 10 microns may be formed on the lateral and/or bottom sides of the vertical GaN LED. Further, a metallic substrate may be used instead of a sapphire substrate. A metallic support layer may be formed to protect the element from being distorted or damaged. Furthermore, a P-type electrode may be partially formed on a P—GaN layer in a mesh form. | 2012-06-14 |
20120146082 | LIGHT EMITTING PACKAGE - The present invention discloses a light emitting package, comprising: a base; a light emitting device on the base; an electrical circuit layer electrically connected to the light emitting device; a gold layer on the electrical circuit layer; a wire electrically connected between the light emitting device and the gold layer; a screen member having an opening and disposed on the base adjacent to the light emitting device; and a lens covering the light emitting device, wherein a bottom surface of the screen member is positioned higher than the light emitting device, and wherein an entire uppermost surface of the screen member is in contact with the lens. | 2012-06-14 |
20120146083 | VERTICAL LED WITH CURRENT-GUIDING STRUCTURE - Techniques for controlling current flow in semiconductor devices, such as LEDs are provided. For some embodiments, a current-guiding structure may be provided including adjacent high and low contact areas. For some embodiments, a second current path (in addition to a current path between an n-contact pad and a substrate) may be provided. For some embodiments, both a current-guiding structure and second current path may be provided. | 2012-06-14 |
20120146084 | LIGHT-EMITTING DIODE PACKAGE STRUCTURE - The present invention discloses a light-emitting diode (LED) package structure, which includes a housing, a first electrode plate, a second electrode plate, a light-emitting diode, and a voltage regulation diode. The housing has a top surface forming a cavity, and the cavity contains therein a wall that divides the cavity into a light emission section and a voltage regulation section. By separately arranging the light-emitting diode and the voltage regulation diode in two different sections of the light emission section and the voltage regulation section, the present invention prevents the voltage regulation diode from affecting light flux of the light-emitting diode by absorbing light, thereby enhancing overall lighting performance of the LED package structure. | 2012-06-14 |
20120146085 | DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A display substrate includes a substrate, a pixel part, a pad part and a sacrificial electrode. The substrate includes a display area and a peripheral area. The pixel part is on the display area and includes a switching element, and a pixel electrode electrically connected to the switching element. The pad part is on the peripheral area and contacts a terminal of an external device. The pad part includes a pad electrode a contact electrode. The pad electrode includes a first metal layer, and a second metal layer on the first metal layer, and the contact electrode contacts the second metal layer. The sacrificial electrode is spaced apart from the pad electrode and contacts the contact electrode. An exposed portion of the sacrificial electrode is exposed to an external side of the display substrate. | 2012-06-14 |
20120146086 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device having an n-electrode and a p-electrode provided on the same surface side of a semiconductor film, wherein current spread in the semiconductor film is promoted, so that the improvements in luminous efficiency and reliability, the emission intensity uniformalization across the surface, and a reduction in the forward voltage, can be achieved. The semiconductor light emitting device includes a semiconductor film including an n-type semiconductor layer, an active layer, and a p-type semiconductor layer; the n-electrode formed on an exposed surface of the n-type semiconductor layer exposed by removing parts of the p-type semiconductor layer, of the active layer, and of the n-type semiconductor layer with accessing from the surface side of the p-type semiconductor layer; and the p-electrode. A current guide portion having conductivity higher than that of the n-type semiconductor layer is provided on or in the n-type semiconductor layer over the p-type electrode. | 2012-06-14 |
20120146087 | LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A light-emitting device is disclosed. The light-emitting device comprises a substrate, an ion implanted layer on the substrate, a light-emitting stack layer disposed on the ion implanted layer, and an adhesive layer connecting the substrate with the light-emitting stack layer, wherein the adhesive layer comprises a thin silicon film disposed between the ion implanted layer and the light-emitting layer. This invention also discloses a method of manufacturing a light-emitting device comprising the steps of forming a light-emitting stack layer, forming a thin silicon film on the light-emitting stack layer, providing a substrate, forming an ion implanted layer on the substrate, and providing an electrode potential difference to form an oxide layer between the thin silicon film and the ion implanted layer. | 2012-06-14 |
20120146088 | ENCAPSULANT FOR OPTICAL SEMICONDUCTOR DEVICE AND OPTICAL SEMICONDUCTOR DEVICE USING SAME - The present invention provides a sealant for an optical semiconductor device which is less likely to reduce its luminance and is also less likely to change its color even used in an energized state in harsh environments of high temperature and high humidity. | 2012-06-14 |
20120146089 | FOUR-QUADRANT TRIAC - A vertical four-quadrant triac wherein the gate region, arranged on the side of a front surface, includes a U-shaped region of a first conductivity type, the base of the U lying against one side of the structure, the main front surface region of the second conductivity type extending in front of the gate region and being surrounded with portions of the main front surface region of the first conductivity type. | 2012-06-14 |
20120146090 | SELF ALIGNED TRENCH MOSFET WITH INTEGRATED DIODE - Transistor devices can be fabricated with an integrated diode using a self-alignment. The device includes a doped semiconductor substrate having one or more electrically insulated gate electrodes formed in trenches in the substrate. One or more body regions are formed in a top portion of the substrate proximate each gate trench. One or more source regions are formed in a self-aligned fashion in a top portion of the body regions proximate each gate trench. One or more thick insulator portions are formed over the gate electrodes on a top surface of the substrate with spaces between adjacent thick insulator portions. A metal is formed on top of the substrate over the thick insulator portions. The metal forms a self-aligned contact to the substrate through the spaces between the thick insulator portions. An integrated diode is formed under the self-aligned contact. | 2012-06-14 |
20120146091 | INSULATED GATE SEMICONDUCTOR DEVICE - An insulated gate semiconductor device includes a first conductivity-type semiconductor substrate, a second conductivity-type base layer on a first surface side of the substrate, a trench dividing the base layer into channel and floating layers, and a first conductivity-type emitter region that is formed in the channel layer and in contact with the trench. The semiconductor device includes a gate insulation layer in the trench, a gate electrode on the insulation layer, an emitter electrode electrically connected to the emitter region and the floating layer, a second conductivity-type collector layer in the substrate, and a collector electrode on the collector layer. The floating layer has a lower impurity concentration than the channel layer. The floating layer has a first conductivity-type hole stopper layer located at a predetermined depth from the first surface of the substrate and at least partially spaced from the insulation layer. | 2012-06-14 |
20120146092 | STRUCTURE AND METHOD FOR MOBILITY ENHANCED MOSFETS WITH UNALLOYED SILICIDE - While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices. | 2012-06-14 |
20120146093 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes a semiconductor multilayer formed on a substrate, a first ohmic electrode and a Schottky electrode spaced apart from each other on the semiconductor multilayer; and a passivation film covering a top of the semiconductor multilayer. The semiconductor multilayer | 2012-06-14 |
20120146094 | NITRIDE BASED SEMICONDUCTOR DEVICE - Disclosed herein is a nitride based semiconductor device. There is provided a nitride based semiconductor device including: a base substrate; a semiconductor layer disposed on the base substrate; and an electrode structure disposed on the semiconductor layer, wherein the electrode structure includes: a cathode structure ohmic-contacting the semiconductor layer; and an anode structure having a schottky electrode schottky-contacting the semiconductor layer and an ohmic electrode ohmic-contacting the nitride layer. | 2012-06-14 |
20120146095 | NITRIDE BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein is a nitride based semiconductor device including: a base substrate; an epitaxial growth layer disposed on the base substrate and generating a 2-dimensional electron gas in an inner portion thereof; and an electrode structure disposed on the epitaxial growth layer, wherein the electrode structure includes: a gate electrode; a source electrode disposed at one side of the gate electrode; and a drain electrode disposed at the other side of the gate electrode and having an extension part extended to the inner portion of the epitaxial growth layer to contact the 2-dimensional electron gas. | 2012-06-14 |
20120146096 | NITRIDE BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein is a nitride based semiconductor device. There is provided a nitride based semiconductor device according to the exemplary embodiment of the present invention including: a base substrate, an epitaxial growth layer disposed on the base substrate and generating 2-dimensional electron gas ( | 2012-06-14 |
20120146097 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer disposed over a substrate, a second semiconductor layer disposed over the first semiconductor layer, a gate recess disposed, through removal of a part of or all the second semiconductor layer, in a predetermined region over the first semiconductor layer, an insulating film disposed over the gate recess and the second semiconductor layer, a gate electrode disposed over the gate recess with the insulating film therebetween, and a source electrode and a drain electrode disposed over the first semiconductor layer or the second semiconductor layer, whereby a central portion of the gate recess is higher than a peripheral portion of the gate recess. | 2012-06-14 |
20120146098 | DEVICE ISOLATION WITH IMPROVED THERMAL CONDUCTIVITY - A method of making a semiconductor structure includes forming a trench through a shallow trench isolation (STI) structure and into a substrate, and forming a liner including an electrical insulator material on sidewalls of the trench. The method also includes forming a core including a high thermal conductivity material in the trench and on the liner, and forming a cap in the trench and on the core. | 2012-06-14 |
20120146099 | RECONFIGURABLE RF/DIGITAL HYBRID 3D INTERCONNECT - Reconfigurable | 2012-06-14 |
20120146100 | SOLID STATE IMAGE PICKUP DEVICE AND MANUFACTURING METHOD THEREFOR - A MOS-type solid-state image pickup device is provided on a semiconductor substrate and includes a photoelectric conversion unit having a first semiconductor region, a second semiconductor region, and a third semiconductor region. A transfer gate electrode is disposed on an insulation film and transfers a carrier from the second semiconductor region to a fourth semiconductor region, and an amplifying MOS transistor has a gate electrode connected to the fourth semiconductor region. In addition, a fifth semiconductor region is continuously disposed to the second semiconductor region, under the gate electrode. An entire surface of the third semiconductor region is covered with the insulation film, and a side portion of the third semiconductor region that is laterally opposite to the transfer gate is in contact with the first semiconductor region. | 2012-06-14 |
20120146101 | MULTI-GATE TRANSISTOR DEVICES AND MANUFACTURING METHOD THEREOF - A method for manufacturing multi-gate transistor devices includes providing a semiconductor substrate having a first patterned hard mask for defining at least a first fin formed thereon, forming the first fin having a first crystal plane orientation on the semiconductor substrate, forming a second patterned hard mask for defining at least a second fin on the semiconductor substrate, forming the second fin having a second crystal plane orientation that is different from the first crystal plane orientation on the semiconductor substrate, forming a gate dielectric layer and a gate layer covering a portion of the first fin and a portion of the second fin on the semiconductor substrate, and forming a first source/drain in the first fin and a second source/drain in the second fin, respectively. | 2012-06-14 |
20120146102 | TRANSISTOR AND SEMICONDUCTOR DEVICE - An accumulation mode transistor has an impurity concentration of a semiconductor layer in a channel region at a value higher than 2×10 | 2012-06-14 |
20120146103 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present application discloses a semiconductor device and a method of manufacturing the same. Wherein, the semiconductor device comprises: a semiconductor substrate; a stressor embedded in the semiconductor substrate; a channel region disposed on the stressor; a gate stack disposed on the channel region; a source/drain region disposed on two sides of the channel region and embedded in the semiconductor substrate; wherein, surfaces of the stressor comprise a top wall, a bottom wall, and side walls, the side walls comprising a first side wall and a second side wall, the first side wall connecting the top wall and the second side wall, the second side wall connecting the first side wall and the bottom wall, the angle between the first side wall and the second side wall being less than | 2012-06-14 |
20120146104 | STRUCTURE AND LAYOUT OF A FET PRIME CELL - Method of making a semiconductor device that includes forming a source and a drain in a substrate, forming a gate on the substrate between the source and drain, forming a substrate contact in electrical contact with the source, and forming an electrical contact to the source, drain and gate, and the substrate. | 2012-06-14 |
20120146105 | High-voltage transistor device with integrated resistor - A high-voltage device structure comprises a resistor coupled to a tap transistor that includes a JFET in a configuration wherein a voltage provided at a terminal of the JFET is substantially proportional to an external voltage when the external voltage is less than a pinch-off voltage of the JFET. The voltage provided at the terminal being substantially constant when the external voltage is greater than the pinch-off voltage. One end of the resistor is substantially at the external voltage when the external voltage is greater than the pinch-off voltage. When the external voltage is negative, the resistor limits current injected into the substrate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. | 2012-06-14 |
20120146106 | SEMICONDUCTOR DEVICES HAVING THROUGH-CONTACTS AND RELATED FABRICATION METHODS - Apparatus for semiconductor device structures and related fabrication methods are provided. One method for fabricating a semiconductor device structure involves forming a layer of dielectric material overlying a doped region formed in a semiconductor substrate adjacent to a gate structure and forming a conductive contact in the layer of dielectric material. The conductive contact overlies and electrically connects to the doped region. The method continues by forming a second layer of dielectric material overlying the conductive contact, forming a voided region in the second layer overlying the conductive contact, forming a third layer of dielectric material overlying the voided region, and forming another voided region in the third layer overlying at least a portion of the voided region in the second layer. The method continues by forming a conductive material that fills both voided regions to contact the conductive contact. | 2012-06-14 |
20120146107 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed are a semiconductor device and a method of manufacturing the same. In the semiconductor device according to an exemplary embodiment of the present disclosure, at the time of forming a source electrode, a drain electrode, a field plate electrode, and a gate electrode on a substrate having a heterojunction structure such as AlGaN/GaN, the field plate electrode made of the same metal as the gate electrode is formed on the side surface of a second support part positioned below a head part of the gate electrode so as to prevent the gate electrode from collapsing and improve high-frequency and high-voltage characteristic of the semiconductor device. | 2012-06-14 |
20120146108 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and an opposite second surface; a drain region located in the semiconductor substrate; a source region located in the semiconductor substrate; a gate located on the semiconductor substrate or at least partially buried in the semiconductor substrate, wherein a gate dielectric layer is between the gate and the semiconductor substrate; a drain conducting structure disposed on the first surface of the semiconductor substrate and electrically connected to the drain region; a source conducting structure disposed on the second surface of the semiconductor substrate and electrically connected to the source region; and a gate conducting structure disposed on the first surface of the semiconductor substrate and electrically connected to the gate. | 2012-06-14 |
20120146109 | SEMICONDUCOR DEVICE - A semiconductor device such as a transistor with an excellent OFF characteristic even when a channel is short is provided. A periphery of a source is surrounded by an extension region and a halo region, a periphery of a drain is surrounded by an extension region and a halo region, and a substrate with low impurity concentration is not in contact with the source or the drain. Moreover, a high-work-function electrode is provided via a gate insulator, and electrons entering the vicinity of a surface of the substrate from the extension regions are eliminated. With such a structure, the impurity concentration of the channel region can be decreased even when the channel is short, and a favorable transistor characteristic can be obtained. | 2012-06-14 |
20120146110 | SEMICONDUCTOR DEVICE AND FORMING METHOD OF THE SAME - A semiconductor device includes contact structures and conductive wires formed over the contact structures and coupled to the respective contact structures. Part of each of the conductive wires crosses the contact structure. | 2012-06-14 |
20120146111 | CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - An embodiment of the invention provides a chip package including a semiconductor substrate, a drain electrode, a source electrode and a gate electrode. The semiconductor substrate has a first surface and an opposite second surface wherein the second surface has a recess. The drain electrode is disposed on the first surface and covers the recess. The source electrode is disposed on the second surface in a position corresponding to the drain electrode covering the recess. The gate electrode is disposed on the second surface. An embodiment of the invention further provides a manufacturing method of a chip package. | 2012-06-14 |
20120146112 | FINFET WITH REDUCED GATE TO FIN OVERLAY SENSITIVITY - Embodiments of the invention provide a relatively uniform width fin in a Fin Field Effect Transistors (FinFETs) and apparatus and methods for forming the same. A fin structure may be formed such that the surface of a sidewall portion of the fin structure is normal to a first crystallographic direction. Tapered regions at the end of the fin structure may be normal to a second crystal direction. A crystallographic dependent etch may be performed on the fin structure. The crystallographic dependent etch may remove material from portions of the fin normal to the second crystal direction relatively faster, thereby resulting in a relatively uniform width fin structure. | 2012-06-14 |
20120146113 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device, the method comprising: forming a metal containing film on a substrate; exposing the metal containing film to an ammonia radical in a reaction chamber; evacuating gas generated in the exposing by supplying an inert gas into the reaction chamber; and after repeating the exposing and the supplying a predetermined number of times, forming a silicon nitride film covering the metal containing film in the reaction chamber without atmospheric exposure. | 2012-06-14 |
20120146114 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device according to an embodiment includes: forming a plurality of semiconductor layers located at a distance from one another on a first insulating film; forming a gate insulating film that covers both side faces and an upper face of each of the semiconductor layers; forming a gate electrode of a polysilicon film to cover the gate insulating film of each of the semiconductor layers; forming a second insulating film on an entire surface; exposing an upper face of the gate electrode by performing selective etching on a portion of the second insulating film; siliciding the gate electrode; and forming a stress applying film that applies a stress in a direction perpendicular to the extending direction of each of the semiconductor layers and parallel to an upper face of the first insulating film. | 2012-06-14 |
20120146115 | Design Structure, Methods, and Apparatus Involving Photoconductor-on-Active Pixel Devices - A design structure embodied in a machine readable medium used in a design process includes a first dielectric layer disposed on an intermediary layer, a first conductive pad portion and a first interconnect portion disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer, a first capping layer disposed on the first interconnect portion and a portion of the first conductive pad portion, a second capping layer disposed on the first capping layer and a portion of the second dielectric layer, an n-type doped silicon layer disposed on the second capping layer and the first conductive pad portion, an intrinsic silicon layer disposed on the n-type doped silicon layer, and a p-type doped silicon layer disposed on the intrinsic silicon layer. | 2012-06-14 |
20120146116 | BACK SIDE ILLUMINATION TYPE SOLID STATE IMAGING DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, an imaging device includes a semiconductor substrate having a first conductivity type, a well region which is arranged on a front surface side of the semiconductor substrate and has the first conductivity type, photodiodes which are arranged in the well region and have a second conductivity type, a diffusion layer which is arranged between the photodiodes, supplies a potential to the well region, and has the first conductivity type, an overflow drain layer which is arranged on a back surface side of the semiconductor substrate and has the second conductivity type, an overflow drain electrode which extends from the front surface side of the semiconductor substrate to the overflow drain layer and supplies a bias potential to the overflow drain layer from the front surface side of the semiconductor substrate, and a wiring layer which is arranged on the front surface of the semiconductor substrate. | 2012-06-14 |
20120146117 | SOLID-STATE IMAGING DEVICE - A solid-state imaging device includes: a first photodiode receiving light of a first color; a second photodiode that is arranged next to the first photodiode in a first direction and receives light of a second color; a third photodiode that is arranged next to the second photodiode in a second direction and receives light of the first color; a fourth photodiode that is arranged next to the third photodiode in the first direction and receives light of a third color; a first reset transistor for discharging a charge generated in the first photodiode and the second photodiode; and a second reset transistor for discharging a charge generated in the third photodiode and the fourth photodiode. The first photodiode and the third photodiode have a small difference in area. | 2012-06-14 |
20120146118 | NON-VOLATILE MEMORY DEVICE WITH HIGH SPEED OPERATION AND LOWER POWER CONSUMPTION - A semiconductor memory device has a memory cell region and a peripheral region. The device includes low voltage transistors at the peripheral region having gate insulation films with different thicknesses. For example, a gate insulation film of a low voltage transistor used in an input/output circuit of the memory device may be thinner than the gate insulation film of a low voltage transistor used in a core circuit for the memory device. Since low voltage transistors used at an input/output circuit are formed to be different from low voltage transistors used at a core circuit or a high voltage pump circuit, high speed operation and low power consumption characteristics of a non-volatile memory device may be. | 2012-06-14 |
20120146119 | Semiconductor Device - A semiconductor device to improve layout uniformity may include an active region formed in a substrate, a dummy active region formed in the substrate and separated from the active region, a word line crossing over the active region, and a dummy word line. The dummy word line is formed over the dummy active region to overlap at least part of the dummy active region and may have an end positioned within the dummy active region. | 2012-06-14 |
20120146120 | Non-Volatile Memory Device - A non-volatile memory device includes memory cell active regions and common source active regions extending in parallel on a semiconductor substrate, a self aligned source active region disposed on the semiconductor substrate that intersects the memory cell active regions and the common source active regions and connects the memory cell active regions to the common source active regions, word lines disposed on the memory cell active regions and the common source active regions that intersect the memory cell active regions and the common source active regions, and memory cell transistors formed by the intersection of the word lines and the memory cell active regions, and common source line transistors formed by the intersection of the word lines and the common source active regions, wherein source and drain regions of each of the common source line transistors are separated from each other in the semiconductor substrate. | 2012-06-14 |
20120146121 | SEMICONDUCTOR DEVICE INCLUDING LINE-TYPE ACTIVE REGION AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having a line-type active region and a method for manufacturing the same are disclosed. The semiconductor device includes an active region configured in a successive line type, at least one active gate having a first width and crossing the active region, and an isolation gate having a second width different from the first width and being formed between the active gates. The isolation gate's width and the active gate's width are different from each other to guarantee a large storage node contact region, resulting in increased device operation characteristics (write characteristics). | 2012-06-14 |
20120146122 | 3-D NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A three-dimensional (3-D) non-volatile memory device includes a plurality of word line structures extended in parallel and including a plurality of interlayer dielectric layers and a plurality of word lines that are alternately stacked over a substrate, a plurality of channels protruding from the substrate configured to penetrate the plurality of interlayer dielectric layers and the plurality of word lines, and an air gap formed between the plurality of word line structures. | 2012-06-14 |
20120146123 | SCALABLE FLASH EEPROM MEMORY CELL WITH FLOATING GATE SPACER WRAPPED BY CONTROL GATE AND METHOD OF MANUFACTURE - A flash memory cell includes a substrate having a surface region and a flash memory cell structure on the surface region. The flash memory cell structure includes a gate dielectric layer on the surface region, a select gate on the gate dielectric layer, a cap oxide layer on the select gate, an oxide spacer on a first edge of the select gate, a tunnel oxide layer on a first region and on a second region of the surface region. The second region is an active region. The flash memory cell structure further includes a poly spacer on the first edge of the oxide spacer and a portion of the tunnel oxide layer on the first region, an ONO layer on at least the poly spacer and a control gate layer on the ONO layer. | 2012-06-14 |
20120146124 | NON-VOLATILE STORAGE ELEMENT HAVING DUAL WORK-FUNCTION ELECTRODES - A non-volatile storage element and a method of forming the storage element. The non-volatile storage element comprises: a first electrode including a first material having a first work function; a second electrode including a second material having a second work function higher than the first work function; a first dielectric disposed between the first electrode and the second electrode, the first dielectric having a first bandgap; a second dielectric disposed between the first dielectric and the second electrode, the second dielectric having a second bandgap wider than the first bandgap and being disposed such that a quantum well is created in the first dielectric; and a third dielectric disposed between the first electrode and the first dielectric, the third dielectric being thinner than the second dielectric and having a third bandgap wider than the first bandgap. | 2012-06-14 |
20120146125 | NON-VOLATILE MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - A non-volatile memory device comprises a substrate, a control gate electrode on the substrate, and a charge storage region between the control gate electrode and the substrate. A control gate mask pattern is on the control gate electrode, the control gate electrode comprising a control base gate and a control metal gate on the control base gate. A width of the control metal gate is less than a width of the control gate mask pattern. An oxidation-resistant spacer is at sidewalls of the control metal gate positioned between the control gate mask pattern and the control base gate. | 2012-06-14 |
20120146126 | HIGH-K CAPPED BLOCKING DIELECTRIC BANDGAP ENGINEERED SONOS AND MONOS - A blocking dielectric engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking dielectric including a buffer layer in contact with the charge trapping element, such as silicon dioxide which can be made with high-quality, and a second capping layer in contact with said one of the gate and the channel. The capping layer has a dielectric constant that is higher than that of the first layer, and preferably includes a high-κ material. The second layer also has a conduction band offset that is relatively high. A bandgap engineered tunneling layer between the channel and the charge trapping element is provided which, in combination with the multilayer blocking dielectric described herein, provides for high-speed erase operations by hole tunneling. In an alternative, a single layer tunneling layer is used. | 2012-06-14 |
20120146127 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a pipe gate having a pipe channel hole; a plurality of interlayer insulation layers and a plurality of gate electrodes alternately stacked over the pipe gate; a pair of columnar cell channels passing through the interlayer insulation layers and the gate electrodes and coupling a pipe channel formed in the pile channel hole; a first blocking layer and a charge trapping and charge storage layer formed on sidewalk of the columnar cell channels; and a second blocking layer formed between the first blocking layer and the plurality of gate electrodes. | 2012-06-14 |
20120146128 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - In a nonvolatile semiconductor memory device provided with memory cell transistors arranged in a direction and a select transistor to select the memory cell transistors, each of the memory cell transistors of a charge trap type are at least composed of a first insulating layer and a first gate electrode respectively, and the select transistor is at least composed of a second insulating layer and a second gate electrode. The first gate electrode is provided with a first silicide layer of a first width formed on the first insulating layer. The second gate electrode is provided with an impurity-doped silicon layer formed on the second insulating layer and with a second silicide layer of a second width formed on the impurity-doped silicon layer. The second silicide has the same composition as the first silicide. The second width is larger than the first width. | 2012-06-14 |
20120146129 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE - A semiconductor device capable of ensuring a withstand voltage of a transistor and reducing a forward voltage of a Schottky barrier diode in a package with the transistor and the Schottky barrier diode formed on chip, and a semiconductor package formed by a resin package covering the semiconductor device are provided. The semiconductor device | 2012-06-14 |
20120146130 | SEMICONDUCTOR COMPONENT WITH A SEMICONDUCTOR VIA - A method for producing a semiconductor component includes providing a semiconductor body with a first surface and a second surface opposite the first surface, forming an insulation trench which extends into the semiconductor body from the first surface and which in a horizontal plane of the semiconductor body has a geometry such that the insulation trench defines a via region of the semiconductor body, forming a first insulation layer on one or more sidewalls of the insulation trench, removing semiconductor material of the semiconductor body from the second surface to expose at least parts of the first insulation layer, to remove at least parts of the first insulation layer, or to leave at least partially a semiconductor layer with a thickness of less than 1 μm between the first insulation layer and the second surface, and forming first and second contact electrodes on the via region. | 2012-06-14 |
20120146131 | VERTICAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A vertical semiconductor device includes a first active pillar vertically protruded from a semiconductor substrate; a first vertical gate connected to at least one side of the first active pillar and formed along a direction that crosses a buried bit line; and a first body line connected to at least one side of the first active pillar which is not connected to the first vertical gate. | 2012-06-14 |
20120146132 | MEMORY ARRAY WITH SURROUNDING GATE ACCESS TRANSISTORS AND CAPACITORS WITH GLOBAL AND STAGGERED LOCAL BIT LINES - A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned generally atop a corresponding local data/bit line. Selected columns of the memory cell access transistors are sacrificed to define local data/bit access transistors which are interconnected with overlying low resistance global data/bit lines. The global data/bit lines provide selectable low resistance paths between memory cells and sense amplifiers. The sacrificed memory cell access transistors and staggered local data/bit lines provide increased footprints for sense amplifiers to facilitate increased circuit integration. | 2012-06-14 |
20120146133 | Method for Producing a Semiconductor Component with Insulated Semiconductor Mesas - A method for producing a semiconductor component is provided. The method includes providing a semiconductor body with a first surface and a second surface opposite to the first surface, etching an insulation trench from the first surface partially into the semiconductor body, forming a first insulation layer on one or more sidewalls of the insulation trench, processing the second surface by at least one of grinding, polishing and a CMP-process to expose the first insulation layer, and depositing on the processed second surface a second insulation layer which extends to the first insulation layer. | 2012-06-14 |
20120146134 | COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURE PROCESS THEREOF - A compound semiconductor device includes a compound semiconductor layer, a gate electrode disposed above the compound semiconductor layer, and a gate insulation film. The gate insulation film is interposed between the compound semiconductor layer and the gate electrode. The gate insulation film contains a fluorine compound at least in the vicinity of the interface with the compound semiconductor layer. | 2012-06-14 |
20120146135 | METHOD AND A STRUCTURE FOR ENHANCING ELECTRICAL INSULATION AND DYNAMIC PERFORMANCE OF MIS STRUCTURES COMPRISING VERTICAL FIELD PLATES - In an MIS structure a field plate electrode is incorporated below a buried gate electrode by using an insulating oxide layer, which is formed concurrently with the gate dielectric layer. In order to obtain superior dynamic behavior and enhanced dielectric strength the oxidation behavior of the field plate electrode is modified, for instance by incorporating a desired high concentration of arsenic. | 2012-06-14 |
20120146136 | VERTICAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A vertical semiconductor device includes a first pillar and a second pillar, a first bit line contact formed at a lower portion of a first sidewall of the first pillar, a second bit line contact formed at a lower portion of a second sidewall of the second pillar which face the first sidewall of the first pillar, a bit line commonly connected to the first bit line contact and the second bit line contact, and a gate formed at both sides of the first pillar and the second pillar to be crossed with the bit line. | 2012-06-14 |
20120146137 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTORDEVICE - A semiconductor device according to the present invention includes a semiconductor layer. A first conductivity type region is formed on a base layer portion of the semiconductor layer. A body region of a second conductivity type is formed on the semiconductor layer to be in contact with the first conductivity type region. A trench in which a gate electrode is embedded through a gate insulating film is formed on the semiconductor layer. The trench penetrates through the body region, so that a deepest portion thereof reaches the first conductivity type region. A source region of the first conductivity type is formed on a surface layer portion of the semiconductor layer around the trench. The gate insulating film includes a thick-film portion having a relatively large thickness on a bottom surface of the trench. | 2012-06-14 |
20120146138 | POWER DEVICE WITH LOW PARASITIC TRANSISTOR AND METHOD OF MAKING THE SAME - The power device with low parasitic transistor comprises a recessed transistor and a heavily doped region at a side of a source region of the recessed transistor. The conductive type of the heavily doped region is different from that of the source region. In addition, a contact plug contacts the heavily doped region and connects the heavily doped region electrically. A source wire covers and contacts the source region and the contact plug to make the source region and the heavily doped region have the same electrical potential. | 2012-06-14 |
20120146139 | HIGH VOLTAGE SEMICONDUCTOR DEVICE - A semiconductor device for a high voltage application includes a doped source base region, an N+ source region, a P+ source region and a gate structure. The doped source base region has P-type. The N+ source region extends downwards into the doped source base region. The P+ source region is close to the N+ source region, extends downwards into the doped source base region, and is doped heavier than the doped source base region. The gate structure is coupled to the N+ source region and is near to the P+ source region. | 2012-06-14 |
20120146140 | HIGH-VOLTAGE SEMICONDUCTOR DEVICE WITH LATERAL SERIES CAPACITIVE STRUCTURE - A semiconductor device includes a semiconductor substrate, a source region extending along a top surface of the semiconductor substrate, a drain region extending along the top surface of the semiconductor substrate, and a field shaping region disposed within the semiconductor substrate between the source region and the drain region. A cross-section of the semiconductor substrate extending from the source region to the drain region through the field shaping region includes an insulating region. The semiconductor device also includes an active region disposed within the semiconductor substrate between the source region and the drain region. The active region is disposed adjacent to the field shaping region in a direction perpendicular to the cross-section of the semiconductor substrate extending from the source region to the drain region through the field shaping region. | 2012-06-14 |
20120146141 | ELECTRONIC CIRCUIT CONTROL ELEMENT WITH TAP ELEMENT - A technique for controlling a power supply with power supply control element with a tap element. An example power supply control element includes a power transistor that has first and second main terminals, a control terminal and a tap terminal. A control circuit is coupled to the control terminal. The tap terminal and the second main terminal of the power transistor are to control switching of the power transistor. The tap terminal is coupled to provide a signal to the control circuit substantially proportional to a voltage between the first and second main terminals when the voltage is less than a pinch off voltage. The tap terminal is coupled to provide a substantially constant voltage that is less than the voltage between the first and second main terminals to the control circuit when the voltage between the first and second main terminals is greater than the pinch-off voltage. | 2012-06-14 |
20120146142 | MOS TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a MOS transistor and a method for manufacturing the same. The MOS transistor includes: a SOI substrate comprising a silicon substrate layer, an ultra-thin BOX layer, and an ultra-thin SOI layer; a metal gate layer formed on the SOI substrate; and a ground halo region formed in the silicon substrate layer and beneath the metal gate layer. The method for manufacturing a MOS transistor comprises: providing a SOI substrate, which comprises a silicon substrate layer, an ultra-thin BOX layer, and an ultra-thin SOI layer: forming a dummy gate conductive layer on the SOI substrate and a plurality of spacers surrounding the dummy gate conductive layer, removing the dummy gate conductive layer to form a opening; performing an ion-implantation process in the opening to form a ground halo region in the silicon substrate layer; and forming a metal gate layer in the opening. | 2012-06-14 |