24th week of 2014 patent applcation highlights part 17 |
Patent application number | Title | Published |
20140159074 | EL DISPLAY DEVICE AND METHOD FOR MANUFACTURING SAME - An EL display device of the present invention includes a plurality of pixel electrodes, wiring, a common electrode, a plurality of light-emitting layer portions, and a protective layer. The pixel electrodes are formed in one-to-one correspondence with a plurality of pixels. The wiring is formed in at least one of a plurality of intervals between the pixels. The common electrode is formed above each of the pixel electrodes and is in electrical connection with the wiring. The common electrode is made of alkali metal or alkaline earth metal. The light-emitting layer portions are each located between a corresponding one of the pixel electrodes and the common electrode. The protective layer is located on the common electrode, preventing oxidization thereof. The EL display device suppresses voltage drop in the common electrode, while also suppressing reduction in a property of electron injection to the light-emitting layer portions. | 2014-06-12 |
20140159075 | LIGHT-EMITTING DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - A light-emitting device package uses a metal layer as a reflective region and includes a light-emitting device chip and an electrode pad that are disposed on an insulating layer. In addition, the electrode pad and an electrode pattern of a printed circuit board are connected to each other by an electrode pattern formed of conductive ink. A method of manufacturing a light-emitting device package includes forming an insulating layer on a metal layer, and bonding a light-emitting device chip and an electrode pad on the insulating layer. The electrode pad and a printed circuit board are connected to each other by conductive ink. | 2014-06-12 |
20140159076 | LIGHT-EMITTING DEVICE - Improves light extraction efficiency. A light emitting device | 2014-06-12 |
20140159077 | SYSTEM FOR THERMAL CONTROL OF RED LED(S) CHIPS - A light emitting diode assembly includes a first light emitting diode disposed on a first substrate and a second light emitting diode disposed on a second substrate that is disposed substantially adjacent to the first substrate. The second light emitting diode has a higher rate of performance degradation over time due to temperature than the first light emitting diode. A heat sink is thermally coupled to the first substrate and an electrical cooling circuit is thermally coupled to the second substrate. The electrical cooling circuit is configured to reduce a temperature of the second substrate when the electrical cooling circuit is electrically energized. | 2014-06-12 |
20140159078 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device and a method of manufacturing the display device are disclosed. In one aspect, the display device includes a first substrate, a light-emitting portion formed on the first substrate, and a sealing portion which is attached to the first substrate so as to shield the light-emitting portion from ambient environmental conditions. At least a portion of an edge of the first substrate is chamfered. | 2014-06-12 |
20140159079 | COST-EFFECTIVE LED LIGHTING INSTRUMENT WITH GOOD LIGHT OUTPUT UNIFORMITY - The present disclosure involves a lighting instrument. The lighting instrument includes a board or substrate, for example, a printed circuit board. The lighting instrument also includes a plurality of light-emitting devices disposed on the substrate. The light-emitting devices may be light-emitting diode (LED) dies. The LED dies belong to a plurality of different bins. The bins are categorized based on the light output performance of the LED dies. In some embodiments, the LED dies may be binned based on the wavelength or radiant flux of the light output. The LED dies are distributed on the substrate according to a predefined pattern based on their bins. In some embodiments, the LED dies are bin-mixed in an interleaving manner. | 2014-06-12 |
20140159080 | LED LAMP - A LED lamp is disclosed which has a plurality of light unit, each of the light unit has at least one flat metal lead for heat dissipation and the lower part of the metal lead is mounted on a heat sink for a further heat dissipation. | 2014-06-12 |
20140159081 | METHOD OF FORMING SEMICONDUCTOR LAYER AND SEMICONDUCTOR LIGHT EMITTING DEVICE - A method of forming a semiconductor layer is provided. The method includes forming a plurality of nanorods on a substrate and forming a lower semiconductor layer on the substrate so as to expose at least portions of the nanorods.
| 2014-06-12 |
20140159082 | LIGHT-EMITTING DEVICE - A light-emitting device including a substrate, a photoelectric structure and a coarse structure is provided. The substrate has an upper surface and a lower surface opposite to each other, and an annular side surface connecting the upper surface and the lower surface. The photoelectric structure is disposed on the upper surface of the substrate. The coarse structure is formed on the annular side surface of the substrate. A ratio of a thickness of the substrate and a thickness of the coarse structure is greater than or equal to 1 and less than or equal to 20. Therefore, the overall light-emitting efficiency of the light-emitting device may be improved. | 2014-06-12 |
20140159083 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND FABRICATION METHOD THEREOF - A semiconductor light emitting device includes a first conductivity-type semiconductor layer, an active layer, a second conductivity-type semiconductor layer, an insulating region formed along the outer edges of an upper surface of the second conductivity-type semiconductor layer, and an ohmic-electrode layer disposed on the second conductivity-type semiconductor layer. | 2014-06-12 |
20140159084 | LED DOME WITH IMPROVED COLOR SPATIAL UNIFORMITY - A light emitting diode (LED) package comprising an encapsulant designed to improve color spatial uniformity in comparison to hemispherical encapsulants is described. In some embodiments, the encapsulant comprises a segment of a hemisphere as a lower portion and an upper portion of a second shape. In some embodiments this second shape is defined by a spline curve. The encapsulant improves color uniformity over a wide range of angles while only minimally affecting other attributes such as photometric polar distribution, extraction efficiency, and luminous intensity. Embodiments of the present invention can also utilize light emitting systems comprising such LED packages. | 2014-06-12 |
20140159085 | LIGHT EMITTING DIODE PACKAGE AND MANUFACTURING METHOD THEREOF - A light emitting package includes a circuit board, a light emitting chip disposed on the circuit board and electrically connected to the circuit board, a resin layer disposed on the light emitting chip, and a fluorescent layer disposed on the resin layer. The light emitting chip is disposed between the resin layer and the circuit board. The resin layer is disposed between the light emitting chip and the fluorescent layer. For a light, a refractive index of the resin layer is smaller than a refractive index of the light emitting chip and is larger than a refractive of the fluorescent layer. | 2014-06-12 |
20140159086 | ACTIVE DEVICE ARRAY SUBSTRATE AND DISPLAY PANEL - An active device array substrate and a display panel are provided. The active device array substrate includes a substrate, a first conductor layer, a gate dielectric layer, a second conductor layer, an overcoat layer, a transparent electrode, a capacitive layer and pixel electrodes. The first conductor layer includes gate lines and light-shielding patterns. The gate dielectric layer covers the first conductor layer. The second conductor layer includes data lines and drain electrodes. Each of the data lines correspondingly overlaps one of the light-shielding patterns. The transparent electrode covers the overcoat layer. The pixel electrode is disposed on the capacitive layer and covers a portion of the shielding pattern. Each of the light-shielding patterns has a width greater than that of the overlapping data line. The gap between the edge of the light-shielding pattern and that of the overlapping data line is not greater than 2.5 microns. | 2014-06-12 |
20140159087 | LIGHT EMITTING DEVICE - A light emitting device comprising a carrier, a first and a second reflective layers, a first and a second micro-structures, a LED package device, a light guide device and a light directing cover is provided. The carrier comprises an upper plate and a lower plate each having a first surface and a second surface. The lower plate has a through hole. The first and second reflective layers are formed on the edges of the second surface of the upper plate and the first surface of the lower plate, respectively. The first and second micro-structures are formed on the edges of the second surface of the upper plate and the first surface of the lower plate, respectively. The LED package device is disposed below the through hole. The light guide device is connected to the LED package device. The light directing cover surrounds the light guide device. | 2014-06-12 |
20140159088 | LIGHT EMITTING DEVICE PACKAGES WITH IMPROVED HEAT TRANSFER - Packages containing one or more light emitting devices, such as light emitting diodes (LEDs), are disclosed. In one embodiment, LED package can include a thermal element having improved solder reliability to improve heat dissipation capacity of the LED package. LED package can include a molded plastic body having one or more LEDs attached to one or more electrical elements. The LEDs can be connected to an upper surface of the thermal element. The thermal element can include a bottom surface which can extend further away in distance from a body of the LED package than a bottom surface of the electrical element. This configuration can result in an improved connection between the LED package and an external circuitry source, thereby increasing heat transfer ability of the LED package. | 2014-06-12 |
20140159089 | LIGHT-EMITTING DIODE AND METHOD OF FABRICATING THE SAME - Exemplary embodiments of the present invention disclose a light-emitting diode (LED) including a semiconductor stack structure including a first semiconductor layer, an active layer, and a second semiconductor layer, the semiconductor stack disposed on a substrate, a conductive substrate disposed on the semiconductor stack structure, and an electrode disposed on the conductive substrate and in ohmic contact with the conductive substrate, wherein the electrode comprises grooves penetrating the electrode and a portion of the conductive substrate. | 2014-06-12 |
20140159090 | light emitting device - A light-emitting device is disclosed and comprises: a semiconductor stack; a transparent substrate comprising a first material; a bonding layer which bonds the semiconductor stack and the transparent substrate; and a medium in the transparent substrate, the medium comprising a second material different from the first material. | 2014-06-12 |
20140159091 | LIGHT-EMITTING ELEMENT - A light-emitting element comprises: a light-emitting semiconductor stack comprising a first semiconductor layer; a second semiconductor layer on the first semiconductor layer; and a light-emitting layer between the first semiconductor layer and the second semiconductor layer; a first electrode on the first semiconductor layer; a first protection layer on the light-emitting semiconductor stack and comprising a first through hole; and a conductive contact layer on the first protection layer and electrically connected to the first electrode through the first through hole. | 2014-06-12 |
20140159092 | LIGHT-EMITTING APPARATUS - A light-emitting apparatus of the present invention has (i) a semiconductor device which emits light toward a higher position than a substrate and (ii) a plurality of external connection terminals, and includes: a light-reflecting layer, provided on the substrate, which reflects the light emitted by the semiconductor device; and a covering layer which covers at least the light-reflecting layer and which transmits the light reflected by the light-reflecting layer. Further, the semiconductor device is provided on the covering layer, and is electrically connected to the external connection terminals via connecting portions, and the semiconductor device and the connecting portions are sealed with a sealing resin so as to be covered. Therefore, the light-emitting apparatus has increased efficiency with which light is taken out, and can prevent a reflecting layer from being altered, deteriorating, and decreasing in reflectance. | 2014-06-12 |
20140159093 | Carrier, Optoelectronic Unit Comprising a Carrier and Methods for the Production of Both - A carrier for an optoelectronic unit has a carrier material which includes polyethylene terephthalate which contains reflector particles and a further filler. Methods for the production of the optoelectronic unit and the carrier are also disclosed. | 2014-06-12 |
20140159094 | WAVELENGTH-CONVERTING LIGHT EMITTING DIODE (LED) CHIP AND LED DEVICE EQUIPPED WITH CHIP - A wavelength-converted light emitting diode (LED) chip is provided. The wavelength-converted LED chip includes an LED chip and a wavelength-converted layer. The LED chip emits light in a predetermined wavelength region. The wavelength-converted layer is formed of a resin containing phosphor bodies of at least one kind which convert a portion of the light emitted from the LED chip into light in a different wavelength region. The wavelength-converted layer is formed on an upper surface of the LED chip, and has a convex meniscus-shaped upper surface. | 2014-06-12 |
20140159095 | LIGHT EMITTING DEVICE - A light emitting device includes a metal layer, a light emitting structure, an electrode disposed on a first upper portion of a second conductive type semiconductor layer, a current spreading portion disposed on a second upper portion of the second conductive type semiconductor layer, an adhesive layer disposed under a first conductive type semiconductor layer, an insulating layer disposed between the electrode and the adhesive layer, a passivation layer disposed on a side surface of the light emitting structure and on a at least one upper surface of the light emitting structure, and a reflective layer disposed between the metal layer and the first conductive type semiconductor layer. | 2014-06-12 |
20140159096 | Micro-Interconnects for Light-Emitting Diodes - The present disclosure provides a method of fabricating a light emitting diode (LED) package. The method includes bonding a plurality of separated light emitting diode (LED) dies to a substrate, wherein each of the plurality of separated LED dies includes an n-doped layer, a quantum well active layer, and a p-doped layer; depositing an isolation layer over the plurality of separated LED dies and the substrate; etching the isolation layer to form a plurality of via openings to expose portions of each LED die and portions of the substrate; forming electrical interconnects over the isolation layer and inside the plurality of via openings to electrically connect between one of the doped layers of each LED die and the substrate; and dicing the plurality of separated LED dies and the substrate into a plurality of LED packages. | 2014-06-12 |
20140159097 | Light-Emitting Element, Light-Emitting Device, Display Device, Electronic Device, and Lighting Device - An object is to provide a light-emitting element which uses a plurality of kinds of light-emitting dopants and has high emission efficiency. In one embodiment of the present invention, a light-emitting device, a light-emitting module, a light-emitting display device, an electronic device, and a lighting device each having reduced power consumption by using the above light-emitting element are provided. Attention is paid to Förster mechanism, which is one of mechanisms of intermolecular energy transfer. Efficient energy transfer by Förster mechanism is achieved by making an emission wavelength of a molecule which donates energy overlap with a local maximum peak on the longest wavelength side of a graph obtained by multiplying an absorption spectrum of a molecule which receives energy by a wavelength raised to the fourth power. | 2014-06-12 |
20140159098 | SEMICONDUCTOR LEAD FRAME PACKAGE AND LED PACKAGE - The present invention relates to a semiconductor lead frame package and LED package. The semiconductor lead frame package includes a die pad, a lead, a die and an insulator body. The lead is electrically isolated from the die pad. The die is disposed on the die pad and electrically connected to the lead. The insulator body partially encapsulates the die pad and the lead, and has a top surface and a bottom surface, wherein a part of the lead is folded onto the top surface of the insulator body. | 2014-06-12 |
20140159099 | Method of making a light emitting device and light emitting device made thereof - A method of manufacturing a light-emitting device comprises: providing a substrate, forming a light-emitting structure on the substrate, the light-emitting structure having an active layer; forming a protective layer on the light-emitting structure, the protective layer having a first thickness; etching the protective layer such that the protective layer has a second thickness less than the first thickness; and patterning the protective layer. | 2014-06-12 |
20140159100 | PATTERNED SUBSTRATE AND ELECTRO-OPTICAL SEMICONDUCTOR ELEMENT - A patterned substrate comprises a substrate body and a plurality of solid patterns disposed on the substrate body. The pitch of at least a part of the adjacent solid patterns is between 1.5 μm and 2.5 μm, the space of at least a part of the adjacent solid patterns is between 0.1 μm and 0.7 μm, and the height of at least a part of the solid patterns is between 0.7 μm and 1.7 μm. An electro-optical semiconductor element containing the patterned substrate is also disclosed. | 2014-06-12 |
20140159101 | STRUCTURAL COMPONENT AND METHOD FOR PRODUCING A STRUCTURAL COMPONENT - The invention relates to a structural component which comprises a support ( | 2014-06-12 |
20140159102 | HIGH HOLDING VOLTAGE ELECTROSTATIC DISCHARGE PROTECTION DEVICE - A high holding voltage (HV) electrostatic discharge (ESD) protection circuit comprises a silicon controlled rectifier (SCR) device and compensation regions located within the length between the anode and cathode (LAC) of the SCR device which increase the holding voltage of the SCR device. The compensation regions may introduce negative feedback mechanisms into the SCR device which may influence the loop gain of the SCR and cause it to reach regenerative feedback at a higher holding voltage. | 2014-06-12 |
20140159103 | PARTIAL SOI ON POWER DEVICE FOR BREAKDOWN VOLTAGE IMPROVEMENT - The present disclosure relates to a method and apparatus to increase breakdown voltage of a semiconductor power device. A bonded wafer is formed by bonding a device wafer to a handle wafer with an intermediate oxide layer. The device wafer is thinned substantially from its original thickness. A power device is formed within the device wafer through a semiconductor fabrication process. The handle wafer is patterned to remove section of the handle wafer below the power device, resulting in a breakdown voltage improvement for the power device as well as a uniform electrostatic potential under reverse biasing conditions of the power device, wherein the breakdown voltage is determined. Other methods and structures are also disclosed. | 2014-06-12 |
20140159104 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device including: a first semiconductor region having a first conductivity; a second semiconductor region having a second conductivity and formed on a surface of the first semiconductor region; a third semiconductor region having the first conductivity and formed on a surface of the second semiconductor region; a gate electrode disposed in a trench that passes through the third semiconductor region in a depth direction and extends to an inside of the second semiconductor region; a first insulation layer formed between the gate electrode and the third semiconductor region; a second insulation layer formed between the gate electrode and the second semiconductor region; and a fourth semiconductor region having the second conductivity and formed in a portion of a surface of the third semiconductor region, wherein a thickness of a portion of the second insulation layer is greater than that of the first insulation layer. | 2014-06-12 |
20140159105 | POWER SEMICONDUCTOR DEVICE - Disclosed herein is a power semiconductor device, including: a drift layer formed on the first surface of the semiconductor substrate, a well layer of a first conductive type, formed on the drift layer, a trench formed to reach the drift layer through the well layer, a first electrode formed in the trench, a second conductive type of second electrode region formed on the well layer, including a first region contacting the trench in a perpendicular direction and a second region spaced apart from the trench in a parallel direction and being perpendicular to the first region, a first conductive type of second electrode region formed to contact a side surface of the second conductive type of second electrode region, and a second electrode formed on the well layer and electrically connected to the second conductive type of second electrode region and the first conductive type of second electrode region. | 2014-06-12 |
20140159106 | POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - There is provided a power semiconductor device, including: a first conductive type drift layer, a second conductive type termination layer formed on an upper portion of an edge of the drift layer, and a high concentration first conductive type channel stop layer formed on a side surface of the edge of the drift layer. | 2014-06-12 |
20140159107 | SEMICONDUCTOR DEVICE - Some aspects of the invention include a trench gate structure including a p base layer, an n | 2014-06-12 |
20140159108 | METHOD OF FORMING AN ESD DEVICE AND STRUCTURE THEREFOR - In one embodiment, an ESD device is configured to include a trigger device that assists in forming a trigger of the ESD device. The trigger device is configured to enable a transistor or a transistor of an SCR responsively to an input voltage having a value that is no less than the trigger value of the ESD device. | 2014-06-12 |
20140159109 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate on which a diode region and an IGBT region are formed. The diode region of the semiconductor substrate includes a first conductive type specific semiconductor region that is formed in a portion of an area facing a front surface of the semiconductor substrate, a second conductive type anode region that is formed in another portion of the area facing the front surface of the semiconductor substrate and is formed along a lower side of the specific semiconductor region, and a first conductive type diode drift region that is formed on a lower side of the anode region. The specific semiconductor region is separated from the diode drift region by the anode region, and is electrically connected to the trench gate electrode. | 2014-06-12 |
20140159110 | SEMICONDUCTOR DEVICE AND OPERATING METHOD FOR THE SAME - A semiconductor device and an operating method for the same are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region, a fourth doped region and a first gate structure. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The first doped region is surrounded by the second doped region. The third doped region has the first type conductivity. The fourth doped region has the second type conductivity. The first gate structure is on the second doped region. The third doped region and the fourth doped region are in the second doped region and the first doped region on opposing sides of the first gate structure respectively. | 2014-06-12 |
20140159111 | SEMICONDUCTOR COMPOSITE FILM WITH HETEROJUNCTION AND MANUFACTURING METHOD THEREOF - The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface. The recess is for mitigating a strain in the semiconductor composite film. | 2014-06-12 |
20140159112 | METHOD FOR FORMING GROUP III/V CONFORMAL LAYERS ON SILICON SUBSTRATES - A method for forming a conformal group III/V layer on a silicon substrate and the resulting substrate with the group III/V layers formed thereon. The method includes removing the native oxide from the substrate, positioning a substrate within a processing chamber, heating the substrate to a first temperature, cooling the substrate to a second temperature, flowing a group III precursor into the processing chamber, maintaining the second temperature while flowing a group III precursor and a group V precursor into the processing chamber until a conformal layer is formed, heating the processing chamber to an annealing temperature, while stopping the flow of the group III precursor, and cooling the processing chamber to the second temperature. Deposition of the III/V layer may be made selective through the use of halide gas etching which preferentially etches dielectric regions. | 2014-06-12 |
20140159113 | IMPLANT DAMAGE CONTROL BY IN-SITU C DOPING DURING SIGE EPITAXY FOR DEVICE APPLICATIONS - Some example embodiments of the invention comprise methods for and semiconductor structures comprised of: a MOS transistor comprised of source/drain regions, a gate dielectric, a gate electrode, channel region; a carbon doped SiGe region that applies a stress on the channel region whereby the carbon doped SiGe region retains stress/strain on the channel region after subsequent heat processing. | 2014-06-12 |
20140159114 | VERTICAL NANOWIRE BASED HETERO-STRUCTURE SPLIT GATE MEMORY - A memory cell is disclosed. The memory cell includes a vertical base disposed on a substrate. The vertical base includes first and second channels between top and bottom terminals. The memory cell also includes a first gate surrounding the first channel and a second gate surrounding the second channel. The first and second gates form a gate-all-around transistor of the memory cell. | 2014-06-12 |
20140159115 | TRANSISTOR AND METHOD OF FABRICATING THE SAME - A high electron mobility transistor includes a T-type gate electrode disposed on a substrate between source and drain electrodes and insulating layers disposed between the substrate and the T-type gate electrode. The insulating layers include first, second, and third insulating layers. The third insulating layer is disposed between the substrate and a head portion of the T-type gate electrode such that a portion of the third insulating layer is in contact with a foot portion of the T-type gate electrode. The second insulating layer is disposed between the substrate and the head portion of the T-type gate electrode to be in contact with the third insulating layer. The first insulating layer and another portion of the third insulating layer are sequentially stacked between the substrate and the head portion of the T-type gate electrode to be in contact with the second insulating layer. | 2014-06-12 |
20140159116 | III-Nitride Device Having an Enhanced Field Plate - In an exemplary implementation, a semiconductor device includes a III-nitride heterojunction including a III-nitride barrier layer situated over a III-nitride channel layer to form a conduction channel including a two-dimensional electron gas. The semiconductor device further includes a gate electrode coupled to a field plate. The field plate includes a plurality of steps insulated from the conduction channel by a dielectric body and the III-nitride barrier layer. The dielectric body under each one of the plurality of steps contributes to a breakdown voltage that is at least twice a breakdown voltage of the semiconductor device at each corresponding step. The breakdown voltage can correspond to a breakdown voltage of the dielectric body and the III-nitride barrier layer. | 2014-06-12 |
20140159117 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a channel layer; and a high resistance layer that is provided on the channel layer, and is made of a semiconductor with high resistance which has a conduction band position higher than that of the semiconductor which forms the channel layer. The semiconductor device includes a first conduction-type low resistance region provided on a surface layer of the high resistance layer, and is made of a semiconductor including first conduction type impurities. The semiconductor device includes: a source electrode and a drain electrode that are connected to the high resistance layer, in a position crossing the low resistance region; a gate insulating film provided on the low resistance region; and a gate electrode provided on the low resistance region via the gate insulating film. The semiconductor device includes current block regions between the low resistance region, and between the source electrode and the drain electrode respectively. | 2014-06-12 |
20140159118 | III-Nitride Transistor with Source-Connected Heat Spreading Plate - Disclosed are semiconductor devices and methods for manufacturing them. An example device may include a III-nitride stack having a front side surface and a back side surface. The III-nitride stack may be formed of at least a first layer and a second layer, between which a heterojunction may be formed, such that a two-dimensional electron gas layer is formed in the second layer. A source electrode, a drain electrode, and a gate electrode positioned between the source and drain electrodes may be formed on the front side surface, and an insulation layer may be formed over the electrodes on the front side surface. A carrier substrate may be attached to the insulation layer. An electrically conductive back plate may be formed on the back side surface. The back plate may directly face the source electrode and the gate electrode, but not the drain electrode. | 2014-06-12 |
20140159119 | Method for Growing III-V Epitaxial Layers and Semiconductor Structure - Disclosed are methods of growing III-V epitaxial layers on a substrate, a semiconductor structure comprising a substrate, a device comprising such a semiconductor structure, and an electronic circuit. Group III-nitride devices, such as, for example, high-electron-mobility transistors, may include a two-dimensional electron gas (2DEG) between two active layers. For example, the 2DEG may be between a GaN layer and a AlGaN layer. These transistors may work in depletion-mode operation, which means the channel has to be depleted to turn the transistor off. For certain applications, such as, for example, power switching or integrated logic, negative polarity gate supply is undesired. Transistors may then work in enhancement mode (E-mode). | 2014-06-12 |
20140159120 | Conformal Doping - Methods for doping a three-dimensional semiconductor structure are disclosed. A conformal coating is formed on the three-dimensional semiconductor structure by Atomic Layer Deposition, and subsequent annealing causes dopant atoms to migrate into the three-dimensional semiconductor structure. Any residual conformal coating is then removed by etching. The semiconductor can be a type IV semiconductor such as Si, SiC, SiGe, or Ge, for which Sb and Te are suitable dopants. Sb and Te can be provided from a Ge | 2014-06-12 |
20140159121 | NONVOLATILE MAGNETIC ELEMENT AND NONVOLATILE MAGNETIC DEVICE - Provided is a nonvolatile magnetic device that is capable of realizing low power consumption by performing writing with a voltage and is also excellent in retention characteristics. The nonvolatile magnetic device includes a nonvolatile magnetic element. The nonvolatile magnetic element includes: a first free layer made of a ferromagnetic substance; a first insulating layer made of an insulator, the first insulating layer being provided to be connected to the first free layer; a charged layer provided adjacent to the first insulating layer; a second insulating layer made of an insulator, the second insulating layer being provided adjacent to the charged layer; and an injection layer provided adjacent to the second insulating layer. The charged layer is smaller in electric resistivity than both of the first insulating layer and the second insulating layer. The injection layer is smaller in electric resistivity than the second insulating layer. | 2014-06-12 |
20140159122 | SEMICONDUCTOR PRESSURE SENSOR AND FABRICATION METHOD THEREOF - At a pressure sensor region, a pressure sensor including a fixed electrode, a void and a movable electrode is formed. At a CMOS region, a memory cell transistor and a field effect transistor are formed. An etching hole communicating with the void is closed by a first sealing film. The void is formed by removing a region of a film identical to the film of a gate electrode of the memory cell transistor. The movable electrode is formed of a film identical to the film of a gate electrode. | 2014-06-12 |
20140159123 | ETCH RESISTANT RAISED ISOLATION FOR SEMICONDUCTOR DEVICES - A method including providing fins etched from a semiconductor substrate, the fins covered by an oxide layer and a nitride layer, the oxide layer located between the fins and the nitride layer, removing a portion of the fins to form an opening, and forming a spacer on a sidewall of the opening. The method further including filling the opening above the semiconductor substrate with a first fill material, where a top surface of the fill material is substantially flush with a top surface of the nitride layer, removing the spacer to expose a vertical sidewall of the first fill material, and depositing an encapsulation layer conformally on top of the first fill material, where the encapsulation layer is resistant to wet etching techniques and protects from the unwanted removal of the first fill material during subsequent process techniques. | 2014-06-12 |
20140159124 | EPITAXIAL GROWN EXTREMELY SHALLOW EXTENSION REGION - A method to scale a MOSFET structure while maintaining gate control is disclosed. The extension regions of the MOSFET are formed by epitaxial growth and can be formed after the completion of high temperature processing. The extensions can be extremely shallow and have an abrupt interface with the channel. A dummy gate can establish the position of the abrupt interfaces and thereby define the channel length. The gate electrode can be formed to align perfectly with the channel, or to overlap the extension tip. | 2014-06-12 |
20140159125 | CONTACT LANDING PADS FOR A SEMICONDUCTOR DEVICE AND METHODS OF MAKING SAME - One device herein includes first and second spaced-apart active regions, a transistor formed in and above the first active region, wherein the transistor has a gate electrode, a conductive contact landing pad that is coupled to the second active region, wherein the contact landing pad is made of the same conductive material as the gate electrode, and a contact that is coupled to the contact landing pad. One method herein includes forming first and second spaced-apart active regions, forming a layer of gate insulation material on the active regions, performing an etching process to remove the gate insulation material formed on the second active region, performing a common process operation to form a gate electrode structure above the gate insulation material on the first active region and the contact landing pad that is conductively coupled to the second active region and forming a contact to the contact landing pad. | 2014-06-12 |
20140159126 | METHODS OF FORMING A FINFET SEMICONDUCTOR DEVICE WITH UNDOPED FINS - One method disclosed herein includes, prior to forming an isolation region in a semiconducting substrate for the device, forming a doped well region and a doped punch-stop region in the substrate, introducing a dopant material that is adapted to retard diffusion of boron or phosphorous into the substrate to form a dopant-containing layer proximate an upper surface of the substrate, performing an epitaxial deposition process to form an undoped semiconducting material above the dopant-containing layer, forming a plurality of spaced-apart trenches that extend at least partially into the substrate, wherein the trenches define a fin for the device comprised of at least the undoped semiconducting material, forming at least a local isolation insulating material in the trenches, and forming a gate structure around at least the undoped semiconducting material, wherein a bottom of a gate electrode is positioned approximately level with or below a bottom of the undoped semiconducting material. | 2014-06-12 |
20140159127 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having reduced contact region area achieved at least in part by forming pad portions of the word lines using an asymmetric stair shape separately formed in first and second pad structures. Contact region area is reduced when compared with manufacturing processes known in the art. This leads to an increase in device integrity and a less complex manufacturing process. | 2014-06-12 |
20140159128 | PHOTODETECTOR AND IMAGE SENSOR INCLUDING THE SAME - A photodetector may have a structure including conductive patterns and an intermediate layer interposed between the conductive patterns. A length L of at least one side of the second conductive pattern that overlaps the first conductive pattern and the intermediate layer satisfies the equation L=λ/2n | 2014-06-12 |
20140159129 | NEAR-INFRARED-VISIBLE LIGHT ADJUSTABLE IMAGE SENSOR - The disclosure belongs to the field of semiconductor photoreceptors, in particular to a near-infrared-visible light adjustable image sensor. By adding a transfer transistor, the disclosure integrates a silicon-based photoelectric diode and a silicon germanium-based photoelectric diode on the same chip to realize that the silicon-based photoelectric diode and a silicon germanium-based photoelectric diode are controlled by the same readout circuit at different time, thus widening the spectrum response scope of the photoreceptor, realizing high integration and multifunction of the chip and reducing the manufacturing cost of the chip. The disclosure is applicable for intermediate and high-end products with low power consumption and photoreceptors for specific wave bands, in particular to military, communicative and other special fields. | 2014-06-12 |
20140159130 | APPARATUS INCLUDING A SEMICONDUCTOR DEVICE COUPLED TO A DECOUPLING DEVICE - An apparatus and method of forming the same including, in one embodiment, a printed circuit board and a semiconductor device coupled to the printed circuit board. The apparatus also includes a decoupling device coupled to the printed circuit board and positioned under the semiconductor device. | 2014-06-12 |
20140159131 | RESERVOIR CAPACITOR OF SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a reservoir capacitor of a semiconductor device where a first peripheral circuit region and a second peripheral circuit region are defined comprises: forming a gate on an upper portion of a semiconductor substrate of the second peripheral circuit region; forming an interlayer insulating film on the entire upper portion of the semiconductor substrate including the gate; etching the interlayer insulating film of the second peripheral circuit region to form a bit line contact hole; forming a bit line material and a sacrificial film on the upper portion of the interlayer insulating film including the bit line contact hole; and etching the sacrificial film of the first peripheral circuit region to form a trench that exposes the bit line material. | 2014-06-12 |
20140159132 | MEMORY ARRAYS WITH AIR GAPS BETWEEN CONDUCTORS AND THE FORMATION THEREOF - Memory arrays and their formation are disclosed. The formation of one such memory array includes forming first and second spacers respectively adjacent to sidewalls of first and second conductors so that the first and second spacers extend into an opening between the first and second conductors and terminate above bottoms of the first and second conductors, and closing the opening with a material that extends between the first and second spacers so that an air gap is formed in the closed opening. | 2014-06-12 |
20140159133 | NON-VOLATILE MEMORY CIRCUIT - Provided is a non-volatile memory circuit capable of preventing erroneous writing while maintaining write efficiency. A non-volatile memory transistor having a one-sided LOCOS offset structure is used as a non-volatile memory element, and two pairs of switch transistors connected in parallel to the non-volatile memory element are controlled so that the non-LOCOS offset side serves as a drain in writing and the LOCOS offset side serves as the drain in reading. In a steady state (a state in which power supply is turned on, but the writing or reading is not performed), no potential is applied between the source and the drain of the non-volatile memory element. | 2014-06-12 |
20140159134 | NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF - A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory including a gate structure disposed on a substrate, doped regions, charge storage layers, and a first dielectric layer. There are recesses in the substrate at two sides of the gate structure. The gate structure includes a gate dielectric layer disposed on the substrate and a gate disposed on the gate dielectric layer. There is an interface between the gate dielectric layer and the substrate. The doped regions are disposed in the substrate around the recesses. The charge storage layers are disposed in the recesses, and a top surface of each of the charge storage layers is higher than the interface. The first dielectric layer is disposed between the charge storage layers and the substrate, and between the charge storage layers and the gate structure. | 2014-06-12 |
20140159135 | Air Gap Isolation In Non-Volatile Memory Using Sacrificial Films - Electrical isolation in non-volatile memory is provided by air gaps formed using sacrificial films of differing etch rates. A high etch rate material is formed in an isolation trench. Flowable chemical vapor deposition processes are used to form high etch rate films, and curing is performed to increase their etch rate. A low etch material is formed over the high etch rate material and provides a controlled etch back between charge storage regions in a row direction. A discrete low etch rate layer can be formed or the high etch rate material can be oxidized to form an upper region with a lower etch rate. A controlled etch back enables formation of a wrap-around dielectric and control gate structure in the row direction with minimized variability in the dimensions of the structures. At least a portion of the high etch rate material is removed to form air gaps for isolation. | 2014-06-12 |
20140159136 | THICKENED SIDEWALL DIELECTRIC FOR MEMORY CELL - Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area. | 2014-06-12 |
20140159137 | GATE STRUCTURE IN NON-VOLATILE MEMORY DEVICE - A gate structure of a non-volatile memory device and a method of forming the same including a tunnel oxide layer pattern, a charge trap layer pattern, a blocking dielectric layer pattern having the uppermost layer including a material having a first dielectric constant greater than that of a material included in the tunnel oxide layer pattern, and first and second conductive layer patterns. The gate structure includes a first spacer to cover at least the sidewall of the second conductive layer pattern. The gate structure includes a second spacer covering the sidewall of the first spacer and the sidewall of the first conductive layer pattern and including a material having a second dielectric constant equal to or greater than the first dielectric constant. In the non-volatile memory device including the gate structure, erase saturation caused by back tunneling is reduced. | 2014-06-12 |
20140159138 | GATE FRINGINE EFFECT BASED CHANNEL FORMATION FOR SEMICONDUCTOR DEVICE - Methods and structures for forming semiconductor channels based on gate fringing effect are disclosed. In one embodiment, a NAND flash memory device comprises multiple NAND strings of memory transistors. Each memory transistor includes a charge trapping layer and a gate electrode formed on the charge trapping layer. The memory transistors are formed close to each other to form a channel between an adjacent pair of the memory transistors based on a gate fringing effect associated with the adjacent pair of the memory transistors. | 2014-06-12 |
20140159139 | LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR WITH PARTIALLY UNSILICIDED SOURCE/DRAIN - A transistor includes a substrate, a gate over the substrate, a source and a drain over the substrate on opposite sides of the gate, a first silicide on the source, and a second silicide on the drain. Only one of the drain or the source has an unsilicided region adjacent to the gate to provide a resistive region. | 2014-06-12 |
20140159140 | BURIED WORD LINE STRUCTURE AND METHOD OF FORMING THE SAME - A method of forming a buried word line structure is provided. A first mask layer, an interlayer and a second mask layer are sequentially formed on a substrate, wherein the second mask layer has a plurality of mask patterns and a plurality of gaps arranged alternately, and the gaps includes first gaps and second gaps arranged alternately. A dielectric pattern is formed in each first gap and spacers are simultaneously formed on sidewalls of each second gap, wherein a first trench is formed between the adjacent spacers and exposes a portion of the first mask layer. The mask patterns are removed to form second trenches. An etching process is performed by using the dielectric patterns and the spacers as a mask, so that the first trenches are deepened to the substrate and the second trenches are deepened to the first mask layer. | 2014-06-12 |
20140159141 | INSULATING GATE FIELD EFFECT TRANSISTOR DEVICE AND METHOD FOR PROVIDING THE SAME - An insulating gate field effect transistor (IGFET) device includes a semiconductor body and a gate oxide. The semiconductor body includes a first well region doped with a first type of dopant and a second well region that is doped with an oppositely charged second type of dopant and is located within the first well region. The gate oxide includes an outer section and an interior section having different thickness dimensions. The outer section is disposed over the first well region and the second well region of the semiconductor body. The interior section is disposed over a junction gate field effect transistor region of the semiconductor body. The semiconductor body is configured to form a conductive channel through the second well region and the junction gate field effect transistor region when a gate signal is applied to a gate contact disposed on the gate oxide. | 2014-06-12 |
20140159142 | Recessed Channel Insulated-Gate Field Effect Transistor with Self-Aligned Gate and Increased Channel Length - A metal-oxide-semiconductor transistor (MOS) and method of fabricating the same, in which the effective channel length is increased relative to the width of the gate electrode. A dummy gate electrode overlying dummy gate dielectric material is formed at the surface of the structure, with self-aligned source/drain regions, and dielectric spacers on the sidewalls of the dummy gate structure. The dummy gate dielectric underlies the sidewall spacers. Following removal of the dummy gate electrode and the underlying dummy gate dielectric material, including from under the spacers, a silicon etch is performed to form a recess in the underlying substrate. This etch is self-limiting on the undercut sides, due to the crystal orientation, relative to the etch of the bottom of the recess. The gate dielectric and gate electrode material are then deposited into the remaining void, for example to form a high-k metal gate MOS transistor. | 2014-06-12 |
20140159143 | SUPER JUNCTION SEMICONDUCTOR DEVICE AND ASSOCIATED FABRICATION METHOD - A semiconductor device with a substrate, an epitaxy layer formed on the substrate, a plurality of deep wells formed in the epitaxy layer, a plurality of trench gate MOSFET units each of which is formed in top of the epitaxy layer between two adjacent deep well, wherein a trench gate of the trench gate MOSFET unit is shallower than half of the distance between two adjacent deep wells, which may reduce the product of on-state resistance and the gate charge of the semiconductor device. | 2014-06-12 |
20140159144 | TRENCH GATE MOSFET AND METHOD OF FORMING THE SAME - A trench gate MOSFET is provided. An N-type epitaxial layer on an N-type substrate has a wider first trench and a narrower second trench below the first trench. A first insulating layer is in the second trench. First and second conductive layers are respectively in lower and upper portions of the first trench. A thicker second insulating layer is between the first conductive layer and N-type epitaxial layer and between the first insulating layer and first conductive layer, and a thinner third insulating layer is between the second conductive layer and N-type epitaxial layer. A P-type first doped region is in the N-type epitaxial layer below the first trench and surrounds the top of the second trench. A P-type second doped region is in the N-type epitaxial layer below the second trench. A source region is in the N-type epitaxial layer and surrounds the top of the first trench. | 2014-06-12 |
20140159145 | SEMICONDUCTOR DEVICE - A semiconductor device includes a gate trench across an active region of a semiconductor substrate, a gate structure filling the gate trench, and source/drain regions formed in the active region at respective sides of the gate structure. The gate structure includes a sequentially stacked gate electrode and insulating capping pattern, and a gate dielectric layer between the gate electrode and the active region. The gate electrode is located at a lower level than an upper surface of the active region and includes a barrier conductive pattern and a gate conductive pattern. The gate conductive pattern includes a first part having a first width and a second part having a second width greater than the first width. The barrier conductive pattern is interposed between the first part of the gate conductive pattern and the gate dielectric layer. | 2014-06-12 |
20140159146 | TRENCH GATE TRANSISTOR AND METHOD OF FABRICATING SAME - A trench gate transistor is formed from a semiconductor substrate with its upper surface covered in an oxide dielectric layer. The trench gate transistor has a drain region, a body region, source region and a trench lined with a gate insulator that electrically insulates a conductive gate electrode formed in the trench from the body region. The body region has a sloping upper surface that extends away from the trench towards the drain region. The sloping upper surface is formed by exposing the oxide dielectric layer to an oxidized atmosphere, through an opening in a mask, so as to form a dielectric region. The dielectric region includes the oxide dielectric layer and a sacrificial area of the semiconductor substrate. | 2014-06-12 |
20140159147 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate having a drift layer of a first conductivity type, a body layer of a second conductivity type formed on a surface of the drift layer, and a source layer formed on a portion of a surface of the body layer; a gate insulation film formed on an inner wall of a trench that extends from the surface of the semiconductor substrate through the source layer and the body layer to the drift layer; and a gate electrode housed in the trench and covered with the gate insulation film, the gate electrode including, in a region located at a drift layer side of a boundary between the body and drift layers, at least one first semiconductor layer of the first conductivity type and at least one second semiconductor layer of the second conductivity type that are alternately disposed and joined to each other. | 2014-06-12 |
20140159148 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor device includes forming device isolation layer in a substrate to define active regions of which each has first regions and a second region between the first regions, forming a first trench and a pair of second trenches in the substrate, and forming gates in the second trenches, respectively. The first trench extends in a first direction and crosses the active regions and the device isolation layer. The second trenches are connected to a bottom of the first trench and extend in the first direction at both sides of the second regions. | 2014-06-12 |
20140159149 | SHORT CHANNEL TRENCH MOSFETS - A trench MOSFET with a short channel length is disclosed for reducing channel resistance, wherein at least one field relief region is formed underneath the body region in an epitaxial layer between every two adjacent gate trenches and self-aligned with a trenched source-body contact for prevention of drain/source punch-through issue. | 2014-06-12 |
20140159150 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - In aspects of the invention, an n-type epitaxial layer that forms an n | 2014-06-12 |
20140159151 | Power MOS Device Structure - Various embodiments of a power MOS device structure are disclosed. In one aspect, a power MOS device structure includes a plurality of LDMOS and a plurality of bonding pads. The basic units of LDMOS are coupled in parallel and electrically coupled to the bonding pads to couple to a gate terminal, a source terminal, a drain terminal and a substrate of each of the basic units of LDMOS. The basic units of LDMOS are disposed below the bonding pads. The bonding pads include a single layer of metal with a thickness of 3.5 um to 4.5 um and a width of 1.5 um to 2.5 um. The region below the bonding pads of the power MOS device of the present disclosure is utilized to increase the number of basic units of LDMOS, thereby effectively reducing the on-resistance. | 2014-06-12 |
20140159152 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device is provided, which can prevent an electric field from concentrating on a diode region, and can improve a breakdown voltage by creating an impurity concentration gradient in the diode region to increase from a termination region to an active cell region to cause reverse current to be distributed to the active cell region. | 2014-06-12 |
20140159153 | RF LDMOS DEVICE AND METHOD OF FORMING THE SAME - A radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) device is disclosed, which includes: a gate structure on a surface of a substrate; and a source region and a drain region beneath the surface of the substrate, the source region and the drain region formed on opposite sides of the gate structure, wherein the gate structure includes a first section proximal to the source region and a second section proximal to the drain region, and wherein the first section of the gate structure has a dopant concentration at least one decimal order higher than a dopant concentration of the second section of the gate structure. A method of forming an RF LDMOS device is also disclosed. With the gate structure including two sections having different dopant concentrations, the present invention is capable of reducing the hot carrier injection effect while possessing a low on-resistance. | 2014-06-12 |
20140159154 | Semiconductor Device with an Insulating Structure for Insulating an Electrode from a Semiconductor Body - A semiconductor device includes an electrode arranged on a main surface of a semiconductor body and an insulating structure insulating the electrode from the semiconductor body. The insulating structure includes in a vertical cross-section a gate dielectric portion forming a first horizontal interface at least with a drift region of the device and having a first maximum vertical extension between the first horizontal interface and the electrode, and a field dielectric portion forming with the drift region second, third and fourth horizontal interfaces. The second through fourth horizontal interfaces are arranged below the main surface. The third horizontal interface is arranged between the second and fourth horizontal interfaces. A second maximum vertical extension is larger than the first maximum vertical extension and a third maximum vertical extension is larger than the second maximum vertical extension. The electrode only partially overlaps the third horizontal interface. | 2014-06-12 |
20140159155 | HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE AND LAYOUT PATTERN THEREOF - A layout pattern of an implant layer includes at least a linear region and at least a non-linear region. The linear region includes a plurality of first patterns to accommodate first dopants and the non-linear region includes a plurality of second patterns to accommodate the first dopants. The linear region abuts the non-linear region. Furthermore, a pattern density of the first patterns in the linear region is smaller than a pattern density of the second patterns in the non-linear region. | 2014-06-12 |
20140159156 | Compact Semiconductor Memory Device Having Reduced Number of Contacts, Methods of Operating and Methods of Making - An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link. | 2014-06-12 |
20140159157 | ANTENNA DIODE CIRCUITRY AND METHOD OF MANUFACTURE - An integrated circuit with an antenna diode is described. The integrated circuit includes a substrate, a transistor, first and second diffusion regions, and a dummy gate. The transistor and the first and second diffusion regions may be formed within the substrate. The transistor has its gate structure disposed on the substrate. The dummy gate structure may be disposed on a region of the substrate such that it separates the first diffusion region from the second diffusion region. The dummy gate structure may also be coupled to the transistor gate structure. | 2014-06-12 |
20140159158 | Semiconductor Devices - A semiconductor device includes transistors provided on a substrate and including first dopant regions, first contacts extending from the first dopant regions in a first direction, a long via provided on the first contacts and connected in common to first contacts that are adjacent one another, and a common conductive line provided on the long via and extending in a second direction crossing the first direction. The common conductive line electrically connects the first dopant regions to each other. | 2014-06-12 |
20140159159 | WRAP-AROUND TRENCH CONTACT STRUCTURE AND METHODS OF FABRICATION - A wrap-around source/drain trench contact structure is described. A plurality of semiconductor fins extend from a semiconductor substrate. A channel region is disposed in each fin between a pair of source/drain regions. An epitaxial semiconductor layer covers the top surface and sidewall surfaces of each fin over the source/drain regions, defining high aspect ratio gaps between adjacent fins. A pair of source/drain trench contacts are electrically coupled to the epitaxial semiconductor layers. The source/drain trench contacts comprise a conformal metal layer and a fill metal. The conformal metal layer conforms to the epitaxial semiconductor layers. The fill metal comprises a plug and a barrier layer, wherein the plug fills a contact trench formed above the fins and the conformal metal layer, and the barrier layer lines the plug to prevent interdiffusion of the conformal metal layer material and plug material. | 2014-06-12 |
20140159160 | SEMICONDUCTOR DEVICE - A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained. | 2014-06-12 |
20140159161 | MEASUREMENT OF CMOS DEVICE CHANNEL STRAIN BY X-RAY DIFFRACTION - A direct measurement of lattice spacing by X-ray diffraction is performed on a periodic array of unit structures provided on a substrate including semiconductor devices. Each unit structure includes a single crystalline strained material region and at least one stress-generating material region. For example, the single crystalline strained material region may be a structure simulating a channel of a field effect transistor, and the at least one stress-generating material region may be a single crystalline semiconductor region in epitaxial alignment with the single crystalline strained material region. The direct measurement can be performed in-situ at various processing states to provide in-line monitoring of the strain in field effect transistors in actual semiconductor devices. | 2014-06-12 |
20140159162 | BULK FINFET WITH SUPER STEEP RETROGRADE WELL - A method for forming a fin transistor in a bulk substrate includes forming a super steep retrograde well (SSRW) on a bulk substrate. The well includes a doped portion of a first conductivity type dopant formed below an undoped layer. A fin material is grown over the undoped layer. A fin structure is formed from the fin material, and the fin material is undoped or doped. Source and drain regions are provided adjacent to the fin structure to form a fin field effect transistor. | 2014-06-12 |
20140159163 | BULK FINFET WITH SUPER STEEP RETROGRADE WELL - A method for forming a fin transistor in a bulk substrate includes forming a super steep retrograde well (SSRW) on a bulk substrate. The well includes a doped portion of a first conductivity type dopant formed below an undoped layer. A fin material is grown over the undoped layer. A fin structure is formed from the fin material, and the fin material is undoped or doped. Source and drain regions are provided adjacent to the fin structure to form a fin field effect transistor. | 2014-06-12 |
20140159164 | DOUBLE SIDEWALL IMAGE TRANSFER PROCESS - Methodology enabling a generation of fins having a variable fin pitch less than 40 nm, and the resulting device are disclosed. Embodiments include: forming a hardmask on a substrate; providing first and second mandrels on the hardmask; providing a first spacer on each side of each of the first and second mandrels; removing the first and second mandrels; providing, after removal of the first and second mandrels, a second spacer on each side of each of the first spacers; and removing the first spacers. | 2014-06-12 |
20140159165 | FACETED FINFET - Among other things, a semiconductor device comprising one or more faceted surfaces and techniques for forming the semiconductor device are provided. A semiconductor device, such as a finFET, comprises a fin formed on a semiconductor substrate. The fin comprises a source region, a channel, and a drain region. A gate is formed around the channel. A top fin portion of the fin is annealed, such as by a hydrogen annealing process, to create one or more faceted surfaces. For example the top fin portion comprises a first faceted surface formed adjacent to a second faceted surface at an angle greater than 90 degrees relative to the second faceted surface, which results in a reduced sharpness of a corner between the first faceted surface and the second faceted surface. In this way, an electrical field near the corner is substantially uniform to electrical fields induced elsewhere within the fin. | 2014-06-12 |
20140159166 | Preventing FIN Erosion and Limiting Epi Overburden in FinFET Structures by Composite Hardmask - A FinFET structure is formed by forming a hardmask layer on a substrate including a silicon-containing layer on an insulating layer. The hardmask layer includes first, second and third layers on the silicon-containing layer. An array of fins is formed from the hardmask layer and the silicon-containing layer. A gate is formed covering a portion but not all of a length of each of the array of fins. The portion covers each of the fins in the array. The gate defines source/drain regions on either side of the gate. A spacer is formed on each side of the gate, the forming of the spacer performed to remove the third layer from portions of the fins in the source/drain regions. The second layer of the hardmask layer is removed from the portions of the fins in the source/drain regions, and the fins in the source/drain regions are merged. | 2014-06-12 |
20140159167 | PREVENTING FIN EROSION AND LIMITING EPI OVERBURDEN IN FINFET STRUCTURES BY COMPOSITE HARDMASK - A FinFET structure is formed by forming a hardmask layer on a substrate including a silicon-containing layer on an insulating layer. The hardmask layer includes first, second and third layers on the silicon-containing layer. An array of fins is formed from the hardmask layer and the silicon-containing layer. A gate is formed covering a portion but not all of a length of each of the array of fins. The portion covers each of the fins in the array. The gate defines source/drain regions on either side of the gate. A spacer is formed on each side of the gate, the forming of the spacer performed to remove the third layer from portions of the fins in the source/drain regions. The second layer of the hardmask layer is removed from the portions of the fins in the source/drain regions, and the fins in the source/drain regions are merged. | 2014-06-12 |
20140159168 | DEEP DEPLETED CHANNEL MOSFET WITH MINIMIZED DOPANT FLUCTUATION AND DIFFUSION LEVELS - CMOS devices are fabricated with a channel layer having minimized dopant fluctuation and diffusion. Embodiments include forming a dummy gate, on a substrate, between a pair of spacers, forming, in the substrate, a source and drain separated by a ground plane layer, removing the dummy gate from the substrate, forming a cavity between the pair of spacers, forming, after removal of the dummy gate, a channel layer on the substrate, forming a high-k layer on the channel layer and on side surfaces of the cavity, and forming a replacement gate in the cavity. | 2014-06-12 |
20140159169 | RECESSING AND CAPPING OF GATE STRUCTURES WITH VARYING METAL COMPOSITIONS - A approach for recessing and capping metal gate structures is disclosed. Embodiments include: forming a dummy gate electrode on a substrate; forming a hard mask over the dummy gate electrode; forming spacers on opposite sides of the dummy gate electrode and the hard mask; forming an interlayer dielectric (ILD) over the substrate adjacent the spacers; forming a first trench in the ILD down to the dummy gate electrode; removing the dummy gate electrode to form a second trench below the first trench; forming a metal gate structure in the first and second trenches; and forming a gate cap over the metal gate structure. | 2014-06-12 |
20140159170 | SEMICONDUCTOR DEVICE DIELECTRIC INTERFACE LAYER - Embodiments related to methods for forming a film stack on a substrate are provided. One example method comprises exposing the substrate to an activated oxygen species and converting an exposed surface of the substrate into a continuous monolayer of a first dielectric material. The example method also includes forming a second dielectric material on the continuous monolayer of the first dielectric material without exposing the substrate to an air break. | 2014-06-12 |
20140159171 | METHODS OF FORMING BULK FINFET SEMICONDUCTOR DEVICES BY PERFORMING A LINER RECESSING PROCESS TO DEFINE FIN HEIGHTS AND FINFET DEVICES WITH SUCH A RECESSED LINER - One method disclosed herein includes forming a conformal liner layer in a plurality of trenches that define a fin, forming a layer of insulating material above the liner layer, exposing portions of the liner layer, removing portions of the liner layer so as to result in a generally U-shaped liner positioned at a bottom of each of the trenches, performing at least one third etching process on the layer of insulating material, wherein at least a portion of the layer of insulating material is positioned within a cavity of the U-shaped liner layer, and forming a gate structure around the fin. A FinFET device disclosed herein includes a plurality of trenches that define a fin, a local isolation that includes a generally U-shaped liner that defines, in part, a cavity and a layer of insulating material positioned within the cavity, and a gate structure positioned around the fin. | 2014-06-12 |
20140159172 | Transistors, Semiconductor Devices, and electronic devices including transistor gates with conductive elements including cobalt silicide - A method for fabricating a transistor gate with a conductive element that includes cobalt silicide includes use of a sacrificial material as a place-holder between sidewall spacers of the transistor gate until after high temperature processes, such as the fabrication of raised source and drain regions, have been completed. In addition, semiconductor devices (e.g., DRAM devices and NAND flash memory devices) with transistor gates that include cobalt silicide in their conductive elements are also disclosed, as are transistors with raised source and drain regions and cobalt silicide in the transistor gates thereof. Intermediate semiconductor device structures that include transistor gates with sacrificial material or a gap between upper portions of sidewall spacers are also disclosed. | 2014-06-12 |
20140159173 | SEMICONDUCTOR DEVICE HAVING AU-CU ELECTRODES, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a biosensor semiconductor device in which copper electrodes at a major surface of the device are modified to form Au—Cu alloy electrodes. Such modification is effected by depositing a gold layer over the device, and then thermally treating the device to promote interdiffusion between the gold and the electrode copper. Alloyed gold-copper is removed from the surface of the device, leaving the exposed electrodes. The electrodes are better compatible with further processing into a biosensor device than is the case with conventional copper electrodes, and the process windows are wider than for gold capped copper electrodes. A biosensor semiconductor device having Au—Cu alloy electrodes is also disclosed. | 2014-06-12 |