24th week of 2020 patent applcation highlights part 71 |
Patent application number | Title | Published |
20200185479 | OLED DISPLAY PANEL AND METHOD FOR MANUFACTURING SAME - The present disclosure provides an organic light emitting diode (OLED) display panel and a method for manufacturing same. The OLED display panel includes a substrate, a thermal insulating layer, a buffer, a driving TFT, and a storage capacitor. The substrate includes an arrangement area. The thermal insulating layer is disposed in the arrangement area. The buffer layer is disposed on the substrate. Both the driving TFT and the storage capacitor are disposed on the buffer layer to correspond to the arrangement area. According to the present disclosure, the thermal insulating layer prevents heat in the amorphous silicon layer from dissipating rapidly when an annealing treatment is performed for the amorphous silicon layer to have amorphous silicon crystallize. | 2020-06-11 |
20200185480 | Organic Light-Emitting Display Device and Method of Manufacturing the Same - An organic light-emitting display device and a method of manufacturing the same are disclosed and these improve electrical connection between a cathode and an auxiliary electrode in order to reduce the resistance of the cathode that covers a plurality of sub-pixels, and may prevent lateral current leakage using the same structure. | 2020-06-11 |
20200185481 | ORGANIC LIGHT EMITTING DIODE DISPLAY - According to an exemplary embodiment, an organic light emitting diode display includes: a substrate; a semiconductor layer; a first gate insulating layer disposed on the oxide semiconductor layer; a first gate layer disposed on the first gate insulating layer; a first interlayer insulating layer disposed on the first gate layer; a first data layer disposed on the first interlayer insulating layer; a second interlayer insulating layer disposed on the first data layer; a driving voltage line and a driving low voltage line disposed on the second interlayer insulating layer and separated from each other; an upper insulating layer covering the driving voltage line and the driving low voltage line; and an anode disposed on the upper insulating layer and overlapping the driving voltage line or the driving low voltage line. | 2020-06-11 |
20200185482 | DISPLAY SUBSTRATE, METHOD FOR PREPARING THE SAME, AND DISPLAY DEVICE - The present disclosure provides a display substrate, a method for preparing the same, and a display device. The display substrate includes: a substrate, a display unit arranged on the substrate, and an ultraviolet shielding layer arranged on a side of the display unit away from the substrate, wherein the ultraviolet shielding layer covers at least a portion of the display unit and includes at least two ultraviolet absorbing materials having different ultraviolet absorption bands. | 2020-06-11 |
20200185483 | ORGANIC LIGHT EMITTING DIODE ARRAY SUBSTRATE AND ELECTRONIC DEVICE - An organic light emitting diode array substrate and an electronic device. The organic light emitting diode array substrate includes a display region, and a first package test electrode and a first package test lead which are outside the display region. The display region includes a first power supply line and a first signal line; the first package test lead is configured to connect the first package test electrode with the first power supply line to provide a first supply voltage for the display region; the first signal line is configured to provide a first electrical signal for the display region; and a thermal conductivity of the first package test lead is higher than a thermal conductivity of the first signal line. | 2020-06-11 |
20200185484 | DISPLAY DEVICE - A display device includes a substrate including a pixel area and a peripheral area, a plurality of pixels disposed in the pixel area of the substrate, a first initialization line disposed in the peripheral area of the substrate, the first initialization line being configured to provide a first initialization voltage to the plurality of pixels, and a second initialization line disposed in the peripheral area of the substrate, the second initialization line being configured to provide a second initialization voltage to the plurality of pixels. At least a portion of the first initialization line may overlap with the second initialization line. | 2020-06-11 |
20200185485 | DISPLAY DEVICE - A display device includes a substrate having a pixel area with at least a first rounded corner portion and first to third non-pixel areas arranged sequentially along an outer circumference of the pixel area. An internal circuit in the first non-pixel area has a first end portion adjacent to the first rounded corner portion of the pixel area. The first end portion of the internal circuit is rounded in accordance with the first rounded corner portion. A plurality of routing wires are in the third non-pixel area below the pixel area. The routing wires extending to the pixel area via the second non-pixel area and the first non-pixel area. The routing wires include at least a first routing wire connected to the pixel area passing an area of the first end portion of the internal circuit. | 2020-06-11 |
20200185486 | DISPLAY DEVICE - A display device including: a substrate including a first region and a second region; a signal line on the substrate and including a first layer and a second layer that overlap each other; and a first insulating layer between the substrate and the signal line, wherein a first organic layer may be between the first layer and the second layer in the first region, and the first layer and the second layer may be in direct contact with each other in the second region, and the first insulating layer may be disposed in an area in which the first organic layer is. | 2020-06-11 |
20200185487 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode display includes a plurality of pixels. At least one pixel is connected to a scan line receive a scan signal, a data line to receive a data signal, and voltage line to receive a driving voltage. The at least one pixel includes a switching transistor including a switching drain electrode to output the data voltage, a driving transistor including a driving source electrode connected to the switching drain electrode, and an organic light emitting diode connected to a driving drain electrode of the driving transistor. The driving source electrode is separated from the data line. | 2020-06-11 |
20200185488 | DISPLAY DEVICE - A display device includes: a substrate on which a plurality of islands and a plurality of bridges connecting the plurality of islands to each other are defined; a plurality of pixels disposed in each of the plurality of islands; and a wire disposed in each of the plurality of bridges and connected to the plurality of pixels, where the plurality of islands and the plurality of bridges are defined based on cutout portions of the substrate, and a vertex of a cutout portion between one of the plurality of islands and a bridge connected to the one of the plurality of islands is an intersection of a straight line and a curved line. | 2020-06-11 |
20200185489 | DISPLAY DEVICE - A display device including: a substrate; an active layer disposed on the substrate and including active patterns; a first conductive layer disposed on the active layer; a second conductive layer disposed on the first conductive layer and including a data line; a third conductive layer disposed on the second conductive layer; and a light-emitting element disposed on the third conductive layer, wherein the first conductive layer includes a scan line, a first voltage line, and a second voltage line, the third conductive layer includes a third voltage line connected to the first voltage line and a fourth voltage line connected to the second voltage line, the first voltage line and the second voltage line extend in a first direction, the third voltage line and the fourth voltage line extend in a second direction, and the third voltage line and the fourth voltage line are alternately arranged in the first direction. | 2020-06-11 |
20200185490 | SEMICONDUCTOR INDUCTORS - The present disclosure is directed to systems and methods for fabricating a semiconductor inductor that includes a coil deposited on a stop layer that is deposited on a sacrificial substrate. The semiconductor inductor may be fabricated on a silicon wafer and singulated. The sacrificial substrate beneficially provides structural support for the singulated semiconductor inductor. The singulated semiconductor inductor advantageously requires minimal active die surface area. The removal of the sacrificial substrate after coupling to the active die beneficially reduces the overall thickness (or height) of the semiconductor package, providing a decided advantage in low profile, portable, electronic devices. | 2020-06-11 |
20200185491 | FINGERPRINT SENSORS - A fingerprint sensor includes: a base substrate including a plurality of pixel regions; a sensing dielectric structure formed on the base substrate in the pixel regions; and a sensing connection structure formed in the sensing dielectric structure. The sensing dielectric structure exposes the sensing connection structure and the sensing connection structure is connected to the base substrate. The fingerprint sensor further includes a plurality of electrode plates formed on surfaces of the sensing dielectric structure and the sensing connection structure. A plurality of protrusions are formed on surfaces of the electrode plates. The fingerprint sensor further includes an insulation medium structure formed on the plurality of electrode plates. | 2020-06-11 |
20200185492 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a semiconductor member, and a first crystal member. A direction from the first electrode toward the second electrode is aligned with a first direction. A position in the first direction of the third electrode is between positions in the first direction of the first electrode and the second electrode. The semiconductor member includes at least one selected from the group consisting of silicon carbide, silicon, carbon, and germanium. The semiconductor member includes a first region, and first and second partial regions. The first region is between the first and second electrodes in the first direction. A second direction from the first region toward the third electrode crosses the first direction. The first crystal member is provided between the first and third electrodes in the second direction. | 2020-06-11 |
20200185493 | SEMICONDUCTOR DEVICE AND METHOD OF MAKING THEREOF - Embodiments of a semiconductor device and methods of forming thereof are provided herein. In some embodiments, a power semiconductor device may include a first layer having a first conductivity type; a second layer disposed atop the first layer, the second layer having the first conductivity type; a termination region formed in the second layer, the termination region having a second conductivity type opposite the first type; and an active region at least partially formed in the second layer, wherein the active region is disposed adjacent to the termination region proximate a first side of the termination region and wherein the second layer is at least partially disposed adjacent to the termination region proximate a second side of the termination region opposite the first side. | 2020-06-11 |
20200185494 | Semiconductor Device and Method for Producing a Semiconductor Device - A method includes forming a layer stack with a plurality of first layers of a first doping type and a plurality of second layers of a second doping type complementary to the first doping type on top of a carrier. Forming the layer stack includes forming a plurality of epitaxial layers on the carrier. Forming each of the plurality of epitaxial layers includes depositing a layer of semiconductor material, forming at least two first implantation regions of one of a first type or a second type at different vertical positions of the respective layer of semiconductor material, and forming at least one second implantation region of a type that is complementary to the type of the first implantation regions, the first implantation regions and the second implantation regions being arranged alternatingly. | 2020-06-11 |
20200185495 | SEMICONDUCTOR DEVICES AND METHODS FOR FORMING SAME - A semiconductor device is provided, including a substrate; a dielectric structure over the substrate; and a capping layer over the dielectric structure. The bottom of the capping layer has an M-shaped cross section. The capping layer and the dielectric structure are formed of different materials. | 2020-06-11 |
20200185496 | Semiconductor Device - A semiconductor device according to an exemplary embodiment of the present disclosure includes a substrate, an n− type layer, a plurality of trenches, a p type region, a p+ type region, an n+ type region, a gate electrode, a source electrode, and a drain electrode. The semiconductor device may include a plurality of unit cells. A unit cell among the plurality of unit cells may include a contact portion with which the source electrode and the n+ type region are in contact, a first branch part disposed above the contact portion on a plane, and a second branch part disposed below the contact portion on a plane, the plurality of trenches are separated from each other and disposed with a stripe shape on a plane. | 2020-06-11 |
20200185497 | METHOD FOR MANUFACTURING AN ELECTRONIC COMPONENT HAVING MULTIPLE QUANTUM DOTS - A process for fabricating an electronic component with multiple quantum dots is provided, including providing a stack including a substrate, a nanostructure made of semiconductor material superposed over the substrate and including first and second quantum dots and a link linking the quantum dots, first and second control gate stacks arranged on the quantum dots, the gate stacks separated by a gap, the quantum dots and the link having a same thickness; partially thinning the link while using the gate stacks as masks to obtain the link, a thickness of which is less than that of the quantum dots; and conformally forming a dielectric layer on either side of the gate stacks so as to fill the gap above the partially thinned link. An electronic component with multiple quantum dots is also provided. | 2020-06-11 |
20200185498 | GRAPHENE FET WITH GRAPHITIC INTERFACE LAYER AT CONTACTS - A method for forming a graphene FET includes providing a graphene layer having a surface. A first metal layer having a work function <4.3 eV is deposited on the graphene surface. The first metal layer is oxidized to form a first metal oxide layer. The first metal oxide layer is etched to provide open surface contact regions including a first and a second region of the graphene layer for providing a graphene surface source and drain contact. A second metal layer is deposited including a second metal layer portion providing a source with a source contact over the graphene surface source contact and a second metal layer portion providing a drain with a drain contact over the graphene surface drain contact. A grown-in graphitic interface layer is formed at an interface between the source contact and graphene surface source contact and the drain contact and graphene surface drain contact. | 2020-06-11 |
20200185499 | TRANSISTOR WITH MULTIPLE GAN-BASED ALLOY LAYERS - In some examples, a transistor comprises a gallium nitride (GaN) layer; a first GaN-based alloy layer having a top side and disposed on the GaN layer; a second GaN-based alloy layer disposed on the first GaN-based alloy layer, wherein the second GaN-based alloy layer covers a first portion of the top side; and a source contact structure, a drain contact structure, and a gate contact structure, wherein the source, drain, and gate contact structures are supported by the first GaN-based alloy layer. | 2020-06-11 |
20200185500 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing a semiconductor device capable of suppressing breakdown due to current concentration while suppressing an increase in chip size are provided. According to one embodiment, a semiconductor device has a gate resistance on a main surface side of a semiconductor substrate, a first contact and a second contact connected to an upper surface of the gate resistance, and a carrier discharging portion that discharges the carrier formed in the semiconductor substrate below the gate resistance, the gate resistance having a first contacting portion to which a first contact is connected, a second contacting portion to which a second contact is connected, and a plurality of extending portions with one end connected to the first contacting portion and the other end connected to the second contacting portion. The gate resistance forms an opening between adjacent extending portions and the carrier discharge portion is formed in the opening. | 2020-06-11 |
20200185501 | DEVICE ISOLATION BY FIXED CHARGE - Disclosed herein are tri-gate and all-around-gate transistor arrangements, and related methods and devices. For example, in some embodiments, a transistor arrangement may include a channel material disposed over a substrate; a gate electrode of a first tri-gate or all-around-gate transistor, disposed over a first part of the channel material; and a gate electrode of a second tri-gate or all-around-gate transistor, disposed over a second part of the channel material. The transistor arrangement may further include a device isolation structure made of a fixed charge dielectric material disposed over a third part of the channel material, the third part being between the first part and the second part of the channel material. | 2020-06-11 |
20200185502 | DEVICES COMPRISING FLOATING GATE MATERIALS, TIER CONTROL GATES, CHARGE LOCKING MATERIALS, AND CHANNEL MATERIALS - Methods of fabricating a semiconductor structure comprise forming an opening through a stack of alternating tier dielectric materials and tier control gate materials, and laterally removing a portion of each of the tier control gate materials to form control gate recesses. A charge blocking material comprising a charge trapping portion is formed on exposed surfaces of the tier dielectric materials and tier control gate materials in the opening. The control gate recesses are filled with a charge storage material. The method further comprises removing the charge trapping portion of the charge blocking material disposed horizontally between the charge storage material and an adjacent tier dielectric material to produce air gaps between the charge storage material and the adjacent tier dielectric material. The air gaps may be substantially filled with dielectric material or conductive material. Also disclosed are semiconductor structures obtained from such methods. | 2020-06-11 |
20200185503 | SEMICONDUCTOR DEVICE, MANUFACTURE THEREOF, AND A RADIATION MEASUREMENT METHOD - A semiconductor device, its manufacturing method, and a radiation measurement method are presented, relating to semiconductor techniques. The semiconductor device includes: a substrate comprising a base area and a collector area adjacent to each other; a plurality of semiconductor fins on the substrate, wherein the plurality of semiconductor fins comprises at least a first semiconductor fin and a second semiconductor fin on the base area and separated from each other, the first semiconductor fin comprises an emission area adjacent to the base area, and the second semiconductor fin comprises a first region adjacent to the base area; a first gate structure on the second semiconductor fin; and a first source and a first drain at two opposite sides of the first gate structure and at least partially in the first region. Radiation in a semiconductor apparatus can be measured through this semiconductor device. | 2020-06-11 |
20200185504 | THIN FILM TRANSISTOR WITH CHARGE TRAP LAYER - An embodiment includes an apparatus comprising: a substrate; a thin film transistor (TFT) comprising: source, drain, and gate contacts; a semiconductor material, comprising a channel, between the substrate and the gate contact; a gate dielectric layer between the gate contact and the channel; and an additional layer between the channel and the substrate; wherein (a)(i) the channel includes carriers selected from the group consisting of hole carriers or electron carriers, (a)(ii) the additional layer includes an insulator material that includes charged particles having a polarity equal to a polarity of the carriers. Other embodiments are described herein. | 2020-06-11 |
20200185505 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a substrate having at least a trench formed therein. A conductive material fills a lower portion of the trench. A barrier layer is between the conductive material and the substrate. An insulating layer is in the trench and completely covers the conductive material and the barrier layer, wherein a portion of the insulating layer covering the barrier layer has a bird's peak profile. | 2020-06-11 |
20200185506 | NITRIDE SEMICONDUCTOR TRANSISTOR DEVICE - A nitride semiconductor transistor device is disclosed. The device includes a first nitride semiconductor layer disposed over a substrate, and a second nitride semiconductor layer with a band gap larger than the first nitride semiconductor disposed over the first nitride semiconductor layer. Over the second nitride semiconductor layer, a first insulating film, a charge-storing gate electrode, a second insulating film, and a second gate electrode are formed in order thereon. A source electrode and a drain electrode are disposed over the second nitride semiconductor layer interposing the charge-storing gate electrode in a plane direction. The device further includes a first gate electrode capacitively coupling with the charge-storing gate electrode with an insulating film therebetween forming a first capacitor, and the charge-storing gate electrode is charged by an electron injection from the first gate electrode through the first capacitor. | 2020-06-11 |
20200185507 | SEMICONDUCTOR DEVICE WITH NEGATIVE CAPACITANCE MATERIAL IN BURIED CHANNEL - A semiconductor device includes a substrate, at least one trench, an insulating layer, a lower metal layer, a negative capacitance material layer, and an upper metal layer. The trench has an inner surface in the substrate. The insulating layer is disposed on and lining the inner surface of the trench. The lower metal layer is disposed on the insulating layer and partially filling the trench. The negative capacitance material layer is disposed on and lining the insulating layer and the lower metal layer, in which a remained portion of the trench is defined by the negative capacitance material layer. The upper metal layer is disposed on the negative capacitance material layer and filling the remained portion of the trench. | 2020-06-11 |
20200185508 | GaN HEMT DEVICE STRUCTURE AND METHOD OF FABRICATION - GaN HEMT device structures and methods of fabrication are provided. A masking layer forms a p-dopant diffusion barrier and selective growth of p-GaN in the gate region, using low temperature processing, reduces deleterious effects of out-diffusion of p-dopant into the 2DEG channel. A structured Al | 2020-06-11 |
20200185509 | METHODS, APPARATUS AND SYSTEM FOR A SELF-ALIGNED GATE CUT ON A SEMICONDUCTOR DEVICE - At least one method, apparatus and system disclosed herein involves adjusting for a misalignment of a gate cut region with respect to semiconductor processing. A plurality of fins are formed on a semiconductor substrate. A gate region is formed over a portion of the fins. The gate region comprises a first dummy gate and a second dummy gate. A gate cut region is formed over the first dummy gate. A conformal fill material is deposited into the gate cut region. At least one subsequent processing step is performed. | 2020-06-11 |
20200185510 | TRANSISTORS AND METHODS OF FORMING TRANSISTORS USING VERTICAL NANOWIRES - Devices and methods of fabricating vertical nanowires on semiconductor devices. A doped silicon substrate, a first insulator over the doped silicon substrate, a gate conductor over the first insulator, and a second insulator over the gate conductor. Silicon nanowires extend from the top surface of the substrate through the first insulator, the gate conductor, and the second insulator. A first contact extends from the gate conductor through the second insulator, a second contact extends from the substrate through the first insulator, the gate conductor, and the second insulator layer, and an insulating spacer material is positioned between the second contact and the gate conductor. | 2020-06-11 |
20200185511 | SEMICONDUCTOR STRUCTURE - Provided is a semiconductor structure including a substrate, a doping layer, and a dielectric layer. The substrate has a plurality of fin portions and at least one recessed portion, wherein the at least one recessed portion is located between two adjacent fin portions of the plurality of fin portions and a bottom surface of the at least one recessed portion is lower than a surface of the substrate between the two of the plurality of fin portions. The doping layer is disposed on a sidewall of the plurality of fin portions, the surface of the substrate, and a sidewall and a bottom portion of the at least one recessed portion. The dielectric layer is disposed on the doping layer. A top surface of the doping layer and a top surface of the dielectric layer are lower than a top surface of each of the plurality of fin portions. | 2020-06-11 |
20200185512 | MONOLITHIC QUBIT INTEGRATED CIRCUITS - Described is a monolithic integrated circuit for use in quantum computing based on single and multiple coupled quantum dot electron- and hole-spin qubits monolithically integrated with the mm-wave spin manipulation and readout circuitry in commercial complementary metal-oxide-semiconductor (CMOS) technology. The integrated circuit includes a plurality of n-channel or p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) cascodes each including a single-spin qubit or two coupled quantum dot qubits formed in an undoped semiconductor film adjacent at least one top gate. There is also a back gate formed in a silicon substrate adjacent a buried oxide layer or the at least one top gate, where the back gate controls the electron or hole entanglement and exchange interaction between the two coupled quantum dot qubits. The monolithic integrated circuits described may be used for monolithically integrated semiconductor quantum processors for quantum information processing. | 2020-06-11 |
20200185513 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE - The present disclosure relates to a bipolar transistor semiconductor device including: a substrate layer, a collector epitaxial layer supported by the substrate layer, a base region supported by a portion of the collector epitaxial layer, and an emitter region supported by a portion of the base region. The emitter region includes a polysilicon material. | 2020-06-11 |
20200185514 | SEMICONDUCTOR DEVICES AND METHODS FOR FORMING THE SAME - A semiconductor device is provided. The semiconductor device includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a dopant holding layer, a source/drain pair, and a gate. The channel layer is disposed over the substrate. The barrier layer is disposed over the channel layer. The compound semiconductor layer and the dopant holding layer are disposed over the barrier layer. The source/drain pair are disposed over the substrate and on both sides of the compound semiconductor layer. The gate is disposed over the compound semiconductor layer. | 2020-06-11 |
20200185515 | SEMICONDUCTOR STRUCTURE COMPRISING III-N MATERIAL - A semiconductor structure comprising III-N materials, includes: a support substrate; a main layer of III-N material, the main layer comprising a first section disposed on the support substrate and a second section disposed on the first section; an inter-layer of III-N material, disposed between the first section and the second section in order to compress the second section of the main layer, wherein the structure's inter-layer consists of a lower layer disposed on the first section and an upper layer disposed on the lower layer and formed by a superlattice. | 2020-06-11 |
20200185516 | BODY CONTACT IN FIN FIELD EFFECT TRANSISTOR DESIGN - A method for forming the semiconductor device that includes forming a gate opening to a channel region of a fin structure; and forming a dielectric layer on the fin structure, in which an upper portion of the fin structure is exposed. A metal is formed within the gate opening. The portions of the metal directly contacting the upper surface of fin structure provide a body contact. The combination of the metal within the gate opening to the channel region of the fin structure and the dielectric layer provide a functional gate structure to the semiconductor device. | 2020-06-11 |
20200185517 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a plurality of semiconductor switching elements that are a plurality of MOSFETs each including a Schottky barrier diode; a first ohmic electrode disposed above a first region of a well region and electrically connected to the first region, the first region being on the opposite side from a predefined region; a first Schottky electrode disposed on a semiconductor layer exposed at the first region of the well region; and a line electrically connected to the first ohmic electrode, the first Schottky electrode, and a source electrode. The device enables reduction of a breakdown in a gate insulating film. | 2020-06-11 |
20200185518 | TIN OXIDE LAYER, TFT HAVING THE SAME AS CHANNEL LAYER, AND MANUFACTURING METHOD FOR THE TFT - Provided are a tin oxide layer, a thin film transistor (TFT) having the same as a channel layer, and a method for manufacturing the TFT. The TFT comprises a gate electrode, a tin oxide channel layer disposed on the gate electrode and being a polycrystalline thin film with preferred orientation in a [001] direction, a gate insulating film disposed between the gate electrode and the channel layer, and source and drain electrodes electrically connected to both ends of the channel layer, respectively. | 2020-06-11 |
20200185519 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide substrate has at least one of a first structure and a second structure. The first structure is such that a first impurity region is in contact with a second impurity region, a third impurity region is separated from a fourth impurity region by a second drift region, and the second impurity region has a width greater than a width of the fourth impurity region in a direction parallel to a first main surface. The second structure is such that the first impurity region is separated from the second impurity region by a first drift region, the third impurity region is in contact with the fourth impurity region, and the fourth impurity region has a width greater than a width of the second impurity region in the direction parallel to the first main surface. | 2020-06-11 |
20200185520 | SEMICONDUCTOR DEVICE - A semiconductor device includes pads arrayed between a region where a transistor portion or a diode portion is disposed and a first end side on an upper surface of a semiconductor substrate, and a gate runner portion that transfers a gate voltage to the transistor portion. The gate runner portion has a first gate runner disposed passing between the first end side of the semiconductor substrate and at least one of the pads in the top view, and a second gate runner disposed passing between at least one of the pads and the transistor portion in the top view. The transistor portion is also disposed in the inter-pad regions, the gate trench portion disposed in the inter-pad regions is connected to the first gate runner, and the gate trench portion arranged so as to face the second gate runner is connected to the second gate runner. | 2020-06-11 |
20200185521 | HIGH VOLTAGE DEVICES AND METHODS OF FORMING THE SAME - A device which includes a substrate having a device region is provided. The device region may be a high voltage device region. A source region and a drain region are disposed in the substrate within the device region. A gate is arranged over the substrate and between the source region and the drain region. A trench structure having a trench is disposed in the substrate within the device region. The trench structure is arranged on a first side of the gate where a predetermined distance is arranged between the trench structure and the first side of the gate. A well tap region is disposed adjacent to the source region. The well tap region is arranged at least around a bottom and a sidewall of the trench. The well tap region has a deeper depth within the substrate as compared to the source region. | 2020-06-11 |
20200185522 | HIGH VOLTAGE (HV) METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) IN SEMICONDUCTOR ON INSULATOR (SOI) TECHNOLOGY - A method of constructing an integrated circuit (IC) includes fabricating a metal oxide semiconductor field effect transistor (MOSFET) on a first surface of an insulator layer of the integrated circuit. The insulator layer is supported by a sacrificial substrate. The MOSFET includes an extended drain region. The method deposits a front-side dielectric layer on the MOSFET, bonds a handle substrate to the front-side dielectric layer, and then removes the sacrificial substrate. The method also fabricates multiple back gates on a second surface of the insulator layer. The second surface is opposite the first surface. | 2020-06-11 |
20200185523 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET. | 2020-06-11 |
20200185524 | FINFETS HAVING STEP SIDED CONTACT PLUGS AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes an active fin extending in a first direction on a substrate, a gate electrode intersecting the active fin and extending in a second direction, source/drain regions disposed on the active fin on both sides of the gate electrode, and a contact plug disposed on the source/drain regions. The contact plug has at least one side extending in the second direction which has a step portion having a step shape. | 2020-06-11 |
20200185525 | FIN FIELD EFFECT TRANSISTOR HAVING CRYSTALLINE TITANIUM GERMANOSILICIDE STRESSOR LAYER - A semiconductor structure includes a semiconductor substrate, at least a silicon germanium (SiGe) epitaxial region disposed in the semiconductor substrate, and a contact structure disposed on the SiGe epitaxial region. The contact structure includes a titanium nitride (TiN) barrier layer and a metal layer surrounded by the TiN barrier layer. A crystalline titanium germanosilicide stressor layer is disposed in the SiGe epitaxial region and between the TiN barrier layer and the SiGe epitaxial region. | 2020-06-11 |
20200185526 | NON-PLANAR SEMICONDUCTOR DEVICE HAVING HYBRID GEOMETRY-BASED ACTIVE REGION - Non-planar semiconductor devices having hybrid geometry-based active regions are described. For example, a semiconductor device includes a hybrid channel region including a nanowire portion disposed above an omega-FET portion disposed above a fin-FET portion. A gate stack is disposed on exposed surfaces of the hybrid channel region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the hybrid channel region. | 2020-06-11 |
20200185527 | THIN-FILM TRANSISTOR AND METHOD OF PRODUCING THIN-FILM TRANSISTOR - A gate driver TFT | 2020-06-11 |
20200185528 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes an oxide; a first conductor and a second conductor over the oxide; a third conductor over the oxide; a first insulator provided between the oxide and the third conductor and covering a side surface of the third conductor; a second insulator over the third conductor and the first insulator; a third insulator positioned over the first conductor and at a side surface of the second insulator; a fourth insulator positioned over the second conductor and at a side surface of the second insulator; a fourth conductor being in contact with a top surface and a side surface of the third insulator and electrically connected to the first conductor; and a fifth conductor being in contact with a top surface and a side surface of the fourth insulator and electrically connected to the second conductor. The first insulator is between the third insulator and the third conductor, and between the fourth insulator and the third conductor. | 2020-06-11 |
20200185529 | MICRON SCALE TIN OXIDE-BASED SEMICONDUCTOR DEVICES - Micron scale tin oxide-based semiconductor devices are provided. Reactive-ion etching is used to produce a micron-scale electronic device using semiconductor films with tin oxides, such as barium stannate (BaSnO | 2020-06-11 |
20200185530 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device which includes a thin film transistor having an oxide semiconductor layer and excellent electrical characteristics is provided. Further, a method for manufacturing a semiconductor device in which plural kinds of thin film transistors of different structures are formed over one substrate to form plural kinds of circuits and in which the number of steps is not greatly increased is provided. After a metal thin film is formed over an insulating surface, an oxide semiconductor layer is formed thereover. Then, oxidation treatment such as heat treatment is performed to oxidize the metal thin film partly or entirely. Further, structures of thin film transistors are different between a circuit in which emphasis is placed on the speed of operation, such as a logic circuit, and a matrix circuit. | 2020-06-11 |
20200185531 | THIN-FILM TRANSISTOR INCLUDING OXIDE SEMICONDUCTOR LAYER, METHOD OF MANUFACTURING THE SAME, AND DISPLAY APPARATUS INCLUDING THE SAME - A thin-film transistor is disclosed. The thin-film transistor includes a gate electrode disposed on a substrate, an oxide semiconductor layer disposed so as to overlap at least a portion of the gate electrode in the state of being isolated from the gate electrode, a gate insulation film disposed between the gate electrode and the oxide semiconductor layer, a source electrode connected to the oxide semiconductor layer, and a drain electrode connected to the oxide semiconductor layer in the state of being spaced apart from the source electrode, wherein the oxide semiconductor layer includes indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O), the content of indium (In) in the oxide semiconductor layer is greater than the content of gallium (Ga), the content of indium (In) is substantially equal to the content of zinc (Zn), and the content ratio (Sn/In) of tin (Sn) to indium (In) is 0.1 to 0.25. | 2020-06-11 |
20200185532 | ADHESION STRUCTURE FOR THIN FILM TRANSISTOR - A transistor structure includes a layer of active material on a base. The base can be insulator material in some cases. The layer has a channel region between a source region and a drain region. A gate structure is in contact with the channel region and includes a gate electrode and a gate dielectric, where the gate dielectric is between the gate electrode and the active material. An electrical contact is on one or both of the source region and the drain region. The electrical contact has a larger portion in contact with a top surface of the active material and a smaller portion extending through the layer of active material into the base. The active material may be, for example, a transition metal dichalcogenide (TMD) in some embodiments. | 2020-06-11 |
20200185533 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The stability of steps of processing a wiring formed using copper or the like is increased. The concentration of impurities in a semiconductor film is reduced. Electrical characteristics of a semiconductor device are improved. A semiconductor device includes a semiconductor film, a pair of first protective films in contact with the semiconductor film, a pair of conductive films containing copper or the like in contact with the pair of first protective films, a pair of second protective films in contact with the pair of conductive films on the side opposite the pair of first protective films, a gate insulating film in contact with the semiconductor film, and a gate electrode overlapping with the semiconductor film with the gate insulating film therebetween. In a cross section, side surfaces of the pair of second protective films are located on the outer side of side surfaces of the pair of conductive films. | 2020-06-11 |
20200185534 | Semiconductor Device - It is an object of the present invention to connect a wiring, an electrode, or the like formed with two incompatible films (an ITO film and an aluminum film) without increasing the cross-sectional area of the wiring and to achieve lower power consumption even when the screen size becomes larger. The present invention provides a two-layer structure including an upper layer and a lower layer having a larger width than the upper layer. A first conductive layer is formed with Ti or Mo, and a second conductive layer is formed with aluminum (pure aluminum) having low electric resistance over the first conductive layer. A part of the lower layer projected from the end section of the upper layer is bonded with ITO. | 2020-06-11 |
20200185535 | Oxide thin film transistor, array substrate, and preparation methods thereof - An oxide thin film transistor, an array substrate, and preparation methods thereof are disclosed. The method for preparing an oxide thin film transistor comprises a step of forming a pattern comprising an oxide semiconductor active layer on a substrate, wherein the step comprises: forming an amorphous oxide semiconductor thin film on the substrate; performing an excimer laser annealing, at least at a position in the amorphous oxide semiconductor thin film corresponding to a channel region of oxide semiconductor active layer to be formed, such that the amorphous oxide semiconductor material at the laser-annealed position is crystallized, to form a crystalline oxide semiconductor material; and forming the pattern comprising the oxide semiconductor active layer. | 2020-06-11 |
20200185536 | TRANSISTOR AND SEMICONDUCTOR DEVICE - A transistor with small parasitic capacitance can be provided. A transistor with high frequency characteristics can be provided. A semiconductor device including the transistor can be provided. Provided is a transistor including an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor has a first region where the first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween; a second region where the first conductor overlaps with the second conductor with the first and second insulators positioned therebetween; and a third region where the first conductor overlaps with the third conductor with the first and second insulators positioned therebetween. The oxide semiconductor including a fourth region where the oxide semiconductor is in contact with the second conductor; and a fifth region where the oxide semiconductor is in contact with the third conductor. | 2020-06-11 |
20200185537 | THIN FILM TRANSISTOR, DISPLAY DEVICE INCLUDING THE THIN FILM TRANSISTOR, AND METHOD OF MANUFACTURING THE THIN FILM TRANSISTOR AND THE DISPLAY DEVICE - A thin film transistor includes an active layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, a capping layer filling a thickness difference between the first portion and the second portion and arranged on the first portion, a gate insulating layer arranged on the capping layer, a gate electrode on the active layer, wherein the gate insulating layer and the capping layer are disposed between the gate electrode and the active layer, and a source electrode and a drain electrode connected to the active layer. | 2020-06-11 |
20200185538 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE INCLUDING THE SEMICONDUCTOR DEVICE - The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. One embodiment of the present invention is a semiconductor device which includes a gate electrode, an insulating film over the gate electrode, an oxide semiconductor film over the insulating film, and a pair of electrodes over the oxide semiconductor film. The oxide semiconductor film includes a first oxide semiconductor film, a second oxide semiconductor film over the first oxide semiconductor film, and a third oxide semiconductor film over the second oxide semiconductor film. The first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film include the same element. The second oxide semiconductor film includes a region having lower crystallinity than one or both of the first oxide semiconductor film and the third oxide semiconductor film. | 2020-06-11 |
20200185539 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode. | 2020-06-11 |
20200185540 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an exemplary embodiment of the present disclosure includes: an n− type layer disposed in a first surface of a substrate; an n type layer disposed on the n− type layer; a first electrode disposed on the n type layer, and a second electrode disposed in a second surface of the substrate, wherein an energy band gap of the n− type layer is larger than an energy band gap of the n type layer. | 2020-06-11 |
20200185541 | OXIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING OXIDE SEMICONDUCTOR DEVICE - An oxide semiconductor device has an improved withstand voltage when an inverse voltage is applied, while suppressing diffusion of different types of materials to a Schottky interface. The oxide semiconductor device includes an n-type gallium oxide epitaxial layer, p-type oxide semiconductor layers of an oxide that is a different material from the material for the gallium oxide epitaxial layer, a dielectric layer formed to cover at least part of a side surface of the oxide semiconductor layer, an anode electrode, and a cathode electrode. Hetero pn junctions are formed between the lower surfaces of the oxide semiconductor layers and a gallium oxide substrate or between the lower surfaces of the oxide semiconductor layers and the gallium oxide epitaxial layer. | 2020-06-11 |
20200185542 | LATERAL SCHOTTKY DIODE WITH HIGH BREAKDOWN VOLTAGE CAPABILITY - A lateral diode with high breakdown voltage capability and a method for forming the lateral diode. The lateral diode has an anode, a cathode, a substrate having a first conductivity type, an epitaxial layer having formed on the substrate, a current region formed in the epitaxial layer and on the substrate, a first well coupled to the anode, a second well coupled to the cathode, a third well with light doping concentration formed beside the first well, and a guard ring with heavy doping concentration formed in the first well and beside the third well, and between the third well and the second well is a drift region, a lateral breakdown occurs in the third well, the drift region and the second well when a reverse voltage added on the lateral diode is equal to or higher than a breakdown voltage. | 2020-06-11 |
20200185543 | METHOD OF MANUFACTURING A SEMICONDUCTOR COMPONENT - A method for manufacturing a semiconductor component includes forming first mesa and second mesa structures from a semiconductor material by etching trenches into the semiconductor material. A doped region having a multi-concentration dopant profile is formed in at least the first mesa structure and doped polysilicon is formed in the trenches. The trenches are formed in a geometric pattern. A contact having three contact types is formed, wherein a first contact type is formed to the first mesa structure, a second contact type is formed to the second mesa structure, and a third contact type is formed to the doped polysilicon in the trenches. The first contact type has electrical properties between a conventional Schottky contact and a conventional Ohmic contact without being a conventional Schottky contact or a conventional Ohmic contact, the second contact type is a Schottky contact, the third contact type is an Ohmic contract. | 2020-06-11 |
20200185544 | MICROELECTRONIC STRUCTURES INCLUDING CAPACITOR STRUTURES AND METHODS OF FORMING MICROELECTRONIC STRUCTURES - A semiconductor structure includes a capacitor structure comprising an active region comprising opposing field edges parallel to a first horizontal direction and a gate region comprising opposing gate edges parallel to a second horizontal direction transverse to the first horizontal direction. The semiconductor structure also comprises a first dielectric material adjacent at least one of the opposing field edges or the opposing gate edges and a second dielectric material adjacent the active area and abutting portions of the first dielectric material. A height of the second dielectric material in a vertical direction may be less than the height of the first dielectric material. Semiconductor devices and related methods are also disclosed. | 2020-06-11 |
20200185545 | COLOR SOLAR ENERGY MODULE AND FABRICATION METHOD THEREFOR - A color solar energy module and fabrication method therefor, the color solar energy module comprising a solar cell module ( | 2020-06-11 |
20200185546 | PROCESS AND STRUCTURES FOR FABRICATION OF SOLAR CELLS - Contact holes of solar cells are formed by laser ablation to accommodate various solar cell designs. Use of a laser to form the contact holes is facilitated by replacing films formed on the diffusion regions with a film that has substantially uniform thickness. Contact holes may be formed to deep diffusion regions to increase the laser ablation process margins. The laser configuration may be tailored to form contact holes through dielectric films of varying thicknesses. | 2020-06-11 |
20200185547 | SOLAR CELL, SOLAR CELL MANUFACTURING SYSTEM, AND SOLAR CELL MANUFACTURING METHOD - An object of the present invention is to provide, at a low cost, a solar cell having high conversion efficiency. A solar cell according to the present invention is characterized by including a passivation film that protects a semiconductor substrate, a first finger electrode connected to the semiconductor substrate on a main surface of the semiconductor substrate, a first bus bar electrode that intersects the first finger electrode, and an intermediate layer provided in an intersecting position of the first finger electrode and the first bus bar electrode. The solar cell is characterized in that the first finger electrode and the first bus bar electrode are electrically connected to each other via the intermediate layer. | 2020-06-11 |
20200185548 | CONDUCTIVE PASTE AND SOLAR CELL - Provided is a conductive paste for forming bus bar electrodes having high adhesive strength with respect to a passivation film in a crystalline silicon solar cell without having a detrimental effect on the passivation film so as to affect solar cell properties. | 2020-06-11 |
20200185549 | COMPOSITION FOR FORMING SOLAR CELL ELECTRODE AND SOLAR CELL ELECTRODE PREPARED USING THE SAME - A composition for solar cell electrodes, a solar cell electrode, and a method of manufacturing a solar cell, the composition including a conductive powder; a glass frit; and an organic vehicle, wherein the conductive powder includes a first silver powder having a cross-sectional particle porosity of about 0.1% to about 6%. | 2020-06-11 |
20200185550 | CATHODE OF SOLAR UNIT AND METHOD FOR MANUFACTURING THEREOF, AND SOLAR CELL - A cathode of a solar unit and a solar cell including thereof are provided. The cathode of solar unit includes a film which is formed by curing a composition, and a pixel electrode which is formed on the film; wherein the composition includes conducting polymer, curing material, ionic liquid and phosphorene, wherein the weight ratio of the phosphorene to the sum of the conducting polymer, the curing material and the ionic liquid is about 2%˜10%. | 2020-06-11 |
20200185551 | SINGLE-STEP METAL BOND AND CONTACT FORMATION FOR SOLAR CELLS - A method for fabricating a solar cell is disclosed. The method can include forming a dielectric region on a surface of a solar cell structure and forming a first metal layer on the dielectric region. The method can also include forming a second metal layer on the first metal layer and locally heating a particular region of the second metal layer, where heating includes forming a metal bond between the first and second metal layer and forming a contact between the first metal layer and the solar cell structure. The method can include forming an adhesive layer on the first metal layer and forming a second metal layer on the adhesive layer, where the adhesive layer mechanically couples the second metal layer to the first metal layer and allows for an electrical connection between the second metal layer to the first metal layer. | 2020-06-11 |
20200185552 | SOLAR CELL AND SOLAR CELL MODULE - A solar cell having a P-type silicon substrate where one main surface is a light-receiving surface and another is a backside, a plurality of back surface electrodes formed on a part of the backside, an N-type layer in at least a part of the light-receiving surface, and contact areas in which the substrate contacts the electrodes. The P-type silicon substrate is a silicon substrate doped with gallium and has a resistivity of 2.5 Ω·cm or less; and a back surface electrode pitch P | 2020-06-11 |
20200185553 | Flexible Double-Junction Solar Cell - A flexible double-junction solar cell includes a flexible substrate including a lower electrode layer, an InGaAs solar cell disposed to be in contact with the lower electrode layer of the flexible substrate, and a GaAs solar cell disposed on the InGaAs solar cell and connected to the InGaAs solar cell in series. The GaAs solar cell includes a metal nanodisk array disposed on a lower surface thereof and a void array, aligned with the metal nanodisk array, is disposed below the metal nanodisk array. | 2020-06-11 |
20200185554 | BLIND BLADE ASSEMBLY FOR SOLAR PHOTOVOLTAIC POWER GENERATION - The present invention relates to a blind blade assembly for solar photovoltaic power generation including solar cells installed on one side thereof to enable solar photovoltaic power generation. In the blind blade assembly of the present invention, solar cells are provided in a prefabricated form, allowing the solar cells to be replaced and repaired individually. | 2020-06-11 |
20200185555 | Array of Photovoltaic Cells - A method of generating electricity from light that utilizes an array of photovoltaic cells, each including a junction between an electron-donating layer, and an electron-accepting layer, and wherein each cell produces a maximum current during exposure to light when it is exposed to a magnetic field having an optimal strength, and wherein the optimal magnetic field strength varies by more than 5% between the photovoltaic cells. For each the cell, a magnetic field is created in an optimal range of magnetic field strength, that is substantially unvarying over the electron donating layer, as the array is being exposed to light. | 2020-06-11 |
20200185556 | SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME, AND SOLAR CELL PANEL - Discussed is a solar cell including a semiconductor substrate, a conductive region disposed in the semiconductor substrate or over the semiconductor substrate, and an electrode electrically connected to the conductive region. The electrode includes a first electrode part and a second electrode part disposed over the first electrode part. The second electrode part includes a particle connection layer formed by connecting a plurality of particles including a first metal and a cover layer including a second metal different from the first metal and covering at least the outside surface of the particle connection layer. | 2020-06-11 |
20200185557 | DEVICE FOR HARVESTING SUNLIGHT - A device for harvesting sunlight includes a frame and a plurality of sunlight harvesting units. Each sunlight harvesting unit includes a first reflector having a first reflective surface; a second reflector having a second reflective surface; a first light collection unit positioned proximate the second reflector and oriented to receive reflected light from first reflective surface, and a second light collection unit positioned proximate the first reflector and oriented to receive reflected light from the second reflective surface. Each light collection unit has a lower-efficiency photovoltaic cell and a higher-efficiency photovoltaic cell, the cells in thermal communication. The cells are arranged such that sunlight parallel to an axial plane impinging on the reflective surface and reflected thereby is focused on the higher-efficiency photovoltaic cell, and sunlight non-parallel to the axial plane impinging on the reflective surface and reflected thereby is collected by the lower-efficiency photovoltaic cell. | 2020-06-11 |
20200185558 | Multi-Junction Tandem Laser Photovoltaic Cell and Manufacturing Method Thereof - The present application discloses a multi-junction tandem laser photovoltaic cell, comprising a photovoltaic cell stack and a bottom electrode and a top electrode electrically connected to a bottom and a top of the photovoltaic cell stack, respectively, wherein the photovoltaic cell stack comprises stacked N AlGaAs PN-junction sub-cells, and adjacent sub-cells are connected in series via a tunneling junction, in which N≥2. The AlGaAs PN-junction sub-cells use an AlGaAs absorbing layer. The present application further discloses a method of making the multi-junction tandem laser photovoltaic cell. The present application uses AlGaAs as the absorbing layer of the multi-junction tandem cell to convert laser energy, which can effectively increase the open circuit voltage of the photovoltaic cell, thereby significantly improving the conversion efficiency of the photovoltaic cell. | 2020-06-11 |
20200185559 | USE OF A LOW BANDGAP ABSORBER REGION IN A LASER POWER CONVERTER - A low bandgap absorber region (LBAR) used in a laser power converter (LPC). The laser power converter is comprised of one or more subcells on a substrate, wherein at least one of the subcells has an emitter and base, with the low bandgap absorber region coupled between the emitter and base. The emitter and base are comprised of a material with a bandgap higher than a wavelength of incident laser light, and the low bandgap absorber region is comprised of a material with a bandgap lower than the emitter and base. The emitter and base are transparent to the incident laser light, and the low bandgap absorber region absorbs the incident laser light and generates a current in response thereto, such that the current is controlled by the material and thickness of the low bandgap absorber region. The low bandgap absorber region is configured to produce a current balanced to the subcells connected in series. | 2020-06-11 |
20200185560 | SPAD-TYPE PHOTODIODE - A SPAD-type photodiode including, in an upper portion of a semiconductor substrate of a first conductivity type, an alternation of vertically stacked regions of the first conductivity type and regions of a second conductivity type, the regions of the first conductivity type being in contact with a same first semiconductor via of the first conductivity type and the regions of the second conductivity type being in contact with a same second semiconductor via of the second conductivity type. | 2020-06-11 |
20200185561 | Waveguide-Integrated Avalanche Photodiode - Various embodiments of a monolithic avalanche photodiode (APD) are described, which may be fabricated on a silicon-on-insulator substrate. The monolithic APD includes an optical waveguide that guides an incident light to an active region of the APD. An optical coupler is integrally formed with the optical waveguide to capture the incident light. The monolithic APD also includes an optical reflector to reflect a portion of the incident light that is not readily captured by the optical coupler back to the optical coupler for further capturing. The active region includes an absorption layer for converting the incident light into a photocurrent, an epitaxial structure for amplifying the photocurrent by avalanche multiplication, as well as a pair of electrical conductors for conducting the amplified photocurrent. | 2020-06-11 |
20200185562 | SINGLE PHOTON AVALANCHE GATE SENSOR DEVICE - A semiconductor substrate doped with a first doping type is positioned adjacent an insulated gate electrode that is biased by a gate voltage. A first region within the semiconductor substrate is doped with the first doping type and biased with a bias voltage. A second region within the semiconductor substrate is doped with a second doping type that is opposite the first doping type. Voltage application produces an electrostatic field within the semiconductor substrate causing the formation of a fully depleted region within the semiconductor substrate. The fully depleted region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at the first and second regions. | 2020-06-11 |
20200185563 | SINGLE PHOTON AVALANCHE GATE SENSOR DEVICE - A semiconductor layer is doped with a first doping type and has an upper surface. A first electrode insulated from the semiconductor layer extending through the semiconductor layer from the upper surface. A second electrode insulated from the semiconductor layer extends through the semiconductor layer from the upper surface. The first and second electrodes are biased by a voltage to produce an electrostatic field within the semiconductor layer causing the formation of a depletion region. The depletion region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at first and second oppositely doped regions within the semiconductor substrate. | 2020-06-11 |
20200185564 | APPARATUS AND METHOD FOR PATTERNED PROCESSING - An apparatus for patterned processing includes a source of input gas, a source of energy suitable for generating a plasma from the input gas in a plasma region and a grounded sample holder configured for receiving a solid sample. The apparatus includes a mask arranged between the plasma region and the grounded sample holder, the mask having a first face oriented toward the plasma region and a second face oriented toward a surface of the solid sample to be processed, the mask including a mask opening extending from the first face to the second face, and an electrical power supply adapted for applying a direct-current bias voltage to the mask, and the mask opening being dimensioned and shaped so as to generate spatially selective patterned processing on the surface of the solid sample. | 2020-06-11 |
20200185565 | MANUFACTURING METHOD OF LIGHT-EMITTING DEVICE - A manufacturing method of a light-emitting device including the following steps is provided. A test trace and a first signal trace are formed on a first substrate. A light-emitting element electrically connected to the test trace and the first signal trace is formed. A test procedure is performed on the light-emitting element via the test trace and the first signal trace. An encapsulation layer is formed on the first substrate to cover the light-emitting element. The test trace is removed, and then a driving unit electrically connected to light-emitting element is formed. | 2020-06-11 |
20200185566 | Method for Fabricating an Optical Device - An optical device and a method for fabricating an optical device are described. The optical device may be a light emitting diode (LED) device, e.g. a micro-LED (μLED) device, or a photodiode (PD) device, e.g. an imager. The method comprises processing, on a first semiconductor wafer, an array including a plurality of compound semiconductor LEDs or compound semiconductor PDs and a plurality of first contacts, each first contact being electrically connected to one of the LEDs or PDs. The method further comprises processing, on a second semiconductor wafer, a CMOS IC and a plurality of second contacts electrically connected to the CMOS IC. The method further comprises hybrid bonding the first semiconductor wafer to the second semiconductor wafer such that the plurality of LEDs or PDs are individually connected to the CMOS IC via the first and second contacts. | 2020-06-11 |
20200185567 | ULTRAVIOLET LED EPITAXIAL PRODUCTION METHOD AND ULTRAVIOLET LED - The present disclosure provides an ultraviolet LED epitaxial production method and an ultraviolet LED, where the method includes: pre-introducing a metal source and a group-V reactant on a substrate, to form a buffer layer through decomposition at a first temperature; growing an N-doped AlwGa1-wN layer on the buffer layer at a second temperature; growing a multi-section LED structure on the N-doped AlwGa1-wN layer at a third temperature, wherein a number of sections of the multi-section LED structure is in a range of 2 to 50; and each section of the LED structure comprises an AlxGa1-xN/AlyGa1-yN multi-quantum well structure and a P-doped AlmGa1-mN layer, and the multi-section LED structure emits light of one or more wavelengths, which realizes that a single ultraviolet LED emits ultraviolet light of different wavelengths, thereby improving the luminous efficiency of the ultraviolet LED. | 2020-06-11 |
20200185568 | Light-emitting Component - A light-emitting component a first layer stack configured to generate light, at least one additional layer stack configured to generate light, where each of the first layer stack and the at least one additional layer stack are separately drivable from one another and where an auxiliary structure is arranged between the first layer stacks and the at least one additional layer stacks. | 2020-06-11 |
20200185569 | LIGHT EMITTING PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A light emitting package structure and a method of manufacturing the light emitting package structure are provided. The method includes: a preparation process: mounting a light emitting unit on a substrate; a dispensing process: coating a sealant on a first joint area of the substrate; a cover-enclosing process: disposing a cover element having a second joint area on the substrate, the first joint area and the second joint area joined to each other by the sealant; a vacuum process: reducing an ambient pressure to a first pressure lower than the original ambient pressure; a pressure-adjusting process: adjusting the ambient pressure around the package structure to a second pressure higher than the first pressure; and a curing process: curing the sealant. | 2020-06-11 |
20200185570 | METHOD FOR MANUFACTURING CHIP-MOUNTING SUBSTRATE, AND CHIP-MOUNTING SUBSTRATE - A method for manufacturing a chip-mounting substrate includes a pre-coating step of forming a precoat on a substrate including a plurality of conductive portions and an insulating portion interposed between the conductive portions, an etching step of etching at least a portion of the precoat through a laser to form a pattern, and a step of forming a metal layer on the substrate. The pattern is disposed on at least one of the conductive portions, and the metal layer is formed in the pattern. | 2020-06-11 |
20200185571 | PHOSPHOR AND SEMICONDUCTOR LIGHT EMITTING DEVICE USING THE SAME - A phosphor according to the present disclosure has excellent light emission properties in a blue-green region and high color rendering properties. The phosphor is represented by a chemical formula of Lu | 2020-06-11 |
20200185572 | STABILIZED FLUORIDE PHOSPHOR FOR LIGHT EMITTING DIODE (LED) APPLICATIONS - A stabilized fluoride phosphor for light emitting diode (LED) applications includes a particle comprising manganese-activated potassium fluorosilicate and an inorganic coating on each of the particles. The inorganic coating comprises a silicate. A method of making a stabilized fluoride phosphor comprises forming a reaction mixture that includes particles comprising a manganese-activated potassium fluorosilicate; a reactive silicate precursor; a catalyst; a solvent; and water in an amount no greater than about 10 vol. %. The reaction mixture is agitated to suspend the particles therein. As the reactive silicate precursor undergoes hydrolysis and condensation in the reaction mixture, an inorganic coating comprising a silicate is formed on the particles. Thus, a stabilized fluoride phosphor is formed. | 2020-06-11 |
20200185573 | DISPLAY DEVICE - A display device that can reduce power consumption is provided. The display device can include a substrate provided with a first subpixel and a second subpixel, a first electrode provided on the substrate, a first light emitting layer provided on the first electrode and emitting light of a first color, a second electrode provided on the first light emitting layer, a second light emitting layer provided on the second electrode and emitting light of a second color, and a third electrode provided on the second light emitting layer. The second electrode is disconnected between the first subpixel and the second subpixel, and the second electrode of the first subpixel is electrically connected with the third electrode. | 2020-06-11 |
20200185574 | LIGHT-EMITTING DEVICE AND LIGHT-EMITTING DEVICE MODULE - A light-emitting device having high output and high contrast with simple configuration is provided. The light-emitting device includes a substrate, a light-emitting element disposed on the substrate, a light-transmitting member disposed on the light-emitting element, and a covering body disposed on the substrate so as to surround the light-transmitting member and cover a side surface of the light-transmitting member. The covering body has a particle group including a plurality of metal oxide particles having a light scattering property and dispersed in the covering body, and the metal oxide particles existing in the vicinity of the side surface of the covering body have a portion having a bandgap smaller than that of other portions in each particle. | 2020-06-11 |
20200185575 | WAVELENGTH CONVERTING MEMBER AND LIGHT EMITTING DEVICE - A wavelength converting member comprising a first wavelength converting layer containing: a first fluorescent material having a light emission peak wavelength in a range of 620 nm or more and 660 nm or less; a second fluorescent material having a light emission peak wavelength in a range of 510 nm or more and 560 nm or less; and a resin, wherein the average particle diameter, as measured according to a Fisher Sub-Sieve Sizer method, of the first fluorescent material is in a range of 2 μm or more and 30 μm or less, wherein the second fluorescent material comprises a β-SiAlON fluorescent material, the circularity of the β-SiAlON fluorescent material is 0.7 or more, and the volume average particle diameter, as measured according to a laser diffraction scattering particle size distribution measuring method, of the β-SiAlON fluorescent material is in a range of 2 μm or more and 30 μm or less, and wherein the thickness of the first wavelength converting layer is in a range of 50 μm or more and 200 μm or less. | 2020-06-11 |
20200185576 | METHOD OF PRODUCING AN OPTOELECTRONIC LIGHTING DEVICE AND OPTOELECTRONIC LIGHTING DEVICE - A method of producing an optoelectronic lighting device includes forming a volume emitter such that it is at least partly transmissive to generated electromagnetic radiation, forming a concavely formed, optically transparent frame element including a curable, flowable material including phosphor particles at a side region of the volume emitter, wherein forming a conversion layer that converts the electromagnetic radiation into a second wavelength range is carried out by a sedimentation process of phosphor particles, and the conversion layer is formed within an optically transparent frame element in a manner adjoining an optically active region, forming a reflection element on the optically transparent frame element, and forming a conversion element that converts the electromagnetic radiation into a second wavelength range, wherein the conversion element is formed in a manner overlapping at least a second surface of the volume emitter and frame element. | 2020-06-11 |
20200185577 | LED LIGHT SOURCE DEVICE AND MANUFACTURING METHOD THEREOF - The present application discloses an LED light source device and a manufacturing method thereof. Methyl-based silica gel or phenyl-based silica gel is blended with a light diffusion agent or a mixed powder of a light diffusion agent and a phosphor at an amount of 2% to 8% by weight to form a novel colloid, which is coated on a blue light chip fixed in the form of SMD or COB to form an LED light source device. The light output efficiency thereof reaches more than 92% of the light output efficiency of a light source device not coated with any colloid (that is, the blue light chip is exposed), and is 20% higher than the light output efficiency of a light source device coated with methyl-based silica gel or phenyl-based silica gel. | 2020-06-11 |
20200185578 | METHOD OF ADAPTING LIGHT EXTRACTION FROM A LIGHT EMITTING DIODE - The invention relates to a method of adapting light extraction LEE from at least one light emitting diode ( | 2020-06-11 |